diff options
| author | Richard Sandiford <rsandifo@nildram.co.uk> | 2002-09-30 11:58:10 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@nildram.co.uk> | 2002-09-30 11:58:10 +0000 |
| commit | 6c2bf2433b5076d4801d4278d59c7cecafe41a85 (patch) | |
| tree | 213daad199e9df961772ee592d6ce5a2eb762ee6 /opcodes/mips-dis.c | |
| parent | 2df8cb0969000e82a8b63abe0d1bb27583d8a4bb (diff) | |
| download | gdb-6c2bf2433b5076d4801d4278d59c7cecafe41a85.tar.gz | |
[include/opcode/]
* mips.h: Update comment for new opcodes.
(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
Don't match CPU_R4111 with INSN_4100.
[opcodes/]
* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
and bfd_mach_mips5500.
* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
(N411, N412, N5, N54, N55): New convenience defines.
(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
Change dmadd16 and madd16 from V1 to N411.
Diffstat (limited to 'opcodes/mips-dis.c')
| -rw-r--r-- | opcodes/mips-dis.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 4ffdf9990f4..0a4280108da 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -110,6 +110,8 @@ print_insn_arg (d, l, pc, info) case ',': case '(': case ')': + case '[': + case ']': (*info->fprintf_func) (info->stream, "%c", *d); break; @@ -279,6 +281,16 @@ print_insn_arg (d, l, pc, info) (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); break; + case 'e': + (*info->fprintf_func) (info->stream, "%d", + (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); + break; + + case '%': + (*info->fprintf_func) (info->stream, "%d", + (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); + break; + case 'H': (*info->fprintf_func) (info->stream, "%d", (l >> OP_SH_SEL) & OP_MASK_SEL); @@ -374,6 +386,10 @@ mips_isa_type (mach, isa, cputype) *cputype = CPU_R4111; *isa = ISA_MIPS3; break; + case bfd_mach_mips4120: + *cputype = CPU_VR4120; + *isa = ISA_MIPS3; + break; case bfd_mach_mips4300: *cputype = CPU_R4300; *isa = ISA_MIPS3; @@ -394,6 +410,14 @@ mips_isa_type (mach, isa, cputype) *cputype = CPU_R5000; *isa = ISA_MIPS4; break; + case bfd_mach_mips5400: + *cputype = CPU_VR5400; + *isa = ISA_MIPS4; + break; + case bfd_mach_mips5500: + *cputype = CPU_VR5500; + *isa = ISA_MIPS4; + break; case bfd_mach_mips6000: *cputype = CPU_R6000; *isa = ISA_MIPS2; |