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| author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2007-03-06 13:19:07 +0000 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2007-03-06 13:19:07 +0000 |
| commit | 269ff1efe35720e12ddf718b2c9b68e9814ae1ff (patch) | |
| tree | d8308a0df8d28c24d039e1c21fd15bddd2a296d3 /opcodes/s390-opc.c | |
| parent | 3fd42cb98856d879b5850e25188064d438027524 (diff) | |
| download | gdb-269ff1efe35720e12ddf718b2c9b68e9814ae1ff.tar.gz | |
2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
* opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New
instruction formats added.
(MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF,
MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format
masks added.
* opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point
instructions added.
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
(main): z9-ec cpu type option added.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z9-ec option added.
2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z9-ec.d: New file.
* gas/s390/zarch-z9-ec.s: New file.
* gas/s390/s390.exp: Run the z9-ec testcases.
Diffstat (limited to 'opcodes/s390-opc.c')
| -rw-r--r-- | opcodes/s390-opc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index d5913c0fe21..8b0b72f222e 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -205,15 +205,21 @@ const struct s390_operand s390_operands[] = #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ /* Actually efpc and sfpc do not take an optional operand. This is just a workaround for existing code e.g. glibc. */ #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ +#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ +#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ +#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ @@ -221,6 +227,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ @@ -281,13 +288,19 @@ const struct s390_operand s390_operands[] = #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -295,6 +308,7 @@ const struct s390_operand s390_operands[] = #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |