diff options
| author | Peter Bergner <bergner@vnet.ibm.com> | 2009-02-19 21:18:46 +0000 |
|---|---|---|
| committer | Peter Bergner <bergner@vnet.ibm.com> | 2009-02-19 21:18:46 +0000 |
| commit | 597f03241f93b1a73ab394469992309f93e4bc8e (patch) | |
| tree | 772cc6444136182ab4b345be5980e49668edd845 /opcodes | |
| parent | bdd55903c84984eccaa5345b36415cd767728190 (diff) | |
| download | gdb-597f03241f93b1a73ab394469992309f93e4bc8e.tar.gz | |
gas/testsuite/
* gas/ppc/e500mc.d ("lfdepx", "stfdepx"): Fix tests to expect a
floating point register.
opcodes/
* ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first
operand to be a float point register (FRT/FRS).
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index db66f45e604..d1a0adabbe9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2009-02-19 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first + operand to be a float point register (FRT/FRS). + 2009-02-18 Adam Nemet <anemet@caviumnetworks.com> * mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 5ce87b71650..294af73da23 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4286,7 +4286,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, -{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, +{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, PPCNONE, {FRT, RB}}, {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, @@ -4373,7 +4373,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, -{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, +{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, PPCNONE, {RT, FRB}}, {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, |