2002-12-05 Aldy Hernandez <aldyh@redhat.com>

	* ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub,
	evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq,
	evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi,
	evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa,
	evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian,
	evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa,
	evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan,
	evmwhgsmian, evmwhgumian.
	(mftb): Add to opcode table.
	(mtspefscr): Change RT to RS in opcode table.

2 files changed, 15 insertions, 49 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5a7f7cf6da7..df675ceabbb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,18 @@
 2002-12-05  Aldy Hernandez  <aldyh@redhat.com>
 
+	* ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub,
+	evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq,
+	evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi,
+	evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa,
+	evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian,
+	evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa,
+	evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan,
+	evmwhgsmian, evmwhgumian.
+	(mftb): Add to opcode table.
+	(mtspefscr): Change RT to RS in opcode table.
+
+2002-12-05  Aldy Hernandez  <aldyh@redhat.com>
+
 	* ppc-opc.c: Move mbar and msync up.  Change mask for mbar and
 	msync.
 
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a88651ec747..75f34c87e57 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2192,30 +2192,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "efsctuf",  VX(4, 726), VX_MASK,	PPCEFS,		{ RS, RB } },
 { "efsctsf",  VX(4, 727), VX_MASK,	PPCEFS,		{ RS, RB } },
 
-{ "evsabs",    VX(4, 708), VX_MASK,	PPCSPE,		{ RS, RA } },
-{ "evsnabs",   VX(4, 709), VX_MASK,	PPCSPE,		{ RS, RA } },
-{ "evsneg",    VX(4, 710), VX_MASK,	PPCSPE,		{ RS, RA } },
-{ "evsadd",    VX(4, 704), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evssub",    VX(4, 705), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evsmul",    VX(4, 712), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evsdiv",    VX(4, 713), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evscmpgt",  VX(4, 716), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
-{ "evsgmplt",  VX(4, 717), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
-{ "evsgmpeq",  VX(4, 718), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
-{ "evststgt",  VX(4, 732), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
-{ "evststlt",  VX(4, 733), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
-{ "evststeq",  VX(4, 734), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
-{ "evscfui",   VX(4, 720), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evscfsi",   VX(4, 721), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evscfuf",   VX(4, 722), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evscfsf",   VX(4, 723), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evsctui",   VX(4, 724), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evsctuiz",  VX(4, 728), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evsctsi",   VX(4, 725), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evsctsiz",  VX(4, 730), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evsctuf",   VX(4, 726), VX_MASK,	PPCSPE,		{ RS, RB } },
-{ "evsctsf",   VX(4, 727), VX_MASK,	PPCSPE,		{ RS, RB } },
-
 { "evmhossf",  VX(4, 1031), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmhossfa", VX(4, 1063), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmhosmf",  VX(4, 1039), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
@@ -2285,40 +2261,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "evmwlumi",  VX(4, 1096), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwlumia", VX(4, 1128), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 
-{ "evmwhssfaa",VX(4, 1351), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhssmaa",VX(4, 1349), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhsmfaa",VX(4, 1359), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhsmiaa",VX(4, 1357), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhusiaa",VX(4, 1348), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhumiaa",VX(4, 1356), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-
 { "evmwlssiaaw",VX(4, 1345), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwlusiaaw",VX(4, 1344), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwlumiaaw",VX(4, 1352), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 
-{ "evmwhssfan",VX(4, 1479), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhssian",VX(4, 1477), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhsmfan",VX(4, 1487), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhsmian",VX(4, 1485), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhusian",VX(4, 1476), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhumian",VX(4, 1484), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-
 { "evmwlssianw",VX(4, 1473), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwlsmianw",VX(4, 1481), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwlusianw",VX(4, 1472), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwlumianw",VX(4, 1480), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 
-{ "evmwhgssfaa",VX(4, 1383), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhgsmfaa",VX(4, 1391), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhgsmiaa",VX(4, 1381), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhgumiaa",VX(4, 1380), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-
-{ "evmwhgssfan",VX(4, 1511), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhgsmfan",VX(4, 1519), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhgsmian",VX(4, 1509), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-{ "evmwhgumian",VX(4, 1508), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
-
 { "evmwssf",   VX(4, 1107), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwssfa",  VX(4, 1139), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
 { "evmwsmf",   VX(4, 1115), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
@@ -3799,6 +3751,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mftbl",   XSPR(31,371,268), XSPR_MASK, CLASSIC,	{ RT } },
 { "mftbu",   XSPR(31,371,269), XSPR_MASK, CLASSIC,	{ RT } },
+{ "mftb",    X(31,371),	X_MASK,		CLASSIC,	{ RT, TBR } },
 
 { "lwaux",   X(31,373),	X_MASK,		PPC64,		{ RT, RAL, RB } },
 
@@ -3990,7 +3943,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
-{ "mtspefscr", XSPR(31,467,512),  XSPR_MASK, PPCSPE,	{ RT } },
+{ "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },