diff options
| author | David Carlton <carlton@bactrian.org> | 2003-09-17 21:29:05 +0000 |
|---|---|---|
| committer | David Carlton <carlton@bactrian.org> | 2003-09-17 21:29:05 +0000 |
| commit | 5993e46956fada1bbe5ad7b95b63c22a5c858746 (patch) | |
| tree | 94451834539b4a3459fcd3b18f22ea6cdd838f0f /opcodes | |
| parent | 6ac3a292f75ffbdc018a333c89e23809dc90bc56 (diff) | |
| download | gdb-5993e46956fada1bbe5ad7b95b63c22a5c858746.tar.gz | |
2003-09-17 David Carlton <carlton@kealia.com>
* Merge with mainline; tag is carlton_dictionary-20030917-merge.
Diffstat (limited to 'opcodes')
48 files changed, 2618 insertions, 2535 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7c8edbd5db3..9b109a6e3b6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,212 @@ +2003-09-14 Andreas Jaeger <aj@suse.de> + + * i386-dis.c: Convert to ISO C90 prototypes. + * i370-dis.c: Likewise. + * i370-opc.c: Likewiwse. + * i960-dis.c: Likewise. + * ia64-opc.c: Likewise. + +2003-09-09 Dave Brolley <brolley@redhat.com> + + * frv-desc.c: Regenerated. + +2003-09-08 Dave Brolley <brolley@redhat.com> + + On behalf of Doug Evans <dje@sebabeach.org> + * Makefile.am (run-cgen): Pass new args archfile and opcfile + to cgen.sh. + (stamp-ip2k,stamp-m32r,stamp-fr30,stamp-frv,stamp-openrisc, + stamp-iq2000,stamp-xstormy16): Pass paths of .cpu and .opc files + to cgen.sh. + (stamp-frv): Delete hardcoded path spec workaround. + * Makefile.in: Regenerate. + * cgen.sh: New args archfile and opcfile. Pass on to cgen. + +2003-09-04 Nick Clifton <nickc@redhat.com> + + * v850-dis.c (disassemble): Accept bfd_mach_v850e1. + * v850-opc.c (v850_opcodes): Add DBTRAP and DBRET instructions. + +2003-09-04 Alan Modra <amodra@bigpond.net.au> + + * ppc-dis.c (struct dis_private): New. + (powerpc_dialect): Make static. Accept -Many in addition to existing + options. Save dialect in dis_private. + (print_insn_big_powerpc): Retrieve dialect from dis_private. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Call powpc_dialect here. Remove unnecessary + efs/altivec check. Try harder to disassemble if given -Many. + * ppc-opc.c (insert_fxm): Expand comment. + (PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY. + (POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise. + (POWER4): Remove PPCCOM. + (PPCONLY): Don't define. Update all occurrences to PPC. + +2003-09-03 Andrew Cagney <cagney@redhat.com> + + * dis-init.c (init_disassemble_info): New file and function. + * Makefile.am (CFILES): Add "dis-init.c". + (libopcodes_la_SOURCES): Add "dis-init.c". + (dis-init.lo): Specify dependencies. + * Makefile.in: Regenerate. + +2003-09-03 Dave Brolley <brolley@redhat.com> + + * frv-*: Regenerated. + +2003-09-02 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries. + Move duplicate mnemonic entries together. Use RS instead of RT on + all mt*. + * ppc-dis.c: Convert to ISO C. + +2003-08-29 Dave Brolley <brolley@redhat.com> + + * Makefile.am (stamp-frv): Copy frv.cpu and frv.opc from + $(srcdir)/../cpu temporarily when regenerating source files. + * Makefile.in: Regenerated. + +2003-08-19 Nick Clifton <nickc@redhat.com> + + * arm-dis.c (print_insn_arm: case 'A'): Add code to + disassemble unindexed form of Addressing Mode 5. + +2003-08-19 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (PPC440): Define. + (powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci, + icread instructions when PPC440. Add dlmzb instruction. + +2003-08-14 Alan Modra <amodra@bigpond.net.au> + + * dep-in.sed: Remove libintl.h. + * Makefile.am (POTFILES.in): Unset LC_COLLATE. + Run "make dep-am". + * Makefile.in: Regenerate. + +2003-08-07 Michael Meissner <gnu@the-meissners.org> + + * cgen-asm.c (hash_insn_array): Remove PARAMS macro. + (hash_insn_list): Ditto. + (build_asm_hash_table): Ditto. + (cgen_set_parse_operand_fn): Prototype definition. + (cgen_init_parse_operand): Ditto. + (hash_insn_array): Ditto. + (hash_insn_list): Ditto. + (build_asm_hash_table): Ditto. + (cgen_asm_lookup_insn): Ditto. + (cgen_parse_keyword): Ditto. + (cgen_parse_signed_integer): Ditto. + (cgen_parse_unsigned_integer): Ditto. + (cgen_parse_address): Ditto. + (cgen_validate_signed_integer): Ditto. + (cgen_validate_unsigned_integer): Ditto. + + * cgen-opc.c (hash_keyword_name): Remove PARAMS macro. + (hash_keyword_value): Ditto. + (build_keyword_hash_tables): Ditto. + (cgen_keyword_lookup_name): Prototype definition. + (cgen_keyword_lookup_value): Ditto. + (cgen_keyword_add): Ditto. + (cgen_keyword_search_init): Ditto. + (cgen_keyword_search_next): Ditto. + (hash_keyword_name): Ditto. + (hash_keyword_value): Ditto. + (build_keyword_hash_tables): Ditto. + (cgen_hw_lookup_by_name): Ditto. + (cgen_hw_lookup_by_num): Ditto. + (cgen_operand_lookup_by_name): Ditto. + (cgen_operand_lookup_by_num): Ditto. + (cgen_insn_count): Ditto. + (cgen_macro_insn_count): Ditto. + (cgen_get_insn_value): Ditto. + (cgen_put_insn_value): Ditto. + (cgen_lookup_insn): Ditto. + (cgen_get_insn_operands): Ditto. + (cgen_lookup_get_insn_operands): Ditto. + (cgen_set_signed_overflow_ok): Ditto. + (cgen_clear_signed_overflow_ok): Ditto. + (cgen_signed_overflow_ok_p): Ditto. + + * cgen-dis.c (hash_insn_array): Remove PARAMS macro. + (hash_insn_list): Ditto. + (build_dis_hash_table): Ditto. + (count_decodable_bits): Ditto. + (add_insn_to_hash_chain): Ditto. + (count_decodable_bits): Prototype definition. + (add_insn_to_hash_chain): Ditto. + (hash_insn_array): Ditto. + (hash_insn_list): Ditto. + (build_dis_hash_table): Ditto. + (cgen_dis_lookup_insn): Ditto. + + * cgen-asm.in (parse_insn_normal): Remove PARAMS macro. + (@arch@_cgen_build_insn_regex): Prototype definition. + (parse_insn_normal): Ditto. + (@arch@_cgen_assemble_insn): Ditto. + (@arch@_cgen_asm_hash_keywords): Ditto. + + * cgen-dis.in (print_normal): Remove PARAMS macro. Use void * + instead of PTR. + (print_address): Ditto. + (print_keyword): Ditto. + (print_insn_normal): Ditto. + (print_insn): Ditto. + (default_print_insn): Ditto. + (read_insn): Ditto. + (print_normal): Prototype definition. Use void * instead of PTR. + (print_address): Ditto. + (print_keyword): Ditto. + (print_insn_normal): Ditto. + (read_insn): Ditto. + (print_insn): Ditto. + (default_print_insn): Ditto. + (print_insn_@arch@): Ditto. + + * cgen-ibld.in (insert_normal): Remove PARAMS macro. + (insn_insn_normal): Ditto. + (extract_normal): Ditto. + (extract_insn_normal): Ditto. + (put_insn_int_value): Ditto. + (insert_1): Ditto. + (fill_cache): Ditto. + (extract_1): Ditto. + (insert_1): Prototype definition. + (insert_normal): Ditto. + (insert_insn_normal): Ditto. + (put_insn_int_value): Ditto. + (fill_cache): Ditto. + (extract_1): Ditto. + (extract_normal): Ditto. + (extract_insn_normal): Ditto. + + * fr30-asm.c: Regenerate. + * fr30-dis.c: Ditto. + * fr30-ibld.c: Ditto. + * frv-asm.c: Ditto. + * frv-dis.c: Ditto. + * frv-ibld.c: Ditto. + * ip2k-asm.c: Ditto. + * ip2k-dis.c: Ditto. + * ip2k-ibld.c: Ditto. + * iq2000-asm.c: Ditto. + * iq2000-dis.c: Ditto. + * iq2000-ibld.c: Ditto. + * m32r-asm.c: Ditto. + * m32r-dis.c: Ditto. + * m32r-ibld.c: Ditto. + * openrisc-asm.c: Ditto. + * openrisc-dis.c: Ditto. + * openrisc-ibld.c: Ditto. + * xstormy16-asm.c: Ditto. + * xstormy16-dis.c: Ditto. + * xstormy16-ibld.c: Ditto. + +2003-08-06 Nick Clifton <nickc@redhat.com> + + * po/fr.po: Updated French translation. + 2003-08-05 Nick Clifton <nickc@redhat.com> * configure.in (ALL_LINGUAS): Add nl. @@ -6,7 +215,7 @@ 2003-07-30 Jason Eckhardt <jle@rice.edu> - * i860-dis.c: Convert to ISO C90. Remove superflous prototypes. + * i860-dis.c: Convert to ISO C90. Remove superflous prototypes. 2003-07-30 Nick Clifton <nickc@redhat.com> @@ -24,8 +233,8 @@ * arm-dis.c (parse_arm_disassembler_option): Do not expect option string to be NUL terminated. - (parse_disassembler_options): Allow options to be space or - comma separated. + (parse_disassembler_options): Allow options to be space or + comma separated. 2003-07-17 Nick Clifton <nickc@redhat.com> diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 7097be0f8dd..6859a9d4c98 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -63,6 +63,7 @@ CFILES = \ d30v-opc.c \ dlx-dis.c \ dis-buf.c \ + dis-init.c \ disassemble.c \ fr30-asm.c \ fr30-desc.c \ @@ -281,7 +282,7 @@ INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFI disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c -libopcodes_la_SOURCES = dis-buf.c disassemble.c +libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c libopcodes_la_DEPENDENCIES = $(OFILES) ../bfd/libbfd.la libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ ../bfd/libbfd.la libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ @@ -306,7 +307,7 @@ libopcodes.a: stamp-lib ; @true POTFILES = $(HFILES) $(CFILES) po/POTFILES.in: @MAINT@ Makefile - for file in $(POTFILES); do echo $$file; done | sort > tmp \ + for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \ && mv tmp $(srcdir)/po/POTFILES.in # We should reconfigure whenever bfd/configure.in changes, because @@ -378,8 +379,8 @@ endif run-cgen: $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ - $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) \ - "$(options)" $(extrafiles) + $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) $(archfile) $(opcfile) \ + "$(options)" "$(extrafiles)" touch stamp-${prefix} .PHONY: run-cgen @@ -395,38 +396,47 @@ run-cgen-all: $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) @true stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc - $(MAKE) run-cgen arch=ip2k prefix=ip2k options= extrafiles= + $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ + archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc - $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst + $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ + archfile=$(CPUDIR)/m32r.cpu opcfile=$(CPUDIR)/m32r.opc extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc - $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= + $(MAKE) run-cgen arch=fr30 prefix=fr30 options= \ + archfile=$(CPUDIR)/fr30.cpu opcfile=$(CPUDIR)/fr30.opc extrafiles= $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) @true -stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc - $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= +# .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so +# copy those file to the regular place. +stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= \ + archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc - $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \ + archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles= $(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) @true stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu - $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= extrafiles= + $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= \ + archfile=$(CPUDIR)/iq2000.cpu opcfile=$(CPUDIR)/iq2000.opc extrafiles= $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc - $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \ + archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles= ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -515,9 +525,9 @@ arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ - opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ - $(INCDIR)/elf/reloc-macros.h + opintl.h $(INCDIR)/safe-ctype.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h @@ -547,6 +557,8 @@ dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h +dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -624,7 +636,7 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ $(INCDIR)/safe-ctype.h sysdep.h config.h $(INCDIR)/getopt.h \ ia64-opc.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \ ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ - ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ../intl/libintl.h + ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index a9875a1e5a6..57aee2dcbb5 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -1,6 +1,6 @@ -# Makefile.in generated automatically by automake 1.4-p5 from Makefile.am +# Makefile.in generated automatically by automake 1.4 from Makefile.am -# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc. +# Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. @@ -174,6 +174,7 @@ CFILES = \ d30v-opc.c \ dlx-dis.c \ dis-buf.c \ + dis-init.c \ disassemble.c \ fr30-asm.c \ fr30-desc.c \ @@ -391,7 +392,7 @@ OFILES = @BFD_MACHINES@ INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl -libopcodes_la_SOURCES = dis-buf.c disassemble.c +libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c libopcodes_la_DEPENDENCIES = $(OFILES) ../bfd/libbfd.la libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ ../bfd/libbfd.la libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ @@ -455,7 +456,7 @@ libopcodes_a_SOURCES = libopcodes.a.c libopcodes_a_OBJECTS = libopcodes.a.$(OBJEXT) LTLIBRARIES = $(bfdlib_LTLIBRARIES) -libopcodes_la_OBJECTS = dis-buf.lo disassemble.lo +libopcodes_la_OBJECTS = dis-buf.lo disassemble.lo dis-init.lo CFLAGS = @CFLAGS@ COMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) @@ -616,7 +617,7 @@ maintainer-clean-recursive: dot_seen=no; \ rev=''; list='$(SUBDIRS)'; for subdir in $$list; do \ rev="$$subdir $$rev"; \ - test "$$subdir" != "." || dot_seen=yes; \ + test "$$subdir" = "." && dot_seen=yes; \ done; \ test "$$dot_seen" = "no" && rev=". $$rev"; \ target=`echo $@ | sed s/-recursive//`; \ @@ -840,7 +841,7 @@ stamp-lib: libopcodes.la libopcodes.a: stamp-lib ; @true po/POTFILES.in: @MAINT@ Makefile - for file in $(POTFILES); do echo $$file; done | sort > tmp \ + for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \ && mv tmp $(srcdir)/po/POTFILES.in # We should reconfigure whenever bfd/configure.in changes, because @@ -874,8 +875,8 @@ uninstall_libopcodes: run-cgen: $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ - $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) \ - "$(options)" $(extrafiles) + $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) $(archfile) $(opcfile) \ + "$(options)" "$(extrafiles)" touch stamp-${prefix} .PHONY: run-cgen @@ -891,38 +892,47 @@ run-cgen-all: $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) @true stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc - $(MAKE) run-cgen arch=ip2k prefix=ip2k options= extrafiles= + $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ + archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc - $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst + $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ + archfile=$(CPUDIR)/m32r.cpu opcfile=$(CPUDIR)/m32r.opc extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc - $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= + $(MAKE) run-cgen arch=fr30 prefix=fr30 options= \ + archfile=$(CPUDIR)/fr30.cpu opcfile=$(CPUDIR)/fr30.opc extrafiles= $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) @true -stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc - $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= +# .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so +# copy those file to the regular place. +stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= \ + archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc - $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \ + archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles= $(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) @true stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu - $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= extrafiles= + $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= \ + archfile=$(CPUDIR)/iq2000.cpu opcfile=$(CPUDIR)/iq2000.opc extrafiles= $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc - $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \ + archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles= ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -1011,9 +1021,9 @@ arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ - opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ - $(INCDIR)/elf/reloc-macros.h + opintl.h $(INCDIR)/safe-ctype.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h @@ -1043,6 +1053,8 @@ dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h +dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -1120,7 +1132,7 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ $(INCDIR)/safe-ctype.h sysdep.h config.h $(INCDIR)/getopt.h \ ia64-opc.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \ ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ - ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ../intl/libintl.h + ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 97ec8423485..ac36e88006b 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -445,9 +445,11 @@ print_insn_arm (pc, info, given) case 'A': func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) + + if ((given & (1 << 24)) != 0) { int offset = given & 0xff; + if (offset) func (stream, ", %s#%d]%s", ((given & 0x00800000) == 0 ? "-" : ""), @@ -459,12 +461,18 @@ print_insn_arm (pc, info, given) else { int offset = given & 0xff; - if (offset) - func (stream, "], %s#%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); + + func (stream, "]"); + + if (given & (1 << 21)) + { + if (offset) + func (stream, ", %s#%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * 4); + } else - func (stream, "]"); + func (stream, ", {%d}", offset); } break; diff --git a/opcodes/cgen-asm.c b/opcodes/cgen-asm.c index c71c70de08e..7231e2d7aed 100644 --- a/opcodes/cgen-asm.c +++ b/opcodes/cgen-asm.c @@ -28,16 +28,14 @@ #include "opcode/cgen.h" #include "opintl.h" -static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static void build_asm_hash_table PARAMS ((CGEN_CPU_DESC)); +static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static void build_asm_hash_table (CGEN_CPU_DESC); /* Set the cgen_parse_operand_fn callback. */ void -cgen_set_parse_operand_fn (cd, fn) - CGEN_CPU_DESC cd; - cgen_parse_operand_fn fn; +cgen_set_parse_operand_fn (CGEN_CPU_DESC cd, cgen_parse_operand_fn fn) { cd->parse_operand_fn = fn; } @@ -45,8 +43,7 @@ cgen_set_parse_operand_fn (cd, fn) /* Called whenever starting to parse an insn. */ void -cgen_init_parse_operand (cd) - CGEN_CPU_DESC cd; +cgen_init_parse_operand (CGEN_CPU_DESC cd) { /* This tells the callback to re-initialize. */ (void) (* cd->parse_operand_fn) @@ -66,13 +63,12 @@ cgen_init_parse_operand (cd) list and we want earlier ones to be prefered. */ static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN *insns; - int count; - int entsize ATTRIBUTE_UNUSED; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; +hash_insn_array (CGEN_CPU_DESC cd, + const CGEN_INSN *insns, + int count, + int entsize ATTRIBUTE_UNUSED, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) { int i; @@ -97,11 +93,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) in a list. */ static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; +hash_insn_list (CGEN_CPU_DESC cd, + const CGEN_INSN_LIST *insns, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) { const CGEN_INSN_LIST *ilist; @@ -123,8 +118,7 @@ hash_insn_list (cd, insns, htable, hentbuf) /* Build the assembler instruction hash table. */ static void -build_asm_hash_table (cd) - CGEN_CPU_DESC cd; +build_asm_hash_table (CGEN_CPU_DESC cd) { int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); CGEN_INSN_TABLE *insn_table = &cd->insn_table; @@ -179,9 +173,7 @@ build_asm_hash_table (cd) /* Return the first entry in the hash list for INSN. */ CGEN_INSN_LIST * -cgen_asm_lookup_insn (cd, insn) - CGEN_CPU_DESC cd; - const char *insn; +cgen_asm_lookup_insn (CGEN_CPU_DESC cd, const char *insn) { unsigned int hash; @@ -201,11 +193,10 @@ cgen_asm_lookup_insn (cd, insn) recording something in the keyword table]. */ const char * -cgen_parse_keyword (cd, strp, keyword_table, valuep) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - const char **strp; - CGEN_KEYWORD *keyword_table; - long *valuep; +cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + CGEN_KEYWORD *keyword_table, + long *valuep) { const CGEN_KEYWORD_ENTRY *ke; char buf[256]; @@ -262,11 +253,10 @@ cgen_parse_keyword (cd, strp, keyword_table, valuep) cgen_parse_address. */ const char * -cgen_parse_signed_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +cgen_parse_signed_integer (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { bfd_vma value; enum cgen_parse_operand_result result; @@ -287,11 +277,10 @@ cgen_parse_signed_integer (cd, strp, opindex, valuep) cgen_parse_address. */ const char * -cgen_parse_unsigned_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +cgen_parse_unsigned_integer (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { bfd_vma value; enum cgen_parse_operand_result result; @@ -309,13 +298,12 @@ cgen_parse_unsigned_integer (cd, strp, opindex, valuep) /* Address parser. */ const char * -cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - int opinfo; - enum cgen_parse_operand_result *resultp; - bfd_vma *valuep; +cgen_parse_address (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int opinfo, + enum cgen_parse_operand_result *resultp, + bfd_vma *valuep) { bfd_vma value; enum cgen_parse_operand_result result_type; @@ -337,8 +325,7 @@ cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep) /* Signed integer validation routine. */ const char * -cgen_validate_signed_integer (value, min, max) - long value, min, max; +cgen_validate_signed_integer (long value, long min, long max) { if (value < min || value > max) { @@ -358,8 +345,9 @@ cgen_validate_signed_integer (value, min, max) cases where min != 0 (and max > LONG_MAX). */ const char * -cgen_validate_unsigned_integer (value, min, max) - unsigned long value, min, max; +cgen_validate_unsigned_integer (unsigned long value, + unsigned long min, + unsigned long max) { if (value < min || value > max) { diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in index 1ea076809b9..420f640ec3b 100644 --- a/opcodes/cgen-asm.in +++ b/opcodes/cgen-asm.in @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -60,8 +60,7 @@ static const char * parse_insn_normal Returns NULL for success, an error message for failure. */ char * -@arch@_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +@arch@_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -184,11 +183,10 @@ char * Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -326,12 +324,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -@arch@_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +@arch@_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -435,9 +432,7 @@ const CGEN_INSN * FIXME: Not currently used. */ void -@arch@_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +@arch@_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c index 881ee1470f3..ca621dec2d3 100644 --- a/opcodes/cgen-dis.c +++ b/opcodes/cgen-dis.c @@ -27,19 +27,18 @@ #include "symcat.h" #include "opcode/cgen.h" -static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static void build_dis_hash_table PARAMS ((CGEN_CPU_DESC)); -static int count_decodable_bits PARAMS ((const CGEN_INSN *)); -static void add_insn_to_hash_chain PARAMS ((CGEN_INSN_LIST *, - const CGEN_INSN *, - CGEN_INSN_LIST **, - unsigned int)); +static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static void build_dis_hash_table (CGEN_CPU_DESC); +static int count_decodable_bits (const CGEN_INSN *); +static void add_insn_to_hash_chain (CGEN_INSN_LIST *, + const CGEN_INSN *, + CGEN_INSN_LIST **, + unsigned int); /* Return the number of decodable bits in this insn. */ static int -count_decodable_bits (insn) - const CGEN_INSN *insn; +count_decodable_bits (const CGEN_INSN *insn) { unsigned mask = CGEN_INSN_BASE_MASK (insn); int bits = 0; @@ -54,11 +53,10 @@ count_decodable_bits (insn) /* Add an instruction to the hash chain. */ static void -add_insn_to_hash_chain (hentbuf, insn, htable, hash) - CGEN_INSN_LIST *hentbuf; - const CGEN_INSN *insn; - CGEN_INSN_LIST **htable; - unsigned int hash; +add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf, + const CGEN_INSN *insn, + CGEN_INSN_LIST **htable, + unsigned int hash) { CGEN_INSN_LIST *current_buf; CGEN_INSN_LIST *previous_buf; @@ -100,13 +98,12 @@ add_insn_to_hash_chain (hentbuf, insn, htable, hash) list and we want earlier ones to be prefered. */ static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN * insns; - int count; - int entsize ATTRIBUTE_UNUSED; - CGEN_INSN_LIST ** htable; - CGEN_INSN_LIST * hentbuf; +hash_insn_array (CGEN_CPU_DESC cd, + const CGEN_INSN * insns, + int count, + int entsize ATTRIBUTE_UNUSED, + CGEN_INSN_LIST ** htable, + CGEN_INSN_LIST * hentbuf) { int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; int i; @@ -141,11 +138,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) in a list. */ static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; +hash_insn_list (CGEN_CPU_DESC cd, + const CGEN_INSN_LIST *insns, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) { int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; const CGEN_INSN_LIST *ilist; @@ -177,8 +173,7 @@ hash_insn_list (cd, insns, htable, hentbuf) /* Build the disassembler instruction hash table. */ static void -build_dis_hash_table (cd) - CGEN_CPU_DESC cd; +build_dis_hash_table (CGEN_CPU_DESC cd) { int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); CGEN_INSN_TABLE *insn_table = & cd->insn_table; @@ -233,10 +228,7 @@ build_dis_hash_table (cd) /* Return the first entry in the hash list for INSN. */ CGEN_INSN_LIST * -cgen_dis_lookup_insn (cd, buf, value) - CGEN_CPU_DESC cd; - const char * buf; - CGEN_INSN_INT value; +cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value) { unsigned int hash; diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index 9203b71d027..1a3c0fa59d6 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -41,34 +41,32 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -88,13 +86,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -118,12 +115,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -137,17 +133,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -179,14 +174,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -210,12 +204,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -320,10 +313,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -362,9 +352,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_@arch@ (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_@arch@ (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in index d2bfd02a91f..316f183c41e 100644 --- a/opcodes/cgen-ibld.in +++ b/opcodes/cgen-ibld.in @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c index 06544ca057d..882b34898be 100644 --- a/opcodes/cgen-opc.c +++ b/opcodes/cgen-opc.c @@ -33,11 +33,11 @@ #endif static unsigned int hash_keyword_name - PARAMS ((const CGEN_KEYWORD *, const char *, int)); + (const CGEN_KEYWORD *, const char *, int); static unsigned int hash_keyword_value - PARAMS ((const CGEN_KEYWORD *, unsigned int)); + (const CGEN_KEYWORD *, unsigned int); static void build_keyword_hash_tables - PARAMS ((CGEN_KEYWORD *)); + (CGEN_KEYWORD *); /* Return number of hash table entries to use for N elements. */ #define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) @@ -46,9 +46,7 @@ static void build_keyword_hash_tables The result is the keyword entry or NULL if not found. */ const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_name (kt, name) - CGEN_KEYWORD *kt; - const char *name; +cgen_keyword_lookup_name (CGEN_KEYWORD *kt, const char *name) { const CGEN_KEYWORD_ENTRY *ke; const char *p,*n; @@ -87,9 +85,7 @@ cgen_keyword_lookup_name (kt, name) The result is the keyword entry or NULL if not found. */ const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_value (kt, value) - CGEN_KEYWORD *kt; - int value; +cgen_keyword_lookup_value (CGEN_KEYWORD *kt, int value) { const CGEN_KEYWORD_ENTRY *ke; @@ -111,9 +107,7 @@ cgen_keyword_lookup_value (kt, value) /* Add an entry to a keyword table. */ void -cgen_keyword_add (kt, ke) - CGEN_KEYWORD *kt; - CGEN_KEYWORD_ENTRY *ke; +cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke) { unsigned int hash; size_t i; @@ -159,9 +153,7 @@ cgen_keyword_add (kt, ke) It is passed to each call to cgen_keyword_search_next. */ CGEN_KEYWORD_SEARCH -cgen_keyword_search_init (kt, spec) - CGEN_KEYWORD *kt; - const char *spec; +cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec) { CGEN_KEYWORD_SEARCH search; @@ -183,8 +175,7 @@ cgen_keyword_search_init (kt, spec) The result is the next entry or NULL if there are no more. */ const CGEN_KEYWORD_ENTRY * -cgen_keyword_search_next (search) - CGEN_KEYWORD_SEARCH *search; +cgen_keyword_search_next (CGEN_KEYWORD_SEARCH *search) { /* Has search finished? */ if (search->current_hash == search->table->hash_table_size) @@ -218,10 +209,9 @@ cgen_keyword_search_next (search) If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ static unsigned int -hash_keyword_name (kt, name, case_sensitive_p) - const CGEN_KEYWORD *kt; - const char *name; - int case_sensitive_p; +hash_keyword_name (const CGEN_KEYWORD *kt, + const char *name, + int case_sensitive_p) { unsigned int hash; @@ -237,9 +227,7 @@ hash_keyword_name (kt, name, case_sensitive_p) /* Return first entry in hash chain for VALUE. */ static unsigned int -hash_keyword_value (kt, value) - const CGEN_KEYWORD *kt; - unsigned int value; +hash_keyword_value (const CGEN_KEYWORD *kt, unsigned int value) { return value % kt->hash_table_size; } @@ -249,8 +237,7 @@ hash_keyword_value (kt, value) we're using the disassembler, but we keep things simple. */ static void -build_keyword_hash_tables (kt) - CGEN_KEYWORD *kt; +build_keyword_hash_tables (CGEN_KEYWORD *kt) { int i; /* Use the number of compiled in entries as an estimate for the @@ -278,9 +265,7 @@ build_keyword_hash_tables (kt) mach/isa. */ const CGEN_HW_ENTRY * -cgen_hw_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; +cgen_hw_lookup_by_name (CGEN_CPU_DESC cd, const char *name) { unsigned int i; const CGEN_HW_ENTRY **hw = cd->hw_table.entries; @@ -298,9 +283,7 @@ cgen_hw_lookup_by_name (cd, name) Returns NULL if HWNUM is not supported by the currently selected mach. */ const CGEN_HW_ENTRY * -cgen_hw_lookup_by_num (cd, hwnum) - CGEN_CPU_DESC cd; - unsigned int hwnum; +cgen_hw_lookup_by_num (CGEN_CPU_DESC cd, unsigned int hwnum) { unsigned int i; const CGEN_HW_ENTRY **hw = cd->hw_table.entries; @@ -320,9 +303,7 @@ cgen_hw_lookup_by_num (cd, hwnum) mach/isa. */ const CGEN_OPERAND * -cgen_operand_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; +cgen_operand_lookup_by_name (CGEN_CPU_DESC cd, const char *name) { unsigned int i; const CGEN_OPERAND **op = cd->operand_table.entries; @@ -341,9 +322,7 @@ cgen_operand_lookup_by_name (cd, name) mach/isa. */ const CGEN_OPERAND * -cgen_operand_lookup_by_num (cd, opnum) - CGEN_CPU_DESC cd; - int opnum; +cgen_operand_lookup_by_num (CGEN_CPU_DESC cd, int opnum) { return cd->operand_table.entries[opnum]; } @@ -353,8 +332,7 @@ cgen_operand_lookup_by_num (cd, opnum) /* Return number of instructions. This includes any added at runtime. */ int -cgen_insn_count (cd) - CGEN_CPU_DESC cd; +cgen_insn_count (CGEN_CPU_DESC cd) { int count = cd->insn_table.num_init_entries; CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries; @@ -369,8 +347,7 @@ cgen_insn_count (cd) This includes any added at runtime. */ int -cgen_macro_insn_count (cd) - CGEN_CPU_DESC cd; +cgen_macro_insn_count (CGEN_CPU_DESC cd) { int count = cd->macro_insn_table.num_init_entries; CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries; @@ -384,10 +361,7 @@ cgen_macro_insn_count (cd) /* Cover function to read and properly byteswap an insn value. */ CGEN_INSN_INT -cgen_get_insn_value (cd, buf, length) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; +cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) { int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; @@ -423,11 +397,10 @@ cgen_get_insn_value (cd, buf, length) /* Cover function to store an insn value properly byteswapped. */ void -cgen_put_insn_value (cd, buf, length, value) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; - CGEN_INSN_INT value; +cgen_put_insn_value (CGEN_CPU_DESC cd, + unsigned char *buf, + int length, + CGEN_INSN_INT value) { int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; @@ -472,16 +445,14 @@ cgen_put_insn_value (cd, buf, length, value) /* ??? Will need to be revisited for VLIW architectures. */ const CGEN_INSN * -cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields, - alias_p) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - CGEN_FIELDS *fields; - int alias_p; +cgen_lookup_insn (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_INSN_INT insn_int_value, + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value, + int length, + CGEN_FIELDS *fields, + int alias_p) { unsigned char *buf; CGEN_INSN_INT base_insn; @@ -571,11 +542,10 @@ cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields, in. */ void -cgen_get_insn_operands (cd, insn, fields, indices) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const CGEN_FIELDS *fields; - int *indices; +cgen_get_insn_operands (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const CGEN_FIELDS *fields, + int *indices) { const CGEN_OPINST *opinst; int i; @@ -603,16 +573,14 @@ cgen_get_insn_operands (cd, insn, fields, indices) recognized. */ const CGEN_INSN * -cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value, - length, indices, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - int *indices; - CGEN_FIELDS *fields; +cgen_lookup_get_insn_operands (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_INSN_INT insn_int_value, + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value, + int length, + int *indices, + CGEN_FIELDS *fields) { /* Pass non-zero for ALIAS_P only if INSN != NULL. If INSN == NULL, we want a real insn. */ @@ -627,24 +595,21 @@ cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value, /* Allow signed overflow of instruction fields. */ void -cgen_set_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; +cgen_set_signed_overflow_ok (CGEN_CPU_DESC cd) { cd->signed_overflow_ok_p = 1; } /* Generate an error message if a signed field in an instruction overflows. */ void -cgen_clear_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; +cgen_clear_signed_overflow_ok (CGEN_CPU_DESC cd) { cd->signed_overflow_ok_p = 0; } /* Will an error message be generated if a signed field in an instruction overflows ? */ unsigned int -cgen_signed_overflow_ok_p (cd) - CGEN_CPU_DESC cd; +cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd) { return cd->signed_overflow_ok_p; } diff --git a/opcodes/cgen.sh b/opcodes/cgen.sh index a9483bdb972..5a340b6e527 100644 --- a/opcodes/cgen.sh +++ b/opcodes/cgen.sh @@ -23,11 +23,19 @@ # arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch]. # # Usage: -# cgen.sh action srcdir cgen cgendir cgenflags arch prefix options +# cgen.sh action srcdir cgen cgendir cgenflags arch prefix \ +# arch-file opc-file options [extrafiles] # # ACTION is currently always "opcodes". It exists to be consistent with the # simulator. -# OPTIONS is comma separated list of options: +# ARCH is the name of the architecture. +# It is substituted into @arch@ and @ARCH@ in the generated files. +# PREFIX is both the generated file prefix and is substituted into +# @prefix@ in the generated files. +# ARCH-FILE is the name of the .cpu file (including path). +# OPC-FILE is the name of the .opc file (including path). +# OPTIONS is comma separated list of options (???). +# EXTRAFILES is a space separated list (1 arg still) of extra files to build: # - opinst - arch-opinst.c is being made, causes semantic analysis # # We store the generated files in the source directory until we decide to @@ -44,11 +52,13 @@ cgendir=$4 cgenflags=$5 arch=$6 prefix=$7 -options=$8 +archfile=$8 +opcfile=$9 +shift ; options=$9 # List of extra files to build. # Values: opinst (only 1 extra file at present) -extrafiles=$9 +shift ; extrafiles=$9 rootdir=${srcdir}/.. @@ -88,7 +98,8 @@ opcodes) ${cgenflags} \ -f "${options}" \ -m all \ - -a ${arch} \ + -a ${archfile} \ + -OPC ${opcfile} \ -H tmp-desc.h1 \ -C tmp-desc.c1 \ -O tmp-opc.h1 \ diff --git a/opcodes/dep-in.sed b/opcodes/dep-in.sed index e373d4ca84e..94da2adc340 100644 --- a/opcodes/dep-in.sed +++ b/opcodes/dep-in.sed @@ -10,6 +10,7 @@ s!@TOPDIR@/include!$(INCDIR)!g s!@BFDDIR@!$(BFDDIR)!g s!@TOPDIR@/bfd!$(BFDDIR)!g s!@SRCDIR@/!!g +s! \.\./intl/libintl\.h!!g s/\\\n */ /g diff --git a/opcodes/dis-init.c b/opcodes/dis-init.c new file mode 100644 index 00000000000..4c3e36e6e8c --- /dev/null +++ b/opcodes/dis-init.c @@ -0,0 +1,41 @@ +/* Initialize "struct disassemble_info". + + Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "bfd.h" + +void +init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func) +{ + memset (info, 0, sizeof (*info)); + info->flavour = bfd_target_unknown_flavour; + info->arch = bfd_arch_unknown; + info->endian = BFD_ENDIAN_UNKNOWN; + info->octets_per_byte = 1; + info->fprintf_func = fprintf_func; + info->stream = stream; + info->read_memory_func = buffer_read_memory; + info->memory_error_func = perror_memory; + info->print_address_func = generic_print_address; + info->symbol_at_address_func = generic_symbol_at_address; + info->display_endian = BFD_ENDIAN_UNKNOWN; +} + diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c index 8e7c7b80975..f1c18a16bd5 100644 --- a/opcodes/fr30-asm.c +++ b/opcodes/fr30-asm.c @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -356,8 +356,7 @@ fr30_cgen_init_asm (cd) Returns NULL for success, an error message for failure. */ char * -fr30_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +fr30_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -480,11 +479,10 @@ fr30_cgen_build_insn_regex (insn) Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -622,12 +620,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +fr30_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -731,9 +728,7 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) FIXME: Not currently used. */ void -fr30_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +fr30_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index ef7b37a5a24..0b99a4af395 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ @@ -343,13 +342,12 @@ fr30_cgen_init_dis (cd) /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -369,13 +367,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -399,12 +396,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -418,17 +414,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -460,14 +455,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -491,12 +485,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -601,10 +594,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -643,9 +633,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_fr30 (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_fr30 (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c index 96374619e6c..b01e483e323 100644 --- a/opcodes/fr30-ibld.c +++ b/opcodes/fr30-ibld.c @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c index 0e3d8ddf669..1d24b28d405 100644 --- a/opcodes/frv-asm.c +++ b/opcodes/frv-asm.c @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -66,6 +66,12 @@ static const char * parse_u12 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); static const char * parse_even_register PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); +static const char * parse_A0 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_A1 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_A + PARAMS ((CGEN_CPU_DESC, const char **, int, long *, long)); static const char * parse_ulo16 (cd, strp, opindex, valuep) @@ -349,6 +355,49 @@ parse_u12 (cd, strp, opindex, valuep) } static const char * +parse_A (cd, strp, opindex, valuep, A) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; + long A; +{ + const char *errmsg; + + if (**strp == '#') + ++*strp; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + if (errmsg) + return errmsg; + + if (*valuep != A) + return "Value of A operand must be 0 or 1"; + + return NULL; +} + +static const char * +parse_A0 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + return parse_A (cd, strp, opindex, valuep, 0); +} + +static const char * +parse_A1 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + return parse_A (cd, strp, opindex, valuep, 1); +} + +static const char * parse_even_register (cd, strP, tableP, valueP) CGEN_CPU_DESC cd; const char ** strP; @@ -399,8 +448,11 @@ frv_cgen_parse_operand (cd, opindex, strp, fields) switch (opindex) { - case FRV_OPERAND_A : - errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_A, &fields->f_A); + case FRV_OPERAND_A0 : + errmsg = parse_A0 (cd, strp, FRV_OPERAND_A0, &fields->f_A); + break; + case FRV_OPERAND_A1 : + errmsg = parse_A1 (cd, strp, FRV_OPERAND_A1, &fields->f_A); break; case FRV_OPERAND_ACC40SI : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Si); @@ -659,8 +711,7 @@ frv_cgen_init_asm (cd) Returns NULL for success, an error message for failure. */ char * -frv_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +frv_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -783,11 +834,10 @@ frv_cgen_build_insn_regex (insn) Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -925,12 +975,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -frv_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +frv_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -1034,9 +1083,7 @@ frv_cgen_assemble_insn (cd, str, fields, buf, errmsg) FIXME: Not currently used. */ void -frv_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +frv_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index 97d49b3077b..1e660261c85 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -68,15 +68,23 @@ static const CGEN_ATTR_ENTRY UNIT_attr[] = { "I0", UNIT_I0 }, { "I1", UNIT_I1 }, { "I01", UNIT_I01 }, + { "IALL", UNIT_IALL }, { "FM0", UNIT_FM0 }, { "FM1", UNIT_FM1 }, { "FM01", UNIT_FM01 }, + { "FMALL", UNIT_FMALL }, + { "FMLOW", UNIT_FMLOW }, { "B0", UNIT_B0 }, { "B1", UNIT_B1 }, { "B01", UNIT_B01 }, { "C", UNIT_C }, { "MULT_DIV", UNIT_MULT_DIV }, { "LOAD", UNIT_LOAD }, + { "STORE", UNIT_STORE }, + { "SCAN", UNIT_SCAN }, + { "DCPL", UNIT_DCPL }, + { "MDUALACC", UNIT_MDUALACC }, + { "MCLRACC_1", UNIT_MCLRACC_1 }, { "NUM_UNITS", UNIT_NUM_UNITS }, { 0, 0 } }; @@ -2157,10 +2165,6 @@ const CGEN_OPERAND frv_cgen_operand_table[] = { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, -/* A: all accumulator indicator */ - { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* ae: all entries indicator */ { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } }, @@ -2173,6 +2177,14 @@ const CGEN_OPERAND frv_cgen_operand_table[] = { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24, { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, +/* A0: A==0 operand of mclracc */ + { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, + { 0, { (1<<MACH_BASE) } } }, +/* A1: A==1 operand of mclracc */ + { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, + { 0, { (1<<MACH_BASE) } } }, /* FRintieven: (even) source register 1 */ { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, @@ -2272,32 +2284,32 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* add$pack $GRi,$GRj,$GRk */ { FRV_INSN_ADD, "add", "add", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sub$pack $GRi,$GRj,$GRk */ { FRV_INSN_SUB, "sub", "sub", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* and$pack $GRi,$GRj,$GRk */ { FRV_INSN_AND, "and", "and", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* or$pack $GRi,$GRj,$GRk */ { FRV_INSN_OR, "or", "or", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* xor$pack $GRi,$GRj,$GRk */ { FRV_INSN_XOR, "xor", "xor", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* not$pack $GRj,$GRk */ { FRV_INSN_NOT, "not", "not", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sdiv$pack $GRi,$GRj,$GRk */ { @@ -2332,52 +2344,52 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* sll$pack $GRi,$GRj,$GRk */ { FRV_INSN_SLL, "sll", "sll", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* srl$pack $GRi,$GRj,$GRk */ { FRV_INSN_SRL, "srl", "srl", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sra$pack $GRi,$GRj,$GRk */ { FRV_INSN_SRA, "sra", "sra", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* scan$pack $GRi,$GRj,$GRk */ { FRV_INSN_SCAN, "scan", "scan", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CADD, "cadd", "cadd", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSUB, "csub", "csub", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CAND, "cand", "cand", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_COR, "cor", "cor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CXOR, "cxor", "cxor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cnot$pack $GRj,$GRk,$CCi,$cond */ { FRV_INSN_CNOT, "cnot", "cnot", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ { @@ -2397,62 +2409,62 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSLL, "csll", "csll", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRL, "csrl", "csrl", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRA, "csra", "csra", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSCAN, "cscan", "cscan", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ADDCC, "addcc", "addcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SUBCC, "subcc", "subcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ANDCC, "andcc", "andcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ORCC, "orcc", "orcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_XORCC, "xorcc", "xorcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SLLCC, "sllcc", "sllcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SRLCC, "srlcc", "srlcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SRACC, "sracc", "sracc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ { @@ -2467,12 +2479,12 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CADDCC, "caddcc", "caddcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSUBCC, "csubcc", "csubcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ { @@ -2482,77 +2494,77 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CANDCC, "candcc", "candcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CORCC, "corcc", "corcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSLLCC, "csllcc", "csllcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRACC, "csracc", "csracc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ADDX, "addx", "addx", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SUBX, "subx", "subx", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ADDXCC, "addxcc", "addxcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SUBXCC, "subxcc", "subxcc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* addi$pack $GRi,$s12,$GRk */ { FRV_INSN_ADDI, "addi", "addi", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* subi$pack $GRi,$s12,$GRk */ { FRV_INSN_SUBI, "subi", "subi", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* andi$pack $GRi,$s12,$GRk */ { FRV_INSN_ANDI, "andi", "andi", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* ori$pack $GRi,$s12,$GRk */ { FRV_INSN_ORI, "ori", "ori", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* xori$pack $GRi,$s12,$GRk */ { FRV_INSN_XORI, "xori", "xori", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sdivi$pack $GRi,$s12,$GRk */ { @@ -2587,47 +2599,47 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* slli$pack $GRi,$s12,$GRk */ { FRV_INSN_SLLI, "slli", "slli", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* srli$pack $GRi,$s12,$GRk */ { FRV_INSN_SRLI, "srli", "srli", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* srai$pack $GRi,$s12,$GRk */ { FRV_INSN_SRAI, "srai", "srai", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* scani$pack $GRi,$s12,$GRk */ { FRV_INSN_SCANI, "scani", "scani", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ADDICC, "addicc", "addicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SUBICC, "subicc", "subicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ANDICC, "andicc", "andicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ORICC, "oricc", "oricc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_XORICC, "xoricc", "xoricc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ { @@ -2642,62 +2654,62 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SLLICC, "sllicc", "sllicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SRLICC, "srlicc", "srlicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SRAICC, "sraicc", "sraicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ADDXI, "addxi", "addxi", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SUBXI, "subxi", "subxi", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ADDXICC, "addxicc", "addxicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SUBXICC, "subxicc", "subxicc", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cmpb$pack $GRi,$GRj,$ICCi_1 */ { FRV_INSN_CMPB, "cmpb", "cmpb", 32, - { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE } } }, /* cmpba$pack $GRi,$GRj,$ICCi_1 */ { FRV_INSN_CMPBA, "cmpba", "cmpba", 32, - { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE } } }, /* setlo$pack $ulo16,$GRklo */ { FRV_INSN_SETLO, "setlo", "setlo", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* sethi$pack $uhi16,$GRkhi */ { FRV_INSN_SETHI, "sethi", "sethi", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* setlos$pack $slo16,$GRk */ { FRV_INSN_SETLOS, "setlos", "setlos", 32, - { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* ldsb$pack @($GRi,$GRj),$GRk */ { @@ -3092,182 +3104,182 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* stb$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STB, "stb", "stb", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* sth$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STH, "sth", "sth", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* st$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_ST, "st", "st", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stbf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STBF, "stbf", "stbf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* sthf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STHF, "sthf", "sthf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STF, "stf", "stf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stc$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STC, "stc", "stc", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* rstb$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_RSTB, "rstb", "rstb", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rsth$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_RSTH, "rsth", "rsth", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rst$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_RST, "rst", "rst", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rstbf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_RSTBF, "rstbf", "rstbf", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rsthf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_RSTHF, "rsthf", "rsthf", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rstf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_RSTF, "rstf", "rstf", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* std$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STD, "std", "std", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stdf$pack $FRk,@($GRi,$GRj) */ { FRV_INSN_STDF, "stdf", "stdf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stdc$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STDC, "stdc", "stdc", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* rstd$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_RSTD, "rstd", "rstd", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rstdf$pack $FRk,@($GRi,$GRj) */ { FRV_INSN_RSTDF, "rstdf", "rstdf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* stq$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STQ, "stq", "stq", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* stqf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STQF, "stqf", "stqf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* stqc$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STQC, "stqc", "stqc", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rstq$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_RSTQ, "rstq", "rstq", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* rstqf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_RSTQF, "rstqf", "rstqf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* stbu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STBU, "stbu", "stbu", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* sthu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STHU, "sthu", "sthu", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STU, "stu", "stu", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stbfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STBFU, "stbfu", "stbfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* sthfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STHFU, "sthfu", "sthfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STFU, "stfu", "stfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stcu$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STCU, "stcu", "stcu", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stdu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STDU, "stdu", "stdu", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stdfu$pack $FRk,@($GRi,$GRj) */ { FRV_INSN_STDFU, "stdfu", "stdfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stdcu$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STDCU, "stdcu", "stdcu", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stqu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STQU, "stqu", "stqu", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* stqfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STQFU, "stqfu", "stqfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* stqcu$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STQCU, "stqcu", "stqcu", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { @@ -3382,137 +3394,137 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTB, "cstb", "cstb", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTH, "csth", "csth", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CST, "cst", "cst", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTBF, "cstbf", "cstbf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTHF, "csthf", "csthf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTF, "cstf", "cstf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTD, "cstd", "cstd", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTDF, "cstdf", "cstdf", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTQ, "cstq", "cstq", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTBU, "cstbu", "cstbu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTHU, "csthu", "csthu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTU, "cstu", "cstu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTHFU, "csthfu", "csthfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTFU, "cstfu", "cstfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTDU, "cstdu", "cstdu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stbi$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STBI, "stbi", "stbi", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* sthi$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STHI, "sthi", "sthi", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* sti$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STI, "sti", "sti", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stbfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STBFI, "stbfi", "stbfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* sthfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STHFI, "sthfi", "sthfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STFI, "stfi", "stfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stdi$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STDI, "stdi", "stdi", 32, - { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stdfi$pack $FRk,@($GRi,$d12) */ { FRV_INSN_STDFI, "stdfi", "stdfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } }, /* stqi$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STQI, "stqi", "stqi", 32, - { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* stqfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STQFI, "stqfi", "stqfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } }, /* swap$pack @($GRi,$GRj),$GRk */ { @@ -4877,7 +4889,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* dcpl$pack $GRi,$GRj,$lock */ { FRV_INSN_DCPL, "dcpl", "dcpl", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } }, /* icul$pack $GRi */ { @@ -4952,62 +4964,62 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* fitos$pack $FRintj,$FRk */ { FRV_INSN_FITOS, "fitos", "fitos", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fstoi$pack $FRj,$FRintk */ { FRV_INSN_FSTOI, "fstoi", "fstoi", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fitod$pack $FRintj,$FRdoublek */ { FRV_INSN_FITOD, "fitod", "fitod", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fdtoi$pack $FRdoublej,$FRintk */ { FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fditos$pack $FRintj,$FRk */ { FRV_INSN_FDITOS, "fditos", "fditos", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fdstoi$pack $FRj,$FRintk */ { FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* nfditos$pack $FRintj,$FRk */ { FRV_INSN_NFDITOS, "nfditos", "nfditos", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* nfdstoi$pack $FRj,$FRintk */ { FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* cfitos$pack $FRintj,$FRk,$CCi,$cond */ { FRV_INSN_CFITOS, "cfitos", "cfitos", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */ { FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* nfitos$pack $FRintj,$FRk */ { FRV_INSN_NFITOS, "nfitos", "nfitos", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* nfstoi$pack $FRj,$FRintk */ { FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fmovs$pack $FRj,$FRk */ { @@ -5022,7 +5034,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* fdmovs$pack $FRj,$FRk */ { FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* cfmovs$pack $FRj,$FRk,$CCi,$cond */ { @@ -5032,42 +5044,42 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* fnegs$pack $FRj,$FRk */ { FRV_INSN_FNEGS, "fnegs", "fnegs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fnegd$pack $FRdoublej,$FRdoublek */ { FRV_INSN_FNEGD, "fnegd", "fnegd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fdnegs$pack $FRj,$FRk */ { FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* cfnegs$pack $FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fabss$pack $FRj,$FRk */ { FRV_INSN_FABSS, "fabss", "fabss", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fabsd$pack $FRdoublej,$FRdoublek */ { FRV_INSN_FABSD, "fabsd", "fabsd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fdabss$pack $FRj,$FRk */ { FRV_INSN_FDABSS, "fdabss", "fdabss", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* cfabss$pack $FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFABSS, "cfabss", "cfabss", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } }, /* fsqrts$pack $FRj,$FRk */ { @@ -5102,12 +5114,12 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* fadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_FADDS, "fadds", "fadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* fsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FSUBS, "fsubs", "fsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* fmuls$pack $FRi,$FRj,$FRk */ { @@ -5122,32 +5134,32 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FADDD, "faddd", "faddd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FSUBD, "fsubd", "fsubd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FMULD, "fmuld", "fmuld", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } } }, /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FDIVD, "fdivd", "fdivd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } }, /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFADDS, "cfadds", "cfadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */ { @@ -5162,12 +5174,12 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* nfadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFADDS, "nfadds", "nfadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* nfsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* nfmuls$pack $FRi,$FRj,$FRk */ { @@ -5182,72 +5194,72 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* fcmps$pack $FRi,$FRj,$FCCi_2 */ { FRV_INSN_FCMPS, "fcmps", "fcmps", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */ { FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */ { FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } }, /* fdcmps$pack $FRi,$FRj,$FCCi_2 */ { FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } }, /* fmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMADDS, "fmadds", "fmadds", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* fmsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* fdmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* nfdmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* nfmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* nfmsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } }, /* fmas$pack $FRi,$FRj,$FRk */ { @@ -5377,72 +5389,72 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* mhsetlos$pack $u12,$FRklo */ { FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mhsethis$pack $u12,$FRkhi */ { FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mhdsets$pack $u12,$FRintk */ { FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mhsetloh$pack $s5,$FRklo */ { FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mhsethih$pack $s5,$FRkhi */ { FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mhdseth$pack $s5,$FRintk */ { FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mand$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MAND, "mand", "mand", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mor$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MOR, "mor", "mor", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mxor$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MXOR, "mxor", "mxor", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMAND, "cmand", "cmand", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMOR, "cmor", "cmor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMXOR, "cmxor", "cmxor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mnot$pack $FRintj,$FRintk */ { FRV_INSN_MNOT, "mnot", "mnot", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMNOT, "cmnot", "cmnot", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mrotli$pack $FRinti,$u6,$FRintk */ { @@ -5487,12 +5499,12 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ { FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* maveh$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MAVEH, "maveh", "maveh", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* msllhi$pack $FRinti,$u6,$FRintk */ { @@ -5512,342 +5524,342 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* mdrotli$pack $FRintieven,$s6,$FRintkeven */ { FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* mcplhi$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* mcpli$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MCPLI, "mcpli", "mcpli", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* msaths$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSATHS, "msaths", "msaths", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* msathu$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSATHU, "msathu", "msathu", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mcmpsh$pack $FRinti,$FRintj,$FCCk */ { FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mcmpuh$pack $FRinti,$FRintj,$FCCk */ { FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mabshs$pack $FRintj,$FRintk */ { FRV_INSN_MABSHS, "mabshs", "mabshs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* maddhss$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MADDHSS, "maddhss", "maddhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* maddhus$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MADDHUS, "maddhus", "maddhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* msubhss$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* msubhus$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, /* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, /* maddaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* msubaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mdaddaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* mdsubaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* masaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MASACCS, "masaccs", "masaccs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } }, /* mdasaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMACHS, "mmachs", "mmachs", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */ { FRV_INSN_MMACHU, "mmachu", "mmachu", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */ { FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ { FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ { FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ { FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32, - { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, /* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, /* mexpdhw$pack $FRinti,$u6,$FRintk */ { @@ -5919,10 +5931,20 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32, { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } } }, -/* mclracc$pack $ACC40Sk,$A */ +/* mnop$pack */ + { + FRV_INSN_MNOP, "mnop", "mnop", 32, + { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mclracc$pack $ACC40Sk,$A0 */ + { + FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } } + }, +/* mclracc$pack $ACC40Sk,$A1 */ { - FRV_INSN_MCLRACC, "mclracc", "mclracc", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } } + FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32, + { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR500_MAJOR_M_6 } } }, /* mrdacc$pack $ACC40Si,$FRintk */ { @@ -5957,7 +5979,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* fnop$pack */ { FRV_INSN_FNOP, "fnop", "fnop", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } } + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } } }, }; diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h index a169e7a6092..5e6b061d412 100644 --- a/opcodes/frv-desc.h +++ b/opcodes/frv-desc.h @@ -541,9 +541,11 @@ typedef enum isa_attr { /* Enum declaration for parallel execution pipeline selection. */ typedef enum unit_attr { UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01 - , UNIT_FM0, UNIT_FM1, UNIT_FM01, UNIT_B0 - , UNIT_B1, UNIT_B01, UNIT_C, UNIT_MULT_DIV - , UNIT_LOAD, UNIT_NUM_UNITS + , UNIT_IALL, UNIT_FM0, UNIT_FM1, UNIT_FM01 + , UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1 + , UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_LOAD + , UNIT_STORE, UNIT_SCAN, UNIT_DCPL, UNIT_MDUALACC + , UNIT_MCLRACC_1, UNIT_NUM_UNITS } UNIT_ATTR; /* Enum declaration for fr400 major insn categories. */ @@ -676,17 +678,17 @@ typedef enum cgen_operand_type { , FRV_OPERAND_U16, FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1 , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI - , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE - , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN - , FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12, FRV_OPERAND_U12 - , FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16 - , FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET - , FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT - , FRV_OPERAND_MAX + , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16 + , FRV_OPERAND_LABEL24, FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN + , FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12 + , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16 + , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS + , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA + , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS 80 +#define MAX_OPERANDS 81 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 8 diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index dfe053d5c15..b0f51bce0ab 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ @@ -152,8 +151,11 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) switch (opindex) { - case FRV_OPERAND_A : - print_normal (cd, info, fields->f_A, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + case FRV_OPERAND_A0 : + print_normal (cd, info, fields->f_A, 0, pc, length); + break; + case FRV_OPERAND_A1 : + print_normal (cd, info, fields->f_A, 0, pc, length); break; case FRV_OPERAND_ACC40SI : print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0); @@ -394,13 +396,12 @@ frv_cgen_init_dis (cd) /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -420,13 +421,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -450,12 +450,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -469,17 +468,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -511,14 +509,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -542,12 +539,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -652,10 +648,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -694,9 +687,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_frv (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_frv (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c index bac1837e1be..565f4f49a0e 100644 --- a/opcodes/frv-ibld.c +++ b/opcodes/frv-ibld.c @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; @@ -569,7 +571,10 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc) switch (opindex) { - case FRV_OPERAND_A : + case FRV_OPERAND_A0 : + errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_A1 : errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer); break; case FRV_OPERAND_ACC40SI : @@ -868,7 +873,10 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) switch (opindex) { - case FRV_OPERAND_A : + case FRV_OPERAND_A0 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A); + break; + case FRV_OPERAND_A1 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A); break; case FRV_OPERAND_ACC40SI : @@ -1156,7 +1164,10 @@ frv_cgen_get_int_operand (cd, opindex, fields) switch (opindex) { - case FRV_OPERAND_A : + case FRV_OPERAND_A0 : + value = fields->f_A; + break; + case FRV_OPERAND_A1 : value = fields->f_A; break; case FRV_OPERAND_ACC40SI : @@ -1390,7 +1401,10 @@ frv_cgen_get_vma_operand (cd, opindex, fields) switch (opindex) { - case FRV_OPERAND_A : + case FRV_OPERAND_A0 : + value = fields->f_A; + break; + case FRV_OPERAND_A1 : value = fields->f_A; break; case FRV_OPERAND_ACC40SI : @@ -1633,7 +1647,10 @@ frv_cgen_set_int_operand (cd, opindex, fields, value) { switch (opindex) { - case FRV_OPERAND_A : + case FRV_OPERAND_A0 : + fields->f_A = value; + break; + case FRV_OPERAND_A1 : fields->f_A = value; break; case FRV_OPERAND_ACC40SI : @@ -1864,7 +1881,10 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value) { switch (opindex) { - case FRV_OPERAND_A : + case FRV_OPERAND_A0 : + fields->f_A = value; + break; + case FRV_OPERAND_A1 : fields->f_A = value; break; case FRV_OPERAND_ACC40SI : diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index de27a43f5a0..7143a0e7c01 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -141,7 +141,7 @@ frv_is_media_insn (const CGEN_INSN *insn) /* This table represents the allowable packing for vliw insns for the fr400. The fr400 has only 2 vliw slots. Represent this by not allowing any insns - in slots 2 and 3. + in the extra slots. Subsets of any given row are also allowed. */ static VLIW_COMBO fr400_allowed_vliw[] = { @@ -184,15 +184,23 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = /* I0 */ UNIT_I0, /* I1 */ UNIT_I1, /* I01 */ UNIT_I01, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ /* FM0 */ UNIT_FM0, /* FM1 */ UNIT_FM1, /* FM01 */ UNIT_FM01, +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ /* B0 */ UNIT_B0, /* branches only in B0 unit. */ /* B1 */ UNIT_B0, /* B01 */ UNIT_B0, /* C */ UNIT_C, -/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ -/* LOAD */ UNIT_I0 /* load only in I0 unit. */ +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* LOAD */ UNIT_I0, /* load only in I0 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ +/* DCPL */ UNIT_C, /* dcpl only in C unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ }; static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = @@ -202,15 +210,23 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = /* I0 */ UNIT_I0, /* I1 */ UNIT_I1, /* I01 */ UNIT_I01, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ /* FM0 */ UNIT_FM0, /* FM1 */ UNIT_FM1, /* FM01 */ UNIT_FM01, +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ /* B0 */ UNIT_B0, /* B1 */ UNIT_B1, /* B01 */ UNIT_B01, /* C */ UNIT_C, /* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ -/* LOAD */ UNIT_I01 /* load in I0 or I1 unit. */ +/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */ +/* DCPL */ UNIT_C, /* dcpl only in C unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; void @@ -493,10 +509,15 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) if (unit == UNIT_NIL) abort (); /* no UNIT specified for this insn in frv.cpu */ - if (vliw->mach == bfd_mach_fr400) - major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); - else - major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); + switch (vliw->mach) + { + case bfd_mach_fr400: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); + break; + default: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); + break; + } if (index <= 0) { @@ -1133,8 +1154,12 @@ static const CGEN_IFMT ifmt_cmbtohe = { 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; -static const CGEN_IFMT ifmt_mclracc = { - 32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +static const CGEN_IFMT ifmt_mnop = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mclracc_0 = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } }; static const CGEN_IFMT ifmt_mrdacc = { @@ -5560,11 +5585,23 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmbtohe, { 0x1dc0080 } }, -/* mclracc$pack $ACC40Sk,$A */ +/* mnop$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_mnop, { 0x7fee0ec0 } + }, +/* mclracc$pack $ACC40Sk,$A0 */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A), 0 } }, - & ifmt_mclracc, { 0x1ec0ec0 } + { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A0), 0 } }, + & ifmt_mclracc_0, { 0x1ec0ec0 } + }, +/* mclracc$pack $ACC40Sk,$A1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A1), 0 } }, + & ifmt_mclracc_0, { 0x1ee0ec0 } }, /* mrdacc$pack $ACC40Si,$FRintk */ { @@ -5626,10 +5663,6 @@ static const CGEN_IFMT ifmt_nop = { 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } }; -static const CGEN_IFMT ifmt_mnop = { - 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } -}; - static const CGEN_IFMT ifmt_ret = { 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } }; @@ -5678,12 +5711,7 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] = /* nop$pack */ { -1, "nop", "nop", 32, - { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } - }, -/* mnop$pack */ - { - -1, "mnop", "mnop", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } } + { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* ret$pack */ { @@ -5693,27 +5721,27 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] = /* cmp$pack $GRi,$GRj,$ICCi_1 */ { -1, "cmp", "cmp", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cmpi$pack $GRi,$s10,$ICCi_1 */ { -1, "cmpi", "cmpi", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* ccmp$pack $GRi,$GRj,$CCi,$cond */ { -1, "ccmp", "ccmp", 32, - { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* mov$pack $GRi,$GRk */ { -1, "mov", "mov", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, /* cmov$pack $GRi,$GRk,$CCi,$cond */ { -1, "cmov", "cmov", 32, - { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } }, }; @@ -5727,12 +5755,6 @@ static const CGEN_OPCODE frv_cgen_macro_insn_opcode_table[] = { { MNEM, OP (PACK), 0 } }, & ifmt_nop, { 0x880000 } }, -/* mnop$pack */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), 0 } }, - & ifmt_mnop, { 0x7fee0ec0 } - }, /* ret$pack */ { { 0, 0, 0, 0 }, diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h index 5d23cf91043..eb0b9022b59 100644 --- a/opcodes/frv-opc.h +++ b/opcodes/frv-opc.h @@ -244,9 +244,10 @@ typedef enum cgen_insn_type { , FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD , FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH , FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB - , FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MCLRACC - , FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC, FRV_INSN_MWTACCG - , FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP + , FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP + , FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG + , FRV_INSN_MWTACC, FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2 + , FRV_INSN_FNOP } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ diff --git a/opcodes/i370-dis.c b/opcodes/i370-dis.c index 51c0ff1dd3e..0f04f27f6bb 100644 --- a/opcodes/i370-dis.c +++ b/opcodes/i370-dis.c @@ -1,6 +1,5 @@ - /* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions - Copyright 1994, 2000 Free Software Foundation, Inc. + Copyright 1994, 2000, 2003 Free Software Foundation, Inc. PowerPC version written by Ian Lance Taylor, Cygnus Support Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> @@ -30,9 +29,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * */ int -print_insn_i370 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info) { bfd_byte buffer[8]; int status; diff --git a/opcodes/i370-opc.c b/opcodes/i370-opc.c index 376dd0eaac9..4ce7994eea8 100644 --- a/opcodes/i370-opc.c +++ b/opcodes/i370-opc.c @@ -1,5 +1,5 @@ /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list - Copyright 1994, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1994, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. PowerPC version written by Ian Lance Taylor, Cygnus Support Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999 @@ -36,12 +36,12 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA file. */ /* Local insertion and extraction functions. */ -static i370_insn_t insert_ss_b2 PARAMS (( i370_insn_t, long, const char **)); -static i370_insn_t insert_ss_d2 PARAMS (( i370_insn_t, long, const char **)); -static i370_insn_t insert_rxf_r3 PARAMS (( i370_insn_t, long, const char **)); -static long extract_ss_b2 PARAMS (( i370_insn_t, int *)); -static long extract_ss_d2 PARAMS (( i370_insn_t, int *)); -static long extract_rxf_r3 PARAMS (( i370_insn_t, int *)); +static i370_insn_t insert_ss_b2 (i370_insn_t, long, const char **); +static i370_insn_t insert_ss_d2 (i370_insn_t, long, const char **); +static i370_insn_t insert_rxf_r3 (i370_insn_t, long, const char **); +static long extract_ss_b2 (i370_insn_t, int *); +static long extract_ss_d2 (i370_insn_t, int *); +static long extract_rxf_r3 (i370_insn_t, int *); /* The operands table. @@ -231,55 +231,43 @@ const struct i370_operand i370_operands[] = /*ARGSUSED*/ static i370_insn_t -insert_ss_b2 (insn, value, errmsg) - i370_insn_t insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; +insert_ss_b2 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) { insn.i[1] |= (value & 0xf) << 28; return insn; } static i370_insn_t -insert_ss_d2 (insn, value, errmsg) - i370_insn_t insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; +insert_ss_d2 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) { insn.i[1] |= (value & 0xfff) << 16; return insn; } static i370_insn_t -insert_rxf_r3 (insn, value, errmsg) - i370_insn_t insn; - long value; - const char **errmsg ATTRIBUTE_UNUSED; +insert_rxf_r3 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) { insn.i[1] |= (value & 0xf) << 28; return insn; } static long -extract_ss_b2 (insn, invalid) - i370_insn_t insn; - int *invalid ATTRIBUTE_UNUSED; +extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) { return (insn.i[1] >>28) & 0xf; } static long -extract_ss_d2 (insn, invalid) - i370_insn_t insn; - int *invalid ATTRIBUTE_UNUSED; +extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) { return (insn.i[1] >>16) & 0xfff; } static long -extract_rxf_r3 (insn, invalid) - i370_insn_t insn; - int *invalid ATTRIBUTE_UNUSED; +extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) { return (insn.i[1] >>28) & 0xf; } @@ -831,45 +819,45 @@ const struct i370_opcode i370_opcodes[] = { { "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, /* S form instructions */ -{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, -{ "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, -{ "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} }, -{ "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} }, -{ "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} }, -{ "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, -{ "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, -{ "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, -{ "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, -{ "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, -{ "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, -{ "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, -{ "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -{ "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} }, -{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, -{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} }, +{ "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} }, +{ "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} }, +{ "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} }, +{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, /* SS form instructions */ { "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 7c03205a191..0ef57efb93c 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -48,53 +48,53 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define UNIXWARE_COMPAT 1 #endif -static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); -static void ckprefix PARAMS ((void)); -static const char *prefix_name PARAMS ((int, int)); -static int print_insn PARAMS ((bfd_vma, disassemble_info *)); -static void dofloat PARAMS ((int)); -static void OP_ST PARAMS ((int, int)); -static void OP_STi PARAMS ((int, int)); -static int putop PARAMS ((const char *, int)); -static void oappend PARAMS ((const char *)); -static void append_seg PARAMS ((void)); -static void OP_indirE PARAMS ((int, int)); -static void print_operand_value PARAMS ((char *, int, bfd_vma)); -static void OP_E PARAMS ((int, int)); -static void OP_G PARAMS ((int, int)); -static bfd_vma get64 PARAMS ((void)); -static bfd_signed_vma get32 PARAMS ((void)); -static bfd_signed_vma get32s PARAMS ((void)); -static int get16 PARAMS ((void)); -static void set_op PARAMS ((bfd_vma, int)); -static void OP_REG PARAMS ((int, int)); -static void OP_IMREG PARAMS ((int, int)); -static void OP_I PARAMS ((int, int)); -static void OP_I64 PARAMS ((int, int)); -static void OP_sI PARAMS ((int, int)); -static void OP_J PARAMS ((int, int)); -static void OP_SEG PARAMS ((int, int)); -static void OP_DIR PARAMS ((int, int)); -static void OP_OFF PARAMS ((int, int)); -static void OP_OFF64 PARAMS ((int, int)); -static void ptr_reg PARAMS ((int, int)); -static void OP_ESreg PARAMS ((int, int)); -static void OP_DSreg PARAMS ((int, int)); -static void OP_C PARAMS ((int, int)); -static void OP_D PARAMS ((int, int)); -static void OP_T PARAMS ((int, int)); -static void OP_Rd PARAMS ((int, int)); -static void OP_MMX PARAMS ((int, int)); -static void OP_XMM PARAMS ((int, int)); -static void OP_EM PARAMS ((int, int)); -static void OP_EX PARAMS ((int, int)); -static void OP_MS PARAMS ((int, int)); -static void OP_XS PARAMS ((int, int)); -static void OP_3DNowSuffix PARAMS ((int, int)); -static void OP_SIMD_Suffix PARAMS ((int, int)); -static void SIMD_Fixup PARAMS ((int, int)); -static void PNI_Fixup PARAMS ((int, int)); -static void BadOp PARAMS ((void)); +static int fetch_data (struct disassemble_info *, bfd_byte *); +static void ckprefix (void); +static const char *prefix_name (int, int); +static int print_insn (bfd_vma, disassemble_info *); +static void dofloat (int); +static void OP_ST (int, int); +static void OP_STi (int, int); +static int putop (const char *, int); +static void oappend (const char *); +static void append_seg (void); +static void OP_indirE (int, int); +static void print_operand_value (char *, int, bfd_vma); +static void OP_E (int, int); +static void OP_G (int, int); +static bfd_vma get64 (void); +static bfd_signed_vma get32 (void); +static bfd_signed_vma get32s (void); +static int get16 (void); +static void set_op (bfd_vma, int); +static void OP_REG (int, int); +static void OP_IMREG (int, int); +static void OP_I (int, int); +static void OP_I64 (int, int); +static void OP_sI (int, int); +static void OP_J (int, int); +static void OP_SEG (int, int); +static void OP_DIR (int, int); +static void OP_OFF (int, int); +static void OP_OFF64 (int, int); +static void ptr_reg (int, int); +static void OP_ESreg (int, int); +static void OP_DSreg (int, int); +static void OP_C (int, int); +static void OP_D (int, int); +static void OP_T (int, int); +static void OP_Rd (int, int); +static void OP_MMX (int, int); +static void OP_XMM (int, int); +static void OP_EM (int, int); +static void OP_EX (int, int); +static void OP_MS (int, int); +static void OP_XS (int, int); +static void OP_3DNowSuffix (int, int); +static void OP_SIMD_Suffix (int, int); +static void SIMD_Fixup (int, int); +static void PNI_Fixup (int, int); +static void BadOp (void); struct dis_private { /* Points to first byte not fetched. */ @@ -161,9 +161,7 @@ static int used_prefixes; ? 1 : fetch_data ((info), (addr))) static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; +fetch_data (struct disassemble_info *info, bfd_byte *addr) { int status; struct dis_private *priv = (struct dis_private *) info->private_data; @@ -427,7 +425,7 @@ fetch_data (info, addr) #define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0 -typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag)); +typedef void (*op_rtn) (int bytemode, int sizeflag); struct dis386 { const char *name; @@ -1699,7 +1697,7 @@ static const struct dis386 x86_64_table[][2] = { #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") static void -ckprefix () +ckprefix (void) { int newrex; rex = 0; @@ -1797,9 +1795,7 @@ ckprefix () prefix byte. */ static const char * -prefix_name (pref, sizeflag) - int pref; - int sizeflag; +prefix_name (int pref, int sizeflag) { switch (pref) { @@ -1893,9 +1889,7 @@ static char scale_char; print_insn_i386_att and print_insn_i386_intel these functions can disappear, and print_insn_i386 be merged into print_insn. */ int -print_insn_i386_att (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_i386_att (bfd_vma pc, disassemble_info *info) { intel_syntax = 0; @@ -1903,9 +1897,7 @@ print_insn_i386_att (pc, info) } int -print_insn_i386_intel (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_i386_intel (bfd_vma pc, disassemble_info *info) { intel_syntax = 1; @@ -1913,9 +1905,7 @@ print_insn_i386_intel (pc, info) } int -print_insn_i386 (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_i386 (bfd_vma pc, disassemble_info *info) { intel_syntax = -1; @@ -1923,9 +1913,7 @@ print_insn_i386 (pc, info) } static int -print_insn (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn (bfd_vma pc, disassemble_info *info) { const struct dis386 *dp; int i; @@ -2034,7 +2022,7 @@ print_insn (pc, info) puts most long word instructions on a single line. */ info->bytes_per_line = 7; - info->private_data = (PTR) &priv; + info->private_data = &priv; priv.max_fetched = priv.the_buffer; priv.insn_start = pc; @@ -2555,8 +2543,7 @@ static char *fgrps[][8] = { }; static void -dofloat (sizeflag) - int sizeflag; +dofloat (int sizeflag) { const struct dis386 *dp; unsigned char floatop; @@ -2602,17 +2589,13 @@ dofloat (sizeflag) } static void -OP_ST (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { oappend ("%st"); } static void -OP_STi (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { sprintf (scratchbuf, "%%st(%d)", rm); oappend (scratchbuf + intel_syntax); @@ -2620,9 +2603,7 @@ OP_STi (bytemode, sizeflag) /* Capital letters in template are macros. */ static int -putop (template, sizeflag) - const char *template; - int sizeflag; +putop (const char *template, int sizeflag) { const char *p; int alt; @@ -2895,15 +2876,14 @@ putop (template, sizeflag) } static void -oappend (s) - const char *s; +oappend (const char *s) { strcpy (obufp, s); obufp += strlen (s); } static void -append_seg () +append_seg (void) { if (prefixes & PREFIX_CS) { @@ -2938,9 +2918,7 @@ append_seg () } static void -OP_indirE (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_indirE (int bytemode, int sizeflag) { if (!intel_syntax) oappend ("*"); @@ -2948,10 +2926,7 @@ OP_indirE (bytemode, sizeflag) } static void -print_operand_value (buf, hex, disp) - char *buf; - int hex; - bfd_vma disp; +print_operand_value (char *buf, int hex, bfd_vma disp) { if (mode_64bit) { @@ -3008,9 +2983,7 @@ print_operand_value (buf, hex, disp) } static void -OP_E (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_E (int bytemode, int sizeflag) { bfd_vma disp; int add = 0; @@ -3293,9 +3266,7 @@ OP_E (bytemode, sizeflag) } static void -OP_G (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_G (int bytemode, int sizeflag) { int add = 0; USED_REX (REX_EXTX); @@ -3336,7 +3307,7 @@ OP_G (bytemode, sizeflag) } static bfd_vma -get64 () +get64 (void) { bfd_vma x; #ifdef BFD64 @@ -3361,7 +3332,7 @@ get64 () } static bfd_signed_vma -get32 () +get32 (void) { bfd_signed_vma x = 0; @@ -3374,7 +3345,7 @@ get32 () } static bfd_signed_vma -get32s () +get32s (void) { bfd_signed_vma x = 0; @@ -3390,7 +3361,7 @@ get32s () } static int -get16 () +get16 (void) { int x = 0; @@ -3401,9 +3372,7 @@ get16 () } static void -set_op (op, riprel) - bfd_vma op; - int riprel; +set_op (bfd_vma op, int riprel) { op_index[op_ad] = op_ad; if (mode_64bit) @@ -3420,9 +3389,7 @@ set_op (op, riprel) } static void -OP_REG (code, sizeflag) - int code; - int sizeflag; +OP_REG (int code, int sizeflag) { const char *s; int add = 0; @@ -3482,9 +3449,7 @@ OP_REG (code, sizeflag) } static void -OP_IMREG (code, sizeflag) - int code; - int sizeflag; +OP_IMREG (int code, int sizeflag) { const char *s; @@ -3531,9 +3496,7 @@ OP_IMREG (code, sizeflag) } static void -OP_I (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_I (int bytemode, int sizeflag) { bfd_signed_vma op; bfd_signed_vma mask = -1; @@ -3585,9 +3548,7 @@ OP_I (bytemode, sizeflag) } static void -OP_I64 (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_I64 (int bytemode, int sizeflag) { bfd_signed_vma op; bfd_signed_vma mask = -1; @@ -3638,9 +3599,7 @@ OP_I64 (bytemode, sizeflag) } static void -OP_sI (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_sI (int bytemode, int sizeflag) { bfd_signed_vma op; bfd_signed_vma mask = -1; @@ -3689,9 +3648,7 @@ OP_sI (bytemode, sizeflag) } static void -OP_J (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_J (int bytemode, int sizeflag) { bfd_vma disp; bfd_vma mask = -1; @@ -3727,17 +3684,13 @@ OP_J (bytemode, sizeflag) } static void -OP_SEG (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_SEG (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { oappend (names_seg[reg]); } static void -OP_DIR (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag; +OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) { int seg, offset; @@ -3760,9 +3713,7 @@ OP_DIR (dummy, sizeflag) } static void -OP_OFF (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag; +OP_OFF (int bytemode ATTRIBUTE_UNUSED, int sizeflag) { bfd_vma off; @@ -3787,9 +3738,7 @@ OP_OFF (bytemode, sizeflag) } static void -OP_OFF64 (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_OFF64 (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { bfd_vma off; @@ -3817,9 +3766,7 @@ OP_OFF64 (bytemode, sizeflag) } static void -ptr_reg (code, sizeflag) - int code; - int sizeflag; +ptr_reg (int code, int sizeflag) { const char *s; if (intel_syntax) @@ -3847,18 +3794,14 @@ ptr_reg (code, sizeflag) } static void -OP_ESreg (code, sizeflag) - int code; - int sizeflag; +OP_ESreg (int code, int sizeflag) { oappend ("%es:" + intel_syntax); ptr_reg (code, sizeflag); } static void -OP_DSreg (code, sizeflag) - int code; - int sizeflag; +OP_DSreg (int code, int sizeflag) { if ((prefixes & (PREFIX_CS @@ -3873,9 +3816,7 @@ OP_DSreg (code, sizeflag) } static void -OP_C (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3886,9 +3827,7 @@ OP_C (dummy, sizeflag) } static void -OP_D (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3902,18 +3841,14 @@ OP_D (dummy, sizeflag) } static void -OP_T (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { sprintf (scratchbuf, "%%tr%d", reg); oappend (scratchbuf + intel_syntax); } static void -OP_Rd (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_Rd (int bytemode, int sizeflag) { if (mod == 3) OP_E (bytemode, sizeflag); @@ -3922,9 +3857,7 @@ OP_Rd (bytemode, sizeflag) } static void -OP_MMX (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3939,9 +3872,7 @@ OP_MMX (bytemode, sizeflag) } static void -OP_XMM (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3952,9 +3883,7 @@ OP_XMM (bytemode, sizeflag) } static void -OP_EM (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_EM (int bytemode, int sizeflag) { int add = 0; if (mod != 3) @@ -3978,9 +3907,7 @@ OP_EM (bytemode, sizeflag) } static void -OP_EX (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_EX (int bytemode, int sizeflag) { int add = 0; if (mod != 3) @@ -4000,9 +3927,7 @@ OP_EX (bytemode, sizeflag) } static void -OP_MS (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_MS (int bytemode, int sizeflag) { if (mod == 3) OP_EM (bytemode, sizeflag); @@ -4011,9 +3936,7 @@ OP_MS (bytemode, sizeflag) } static void -OP_XS (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_XS (int bytemode, int sizeflag) { if (mod == 3) OP_EX (bytemode, sizeflag); @@ -4089,9 +4012,7 @@ static const char *const Suffix3DNow[] = { }; static void -OP_3DNowSuffix (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char *mnemonic; @@ -4127,9 +4048,7 @@ static const char *simd_cmp_op[] = { }; static void -OP_SIMD_Suffix (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { unsigned int cmp_type; @@ -4169,9 +4088,7 @@ OP_SIMD_Suffix (bytemode, sizeflag) } static void -SIMD_Fixup (extrachar, sizeflag) - int extrachar; - int sizeflag ATTRIBUTE_UNUSED; +SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED) { /* Change movlps/movhps to movhlps/movlhps for 2 register operand forms of these instructions. */ @@ -4187,9 +4104,7 @@ SIMD_Fixup (extrachar, sizeflag) } static void -PNI_Fixup (extrachar, sizeflag) - int extrachar ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { if (mod == 3 && reg == 1) { diff --git a/opcodes/i960-dis.c b/opcodes/i960-dis.c index 9210d02d800..fa6f1882781 100644 --- a/opcodes/i960-dis.c +++ b/opcodes/i960-dis.c @@ -1,5 +1,5 @@ /* Disassemble i80960 instructions. - Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 + Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -31,26 +31,24 @@ static const char *const reg_names[] = { static FILE *stream; /* Output goes here */ static struct disassemble_info *info; -static void print_addr PARAMS ((bfd_vma)); -static void ctrl PARAMS ((bfd_vma, unsigned long, unsigned long)); -static void cobr PARAMS ((bfd_vma, unsigned long, unsigned long)); -static void reg PARAMS ((unsigned long)); -static int mem PARAMS ((bfd_vma, unsigned long, unsigned long, int)); -static void ea PARAMS ((bfd_vma, int, const char *, const char *, int, unsigned int)); -static void dstop PARAMS ((int, int, int)); -static void regop PARAMS ((int, int, int, int)); -static void invalid PARAMS ((int)); -static int pinsn PARAMS ((bfd_vma, unsigned long, unsigned long)); -static void put_abs PARAMS ((unsigned long, unsigned long)); +static void print_addr (bfd_vma); +static void ctrl (bfd_vma, unsigned long, unsigned long); +static void cobr (bfd_vma, unsigned long, unsigned long); +static void reg (unsigned long); +static int mem (bfd_vma, unsigned long, unsigned long, int); +static void ea (bfd_vma, int, const char *, const char *, int, unsigned int); +static void dstop (int, int, int); +static void regop (int, int, int, int); +static void invalid (int); +static int pinsn (bfd_vma, unsigned long, unsigned long); +static void put_abs (unsigned long, unsigned long); /* Print the i960 instruction at address 'memaddr' in debugged memory, on INFO->STREAM. Returns length of the instruction, in bytes. */ int -print_insn_i960 (memaddr, info_arg) - bfd_vma memaddr; - struct disassemble_info *info_arg; +print_insn_i960 (bfd_vma memaddr, struct disassemble_info *info_arg) { unsigned int word1, word2 = 0xdeadbeef; bfd_byte buffer[8]; @@ -118,12 +116,10 @@ struct sparse_tabent { }; static int -pinsn (memaddr, word1, word2) - bfd_vma memaddr; - unsigned long word1, word2; +pinsn (bfd_vma memaddr, unsigned long word1, unsigned long word2) { int instr_len; - + instr_len = 4; put_abs (word1, word2); @@ -161,10 +157,7 @@ pinsn (memaddr, word1, word2) /* CTRL format.. */ static void -ctrl (memaddr, word1, word2) - bfd_vma memaddr; - unsigned long word1; - unsigned long word2 ATTRIBUTE_UNUSED; +ctrl (bfd_vma memaddr, unsigned long word1, unsigned long word2 ATTRIBUTE_UNUSED) { int i; static const struct tabent ctrl_tab[] = { @@ -233,15 +226,12 @@ ctrl (memaddr, word1, word2) /* COBR format. */ static void -cobr (memaddr, word1, word2) - bfd_vma memaddr; - unsigned long word1; - unsigned long word2 ATTRIBUTE_UNUSED; +cobr (bfd_vma memaddr, unsigned long word1, unsigned long word2 ATTRIBUTE_UNUSED) { int src1; int src2; int i; - + static const struct tabent cobr_tab[] = { { "testno", 1, }, /* 0x20 */ { "testg", 1, }, /* 0x21 */ @@ -324,18 +314,14 @@ cobr (memaddr, word1, word2) /* Returns instruction length: 4 or 8. */ static int -mem (memaddr, word1, word2, noprint) - bfd_vma memaddr; - unsigned long word1, word2; - int noprint; /* If TRUE, return instruction length, but - don't output any text. */ +mem (bfd_vma memaddr, unsigned long word1, unsigned long word2, int noprint) { int i, j; int len; int mode; int offset; const char *reg1, *reg2, *reg3; - + /* This lookup table is too sparse to make it worth typing in, but not so large as to make a sparse array necessary. We create the table at runtime. */ @@ -395,7 +381,7 @@ mem (memaddr, word1, word2, noprint) && ((mode == 5) || (mode >= 12))) /* With 32-bit displacement. */ len = 8; - else + else len = 4; if (noprint) @@ -426,7 +412,7 @@ mem (memaddr, word1, word2, noprint) { /* MEMA FORMAT */ (*info->fprintf_func) (stream, "0x%x", (unsigned) offset); - if (mode & 8) + if (mode & 8) (*info->fprintf_func) (stream, "(%s)", reg2); (*info->fprintf_func)(stream, ",%s", reg1); @@ -445,7 +431,7 @@ mem (memaddr, word1, word2, noprint) /* MEMA FORMAT */ (*info->fprintf_func) (stream, "%s,0x%x", reg1, (unsigned) offset); - if (mode & 8) + if (mode & 8) (*info->fprintf_func) (stream, "(%s)", reg2); } break; @@ -472,8 +458,7 @@ mem (memaddr, word1, word2, noprint) /* REG format. */ static void -reg (word1) - unsigned long word1; +reg (unsigned long word1) { int i, j; int opcode; @@ -488,14 +473,14 @@ reg (word1) at runtime. */ /* NOTE: In this table, the meaning of 'numops' is: - 1: single operand, which is NOT a destination. - -1: single operand, which IS a destination. - 2: 2 operands, the 2nd of which is NOT a destination. - -2: 2 operands, the 2nd of which IS a destination. - 3: 3 operands - - If an opcode mnemonic begins with "F", it is a floating-point - opcode (the "F" is not printed). */ + 1: single operand, which is NOT a destination. + -1: single operand, which IS a destination. + 2: 2 operands, the 2nd of which is NOT a destination. + -2: 2 operands, the 2nd of which IS a destination. + 3: 3 operands + + If an opcode mnemonic begins with "F", it is a floating-point + opcode (the "F" is not printed). */ static struct tabent *reg_tab; static const struct sparse_tabent reg_init[] = @@ -777,13 +762,8 @@ reg (word1) /* Print out effective address for memb instructions. */ static void -ea (memaddr, mode, reg2, reg3, word1, word2) - bfd_vma memaddr; - int mode; - const char *reg2; - const char *reg3; - int word1; - unsigned int word2; +ea (bfd_vma memaddr, int mode, const char *reg2, const char *reg3, int word1, + unsigned int word2) { int scale; static const int scale_tab[] = { 1, 2, 4, 8, 16 }; @@ -842,8 +822,7 @@ ea (memaddr, mode, reg2, reg3, word1, word2) /* Register Instruction Operand. */ static void -regop (mode, spec, reg, fp) - int mode, spec, reg, fp; +regop (int mode, int spec, int reg, int fp) { if (fp) { @@ -897,8 +876,7 @@ regop (mode, spec, reg, fp) /* Register Instruction Destination Operand. */ static void -dstop (mode, reg, fp) - int mode, reg, fp; +dstop (int mode, int reg, int fp) { /* 'dst' operand can't be a literal. On non-FP instructions, register mode is assumed and "m3" acts as if were "s3"; on FP-instructions, @@ -910,23 +888,20 @@ dstop (mode, reg, fp) } static void -invalid (word1) - int word1; +invalid (int word1) { (*info->fprintf_func) (stream, ".word\t0x%08x", (unsigned) word1); } static void -print_addr (a) - bfd_vma a; +print_addr (bfd_vma a) { (*info->print_address_func) (a, info); } static void -put_abs (word1, word2) - unsigned long word1 ATTRIBUTE_UNUSED; - unsigned long word2 ATTRIBUTE_UNUSED; +put_abs (unsigned long word1 ATTRIBUTE_UNUSED, + unsigned long word2 ATTRIBUTE_UNUSED) { #ifdef IN_GDB return; diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c index 9726381dd6a..fc90213a6b5 100644 --- a/opcodes/ia64-opc.c +++ b/opcodes/ia64-opc.c @@ -1,5 +1,5 @@ /* ia64-opc.c -- Functions to access the compacted opcode table - Copyright 1999, 2000 Free Software Foundation, Inc. + Copyright 1999, 2000, 2003 Free Software Foundation, Inc. Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com> This file is part of GDB, GAS, and the GNU binutils. @@ -25,19 +25,19 @@ #include "ia64-asmtab.h" #include "ia64-asmtab.c" -static void get_opc_prefix PARAMS ((const char **, char *)); -static short int find_string_ent PARAMS ((const char *)); -static short int find_main_ent PARAMS ((short int)); -static short int find_completer PARAMS ((short int, short int, const char *)); -static ia64_insn apply_completer PARAMS ((ia64_insn, int)); -static int extract_op_bits PARAMS ((int, int, int)); -static int extract_op PARAMS ((int, int *, unsigned int *)); -static int opcode_verify PARAMS ((ia64_insn, int, enum ia64_insn_type)); -static int locate_opcode_ent PARAMS ((ia64_insn, enum ia64_insn_type)); +static void get_opc_prefix (const char **, char *); +static short int find_string_ent (const char *); +static short int find_main_ent (short int); +static short int find_completer (short int, short int, const char *); +static ia64_insn apply_completer (ia64_insn, int); +static int extract_op_bits (int, int, int); +static int extract_op (int, int *, unsigned int *); +static int opcode_verify (ia64_insn, int, enum ia64_insn_type); +static int locate_opcode_ent (ia64_insn, enum ia64_insn_type); static struct ia64_opcode *make_ia64_opcode - PARAMS ((ia64_insn, const char *, int, int)); + (ia64_insn, const char *, int, int); static struct ia64_opcode *ia64_find_matching_opcode - PARAMS ((const char *, short int)); + (const char *, short int); const struct ia64_templ_desc ia64_templ_desc[16] = { @@ -65,9 +65,7 @@ const struct ia64_templ_desc ia64_templ_desc[16] = of the opcode, or at the NUL character. */ static void -get_opc_prefix (ptr, dest) - const char **ptr; - char *dest; +get_opc_prefix (const char **ptr, char *dest) { char *c = strchr (*ptr, '.'); if (c != NULL) @@ -89,8 +87,7 @@ get_opc_prefix (ptr, dest) STR; return -1 if one does not exist. */ static short -find_string_ent (str) - const char *str; +find_string_ent (const char *str) { short start = 0; short end = sizeof (ia64_strings) / sizeof (const char *); @@ -124,8 +121,7 @@ find_string_ent (str) return -1 if one does not exist. */ static short -find_main_ent (nameindex) - short nameindex; +find_main_ent (short nameindex) { short start = 0; short end = sizeof (main_table) / sizeof (struct ia64_main_table); @@ -164,10 +160,7 @@ find_main_ent (nameindex) return -1 if one does not exist. */ static short -find_completer (main_ent, prev_completer, name) - short main_ent; - short prev_completer; - const char *name; +find_completer (short main_ent, short prev_completer, const char *name) { short name_index = find_string_ent (name); @@ -200,9 +193,7 @@ find_completer (main_ent, prev_completer, name) return the result. */ static ia64_insn -apply_completer (opcode, completer_index) - ia64_insn opcode; - int completer_index; +apply_completer (ia64_insn opcode, int completer_index) { ia64_insn mask = completer_table[completer_index].mask; ia64_insn bits = completer_table[completer_index].bits; @@ -220,10 +211,7 @@ apply_completer (opcode, completer_index) first byte in OP_POINTER.) */ static int -extract_op_bits (op_pointer, bitoffset, bits) - int op_pointer; - int bitoffset; - int bits; +extract_op_bits (int op_pointer, int bitoffset, int bits) { int res = 0; @@ -259,10 +247,7 @@ extract_op_bits (op_pointer, bitoffset, bits) state entry in bits is returned. */ static int -extract_op (op_pointer, opval, op) - int op_pointer; - int *opval; - unsigned int *op; +extract_op (int op_pointer, int *opval, unsigned int *op) { int oplen = 5; @@ -317,10 +302,7 @@ extract_op (op_pointer, opval, op) PLACE matches OPCODE and is of type TYPE. */ static int -opcode_verify (opcode, place, type) - ia64_insn opcode; - int place; - enum ia64_insn_type type; +opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type) { if (main_table[place].opcode_type != type) { @@ -364,9 +346,7 @@ opcode_verify (opcode, place, type) priority. */ static int -locate_opcode_ent (opcode, type) - ia64_insn opcode; - enum ia64_insn_type type; +locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type) { int currtest[41]; int bitpos[41]; @@ -545,11 +525,7 @@ locate_opcode_ent (opcode, type) /* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ static struct ia64_opcode * -make_ia64_opcode (opcode, name, place, depind) - ia64_insn opcode; - const char *name; - int place; - int depind; +make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind) { struct ia64_opcode *res = (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); @@ -572,9 +548,7 @@ make_ia64_opcode (opcode, name, place, depind) /* Determine the ia64_opcode entry for the opcode specified by INSN and TYPE. If a valid entry is not found, return NULL. */ struct ia64_opcode * -ia64_dis_opcode (insn, type) - ia64_insn insn; - enum ia64_insn_type type; +ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type) { int disent = locate_opcode_ent (insn, type); @@ -633,9 +607,7 @@ ia64_dis_opcode (insn, type) matches NAME. Return NULL if one is not found. */ static struct ia64_opcode * -ia64_find_matching_opcode (name, place) - const char *name; - short place; +ia64_find_matching_opcode (const char *name, short place) { char op[129]; const char *suffix; @@ -696,8 +668,7 @@ ia64_find_matching_opcode (name, place) release any resources used by the returned entry. */ struct ia64_opcode * -ia64_find_next_opcode (prev_ent) - struct ia64_opcode *prev_ent; +ia64_find_next_opcode (struct ia64_opcode *prev_ent) { return ia64_find_matching_opcode (prev_ent->name, prev_ent->ent_index + 1); @@ -710,8 +681,7 @@ ia64_find_next_opcode (prev_ent) release any resources used by the returned entry. */ struct ia64_opcode * -ia64_find_opcode (name) - const char *name; +ia64_find_opcode (const char *name) { char op[129]; const char *suffix; @@ -741,16 +711,14 @@ ia64_find_opcode (name) /* Free any resources used by ENT. */ void -ia64_free_opcode (ent) - struct ia64_opcode *ent; +ia64_free_opcode (struct ia64_opcode *ent) { free ((void *)ent->name); free (ent); } const struct ia64_dependency * -ia64_find_dependency (index) - int index; +ia64_find_dependency (int index) { index = DEP(index); diff --git a/opcodes/ip2k-asm.c b/opcodes/ip2k-asm.c index 524f256a537..593db9db03d 100644 --- a/opcodes/ip2k-asm.c +++ b/opcodes/ip2k-asm.c @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -607,8 +607,7 @@ ip2k_cgen_init_asm (cd) Returns NULL for success, an error message for failure. */ char * -ip2k_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +ip2k_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -731,11 +730,10 @@ ip2k_cgen_build_insn_regex (insn) Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -873,12 +871,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -982,9 +979,7 @@ ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg) FIXME: Not currently used. */ void -ip2k_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +ip2k_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c index f33fcc05ff6..00e764ccced 100644 --- a/opcodes/ip2k-dis.c +++ b/opcodes/ip2k-dis.c @@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ @@ -352,13 +351,12 @@ ip2k_cgen_init_dis (cd) /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -378,13 +376,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -408,12 +405,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -427,17 +423,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -469,14 +464,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -500,12 +494,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -610,10 +603,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -652,9 +642,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_ip2k (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_ip2k (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/ip2k-ibld.c b/opcodes/ip2k-ibld.c index 22e2d8dea6b..e0c53090517 100644 --- a/opcodes/ip2k-ibld.c +++ b/opcodes/ip2k-ibld.c @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c index 7fb795eb155..62d03f857a6 100644 --- a/opcodes/iq2000-asm.c +++ b/opcodes/iq2000-asm.c @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -493,8 +493,7 @@ iq2000_cgen_init_asm (cd) Returns NULL for success, an error message for failure. */ char * -iq2000_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +iq2000_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -617,11 +616,10 @@ iq2000_cgen_build_insn_regex (insn) Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -759,12 +757,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -868,9 +865,7 @@ iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg) FIXME: Not currently used. */ void -iq2000_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +iq2000_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c index b1bfa0ef4b4..c20e9788517 100644 --- a/opcodes/iq2000-dis.c +++ b/opcodes/iq2000-dis.c @@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ @@ -215,13 +214,12 @@ iq2000_cgen_init_dis (cd) /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -241,13 +239,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -271,12 +268,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -290,17 +286,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -332,14 +327,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -363,12 +357,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -473,10 +466,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -515,9 +505,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_iq2000 (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_iq2000 (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/iq2000-ibld.c b/opcodes/iq2000-ibld.c index 4917d9fa3d5..f0640f0774f 100644 --- a/opcodes/iq2000-ibld.c +++ b/opcodes/iq2000-ibld.c @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index 2bd751af6db..a8c9485f20f 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -358,8 +358,7 @@ m32r_cgen_init_asm (cd) Returns NULL for success, an error message for failure. */ char * -m32r_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +m32r_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -482,11 +481,10 @@ m32r_cgen_build_insn_regex (insn) Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -624,12 +622,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +m32r_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -733,9 +730,7 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) FIXME: Not currently used. */ void -m32r_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +m32r_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index 5688049ef16..e8abbc61346 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ @@ -274,13 +273,12 @@ m32r_cgen_init_dis (cd) /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -300,13 +298,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -330,12 +327,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -349,17 +345,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -391,14 +386,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -422,12 +416,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -532,10 +525,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -574,9 +564,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_m32r (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_m32r (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c index ef1ee0e0126..2a8d104e3f7 100644 --- a/opcodes/m32r-ibld.c +++ b/opcodes/m32r-ibld.c @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c index 26b2625957f..9f6ee325888 100644 --- a/opcodes/openrisc-asm.c +++ b/opcodes/openrisc-asm.c @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -277,8 +277,7 @@ openrisc_cgen_init_asm (cd) Returns NULL for success, an error message for failure. */ char * -openrisc_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +openrisc_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -401,11 +400,10 @@ openrisc_cgen_build_insn_regex (insn) Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -543,12 +541,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +openrisc_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -652,9 +649,7 @@ openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg) FIXME: Not currently used. */ void -openrisc_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +openrisc_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c index 5c4da5f3e94..6b721e213fb 100644 --- a/opcodes/openrisc-dis.c +++ b/opcodes/openrisc-dis.c @@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ @@ -161,13 +160,12 @@ openrisc_cgen_init_dis (cd) /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -187,13 +185,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -217,12 +214,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -236,17 +232,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -278,14 +273,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -309,12 +303,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -419,10 +412,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -461,9 +451,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_openrisc (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_openrisc (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/openrisc-ibld.c b/opcodes/openrisc-ibld.c index c2e5156e8d2..751ac07c3cf 100644 --- a/opcodes/openrisc-ibld.c +++ b/opcodes/openrisc-ibld.c @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; diff --git a/opcodes/po/fr.po b/opcodes/po/fr.po index 08ae66193a7..7ec06af1903 100644 --- a/opcodes/po/fr.po +++ b/opcodes/po/fr.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: opcodes 2.14rel030712\n" "POT-Creation-Date: 2003-07-11 13:56+0930\n" -"PO-Revision-Date: 2003-07-22 08:00-0500\n" +"PO-Revision-Date: 2003-08-05 08:00-0500\n" "Last-Translator: Michel Robitaille <robitail@IRO.UMontreal.CA>\n" "Language-Team: French <traduc@traduc.org>\n" "MIME-Version: 1.0\n" @@ -66,12 +66,12 @@ msgstr "contrainte inconnue « %c »" #: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" -msgstr "opérande hors gamme (%ld n'est pas entre %ld et %ld)" +msgstr "opérande hors limite (%ld n'est pas entre %ld et %ld)" #: cgen-asm.c:369 #, c-format msgid "operand out of range (%lu not between %lu and %lu)" -msgstr "opérande hors gamme (%lu n'est pas entre %lu et %lu)" +msgstr "opérande hors limite (%lu n'est pas entre %lu et %lu)" #: d30v-dis.c:312 #, c-format @@ -87,7 +87,7 @@ msgstr "Erreur inconnue %d\n" #: dis-buf.c:62 #, c-format msgid "Address 0x%x is out of bounds.\n" -msgstr "Adresse 0x%x est hors gamme.\n" +msgstr "Adresse 0x%x est hors limite.\n" #: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 #: openrisc-asm.c:261 xstormy16-asm.c:284 @@ -161,13 +161,13 @@ msgstr "Champ non reconnu %d lors de l'impression insn.\n" #: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" -msgstr "opérande hors gamme (%ld n'est pas entre %ld et %lu)" +msgstr "opérande hors limite (%ld n'est pas entre %ld et %lu)" #: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 #: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" -msgstr "opérande hors gamme (%lu n'est pas entre 0 et %lu)" +msgstr "opérande hors limite (%lu n'est pas entre 0 et %lu)" #: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 #: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 @@ -358,13 +358,13 @@ msgstr "décalage(IP) n'a pas un format valide" #. of range. #: ip2k-asm.c:175 msgid "(DP) offset out of range." -msgstr "décalage (DP) est hors gamme." +msgstr "décalage (DP) est hors limite." #. Found something there in front of (SP) but it's out #. of range. #: ip2k-asm.c:221 msgid "(SP) offset out of range." -msgstr "décalage (SP) est hors gamme." +msgstr "décalage (SP) est hors limite." #: ip2k-asm.c:241 msgid "illegal use of parentheses" @@ -372,7 +372,7 @@ msgstr "usage illégal des parenthèses" #: ip2k-asm.c:248 msgid "operand out of range (not between 1 and 255)" -msgstr "opérande hors gamme (n'est pas entre 1 et 255)" +msgstr "opérande hors limite (n'est pas entre 1 et 255)" #. Something is very wrong. opindex has to be one of the above. #: ip2k-asm.c:273 @@ -402,11 +402,11 @@ msgstr "valeur immédiate doit être un registre" #: iq2000-asm.c:120 iq2000-asm.c:151 msgid "immediate value out of range" -msgstr "valeur immédiate est hors gamme" +msgstr "valeur immédiate est hors limite" #: iq2000-asm.c:180 msgid "21-bit offset out of range" -msgstr "décalage de 21 bits est hors gamme" +msgstr "décalage de 21 bits est hors limite" #: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 #: openrisc-asm.c:96 openrisc-asm.c:155 @@ -647,7 +647,7 @@ msgstr "masque de bits illégal" #: ppc-opc.c:1192 msgid "value out of range" -msgstr "valeur hors gamme" +msgstr "valeur hors limite" #: ppc-opc.c:1262 msgid "index register in load range" @@ -706,11 +706,11 @@ msgstr "registre de pile inconnu: %d\n" #. specific command line option is given to GAS. #: v850-opc.c:68 msgid "displacement value is not in range and is not aligned" -msgstr "La valeur de déplacement est hors gamme et n'est pas alignée." +msgstr "La valeur de déplacement est hors limite et n'est pas alignée." #: v850-opc.c:69 msgid "displacement value is out of range" -msgstr "valeur de déplacement est hors gamme" +msgstr "valeur de déplacement est hors limite" #: v850-opc.c:70 msgid "displacement value is not aligned" @@ -718,15 +718,15 @@ msgstr "valeur de déplacement n'est pas alignée" #: v850-opc.c:72 msgid "immediate value is out of range" -msgstr "valeur immédiate est hors gamme" +msgstr "valeur immédiate est hors limite" #: v850-opc.c:83 msgid "branch value not in range and to odd offset" -msgstr "valeur de branchement est hors gamme et a un décalage impair" +msgstr "valeur de branchement est hors limite et a un décalage impair" #: v850-opc.c:85 v850-opc.c:117 msgid "branch value out of range" -msgstr "valeur de branchement hors gamme" +msgstr "valeur de branchement hors limite" #: v850-opc.c:88 v850-opc.c:120 msgid "branch to odd offset" @@ -734,7 +734,7 @@ msgstr "Branchement avec un décalage impair" #: v850-opc.c:115 msgid "branch value not in range and to an odd offset" -msgstr "valeur de branchement est hors gamme et a un décalage impair" +msgstr "valeur de branchement est hors limite et a un décalage impair" #: v850-opc.c:346 msgid "invalid register for stack adjustment" @@ -742,7 +742,7 @@ msgstr "registre invalide pour un ajustement de la pile" #: v850-opc.c:370 msgid "immediate value not in range and not even" -msgstr "valeur immédiate est hors gamme et est impaire" +msgstr "valeur immédiate est hors limite et est impaire" #: v850-opc.c:375 msgid "immediate value must be even" diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index b8b8b1ad592..76af4e7af12 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -30,18 +30,19 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * in both big and little endian mode and also for the POWER (RS/6000) chip. */ -static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *, - int bigendian, int dialect)); +static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); -static int powerpc_dialect PARAMS ((struct disassemble_info *)); +struct dis_private { + /* Stash the result of parsing disassembler_options here. */ + int dialect; +}; /* Determine which set of machines to disassemble for. PPC403/601 or BookE. For convenience, also disassemble instructions supported by the AltiVec vector unit. */ -int -powerpc_dialect(info) - struct disassemble_info *info; +static int +powerpc_dialect (struct disassemble_info *info) { int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC; @@ -49,40 +50,39 @@ powerpc_dialect(info) dialect |= PPC_OPCODE_64; if (info->disassembler_options - && (strcmp (info->disassembler_options, "booke") == 0 - || strcmp (info->disassembler_options, "booke32") == 0 - || strcmp (info->disassembler_options, "booke64") == 0)) + && strstr (info->disassembler_options, "booke") != NULL) dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; - else - if ((info->mach == bfd_mach_ppc_e500) - || (info->disassembler_options - && ( strcmp (info->disassembler_options, "e500") == 0 - || strcmp (info->disassembler_options, "e500x2") == 0))) - { - dialect |= PPC_OPCODE_BOOKE - | PPC_OPCODE_SPE | PPC_OPCODE_ISEL - | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK - | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK - | PPC_OPCODE_RFMCI; - /* efs* and AltiVec conflict. */ - dialect &= ~PPC_OPCODE_ALTIVEC; - } - else - if (info->disassembler_options - && (strcmp (info->disassembler_options, "efs") == 0)) - { - dialect |= PPC_OPCODE_EFS; - /* efs* and AltiVec conflict. */ - dialect &= ~PPC_OPCODE_ALTIVEC; - } + else if ((info->mach == bfd_mach_ppc_e500) + || (info->disassembler_options + && strstr (info->disassembler_options, "e500") != NULL)) + { + dialect |= PPC_OPCODE_BOOKE + | PPC_OPCODE_SPE | PPC_OPCODE_ISEL + | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK + | PPC_OPCODE_RFMCI; + /* efs* and AltiVec conflict. */ + dialect &= ~PPC_OPCODE_ALTIVEC; + } + else if (info->disassembler_options + && strstr (info->disassembler_options, "efs") != NULL) + { + dialect |= PPC_OPCODE_EFS; + /* efs* and AltiVec conflict. */ + dialect &= ~PPC_OPCODE_ALTIVEC; + } else dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON); if (info->disassembler_options - && strcmp (info->disassembler_options, "power4") == 0) + && strstr (info->disassembler_options, "power4") != NULL) dialect |= PPC_OPCODE_POWER4; + if (info->disassembler_options + && strstr (info->disassembler_options, "any") != NULL) + dialect |= PPC_OPCODE_ANY; + if (info->disassembler_options) { if (strstr (info->disassembler_options, "32") != NULL) @@ -91,35 +91,32 @@ powerpc_dialect(info) dialect |= PPC_OPCODE_64; } + ((struct dis_private *) &info->private_data)->dialect = dialect; return dialect; } /* Print a big endian PowerPC instruction. */ int -print_insn_big_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) { - return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info)); + int dialect = ((struct dis_private *) &info->private_data)->dialect; + return print_insn_powerpc (memaddr, info, 1, dialect); } /* Print a little endian PowerPC instruction. */ int -print_insn_little_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) { - return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info)); + int dialect = ((struct dis_private *) &info->private_data)->dialect; + return print_insn_powerpc (memaddr, info, 0, dialect); } /* Print a POWER (RS/6000) instruction. */ int -print_insn_rs6000 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) { return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); } @@ -127,11 +124,10 @@ print_insn_rs6000 (memaddr, info) /* Print a PowerPC or POWER instruction. */ static int -print_insn_powerpc (memaddr, info, bigendian, dialect) - bfd_vma memaddr; - struct disassemble_info *info; - int bigendian; - int dialect; +print_insn_powerpc (bfd_vma memaddr, + struct disassemble_info *info, + int bigendian, + int dialect) { bfd_byte buffer[4]; int status; @@ -140,6 +136,9 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) const struct powerpc_opcode *opcode_end; unsigned long op; + if (dialect == 0) + dialect = powerpc_dialect (info); + status = (*info->read_memory_func) (memaddr, buffer, 4, info); if (status != 0) { @@ -158,6 +157,7 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) /* Find the first match in the opcode table. We could speed this up a bit by doing a binary search on the major opcode. */ opcode_end = powerpc_opcodes + powerpc_num_opcodes; + again: for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) { unsigned long table_op; @@ -177,9 +177,6 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) || (opcode->flags & dialect) == 0) continue; - if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC)) - continue; - /* Make two passes over the operands. First see if any of them have extraction functions, and, if they do, make sure the instruction is valid. */ @@ -288,6 +285,12 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) return 4; } + if ((dialect & PPC_OPCODE_ANY) != 0) + { + dialect = ~PPC_OPCODE_ANY; + goto again; + } + /* We could not find a match. */ (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); @@ -295,7 +298,7 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) } void -print_ppc_disassembler_options (FILE * stream) +print_ppc_disassembler_options (FILE *stream) { fprintf (stream, "\n\ The following PPC specific disassembler options are supported for use with\n\ diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 0f04cfb8468..c37943bd149 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1001,7 +1001,8 @@ insert_fxm (unsigned long insn, ; /* If only one bit of the FXM field is set, we can use the new form - of the instruction, which is faster. */ + of the instruction, which is faster. Unlike the Power4 branch hint + encoding, this is not backward compatible. */ else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value) insn |= 1 << 20; @@ -1762,26 +1763,26 @@ extract_tbr (unsigned long insn, /* Smaller names for the flags so each entry in the opcodes table will fit on a single line. */ #undef PPC -#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY -#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY +#define PPC PPC_OPCODE_PPC +#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM -#define POWER4 PPC_OPCODE_POWER4 | PPCCOM -#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY -#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY -#define PPCONLY PPC_OPCODE_PPC +#define POWER4 PPC_OPCODE_POWER4 +#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC +#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC #define PPC403 PPC_OPCODE_403 #define PPC405 PPC403 +#define PPC440 PPC_OPCODE_440 #define PPC750 PPC #define PPC860 PPC -#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC -#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY -#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY -#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY -#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32 -#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY -#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32 -#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY -#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY +#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC +#define POWER PPC_OPCODE_POWER +#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 +#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 +#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 +#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON +#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 +#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 +#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON #define MFDEC1 PPC_OPCODE_POWER #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE #define BOOKE PPC_OPCODE_BOOKE @@ -1863,90 +1864,90 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, -{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, @@ -2368,12 +2369,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } }, +{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } }, +{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, @@ -2681,186 +2682,186 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, @@ -2905,8 +2906,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, { "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } }, +{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, @@ -2934,143 +2934,143 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, @@ -3158,7 +3158,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, +{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, @@ -3234,6 +3234,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } }, { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } }, +{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, @@ -3263,7 +3264,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, +{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, @@ -3314,6 +3315,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, +{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, + { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, @@ -3353,8 +3357,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, -{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } }, -{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } }, +{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, @@ -3400,8 +3403,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, -{ "wrteei", X(31,163), XE_MASK, PPC403, { E } }, -{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } }, +{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, @@ -3501,8 +3503,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, -{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, - { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, @@ -3581,8 +3581,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, -{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } }, -{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } }, +{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, @@ -3596,21 +3595,24 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, +{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, -{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, +{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, +{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, +{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, @@ -3634,8 +3636,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } }, +{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, +{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, +{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, @@ -3647,19 +3652,32 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, +{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, +{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, +{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, +{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, +{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, +{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, +{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, +{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, +{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, +{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, +{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, +{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, +{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, @@ -3722,12 +3740,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, -{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, -{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, -{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, -{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, -{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, @@ -3738,26 +3751,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, -{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, -{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, -{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, -{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, -{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, -{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, -{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, -{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, -{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, -{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, -{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, @@ -3783,7 +3785,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, -{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } }, +{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, @@ -3797,10 +3799,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, -{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, -{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, -{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, - { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, @@ -3852,42 +3850,41 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, -{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } }, -{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } }, -{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } }, -{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } }, -{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } }, -{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } }, -{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } }, -{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } }, -{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } }, -{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } }, -{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } }, -{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } }, -{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } }, -{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } }, -{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } }, +{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, +{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, +{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, +{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, +{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, +{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, +{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, +{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, +{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, +{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, +{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, +{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, +{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, +{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, @@ -3920,61 +3917,73 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, +{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, +{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, +{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, -{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } }, -{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } }, -{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } }, -{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } }, -{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } }, -{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } }, -{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } }, -{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } }, -{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } }, -{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } }, -{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } }, +{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, +{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, +{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, +{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, +{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, +{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, +{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, +{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, +{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, +{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, +{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } }, -{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } }, -{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } }, -{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } }, -{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } }, -{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } }, -{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } }, -{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } }, -{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } }, -{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } }, -{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } }, -{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } }, -{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } }, +{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, +{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, +{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, +{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, +{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, +{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, +{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, +{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, +{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, +{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, +{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, +{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, +{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, +{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, +{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, +{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, +{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, @@ -4001,61 +4010,45 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, -{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } }, -{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } }, -{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } }, -{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } }, -{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } }, -{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } }, -{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } }, -{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } }, -{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } }, -{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } }, -{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } }, -{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } }, -{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } }, -{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } }, -{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } }, -{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } }, -{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } }, -{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } }, -{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } }, -{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } }, -{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } }, -{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } }, -{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } }, -{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } }, -{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } }, -{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } }, -{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } }, -{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } }, -{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } }, -{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } }, -{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } }, -{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } }, -{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } }, -{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } }, -{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } }, -{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } }, -{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } }, -{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } }, -{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } }, -{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } }, -{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } }, -{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } }, -{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } }, -{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } }, -{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } }, -{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } }, -{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } }, -{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } }, -{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } }, -{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } }, +{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, +{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, +{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, +{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, +{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, +{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, +{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, +{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, +{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, +{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, +{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, +{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, +{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, +{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, +{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, +{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, +{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, +{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, +{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, +{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, +{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, +{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, +{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, +{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, +{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, +{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, +{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, +{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, +{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, +{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, +{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, +{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, +{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, +{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, +{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, @@ -4065,7 +4058,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, -{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }}, +{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, @@ -4144,7 +4137,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } }, -{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } }, +{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, @@ -4202,8 +4195,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } }, -{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } }, -{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } }, +{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, @@ -4247,11 +4239,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mbar", X(31,854), X_MASK, BOOKE, { MO } }, { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, -{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, -{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, - { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } }, { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, @@ -4274,10 +4265,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } }, -{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } }, - { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, +{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } }, { "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } }, { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, @@ -4288,15 +4278,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, -{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } }, - -{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } }, - -{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, +{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, +{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } }, { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } }, +{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, @@ -4305,7 +4293,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, -{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } }, +{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } }, diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c index 7c449f67ad1..b5022cd42d0 100644 --- a/opcodes/v850-dis.c +++ b/opcodes/v850-dis.c @@ -1,20 +1,20 @@ /* Disassemble V850 instructions. - Copyright 1996, 1997, 1998, 2000, 2001, 2002 + Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <stdio.h> @@ -78,6 +78,10 @@ disassemble (memaddr, info, insn) case bfd_mach_v850e: target_processor = PROCESSOR_V850E; break; + + case bfd_mach_v850e1: + target_processor = PROCESSOR_V850E1; + break; } /* Find the opcode. */ diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index 94969ac48f2..2249d16803d 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -1,37 +1,37 @@ /* Assemble V850 instructions. - Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000, 2001, 2003 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" #include "opcode/v850.h" #include <stdio.h> #include "opintl.h" -/* regular opcode */ +/* Regular opcodes. */ #define OP(x) ((x & 0x3f) << 5) #define OP_MASK OP (0x3f) -/* conditional branch opcode */ +/* Conditional branch opcodes. */ #define BOP(x) ((0x0b << 7) | (x & 0x0f)) #define BOP_MASK ((0x0f << 7) | 0x0f) -/* one-word opcodes */ +/* One-word opcodes. */ #define one(x) ((unsigned int) (x)) -/* two-word opcodes */ +/* Two-word opcodes. */ #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **)); @@ -402,15 +402,15 @@ const struct v850_operand v850_operands[] = #define UNUSED 0 { 0, 0, NULL, NULL, 0 }, -/* The R1 field in a format 1, 6, 7, or 9 insn. */ +/* The R1 field in a format 1, 6, 7, or 9 insn. */ #define R1 (UNUSED + 1) { 5, 0, NULL, NULL, V850_OPERAND_REG }, /* As above, but register 0 is not allowed. */ #define R1_NOTR0 (R1 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, + { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, -/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ +/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ #define R2 (R1_NOTR0 + 1) { 5, 11, NULL, NULL, V850_OPERAND_REG }, @@ -418,23 +418,23 @@ const struct v850_operand v850_operands[] = #define R2_NOTR0 (R2 + 1) { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, -/* The imm5 field in a format 2 insn. */ +/* The imm5 field in a format 2 insn. */ #define I5 (R2_NOTR0 + 1) { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, -/* The unsigned imm5 field in a format 2 insn. */ +/* The unsigned imm5 field in a format 2 insn. */ #define I5U (I5 + 1) { 5, 0, NULL, NULL, 0 }, -/* The imm16 field in a format 6 insn. */ +/* The imm16 field in a format 6 insn. */ #define I16 (I5U + 1) { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, -/* The signed disp7 field in a format 4 insn. */ +/* The signed disp7 field in a format 4 insn. */ #define D7 (I16 + 1) { 7, 0, NULL, NULL, 0}, -/* The disp16 field in a format 6 insn. */ +/* The disp16 field in a format 6 insn. */ #define D16_15 (D7 + 1) { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, @@ -446,11 +446,11 @@ const struct v850_operand v850_operands[] = #define CCCC (B3 + 1) { 4, 0, NULL, NULL, V850_OPERAND_CC }, -/* The unsigned DISP8 field in a format 4 insn. */ +/* The unsigned DISP8 field in a format 4 insn. */ #define D8_7 (CCCC + 1) { 7, 0, insert_d8_7, extract_d8_7, 0 }, -/* The unsigned DISP8 field in a format 4 insn. */ +/* The unsigned DISP8 field in a format 4 insn. */ #define D8_6 (D8_7 + 1) { 6, 1, insert_d8_6, extract_d8_6, 0 }, @@ -462,7 +462,7 @@ const struct v850_operand v850_operands[] = #define EP (SR1 + 1) { 0, 0, NULL, NULL, V850_OPERAND_EP }, -/* The imm16 field (unsigned) in a format 6 insn. */ +/* The imm16 field (unsigned) in a format 6 insn. */ #define I16U (EP + 1) { 16, 16, NULL, NULL, 0}, @@ -470,11 +470,11 @@ const struct v850_operand v850_operands[] = #define SR2 (I16U + 1) { 5, 11, NULL, NULL, V850_OPERAND_SRG }, -/* The disp16 field in a format 8 insn. */ +/* The disp16 field in a format 8 insn. */ #define D16 (SR2 + 1) { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, -/* The DISP9 field in a format 3 insn, relaxable. */ +/* The DISP9 field in a format 3 insn, relaxable. */ #define D9_RELAX (D16 + 1) { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, @@ -484,19 +484,19 @@ const struct v850_operand v850_operands[] = #define D22 (D9_RELAX + 1) { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, -/* The signed disp4 field in a format 4 insn. */ +/* The signed disp4 field in a format 4 insn. */ #define D4 (D22 + 1) { 4, 0, NULL, NULL, 0}, -/* The unsigned disp5 field in a format 4 insn. */ +/* The unsigned disp5 field in a format 4 insn. */ #define D5_4 (D4 + 1) { 4, 0, insert_d5_4, extract_d5_4, 0 }, -/* The disp16 field in an format 7 unsigned byte load insn. */ +/* The disp16 field in an format 7 unsigned byte load insn. */ #define D16_16 (D5_4 + 1) { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, -/* Third register in conditional moves. */ +/* Third register in conditional moves. */ #define R3 (D16_16 + 1) { 5, 27, NULL, NULL, V850_OPERAND_REG }, @@ -504,11 +504,11 @@ const struct v850_operand v850_operands[] = #define MOVCC (R3 + 1) { 4, 17, NULL, NULL, V850_OPERAND_CC }, -/* The imm9 field in a multiply word. */ +/* The imm9 field in a multiply word. */ #define I9 (MOVCC + 1) { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, -/* The unsigned imm9 field in a multiply word. */ +/* The unsigned imm9 field in a multiply word. */ #define U9 (I9 + 1) { 9, 0, insert_u9, extract_u9, 0 }, @@ -516,7 +516,7 @@ const struct v850_operand v850_operands[] = #define LIST12 (U9 + 1) { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, -/* The IMM6 field in a call instruction. */ +/* The IMM6 field in a call instruction. */ #define I6 (LIST12 + 1) { 6, 0, NULL, NULL, 0 }, @@ -528,19 +528,19 @@ const struct v850_operand v850_operands[] = #define IMM32 (IMM16 + 1) { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, -/* The imm5 field in a push/pop instruction. */ +/* The imm5 field in a push/pop instruction. */ #define IMM5 (IMM32 + 1) { 5, 1, NULL, NULL, 0 }, -/* Reg2 in dispose instruction. */ +/* Reg2 in dispose instruction. */ #define R2DISPOSE (IMM5 + 1) { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, -/* Stack pointer in prepare instruction. */ +/* Stack pointer in prepare instruction. */ #define SP (R2DISPOSE + 1) { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, -/* The IMM5 field in a divide N step instruction. */ +/* The IMM5 field in a divide N step instruction. */ #define I5DIV (SP + 1) { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, @@ -550,23 +550,24 @@ const struct v850_operand v850_operands[] = /* The list of registers in a PUSHML/POPML instruction. */ #define LIST18_L (LIST18_H + 1) - { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ + /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c. */ + { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, } ; -/* reg-reg instruction format (Format I) */ +/* Reg - Reg instruction format (Format I). */ #define IF1 {R1, R2} -/* imm-reg instruction format (Format II) */ +/* Imm - Reg instruction format (Format II). */ #define IF2 {I5, R2} -/* conditional branch instruction format (Format III) */ +/* Conditional branch instruction format (Format III). */ #define IF3 {D9_RELAX} -/* 3 operand instruction (Format VI) */ +/* 3 operand instruction (Format VI). */ #define IF6 {I16, R1, R2} -/* 3 operand instruction (Format VI) */ +/* 3 operand instruction (Format VI). */ #define IF6U {I16U, R1, R2} @@ -604,17 +605,22 @@ const struct v850_operand v850_operands[] = const struct v850_opcode v850_opcodes[] = { { "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, +{ "dbtrap", one (0xf840), one (0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, -/* load/store instructions */ +/* Load/store instructions. */ +{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, +{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, +{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E1 }, { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, +{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E1 }, { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, @@ -639,7 +645,7 @@ const struct v850_opcode v850_opcodes[] = { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, -/* byte swap/extend instructions */ +/* Byte swap/extend instructions. */ { "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, { "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, { "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, @@ -648,12 +654,12 @@ const struct v850_opcode v850_opcodes[] = { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -/* jump table instructions */ +/* Jump table instructions. */ { "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, { "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, -/* arithmetic operation instructions */ +/* Arithmetic operation instructions. */ { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, @@ -686,14 +692,14 @@ const struct v850_opcode v850_opcodes[] = { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, -/* saturated operation instructions */ +/* Saturated operation instructions. */ { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -/* logical operation instructions */ +/* Logical operation instructions. */ { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, @@ -710,21 +716,21 @@ const struct v850_opcode v850_opcodes[] = { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, -/* branch instructions */ - /* signed integer */ +/* Branch instructions. */ + /* Signed integer. */ { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ + /* Unsigned integer. */ { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ + /* Common. */ { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ + /* Others. */ { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, @@ -741,20 +747,20 @@ const struct v850_opcode v850_opcodes[] = We use the short form in the opcode/mask fields. The assembler will twiddle bits as necessary if the long form is needed. */ - /* signed integer */ + /* Signed integer. */ { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ + /* Unsigned integer. */ { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ + /* Common. */ { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ + /* Others. */ { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, @@ -769,7 +775,7 @@ const struct v850_opcode v850_opcodes[] = { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, { "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, -/* bit manipulation instructions */ +/* Bit manipulation instructions. */ { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, @@ -779,7 +785,7 @@ const struct v850_opcode v850_opcodes[] = { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* special instructions */ +/* Special instructions. */ { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, @@ -787,10 +793,10 @@ const struct v850_opcode v850_opcodes[] = { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, +{ "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, { 0, 0, 0, {0}, 0, 0 }, } ; const int v850_num_opcodes = sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); - diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c index 810938c4a93..618e33b2f07 100644 --- a/opcodes/xstormy16-asm.c +++ b/opcodes/xstormy16-asm.c @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -317,8 +317,7 @@ xstormy16_cgen_init_asm (cd) Returns NULL for success, an error message for failure. */ char * -xstormy16_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +xstormy16_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -441,11 +440,10 @@ xstormy16_cgen_build_insn_regex (insn) Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -583,12 +581,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +xstormy16_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -692,9 +689,7 @@ xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg) FIXME: Not currently used. */ void -xstormy16_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +xstormy16_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c index 17c54a68a15..54af2571ab5 100644 --- a/opcodes/xstormy16-dis.c +++ b/opcodes/xstormy16-dis.c @@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ @@ -194,13 +193,12 @@ xstormy16_cgen_init_dis (cd) /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -220,13 +218,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -250,12 +247,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -269,17 +265,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -311,14 +306,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -342,12 +336,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -452,10 +445,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -494,9 +484,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_xstormy16 (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/opcodes/xstormy16-ibld.c b/opcodes/xstormy16-ibld.c index 0e4876a6f48..13433e0ea63 100644 --- a/opcodes/xstormy16-ibld.c +++ b/opcodes/xstormy16-ibld.c @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; |