diff options
author | Jan Beulich <jbeulich@novell.com> | 2008-02-13 13:29:31 +0000 |
---|---|---|
committer | Jan Beulich <jbeulich@novell.com> | 2008-02-13 13:29:31 +0000 |
commit | 942f2129223fff848732740896281f8271eac2ac (patch) | |
tree | fbe951bdaac715b410cd5167bc7136d46c760108 /opcodes | |
parent | a7d5fd7b6d18773a0a0c2261ef3f77dcf68505d3 (diff) | |
download | gdb-942f2129223fff848732740896281f8271eac2ac.tar.gz |
gas/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (intel_e09): Also special-case 'bound'.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests.
* gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e,
gas/i386/opcode-intel.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (a_mode): New.
(cond_jump_mode): Adjust.
(Ma): Change to a_mode.
(intel_operand_size): Handle a_mode.
* i386-opc.tbl: Allow Dword and Qword for bound.
* i386-tbl.h: Re-generate.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 9 | ||||
-rw-r--r-- | opcodes/i386-dis.c | 13 | ||||
-rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
-rw-r--r-- | opcodes/i386-tbl.h | 2 |
4 files changed, 22 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 233ceab49ac..a2d9646e18c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,14 @@ 2008-02-13 Jan Beulich <jbeulich@novell.com> + * i386-dis.c (a_mode): New. + (cond_jump_mode): Adjust. + (Ma): Change to a_mode. + (intel_operand_size): Handle a_mode. + * i386-opc.tbl: Allow Dword and Qword for bound. + * i386-tbl.h: Re-generate. + +2008-02-13 Jan Beulich <jbeulich@novell.com> + * i386-gen.c (process_i386_registers): Process new fields. * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to unsigned char. Add dw2_regnum and Dw2Inval. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 149bafb74e2..cb6a171edd4 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -231,7 +231,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Em { OP_E, m_mode } #define Ew { OP_E, w_mode } #define M { OP_M, 0 } /* lea, lgdt, etc. */ -#define Ma { OP_M, v_mode } +#define Ma { OP_M, a_mode } #define Mb { OP_M, b_mode } #define Md { OP_M, d_mode } #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ @@ -378,7 +378,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define x_mode (t_mode + 1) /* d_mode in 32bit, q_mode in 64bit mode. */ #define m_mode (x_mode + 1) -#define cond_jump_mode (m_mode + 1) +/* pair of v_mode operands */ +#define a_mode (m_mode + 1) +#define cond_jump_mode (a_mode + 1) #define loop_jcxz_mode (cond_jump_mode + 1) /* operand size depends on REX prefixes. */ #define dq_mode (loop_jcxz_mode + 1) @@ -6544,6 +6546,13 @@ intel_operand_size (int bytemode, int sizeflag) if (!(rex & REX_W)) used_prefixes |= (prefixes & PREFIX_DATA); break; + case a_mode: + if (sizeflag & DFLAG) + oappend ("QWORD PTR "); + else + oappend ("DWORD PTR "); + used_prefixes |= (prefixes & PREFIX_DATA); + break; case d_mode: case dqd_mode: oappend ("DWORD PTR "); diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 7bc61c915dd..6ec8f29140e 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -488,7 +488,7 @@ iret, 0, 0xcf, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 } // i386sl, i486sl, later 486, and Pentium. rsm, 0, 0xfaa, None, 2, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } -bound, 2, 0x62, None, 1, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +bound, 2, 0x62, None, 1, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } hlt, 0, 0xf4, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 128502ba7f2..13ad14fc28d 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -3713,7 +3713,7 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, - 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0 } } } }, { "hlt", 0, 0xf4, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |