bfd:

	Add ms2.
	* archures.c (bfd_mach_ms2): Define.
	* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
	* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
	(ms1_elf_merge_private_bfd_data): Remove unused variables.  Add
	correct merging logic, with workaround.
	(ms1_elf_print_private_bfd_data): Add ms2 case.
	* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.

cpu:
	Add ms2
	* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
	model.
	(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
	f-cb2incr, f-rc3): New fields.
	(LOOP): New instruction.
	(JAL-HAZARD): New hazard.
	(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
	New operands.
	(mul, muli, dbnz, iflush): Enable for ms2
	(jal, reti): Has JAL-HAZARD.
	(ldctxt, ldfb, stfb): Only ms1.
	(fbcb): Only ms1,ms1-003.
	(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
	fbcbincrs, mfbcbincrs): Enable for ms2.
	(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
	* ms1.opc (parse_loopsize): New.
	(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
	(print_pcrel): New.

gas:
	Add ms2.
	* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
	(ms1_architectures): Add ms2.
	(md_parse_option): Add ms2.
	(md_show_usage): Add ms2.
	(md_assemble): Add JAL_HAZARD detection logic.
	(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
	* doc/c-ms1.texi: New.
	* doc/all.texi: Add MS1.
	* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
	* doc/Makefile.in: Rebuilt.
	* doc/Makefile: Rebuilt.

gas/testsuite:
	Add ms2.
	* gas/ms1/allinsn.d: Adjust pcrel disassembly.
	* gas/ms1/errors.exp: Fix target triplet.
	* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
	* gas/ms1/ms1-16-003.s: Tweak label.
	* gas/ms1/ms1.exp: Adjust target triplet.  Add ms2 test.
	* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
	* gas/ms1/relocs.d: Adjust expected machine name and pcrel
	disassembly.
	* gas/ms1/relocs.exp: Adjust target triplet.

include:
	Add ms2.
	* elf/ms1.h (EF_MS1_CPU_MS2): New.


opcodes:
	Add ms2.
	* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
	ms1-opc.c, ms1-opc.h: Regenerated.

8 files changed, 410 insertions, 46 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index de1a1645f4c..c36d8be18bf 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Add ms2.
+	* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
+	ms1-opc.c, ms1-opc.h: Regenerated.
+
 2005-11-07  Steve Ellcey  <sje@cup.hp.com>
 
 	* configure: Regenerate after modifying bfd/warning.m4.
diff --git a/opcodes/ms1-asm.c b/opcodes/ms1-asm.c
index 528a0d5eebe..177198e4991 100644
--- a/opcodes/ms1-asm.c
+++ b/opcodes/ms1-asm.c
@@ -61,6 +61,31 @@ signed_out_of_bounds (long val)
 }
 
 static const char *
+parse_loopsize (CGEN_CPU_DESC cd,
+		const char **strp,
+		int opindex,
+		void *arg)
+{
+  signed long * valuep = (signed long *) arg;
+  const char *errmsg;
+  bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  /* Is it a control transfer instructions?  */ 
+  if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE)
+    {
+      code = BFD_RELOC_MS1_PCINSN8;
+      errmsg = cgen_parse_address (cd, strp, opindex, code,
+                                   & result_type, & value);
+      *valuep = value;
+      return errmsg;
+    }
+
+  abort ();
+}
+
+static const char *
 parse_imm16 (CGEN_CPU_DESC cd,
 	     const char **strp,
 	     int opindex,
@@ -89,7 +114,9 @@ parse_imm16 (CGEN_CPU_DESC cd,
 
   /* If it's not a control transfer instruction, then
      we have to check for %OP relocating operators.  */
-  if (strncmp (*strp, "%hi16", 5) == 0)
+  if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L)
+    ;
+  else if (strncmp (*strp, "%hi16", 5) == 0)
     {
       *strp += 5;
       code = BFD_RELOC_HI16;
@@ -417,6 +444,18 @@ ms1_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_BRC2 :
       errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2));
       break;
+    case MS1_OPERAND_CB1INCR :
+      errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB1INCR, (long *) (& fields->f_cb1incr));
+      break;
+    case MS1_OPERAND_CB1SEL :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB1SEL, (unsigned long *) (& fields->f_cb1sel));
+      break;
+    case MS1_OPERAND_CB2INCR :
+      errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB2INCR, (long *) (& fields->f_cb2incr));
+      break;
+    case MS1_OPERAND_CB2SEL :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB2SEL, (unsigned long *) (& fields->f_cb2sel));
+      break;
     case MS1_OPERAND_CBRB :
       errmsg = parse_cbrb (cd, strp, MS1_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb));
       break;
@@ -474,6 +513,9 @@ ms1_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_IMM16 :
       errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16, (long *) (& fields->f_imm16s));
       break;
+    case MS1_OPERAND_IMM16L :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_IMM16L, (unsigned long *) (& fields->f_imm16l));
+      break;
     case MS1_OPERAND_IMM16O :
       errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s));
       break;
@@ -489,6 +531,9 @@ ms1_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_LENGTH :
       errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_LENGTH, (unsigned long *) (& fields->f_length));
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      errmsg = parse_loopsize (cd, strp, MS1_OPERAND_LOOPSIZE, (unsigned long *) (& fields->f_loopo));
+      break;
     case MS1_OPERAND_MASK :
       errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK, (unsigned long *) (& fields->f_mask));
       break;
@@ -513,6 +558,9 @@ ms1_cgen_parse_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_RC2 :
       errmsg = parse_rc (cd, strp, MS1_OPERAND_RC2, (unsigned long *) (& fields->f_rc2));
       break;
+    case MS1_OPERAND_RC3 :
+      errmsg = parse_rc (cd, strp, MS1_OPERAND_RC3, (unsigned long *) (& fields->f_rc3));
+      break;
     case MS1_OPERAND_RCNUM :
       errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum));
       break;
diff --git a/opcodes/ms1-desc.c b/opcodes/ms1-desc.c
index c48a8a89c85..6dbff2e557a 100644
--- a/opcodes/ms1-desc.c
+++ b/opcodes/ms1-desc.c
@@ -48,6 +48,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
   { "base", MACH_BASE },
   { "ms1", MACH_MS1 },
   { "ms1_003", MACH_MS1_003 },
+  { "ms2", MACH_MS2 },
   { "max", MACH_MAX },
   { 0, 0 }
 };
@@ -113,6 +114,7 @@ const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[] =
   { "AL-INSN", &bool_attr[0], &bool_attr[0] },
   { "IO-INSN", &bool_attr[0], &bool_attr[0] },
   { "BR-INSN", &bool_attr[0], &bool_attr[0] },
+  { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] },
   { "USES-FRDR", &bool_attr[0], &bool_attr[0] },
   { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] },
   { "USES-FRSR1", &bool_attr[0], &bool_attr[0] },
@@ -133,6 +135,7 @@ static const CGEN_ISA ms1_cgen_isa_table[] = {
 static const CGEN_MACH ms1_cgen_mach_table[] = {
   { "ms1", "ms1", MACH_MS1, 0 },
   { "ms1-003", "ms1-003", MACH_MS1_003, 0 },
+  { "ms2", "ms2", MACH_MS2, 0 },
   { 0, 0, 0, 0 }
 };
 
@@ -230,7 +233,9 @@ const CGEN_IFLD ms1_cgen_ifld_table[] =
   { MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
@@ -280,6 +285,13 @@ const CGEN_IFLD ms1_cgen_ifld_table[] =
   { MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
   { MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
@@ -343,7 +355,7 @@ const CGEN_OPERAND ms1_cgen_operand_table[] =
 /* imm16o: immediate value */
   { "imm16o", MS1_OPERAND_IMM16O, HW_H_UINT, 15, 16,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } }, 
-    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* rc: rc */
   { "rc", MS1_OPERAND_RC, HW_H_UINT, 15, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC] } }, 
@@ -504,6 +516,34 @@ const CGEN_OPERAND ms1_cgen_operand_table[] =
   { "fbincr", MS1_OPERAND_FBINCR, HW_H_UINT, 23, 4,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBINCR] } }, 
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* loopsize: immediate value */
+  { "loopsize", MS1_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
+    { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_LOOPO] } }, 
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } }  },
+/* imm16l: immediate value */
+  { "imm16l", MS1_OPERAND_IMM16L, HW_H_UINT, 23, 16,
+    { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16L] } }, 
+    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
+/* rc3: rc3 */
+  { "rc3", MS1_OPERAND_RC3, HW_H_UINT, 7, 1,
+    { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC3] } }, 
+    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
+/* cb1sel: cb1sel */
+  { "cb1sel", MS1_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
+    { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB1SEL] } }, 
+    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
+/* cb2sel: cb2sel */
+  { "cb2sel", MS1_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
+    { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB2SEL] } }, 
+    { 0, { { { (1<<MACH_MS2), 0 } } } }  },
+/* cb1incr: cb1incr */
+  { "cb1incr", MS1_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
+    { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB1INCR] } }, 
+    { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
+/* cb2incr: cb2incr */
+  { "cb2incr", MS1_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
+    { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB2INCR] } }, 
+    { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
@@ -571,12 +611,12 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
 /* mul $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_MUL, "mul", "mul", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* muli $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_MULI, "muli", "muli", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* and $frdrrr,$frsr1,$frsr2 */
   {
@@ -706,12 +746,12 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
 /* jal $frdrrr,$frsr1 */
   {
     MS1_INSN_JAL, "jal", "jal", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dbnz $frsr1,$imm16o */
   {
     MS1_INSN_DBNZ, "dbnz", "dbnz", 32,
-    { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* ei */
   {
@@ -731,7 +771,7 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
 /* reti $frsr1 */
   {
     MS1_INSN_RETI, "reti", "reti", 32,
-    { 0|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
+    { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldw $frdr,$frsr1,#$imm16 */
   {
@@ -751,27 +791,27 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
 /* iflush */
   {
     MS1_INSN_IFLUSH, "iflush", "iflush", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
   {
     MS1_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
-    { 0, { { { (1<<MACH_BASE), 0 } } } }
+    { 0, { { { (1<<MACH_MS1), 0 } } } }
   },
 /* ldfb $frsr1,$frsr2,#$imm16z */
   {
     MS1_INSN_LDFB, "ldfb", "ldfb", 32,
-    { 0, { { { (1<<MACH_BASE), 0 } } } }
+    { 0, { { { (1<<MACH_MS1), 0 } } } }
   },
 /* stfb $frsr1,$frsr2,#$imm16z */
   {
     MS1_INSN_STFB, "stfb", "stfb", 32,
-    { 0, { { { (1<<MACH_BASE), 0 } } } }
+    { 0, { { { (1<<MACH_MS1), 0 } } } }
   },
 /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCB, "fbcb", "fbcb", 32,
-    { 0, { { { (1<<MACH_BASE), 0 } } } }
+    { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } }
   },
 /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
@@ -876,42 +916,72 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
 /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_WFBINC, "wfbinc", "wfbinc", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
   },
 /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
-    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
+    { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
+  },
+/* loop $frsr1,$loopsize */
+  {
+    MS1_INSN_LOOP, "loop", "loop", 32,
+    { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
+  },
+/* loopi #$imm16l,$loopsize */
+  {
+    MS1_INSN_LOOPI, "loopi", "loopi", 32,
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
+  },
+/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+  {
+    MS1_INSN_DFBC, "dfbc", "dfbc", 32,
+    { 0, { { { (1<<MACH_MS2), 0 } } } }
+  },
+/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
+  {
+    MS1_INSN_DWFB, "dwfb", "dwfb", 32,
+    { 0, { { { (1<<MACH_MS2), 0 } } } }
+  },
+/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+  {
+    MS1_INSN_FBWFB, "fbwfb", "fbwfb", 32,
+    { 0, { { { (1<<MACH_MS2), 0 } } } }
+  },
+/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
+  {
+    MS1_INSN_DFBR, "dfbr", "dfbr", 32,
+    { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } }
   },
 };
 
diff --git a/opcodes/ms1-desc.h b/opcodes/ms1-desc.h
index 4a3dd2f5e21..909b32388af 100644
--- a/opcodes/ms1-desc.h
+++ b/opcodes/ms1-desc.h
@@ -40,6 +40,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Selected cpu families.  */
 #define HAVE_CPU_MS1BF
 #define HAVE_CPU_MS1_003BF
+#define HAVE_CPU_MS2BF
 
 #define CGEN_INSN_LSB0_P 1
 
@@ -76,9 +77,9 @@ typedef enum insn_opc {
  , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
  , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
  , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
- , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LDW = 32, OPC_STW = 33
- , OPC_EI = 48, OPC_DI = 49, OPC_SI = 50, OPC_RETI = 51
- , OPC_BREAK = 52, OPC_IFLUSH = 53
+ , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32
+ , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50
+ , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53
 } INSN_OPC;
 
 /* Enum declaration for msopc enums.  */
@@ -107,7 +108,8 @@ typedef enum msys_syms {
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MAX
+  MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2
+ , MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -148,20 +150,22 @@ typedef enum ifield_type {
  , MS1_F_IMM, MS1_F_UU24, MS1_F_SR1, MS1_F_SR2
  , MS1_F_DR, MS1_F_DRRR, MS1_F_IMM16U, MS1_F_IMM16S
  , MS1_F_IMM16A, MS1_F_UU4A, MS1_F_UU4B, MS1_F_UU12
- , MS1_F_UU16, MS1_F_MSOPC, MS1_F_UU_26_25, MS1_F_MASK
- , MS1_F_BANKADDR, MS1_F_RDA, MS1_F_UU_2_25, MS1_F_RBBC
- , MS1_F_PERM, MS1_F_MODE, MS1_F_UU_1_24, MS1_F_WR
- , MS1_F_FBINCR, MS1_F_UU_2_23, MS1_F_XMODE, MS1_F_A23
- , MS1_F_MASK1, MS1_F_CR, MS1_F_TYPE, MS1_F_INCAMT
- , MS1_F_CBS, MS1_F_UU_1_19, MS1_F_BALL, MS1_F_COLNUM
- , MS1_F_BRC, MS1_F_INCR, MS1_F_FBDISP, MS1_F_UU_4_15
- , MS1_F_LENGTH, MS1_F_UU_1_15, MS1_F_RC, MS1_F_RCNUM
- , MS1_F_ROWNUM, MS1_F_CBX, MS1_F_ID, MS1_F_SIZE
- , MS1_F_ROWNUM1, MS1_F_UU_3_11, MS1_F_RC1, MS1_F_CCB
- , MS1_F_CBRB, MS1_F_CDB, MS1_F_ROWNUM2, MS1_F_CELL
- , MS1_F_UU_3_9, MS1_F_CONTNUM, MS1_F_UU_1_6, MS1_F_DUP
- , MS1_F_RC2, MS1_F_CTXDISP, MS1_F_MSYSFRSR2, MS1_F_BRC2
- , MS1_F_BALL2, MS1_F_MAX
+ , MS1_F_UU8, MS1_F_UU16, MS1_F_UU1, MS1_F_MSOPC
+ , MS1_F_UU_26_25, MS1_F_MASK, MS1_F_BANKADDR, MS1_F_RDA
+ , MS1_F_UU_2_25, MS1_F_RBBC, MS1_F_PERM, MS1_F_MODE
+ , MS1_F_UU_1_24, MS1_F_WR, MS1_F_FBINCR, MS1_F_UU_2_23
+ , MS1_F_XMODE, MS1_F_A23, MS1_F_MASK1, MS1_F_CR
+ , MS1_F_TYPE, MS1_F_INCAMT, MS1_F_CBS, MS1_F_UU_1_19
+ , MS1_F_BALL, MS1_F_COLNUM, MS1_F_BRC, MS1_F_INCR
+ , MS1_F_FBDISP, MS1_F_UU_4_15, MS1_F_LENGTH, MS1_F_UU_1_15
+ , MS1_F_RC, MS1_F_RCNUM, MS1_F_ROWNUM, MS1_F_CBX
+ , MS1_F_ID, MS1_F_SIZE, MS1_F_ROWNUM1, MS1_F_UU_3_11
+ , MS1_F_RC1, MS1_F_CCB, MS1_F_CBRB, MS1_F_CDB
+ , MS1_F_ROWNUM2, MS1_F_CELL, MS1_F_UU_3_9, MS1_F_CONTNUM
+ , MS1_F_UU_1_6, MS1_F_DUP, MS1_F_RC2, MS1_F_CTXDISP
+ , MS1_F_IMM16L, MS1_F_LOOPO, MS1_F_CB1SEL, MS1_F_CB2SEL
+ , MS1_F_CB1INCR, MS1_F_CB2INCR, MS1_F_RC3, MS1_F_MSYSFRSR2
+ , MS1_F_BRC2, MS1_F_BALL2, MS1_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) MS1_F_MAX)
@@ -229,11 +233,12 @@ typedef enum cgen_operand_type {
  , MS1_OPERAND_A23, MS1_OPERAND_CR, MS1_OPERAND_CBS, MS1_OPERAND_INCR
  , MS1_OPERAND_LENGTH, MS1_OPERAND_CBX, MS1_OPERAND_CCB, MS1_OPERAND_CDB
  , MS1_OPERAND_MODE, MS1_OPERAND_ID, MS1_OPERAND_SIZE, MS1_OPERAND_FBINCR
- , MS1_OPERAND_MAX
+ , MS1_OPERAND_LOOPSIZE, MS1_OPERAND_IMM16L, MS1_OPERAND_RC3, MS1_OPERAND_CB1SEL
+ , MS1_OPERAND_CB2SEL, MS1_OPERAND_CB1INCR, MS1_OPERAND_CB2INCR, MS1_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 48
+#define MAX_OPERANDS 55
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 8
@@ -245,9 +250,10 @@ typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
- , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_USES_FRDR
- , CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD
+ , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2
+ , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
+ , CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn_attr.  */
@@ -270,6 +276,7 @@ typedef enum cgen_insn_attr {
 #define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0)
 #define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0)
 #define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_JAL_HAZARD)) != 0)
 #define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0)
 #define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0)
 #define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0)
diff --git a/opcodes/ms1-dis.c b/opcodes/ms1-dis.c
index 0026124f7db..bc020de16f5 100644
--- a/opcodes/ms1-dis.c
+++ b/opcodes/ms1-dis.c
@@ -60,6 +60,7 @@ static int read_insn
 
 /* -- dis.c */
 static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
+static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
 
 static void
 print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -77,6 +78,16 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     print_normal (cd, dis_info, value, attrs, pc, length);
 }
 
+static void
+print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	     void * dis_info,
+	     long value,
+	     unsigned int attrs ATTRIBUTE_UNUSED,
+	     bfd_vma pc ATTRIBUTE_UNUSED,
+	     int length ATTRIBUTE_UNUSED)
+{
+  print_address (cd, dis_info, value + pc, attrs, pc, length);
+}
 
 /* -- */
 
@@ -129,6 +140,18 @@ ms1_cgen_print_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_BRC2 :
       print_dollarhex (cd, info, fields->f_brc2, 0, pc, length);
       break;
+    case MS1_OPERAND_CB1INCR :
+      print_dollarhex (cd, info, fields->f_cb1incr, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case MS1_OPERAND_CB1SEL :
+      print_dollarhex (cd, info, fields->f_cb1sel, 0, pc, length);
+      break;
+    case MS1_OPERAND_CB2INCR :
+      print_dollarhex (cd, info, fields->f_cb2incr, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case MS1_OPERAND_CB2SEL :
+      print_dollarhex (cd, info, fields->f_cb2sel, 0, pc, length);
+      break;
     case MS1_OPERAND_CBRB :
       print_dollarhex (cd, info, fields->f_cbrb, 0, pc, length);
       break;
@@ -186,8 +209,11 @@ ms1_cgen_print_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_IMM16 :
       print_dollarhex (cd, info, fields->f_imm16s, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
+    case MS1_OPERAND_IMM16L :
+      print_dollarhex (cd, info, fields->f_imm16l, 0, pc, length);
+      break;
     case MS1_OPERAND_IMM16O :
-      print_dollarhex (cd, info, fields->f_imm16s, 0, pc, length);
+      print_pcrel (cd, info, fields->f_imm16s, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
       break;
     case MS1_OPERAND_IMM16Z :
       print_dollarhex (cd, info, fields->f_imm16u, 0, pc, length);
@@ -201,6 +227,9 @@ ms1_cgen_print_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_LENGTH :
       print_dollarhex (cd, info, fields->f_length, 0, pc, length);
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      print_pcrel (cd, info, fields->f_loopo, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
     case MS1_OPERAND_MASK :
       print_dollarhex (cd, info, fields->f_mask, 0, pc, length);
       break;
@@ -225,6 +254,9 @@ ms1_cgen_print_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_RC2 :
       print_dollarhex (cd, info, fields->f_rc2, 0, pc, length);
       break;
+    case MS1_OPERAND_RC3 :
+      print_dollarhex (cd, info, fields->f_rc3, 0, pc, length);
+      break;
     case MS1_OPERAND_RCNUM :
       print_dollarhex (cd, info, fields->f_rcnum, 0, pc, length);
       break;
diff --git a/opcodes/ms1-ibld.c b/opcodes/ms1-ibld.c
index 3ffbd84f54b..4640211ffce 100644
--- a/opcodes/ms1-ibld.c
+++ b/opcodes/ms1-ibld.c
@@ -576,6 +576,18 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_BRC2 :
       errmsg = insert_normal (cd, fields->f_brc2, 0, 0, 14, 3, 32, total_length, buffer);
       break;
+    case MS1_OPERAND_CB1INCR :
+      errmsg = insert_normal (cd, fields->f_cb1incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, buffer);
+      break;
+    case MS1_OPERAND_CB1SEL :
+      errmsg = insert_normal (cd, fields->f_cb1sel, 0, 0, 25, 3, 32, total_length, buffer);
+      break;
+    case MS1_OPERAND_CB2INCR :
+      errmsg = insert_normal (cd, fields->f_cb2incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, buffer);
+      break;
+    case MS1_OPERAND_CB2SEL :
+      errmsg = insert_normal (cd, fields->f_cb2sel, 0, 0, 22, 3, 32, total_length, buffer);
+      break;
     case MS1_OPERAND_CBRB :
       errmsg = insert_normal (cd, fields->f_cbrb, 0, 0, 10, 1, 32, total_length, buffer);
       break;
@@ -637,6 +649,9 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
       }
       break;
+    case MS1_OPERAND_IMM16L :
+      errmsg = insert_normal (cd, fields->f_imm16l, 0, 0, 23, 16, 32, total_length, buffer);
+      break;
     case MS1_OPERAND_IMM16O :
       {
         long value = fields->f_imm16s;
@@ -656,6 +671,13 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_LENGTH :
       errmsg = insert_normal (cd, fields->f_length, 0, 0, 15, 3, 32, total_length, buffer);
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      {
+        long value = fields->f_loopo;
+        value = ((unsigned int) (value) >> (2));
+        errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer);
+      }
+      break;
     case MS1_OPERAND_MASK :
       errmsg = insert_normal (cd, fields->f_mask, 0, 0, 25, 16, 32, total_length, buffer);
       break;
@@ -680,6 +702,9 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_RC2 :
       errmsg = insert_normal (cd, fields->f_rc2, 0, 0, 6, 1, 32, total_length, buffer);
       break;
+    case MS1_OPERAND_RC3 :
+      errmsg = insert_normal (cd, fields->f_rc3, 0, 0, 7, 1, 32, total_length, buffer);
+      break;
     case MS1_OPERAND_RCNUM :
       errmsg = insert_normal (cd, fields->f_rcnum, 0, 0, 14, 3, 32, total_length, buffer);
       break;
@@ -768,6 +793,18 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_BRC2 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_brc2);
       break;
+    case MS1_OPERAND_CB1INCR :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, pc, & fields->f_cb1incr);
+      break;
+    case MS1_OPERAND_CB1SEL :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_cb1sel);
+      break;
+    case MS1_OPERAND_CB2INCR :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, pc, & fields->f_cb2incr);
+      break;
+    case MS1_OPERAND_CB2SEL :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cb2sel);
+      break;
     case MS1_OPERAND_CBRB :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cbrb);
       break;
@@ -830,6 +867,9 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
         fields->f_imm16s = value;
       }
       break;
+    case MS1_OPERAND_IMM16L :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 16, 32, total_length, pc, & fields->f_imm16l);
+      break;
     case MS1_OPERAND_IMM16O :
       {
         long value;
@@ -850,6 +890,14 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_LENGTH :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_length);
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value);
+        value = ((((value) << (2))) + (8));
+        fields->f_loopo = value;
+      }
+      break;
     case MS1_OPERAND_MASK :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 16, 32, total_length, pc, & fields->f_mask);
       break;
@@ -874,6 +922,9 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
     case MS1_OPERAND_RC2 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_rc2);
       break;
+    case MS1_OPERAND_RC3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_rc3);
+      break;
     case MS1_OPERAND_RCNUM :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rcnum);
       break;
@@ -957,6 +1008,18 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_BRC2 :
       value = fields->f_brc2;
       break;
+    case MS1_OPERAND_CB1INCR :
+      value = fields->f_cb1incr;
+      break;
+    case MS1_OPERAND_CB1SEL :
+      value = fields->f_cb1sel;
+      break;
+    case MS1_OPERAND_CB2INCR :
+      value = fields->f_cb2incr;
+      break;
+    case MS1_OPERAND_CB2SEL :
+      value = fields->f_cb2sel;
+      break;
     case MS1_OPERAND_CBRB :
       value = fields->f_cbrb;
       break;
@@ -1014,6 +1077,9 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_IMM16 :
       value = fields->f_imm16s;
       break;
+    case MS1_OPERAND_IMM16L :
+      value = fields->f_imm16l;
+      break;
     case MS1_OPERAND_IMM16O :
       value = fields->f_imm16s;
       break;
@@ -1029,6 +1095,9 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_LENGTH :
       value = fields->f_length;
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      value = fields->f_loopo;
+      break;
     case MS1_OPERAND_MASK :
       value = fields->f_mask;
       break;
@@ -1053,6 +1122,9 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_RC2 :
       value = fields->f_rc2;
       break;
+    case MS1_OPERAND_RC3 :
+      value = fields->f_rc3;
+      break;
     case MS1_OPERAND_RCNUM :
       value = fields->f_rcnum;
       break;
@@ -1118,6 +1190,18 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_BRC2 :
       value = fields->f_brc2;
       break;
+    case MS1_OPERAND_CB1INCR :
+      value = fields->f_cb1incr;
+      break;
+    case MS1_OPERAND_CB1SEL :
+      value = fields->f_cb1sel;
+      break;
+    case MS1_OPERAND_CB2INCR :
+      value = fields->f_cb2incr;
+      break;
+    case MS1_OPERAND_CB2SEL :
+      value = fields->f_cb2sel;
+      break;
     case MS1_OPERAND_CBRB :
       value = fields->f_cbrb;
       break;
@@ -1175,6 +1259,9 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_IMM16 :
       value = fields->f_imm16s;
       break;
+    case MS1_OPERAND_IMM16L :
+      value = fields->f_imm16l;
+      break;
     case MS1_OPERAND_IMM16O :
       value = fields->f_imm16s;
       break;
@@ -1190,6 +1277,9 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_LENGTH :
       value = fields->f_length;
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      value = fields->f_loopo;
+      break;
     case MS1_OPERAND_MASK :
       value = fields->f_mask;
       break;
@@ -1214,6 +1304,9 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_RC2 :
       value = fields->f_rc2;
       break;
+    case MS1_OPERAND_RC3 :
+      value = fields->f_rc3;
+      break;
     case MS1_OPERAND_RCNUM :
       value = fields->f_rcnum;
       break;
@@ -1286,6 +1379,18 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_BRC2 :
       fields->f_brc2 = value;
       break;
+    case MS1_OPERAND_CB1INCR :
+      fields->f_cb1incr = value;
+      break;
+    case MS1_OPERAND_CB1SEL :
+      fields->f_cb1sel = value;
+      break;
+    case MS1_OPERAND_CB2INCR :
+      fields->f_cb2incr = value;
+      break;
+    case MS1_OPERAND_CB2SEL :
+      fields->f_cb2sel = value;
+      break;
     case MS1_OPERAND_CBRB :
       fields->f_cbrb = value;
       break;
@@ -1343,6 +1448,9 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_IMM16 :
       fields->f_imm16s = value;
       break;
+    case MS1_OPERAND_IMM16L :
+      fields->f_imm16l = value;
+      break;
     case MS1_OPERAND_IMM16O :
       fields->f_imm16s = value;
       break;
@@ -1358,6 +1466,9 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_LENGTH :
       fields->f_length = value;
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      fields->f_loopo = value;
+      break;
     case MS1_OPERAND_MASK :
       fields->f_mask = value;
       break;
@@ -1382,6 +1493,9 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_RC2 :
       fields->f_rc2 = value;
       break;
+    case MS1_OPERAND_RC3 :
+      fields->f_rc3 = value;
+      break;
     case MS1_OPERAND_RCNUM :
       fields->f_rcnum = value;
       break;
@@ -1444,6 +1558,18 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_BRC2 :
       fields->f_brc2 = value;
       break;
+    case MS1_OPERAND_CB1INCR :
+      fields->f_cb1incr = value;
+      break;
+    case MS1_OPERAND_CB1SEL :
+      fields->f_cb1sel = value;
+      break;
+    case MS1_OPERAND_CB2INCR :
+      fields->f_cb2incr = value;
+      break;
+    case MS1_OPERAND_CB2SEL :
+      fields->f_cb2sel = value;
+      break;
     case MS1_OPERAND_CBRB :
       fields->f_cbrb = value;
       break;
@@ -1501,6 +1627,9 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_IMM16 :
       fields->f_imm16s = value;
       break;
+    case MS1_OPERAND_IMM16L :
+      fields->f_imm16l = value;
+      break;
     case MS1_OPERAND_IMM16O :
       fields->f_imm16s = value;
       break;
@@ -1516,6 +1645,9 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_LENGTH :
       fields->f_length = value;
       break;
+    case MS1_OPERAND_LOOPSIZE :
+      fields->f_loopo = value;
+      break;
     case MS1_OPERAND_MASK :
       fields->f_mask = value;
       break;
@@ -1540,6 +1672,9 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MS1_OPERAND_RC2 :
       fields->f_rc2 = value;
       break;
+    case MS1_OPERAND_RC3 :
+      fields->f_rc3 = value;
+      break;
     case MS1_OPERAND_RCNUM :
       fields->f_rcnum = value;
       break;
diff --git a/opcodes/ms1-opc.c b/opcodes/ms1-opc.c
index 4b9a05ccec7..b30db01822d 100644
--- a/opcodes/ms1-opc.c
+++ b/opcodes/ms1-opc.c
@@ -237,6 +237,26 @@ static const CGEN_IFMT ifmt_mfbcbincrs ATTRIBUTE_UNUSED = {
   32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_loop ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0fff00, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU8) }, { F (F_LOOPO) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_loopi ATTRIBUTE_UNUSED = {
+  32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_IMM16L) }, { F (F_LOOPO) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dfbc ATTRIBUTE_UNUSED = {
+  32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_RC3) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dwfb ATTRIBUTE_UNUSED = {
+  32, 32, 0xfc000080, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_UU1) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_dfbr ATTRIBUTE_UNUSED = {
+  32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
+};
+
 #undef F
 
 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
@@ -722,6 +742,42 @@ static const CGEN_OPCODE ms1_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (PERM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
     & ifmt_mfbcbincrs, { 0xfc000000 }
   },
+/* loop $frsr1,$loopsize */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (FRSR1), ',', OP (LOOPSIZE), 0 } },
+    & ifmt_loop, { 0x3e000000 }
+  },
+/* loopi #$imm16l,$loopsize */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '#', OP (IMM16L), ',', OP (LOOPSIZE), 0 } },
+    & ifmt_loopi, { 0x3f000000 }
+  },
+/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+    & ifmt_dfbc, { 0x80000000 }
+  },
+/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+    & ifmt_dwfb, { 0x84000000 }
+  },
+/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+    & ifmt_dfbc, { 0x88000000 }
+  },
+/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', OP (FRSR2), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
+    & ifmt_dfbr, { 0x8c000000 }
+  },
 };
 
 #undef A
diff --git a/opcodes/ms1-opc.h b/opcodes/ms1-opc.h
index 5ac13577bef..dc575845d46 100644
--- a/opcodes/ms1-opc.h
+++ b/opcodes/ms1-opc.h
@@ -68,14 +68,15 @@ typedef enum cgen_insn_type {
  , MS1_INSN_WFBI, MS1_INSN_WFB, MS1_INSN_RCRISC, MS1_INSN_FBCBINC
  , MS1_INSN_RCXMODE, MS1_INSN_INTERLEAVER, MS1_INSN_WFBINC, MS1_INSN_MWFBINC
  , MS1_INSN_WFBINCR, MS1_INSN_MWFBINCR, MS1_INSN_FBCBINCS, MS1_INSN_MFBCBINCS
- , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS
+ , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS, MS1_INSN_LOOP, MS1_INSN_LOOPI
+ , MS1_INSN_DFBC, MS1_INSN_DWFB, MS1_INSN_FBWFB, MS1_INSN_DFBR
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */
 #define CGEN_INSN_INVALID MS1_INSN_INVALID
 
 /* Total number of insns in table.  */
-#define MAX_INSNS ((int) MS1_INSN_MFBCBINCRS + 1)
+#define MAX_INSNS ((int) MS1_INSN_DFBR + 1)
 
 /* This struct records data prior to insertion or after extraction.  */
 struct cgen_fields
@@ -97,7 +98,9 @@ struct cgen_fields
   long f_uu4a;
   long f_uu4b;
   long f_uu12;
+  long f_uu8;
   long f_uu16;
+  long f_uu1;
   long f_msopc;
   long f_uu_26_25;
   long f_mask;
@@ -147,6 +150,13 @@ struct cgen_fields
   long f_dup;
   long f_rc2;
   long f_ctxdisp;
+  long f_imm16l;
+  long f_loopo;
+  long f_cb1sel;
+  long f_cb2sel;
+  long f_cb1incr;
+  long f_cb2incr;
+  long f_rc3;
   long f_msysfrsr2;
   long f_brc2;
   long f_ball2;