PR 10288

        * arm-dis.c (coprocessor): Print the LDC and STC versions of the
        LFM and SFM instructions as comments,.
        Improve consistency of formatting for instructions displayed as
        comments and decimal values displayed with their hexadecimal
        equivalents.
        Formatting tidy ups.

        Updated expected disassembler regexps.

2 files changed, 143 insertions, 103 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2ba42d6ac26..d3febd0f39a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2009-06-30  Nick Clifton  <nickc@redhat.com>
+
+	PR 10288
+	* arm-dis.c (coprocessor): Print the LDC and STC versions of the
+	LFM and SFM instructions as comments,.
+	Improve consistency of formatting for instructions displayed as
+	comments and decimal values displayed with their hexadecimal
+	equivalents.
+	Formatting tidy ups.
+
 2009-06-29  Nick Clifton  <nickc@redhat.com>
 
 	PR 10288
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index bee84549322..20cb875ef92 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -48,8 +48,8 @@
 struct opcode32
 {
   unsigned long arch;		/* Architecture defining this insn.  */
-  unsigned long value;		/* Recognise insn if (op & mask) == value.  */
-  unsigned long mask;		/* If arch == 0 then value is a sentinel.  */
+  unsigned long value;		/* If arch == 0 then value is a sentinel.  */
+  unsigned long mask;		/* Recognise insn if (op & mask) == value.  */
   const char *  assembler;	/* How to disassemble this insn.  */
 };
 
@@ -104,8 +104,7 @@ struct opcode16
 			versions.
    %i			print 5-bit immediate in bits 8,3..0
 			(print "32" when 0)
-   %r			print register offset address for wldt/wstr instruction
-*/
+   %r			print register offset address for wldt/wstr instruction.  */
 
 enum
 {
@@ -206,7 +205,7 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
   { 0, SENTINEL_IWMMXT_END, 0, "" },
 
-  /* Floating point coprocessor (FPA) instructions */
+  /* Floating point coprocessor (FPA) instructions.  */
   {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
   {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
   {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
@@ -248,10 +247,10 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
   {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
   {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
-  {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
-  {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+  {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A\t; (stc%22'l%c %8-11d, cr%12-15d, %A)"},
+  {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A\t; (ldc%22'l%c %8-11d, cr%12-15d, %A)"},
 
-  /* Register load/store */
+  /* Register load/store.  */
   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
@@ -274,7 +273,7 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
   {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 
-  /* Data transfer between ARM and NEON registers */
+  /* Data transfer between ARM and NEON registers.  */
   {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
   {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
   {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
@@ -293,7 +292,7 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_NEON_FP16,   0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
   {FPU_NEON_FP16,   0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 
-  /* Floating point coprocessor (VFP) instructions */
+  /* Floating point coprocessor (VFP) instructions.  */
   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
   {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
   {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
@@ -500,20 +499,20 @@ static const struct opcode32 coprocessor_opcodes[] =
    
    %<bitfield>'c	print specified char iff bitfield is all ones
    %<bitfield>`c	print specified char iff bitfield is all zeroes
-   %<bitfield>?ab...    select from array of values in big endian order  */
+   %<bitfield>?ab...    select from array of values in big endian order.  */
 
 static const struct opcode32 neon_opcodes[] =
 {
-  /* Extract */
+  /* Extract.  */
   {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
   {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 
-  /* Move data element to all lanes */
+  /* Move data element to all lanes.  */
   {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
   {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
   {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
 
-  /* Table lookup */
+  /* Table lookup.  */
   {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
   {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
   
@@ -521,7 +520,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_FP16,   0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
   {FPU_NEON_FP16,   0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
 
-  /* Two registers, miscellaneous */
+  /* Two registers, miscellaneous.  */
   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
@@ -556,7 +555,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
 
-  /* Three registers of the same length */
+  /* Three registers of the same length.  */
   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
@@ -611,7 +610,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 
-  /* One register and an immediate value */
+  /* One register and an immediate value.  */
   {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
   {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
   {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
@@ -626,7 +625,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
   {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
 
-  /* Two registers and a shift amount */
+  /* Two registers and a shift amount.  */
   {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
   {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
   {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
@@ -686,7 +685,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
   {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
 
-  /* Three registers of different lengths */
+  /* Three registers of different lengths.  */
   {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
   {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
   {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
@@ -705,7 +704,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
   {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 
-  /* Two registers and a scalar */
+  /* Two registers and a scalar.  */
   {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
   {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
   {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
@@ -729,7 +728,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
   {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 
-  /* Element and structure load/store */
+  /* Element and structure load/store.  */
   {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
   {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
   {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
@@ -791,7 +790,7 @@ static const struct opcode32 neon_opcodes[] =
 static const struct opcode32 arm_opcodes[] =
 {
   /* ARM instructions.  */
-  {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
+  {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
   {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
   {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"},
   {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
@@ -836,7 +835,7 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
   {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
 
-  /* ARM V6 instructions. */
+  /* ARM V6 instructions.  */
   {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
   {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
   {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
@@ -1109,7 +1108,7 @@ static const struct opcode16 thumb_opcodes[] =
   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
   {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},	/* note: 4 bit register number.  */
   /* ARM V4T ISA (Thumb v1).  */
-  {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"},
+  {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
   /* Format 4.  */
   {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
   {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
@@ -1160,7 +1159,7 @@ static const struct opcode16 thumb_opcodes[] =
   {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
   {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
   /* format 6 */
-  {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
+  {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
   /* format 9 */
   {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
   {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
@@ -1173,7 +1172,7 @@ static const struct opcode16 thumb_opcodes[] =
   {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
   {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
   /* format 12 */
-  {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"},
+  {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
   {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
   /* format 15 */
   {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
@@ -1520,7 +1519,8 @@ static bfd_vma ifthen_address;
 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
 
 /* Cached mapping symbol state.  */
-enum map_type {
+enum map_type
+{
   MAP_ARM,
   MAP_THUMB,
   MAP_DATA
@@ -1547,7 +1547,9 @@ set_arm_regname_option (int option)
 }
 
 int
-get_arm_regnames (int option, const char **setname, const char **setdescription,
+get_arm_regnames (int option,
+		  const char **setname,
+		  const char **setdescription,
 		  const char *const **register_names)
 {
   *setname = regnames[option].name;
@@ -1559,11 +1561,13 @@ get_arm_regnames (int option, const char **setname, const char **setdescription,
 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
    Returns pointer to following character of the format string and
    fills in *VALUEP and *WIDTHP with the extracted value and number of
-   bits extracted.  WIDTHP can be NULL. */
+   bits extracted.  WIDTHP can be NULL.  */
 
 static const char *
-arm_decode_bitfield (const char *ptr, unsigned long insn,
-		     unsigned long *valuep, int *widthp)
+arm_decode_bitfield (const char *ptr,
+		     unsigned long insn,
+		     unsigned long *valuep,
+		     int *widthp)
 {
   unsigned long value = 0;
   int width = 0;
@@ -1635,7 +1639,9 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
    recognised coprocessor instruction.  */
 
 static bfd_boolean
-print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
+print_insn_coprocessor (bfd_vma pc,
+			struct disassemble_info *info,
+			long given,
 			bfd_boolean thumb)
 {
   const struct opcode32 *insn;
@@ -1734,9 +1740,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
 		    if ((given & (1 << 24)) != 0)
 		      {
 			if (offset)
-			  func (stream, ", #%s%d]%s",
-				((given & 0x00800000) == 0 ? "-" : ""),
-				offset * 4,
+			  func (stream, ", #%d]%s",
+				value_in_comment,
 				((given & 0x00200000) != 0 ? "!" : ""));
 			else
 			  func (stream, "]");
@@ -1748,12 +1753,13 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
 			if (given & (1 << 21))
 			  {
 			    if (offset)
-			      func (stream, ", #%s%d",
-				    ((given & 0x00800000) == 0 ? "-" : ""),
-				    offset * 4);
+			      func (stream, ", #%d", value_in_comment);
 			  }
 			else
-			  func (stream, ", {%d}", offset);
+			  {
+			    func (stream, ", {%d}", offset);
+			    value_in_comment = offset;
+			  }
 		      }
 		  }
 		  break;
@@ -1785,6 +1791,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
 			if (!add)
 			  offset = -offset;
 			func (stream, ", #%d", offset);
+			if (rn != 15)
+			  value_in_comment = offset;
 		      }
 		    func (stream, "]");
 		    if (rn == 15)
@@ -1960,7 +1968,7 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
 			  func (stream, "%c", *c);
 			break;
 		      case '?':
-			func (stream, "%c", c[(1 << width) - (int)value]);
+			func (stream, "%c", c[(1 << width) - (int) value]);
 			c += 1 << width;
 			break;
 		      default:
@@ -2491,7 +2499,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 		      break;
 		      
 		    case 'E':
-		      /* Neon encoded constant for mov, mvn, vorr, vbic */
+		      /* Neon encoded constant for mov, mvn, vorr, vbic.  */
 		      {
 			int bits = 0;
 			int cmode = (given >> 8) & 0xf;
@@ -2508,19 +2516,19 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 			if (cmode < 8)
 			  {
 			    shift = (cmode >> 1) & 3;
-			    value = (unsigned long)bits << (8 * shift);
+			    value = (unsigned long) bits << (8 * shift);
                             size = 32;
 			  }
 			else if (cmode < 12)
 			  {
 			    shift = (cmode >> 1) & 1;
-			    value = (unsigned long)bits << (8 * shift);
+			    value = (unsigned long) bits << (8 * shift);
                             size = 16;
 			  }
 			else if (cmode < 14)
 			  {
 			    shift = (cmode & 1) + 1;
-			    value = (unsigned long)bits << (8 * shift);
+			    value = (unsigned long) bits << (8 * shift);
 			    value |= (1ul << (8 * shift)) - 1;
                             size = 32;
 			  }
@@ -2528,7 +2536,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 			  {
 			    if (op)
 			      {
-				/* bit replication into bytes */
+				/* Bit replication into bytes.  */
 				int ix;
 				unsigned long mask;
 				
@@ -2546,20 +2554,20 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 			      }
                             else
                               {
-                                /* byte replication */
-                                value = (unsigned long)bits;
+                                /* Byte replication.  */
+                                value = (unsigned long) bits;
                                 size = 8;
                               }
 			  }
 			else if (!op)
 			  {
-			    /* floating point encoding */
+			    /* Floating point encoding.  */
 			    int tmp;
 			    
-			    value = (unsigned long)(bits & 0x7f) << 19;
-			    value |= (unsigned long)(bits & 0x80) << 24;
+			    value = (unsigned long)  (bits & 0x7f) << 19;
+			    value |= (unsigned long) (bits & 0x80) << 24;
 			    tmp = bits & 0x40 ? 0x3c : 0x40;
-			    value |= (unsigned long)tmp << 24;
+			    value |= (unsigned long) tmp << 24;
                             size = 32;
                             isfloat = 1;
 			  }
@@ -2703,7 +2711,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 			      func (stream, "%c", *c);
 			    break;
 			  case '?':
-			    func (stream, "%c", c[(1 << width) - (int)value]);
+			    func (stream, "%c", c[(1 << width) - (int) value]);
 			    c += 1 << width;
 			    break;
 			  default:
@@ -2796,27 +2804,28 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			}
 		      else
 			{
+			  int offset = ((given & 0xf00) >> 4) | (given & 0xf);
+
+			  if ((given & 0x00800000) == 0)
+			    offset = -offset;
+
 			  func (stream, "[%s",
 				arm_regnames[(given >> 16) & 0xf]);
+
 			  if ((given & 0x01000000) != 0)
 			    {
                               /* Pre-indexed.  */
 			      if ((given & 0x00400000) == 0x00400000)
 				{
                                   /* Immediate.  */
-                                  int offset = ((given & 0xf00) >> 4) | (given & 0xf);
-
 				  if (offset)
-				    func (stream, ", #%s%d",
-					  (((given & 0x00800000) == 0)
-					   ? "-" : ""), offset);
+				    func (stream, ", #%d", offset);
+				  value_in_comment = offset;
 				}
 			      else
 				{
                                   /* Register.  */
-				  func (stream, ", %s%s",
-					(((given & 0x00800000) == 0)
-					 ? "-" : ""),
+				  func (stream, ", %s%s", offset < 0 ? "-" : "",
                                         arm_regnames[given & 0xf]);
 				}
 
@@ -2829,21 +2838,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			      if ((given & 0x00400000) == 0x00400000)
 				{
                                   /* Immediate.  */
-                                  int offset = ((given & 0xf00) >> 4) | (given & 0xf);
-
 				  if (offset)
-				    func (stream, "], #%s%d",
-					  (((given & 0x00800000) == 0)
-					   ? "-" : ""), offset);
+				    func (stream, "], #%d", offset);
 				  else
 				    func (stream, "]");
+
+				  value_in_comment = offset;
 				}
 			      else
 				{
                                   /* Register.  */
-				  func (stream, "], %s%s",
-					(((given & 0x00800000) == 0)
-					 ? "-" : ""),
+				  func (stream, "], %s%s", offset < 0 ? "-" : "",
                                         arm_regnames[given & 0xf]);
 				}
 			    }
@@ -2890,9 +2895,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			{
 			  int rotate = (given & 0xf00) >> 7;
 			  int immed = (given & 0xff);
+
 			  immed = (((immed << (32 - rotate))
 				    | (immed >> rotate)) & 0xffffffff);
-			  func (stream, "#%d\t; 0x%x", immed, immed);
+			  func (stream, "#%d", immed);
+			  value_in_comment = immed;
 			}
 		      else
 			arm_decode_shift (given, func, stream, 1);
@@ -2921,9 +2928,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			if ((given & (1 << 24)) != 0)
 			  {
 			    if (offset)
-			      func (stream, ", #%s%d]%s",
-				    ((given & 0x00800000) == 0 ? "-" : ""),
-				    offset * 4,
+			      func (stream, ", #%d]%s",
+				    value_in_comment,
 				    ((given & 0x00200000) != 0 ? "!" : ""));
 			    else
 			      func (stream, "]");
@@ -2935,12 +2941,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			    if (given & (1 << 21))
 			      {
 				if (offset)
-				  func (stream, ", #%s%d",
-					((given & 0x00800000) == 0 ? "-" : ""),
-					offset * 4);
+				  func (stream, ", #%d", value_in_comment);
 			      }
 			    else
-			      func (stream, ", {%d}", offset);
+			      {
+				func (stream, ", {%d}", offset);
+				value_in_comment = offset;
+			      }
 			  }
 		      }
 		      break;
@@ -2983,12 +2990,12 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 		    case 'U':
 		      switch (given & 0xf)
 			{
-			case 0xf: func(stream, "sy"); break;
-			case 0x7: func(stream, "un"); break;
-			case 0xe: func(stream, "st"); break;
-			case 0x6: func(stream, "unst"); break;
+			case 0xf: func (stream, "sy"); break;
+			case 0x7: func (stream, "un"); break;
+			case 0xe: func (stream, "st"); break;
+			case 0x6: func (stream, "unst"); break;
 			default:
-			  func(stream, "#%d", (int)given & 0xf);
+			  func (stream, "#%d", (int) given & 0xf);
 			  break;
 			}
 		      break;
@@ -3043,7 +3050,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			      func (stream, "%c", *c);
 			    break;
 			  case '?':
-			    func (stream, "%c", c[(1 << width) - (int)value]);
+			    func (stream, "%c", c[(1 << width) - (int) value]);
 			    c += 1 << width;
 			    break;
 			  default:
@@ -3057,6 +3064,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 
 			  imm = (given & 0xf) | ((given & 0xfff00) >> 4);
 			  func (stream, "%d", imm);
+			  value_in_comment = imm;
 			}
 			break;
 
@@ -3066,8 +3074,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			{
 			  long msb = (given & 0x001f0000) >> 16;
 			  long lsb = (given & 0x00000f80) >> 7;
-
 			  long width = msb - lsb + 1;
+
 			  if (width > 0)
 			    func (stream, "#%lu, #%lu", lsb, width);
 			  else
@@ -3082,7 +3090,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			  long hi = (given & 0x000f0000) >> 4;
 			  long lo = (given & 0x00000fff);
 			  long imm16 = hi | lo;
-			  func (stream, "#%lu\t; 0x%lx", imm16, imm16);
+
+			  func (stream, "#%lu", imm16);
+			  value_in_comment = imm16;
 			}
 			break;
 
@@ -3366,6 +3376,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
 }
 
 /* Return the name of an V7M special register.  */
+
 static const char *
 psr_name (int regno)
 {
@@ -3443,16 +3454,19 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 	      case 'I':
 		{
 		  unsigned int imm12 = 0;
+
 		  imm12 |= (given & 0x000000ffu);
 		  imm12 |= (given & 0x00007000u) >> 4;
 		  imm12 |= (given & 0x04000000u) >> 15;
-		  func (stream, "#%u\t; 0x%x", imm12, imm12);
+		  func (stream, "#%u", imm12);
+		  value_in_comment = imm12;
 		}
 		break;
 
 	      case 'M':
 		{
 		  unsigned int bits = 0, imm, imm8, mod;
+
 		  bits |= (given & 0x000000ffu);
 		  bits |= (given & 0x00007000u) >> 4;
 		  bits |= (given & 0x04000000u) >> 15;
@@ -3469,28 +3483,33 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		      imm8 = (bits & 0x07f) | 0x80;
 		      imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
 		    }
-		  func (stream, "#%u\t; 0x%x", imm, imm);
+		  func (stream, "#%u", imm);
+		  value_in_comment = imm;
 		}
 		break;
 		  
 	      case 'J':
 		{
 		  unsigned int imm = 0;
+
 		  imm |= (given & 0x000000ffu);
 		  imm |= (given & 0x00007000u) >> 4;
 		  imm |= (given & 0x04000000u) >> 15;
 		  imm |= (given & 0x000f0000u) >> 4;
-		  func (stream, "#%u\t; 0x%x", imm, imm);
+		  func (stream, "#%u", imm);
+		  value_in_comment = imm;
 		}
 		break;
 
 	      case 'K':
 		{
 		  unsigned int imm = 0;
+
 		  imm |= (given & 0x000f0000u) >> 16;
 		  imm |= (given & 0x00000ff0u) >> 0;
 		  imm |= (given & 0x0000000fu) << 12;
-		  func (stream, "#%u\t; 0x%x", imm, imm);
+		  func (stream, "#%u", imm);
+		  value_in_comment = imm;
 		}
 		break;
 
@@ -3643,7 +3662,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 			  value_in_comment = off * 4 * U ? 1 : -1;
 			}
 		      else
-			func (stream, "{%u}", off);
+			{
+			  func (stream, "{%u}", off);
+			  value_in_comment = off;
+			}
 		    }
 		}
 		break;
@@ -3690,6 +3712,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		{
 		  unsigned int msb = (given & 0x0000001f);
 		  unsigned int lsb = 0;
+
 		  lsb |= (given & 0x000000c0u) >> 6;
 		  lsb |= (given & 0x00007000u) >> 10;
 		  func (stream, "#%u, #%u", lsb, msb - lsb + 1);
@@ -3700,6 +3723,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		{
 		  unsigned int width = (given & 0x0000001f) + 1;
 		  unsigned int lsb = 0;
+
 		  lsb |= (given & 0x000000c0u) >> 6;
 		  lsb |= (given & 0x00007000u) >> 10;
 		  func (stream, "#%u, #%u", lsb, width);
@@ -3750,6 +3774,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 	      case 's':
 		{
 		  unsigned int shift = 0;
+
 		  shift |= (given & 0x000000c0u) >> 6;
 		  shift |= (given & 0x00007000u) >> 10;
 		  if (given & 0x00200000u)
@@ -3763,6 +3788,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 	      case 'R':
 		{
 		  unsigned int rot = (given & 0x00000030) >> 4;
+
 		  if (rot)
 		    func (stream, ", ror #%u", rot * 8);
 		}
@@ -3771,12 +3797,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 	      case 'U':
 		switch (given & 0xf)
 		  {
-		  case 0xf: func(stream, "sy"); break;
-		  case 0x7: func(stream, "un"); break;
-		  case 0xe: func(stream, "st"); break;
-		  case 0x6: func(stream, "unst"); break;
+		  case 0xf: func (stream, "sy"); break;
+		  case 0x7: func (stream, "un"); break;
+		  case 0xe: func (stream, "st"); break;
+		  case 0x6: func (stream, "unst"); break;
 		  default:
-		    func(stream, "#%d", (int)given & 0xf);
+		    func (stream, "#%d", (int) given & 0xf);
 		    break;
 		  }
 		break;
@@ -3844,7 +3870,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		      break;
 
 		    case '?':
-		      func (stream, "%c", c[(1 << width) - (int)val]);
+		      func (stream, "%c", c[(1 << width) - (int) val]);
 		      c += 1 << width;
 		      break;
 
@@ -3871,7 +3897,8 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 /* Print data bytes on INFO->STREAM.  */
 
 static void
-print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info,
+print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
+		 struct disassemble_info *info,
 		 long given)
 {
   switch (info->bytes_per_chunk)
@@ -3967,8 +3994,10 @@ parse_disassembler_options (char *options)
 
 /* Search back through the insn stream to determine if this instruction is
    conditionally executed.  */
+
 static void
-find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
+find_ifthen_state (bfd_vma pc,
+		   struct disassemble_info *info,
 		   bfd_boolean little)
 {
   unsigned char b[2];
@@ -3993,7 +4022,7 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
      IT instruction until we find a definite instruction boundary.  */
   for (;;)
     {
-      if (addr == 0 || info->symbol_at_address_func(addr, info))
+      if (addr == 0 || info->symbol_at_address_func (addr, info))
 	{
 	  /* A symbol must be on an instruction boundary, and will not
 	     be within an IT block.  */
@@ -4003,7 +4032,7 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
 	  return;
 	}
       addr -= 2;
-      status = info->read_memory_func (addr, (bfd_byte *)b, 2, info);
+      status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
       if (status)
 	return;
 
@@ -4047,7 +4076,8 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
    Returns nonzero if *MAP_TYPE was set.  */
 
 static int
-get_sym_code_type (struct disassemble_info *info, int n,
+get_sym_code_type (struct disassemble_info *info,
+		   int n,
 		   enum map_type *map_type)
 {
   elf_symbol_type *es;
@@ -4065,7 +4095,7 @@ get_sym_code_type (struct disassemble_info *info, int n,
     }
 
   /* Check for mapping symbols.  */
-  name = bfd_asymbol_name(info->symtab[n]);
+  name = bfd_asymbol_name (info->symtab[n]);
   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
       && (name[2] == 0 || name[2] == '.'))
     {
@@ -4315,7 +4345,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
       info->bytes_per_chunk = size;
       printer = print_insn_data;
 
-      status = info->read_memory_func (pc, (bfd_byte *)b, size, info);
+      status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
       given = 0;
       if (little)
 	for (i = size - 1; i >= 0; i--)
@@ -4348,7 +4378,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
       info->bytes_per_chunk = 2;
       size = 2;
 
-      status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
+      status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
       if (little_code)
 	given = (b[0]) | (b[1] << 8);
       else