diff options
| author | Nick Clifton <nickc@redhat.com> | 2001-05-11 21:51:07 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2001-05-11 21:51:07 +0000 |
| commit | c34a3a045989be10ab8ad01ef2f97fb9458544cc (patch) | |
| tree | fcb55e74b7238cd194c9e2c1eaf20eae1426d831 /sim/arm/armemu.c | |
| parent | 73ed6fedaf75e5edf02d960c2714e8f21d04d653 (diff) | |
| download | gdb-c34a3a045989be10ab8ad01ef2f97fb9458544cc.tar.gz | |
Fix handling of XScale LDRD and STRD instructions with post indexed addressing modes.
Diffstat (limited to 'sim/arm/armemu.c')
| -rw-r--r-- | sim/arm/armemu.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 0947470abba..4edac6f4112 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -619,7 +619,7 @@ check_PMUintr: /* XScale Load Consecutive insn. */ ARMword temp = GetLS7RHS (state, instr); ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; - ARMword addr = BIT (24) ? temp2 : temp; + ARMword addr = BIT (24) ? temp2 : LHS; if (BIT (12)) ARMul_UndefInstr (state, instr); @@ -628,14 +628,14 @@ check_PMUintr: ARMul_Abort (state, ARMul_DataAbortV); else { - int wb = BIT (24) && BIT (21); + int wb = BIT (21) || (! BIT (24)); state->Reg[BITS (12, 15)] = ARMul_LoadWordN (state, addr); state->Reg[BITS (12, 15) + 1] = ARMul_LoadWordN (state, addr + 4); if (wb) - LSBase = addr; + LSBase = temp2; } goto donext; @@ -645,7 +645,7 @@ check_PMUintr: /* XScale Store Consecutive insn. */ ARMword temp = GetLS7RHS (state, instr); ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; - ARMword addr = BIT (24) ? temp2 : temp; + ARMword addr = BIT (24) ? temp2 : LHS; if (BIT (12)) ARMul_UndefInstr (state, instr); @@ -659,8 +659,8 @@ check_PMUintr: ARMul_StoreWordN (state, addr + 4, state->Reg[BITS (12, 15) + 1]); - if (BIT (21)) - LSBase = addr; + if (BIT (21)|| ! BIT (24)) + LSBase = temp2; } goto donext; |