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| author | Nick Clifton <nickc@redhat.com> | 2002-05-23 12:38:31 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2002-05-23 12:38:31 +0000 |
| commit | de2d89fd8873bdaa7783e7446842a593cf7c1d61 (patch) | |
| tree | d744f07a5d1340a087475793e6d18539dfa36981 /sim/arm/thumbemu.c | |
| parent | cd8aeb71407684e557881187324328822cf7080e (diff) | |
| download | gdb-de2d89fd8873bdaa7783e7446842a593cf7c1d61.tar.gz | |
When decoding a BLX(1) instruction do not add in the second bit of the base
address - this has already been accounted for.
Diffstat (limited to 'sim/arm/thumbemu.c')
| -rw-r--r-- | sim/arm/thumbemu.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c index 4f007333363..283e7d5cf5a 100644 --- a/sim/arm/thumbemu.c +++ b/sim/arm/thumbemu.c @@ -520,12 +520,8 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr) { ARMword tmp = (pc + 2); - /* Bit one of the destination address comes from bit one of the - address of the first (H == 10) half of the instruction, not - from the offset in the instruction. */ state->Reg[15] = ((state->Reg[14] - + ((tinstr & 0x07FE) << 1) - + ((pc - 2) & 2)) + + ((tinstr & 0x07FE) << 1)) & 0xFFFFFFFC); CLEART; state->Reg[14] = (tmp | 1); @@ -538,6 +534,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr) break; } /* else we fall through to process the second half of the BL */ + pc += 2; /* point the pc at the 2nd half */ case 31: /* BL instruction 2 */ /* Format 19 */ /* There is no single ARM instruction equivalent for this |