diff options
| author | Andrew Cagney <cagney@redhat.com> | 2000-04-18 07:55:35 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2000-04-18 07:55:35 +0000 |
| commit | 2f16f04ef787c5f23d4104184dee21ee78b07778 (patch) | |
| tree | 8153a88596350e5227d08b7b69961f1bdb5ec606 /sim/d10v/interp.c | |
| parent | e0c4e11ea70cbc623023dc29e82fd78364558dbc (diff) | |
| download | gdb-2f16f04ef787c5f23d4104184dee21ee78b07778.tar.gz | |
Add support for SIGILL (reserved-instruction-exception).
Diffstat (limited to 'sim/d10v/interp.c')
| -rw-r--r-- | sim/d10v/interp.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 91ebee56ce9..ce4b7694bb3 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -99,8 +99,6 @@ lookup_hash (ins, size) { if (h->next == NULL) { - (*d10v_callback->printf_filtered) - (d10v_callback, "ERROR: Illegal instruction %x at PC %x\n", ins, PC); State.exception = SIGILL; State.pc_changed = 1; /* Don't increment the PC. */ return NULL; @@ -979,6 +977,13 @@ sim_resume (sd, step, siggnal) JMP (AE_VECTOR_START); SLOT_FLUSH (); break; + case SIGILL: + SET_BPC (PC); + SET_BPSW (PSW); + SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); + JMP (RIE_VECTOR_START); + SLOT_FLUSH (); + break; default: /* just ignore it */ break; |