Initial revision

29 files changed, 41829 insertions, 0 deletions

diff --git a/sim/i960/ChangeLog b/sim/i960/ChangeLog
new file mode 100644
index 00000000000..5a87da546fb
--- /dev/null
+++ b/sim/i960/ChangeLog
@@ -0,0 +1,86 @@
+1999-02-09  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (I960_OBJS): Add i960-desc.o.
+	(SIM_EXTRA_DEPS): Replace cpu-opc.h with i960-desc.h,i960-opc.h.
+	* configure.in (sim_link_files,sim_link_links): Delete.
+	* configure: Rebuild.
+	* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+	* devices.c: s/m32r/i960/.
+	* i960-desc.c: New file.
+	* i960-desc.h: New file.
+	* i960-opc.h: New file.
+	* i960-sim.h (I960_MISC_PROFILE): Delete.
+	* i960.c (i960base_model_insn_before): Delete unused code.
+	(i960base_model_insn_after): Ditto.
+	(i960_model_init_insn_cycles,i960_model_update_insn_cycles): Ditto.
+	(i960_model_record_cycles): Ditto.
+	* mloop.in (execute): CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
+	(extract-pbb): Use idesc->length to get insn length.
+	* sim-if.c (i960_disassemble_insn): New function.
+	(sim_open): Delete misc. profiling support.  i960_cgen_cpu_open renamed
+	from i960_cgen_opcode_open.  Set disassembler.
+	(sim_close): i960_cgen_cpu_open renamed from i960_cgen_opcode_open.
+	* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
+	i960-desc.h,i960-opc.h,i960-sim.h.
+	(struct _sim_cpu): Delete member i960_misc_profile.
+
+1999-01-27  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+
+1999-01-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* arch.c,arch.c,cpuall.h: Regenerate.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
+
+1999-01-11  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (i960-clean): rm eng.h.
+	* sim-main.h: Delete inclusion of ansidecl.h.
+	Delete inclusion of cgen-scache.h,cgen-cpu.h,cgen-trace.h,cpuall.h.
+	(SIM_CORE_SIGNAL): m32r -> i960.
+	* cpu.h: Regenerate.
+	* traps.c: m32r -> i960.
+
+1999-01-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (SIM_EXTRA_DEPS): Use CGEN_INCLUDE_DEPS.
+	(MAIN_INCLUDE_DEPS,INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
+	(sim-if.o): Use SIM_MAIN_DEPS.
+	(arch.o): Ditto.
+	(traps.o): Ditto.
+	(devices.o): Ditto.
+	(I960BASE_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
+	(i960.o): Use I960BASE_INCLUDE_DEPS.
+	(mloop.o,cpu.o,decode.o,sem.o,model.o): Ditto.
+	(stamp-arch): Pass mach=all to cgen-arch.
+	* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+	* sim-if.c (sim_open): Model probing code moved to sim-model.c.
+
+1998-12-14  James E Wilson  <wilson@wilson-pc.cygnus.com>
+
+	* cpu.h, decode.c, sem-switch.c, sem.c: Rebuilt.
+	* traps.c (i960_trap): Store syscall results in regs 16 to 18 instead
+	of regs 0 to 2.
+
+Mon Dec 14 22:33:38 1998  Jim Wilson  <wilson@cygnus.com>
+
+	* mloop.in (extract32): Add calls to @cpu@_fill_argbuf and
+	@cpu@_fil_argbuf_tp.
+
+1998-12-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* configure.in: --enable-cgen-maint support moved to common/aclocal.m4.
+	* configure: Regenerate.
+
+	* sem-switch.c,sem.c: Regenerate.
+
+1998-12-09  James E Wilson  <wilson@wilson-pc.cygnus.com>
+
+	* mloop.in execute): Test ARGBUF_PROFILE_P before profiling.
+	Update calls to TRACE_INSN_INIT,TRACE_INSN_FINI.
+	* cpu.h, cpuall.h, decode.c, sem-switch.c, sem.c: Regenerate.
+
+1998-12-08  James E Wilson  <wilson@wilson-pc.cygnus.com>
+
+	* New directory.
diff --git a/sim/i960/Makefile.in b/sim/i960/Makefile.in
new file mode 100644
index 00000000000..deb26727c9f
--- /dev/null
+++ b/sim/i960/Makefile.in
@@ -0,0 +1,101 @@
+# Makefile template for Configure for the i960 simulator
+# Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+# Contributed by Cygnus Support.
+#
+# This file is part of GDB, the GNU debugger.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+I960_OBJS = i960.o cpu.o decode.o sem.o model.o mloop.o i960-desc.o
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+	$(SIM_NEW_COMMON_OBJS) \
+	sim-cpu.o \
+	sim-engine.o \
+	sim-hload.o \
+	sim-hrw.o \
+	sim-model.o \
+	sim-reason.o \
+	cgen-utils.o cgen-trace.o cgen-scache.o \
+	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+	sim-if.o arch.o \
+	$(I960_OBJS) \
+	traps.o devices.o \
+	$(CONFIG_DEVICES)
+
+# Extra headers included by sim-main.h.
+SIM_EXTRA_DEPS = \
+	$(CGEN_INCLUDE_DEPS) \
+	arch.h cpuall.h i960-sim.h i960-desc.h i960-opc.h
+
+SIM_EXTRA_CFLAGS =
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = i960-clean
+
+# This selects the i960 newlib/libgloss syscall definitions.
+#
+# ??? This affects what stuff gets included from ../common/nltvals.def.
+# For now, we need SYS_exit because of traps.c.  If we really need this,
+# then we need to add i960 specific definitions to nltvals.def.
+NL_TARGET = -DNL_TARGET_i960
+
+## COMMON_POST_CONFIG_FRAG
+
+arch = i960
+
+sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+
+traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
+devices.o: devices.c $(SIM_MAIN_DEPS)
+
+# I960 objs
+
+I960BASE_INCLUDE_DEPS = \
+	$(CGEN_MAIN_CPU_DEPS) \
+	cpu.h decode.h eng.h
+
+i960.o: i960.c $(I960BASE_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloop.c eng.h: stamp-mloop
+stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+	$(SHELL) $(srccom)/genmloop.sh \
+		-mono -fast -pbb -switch sem-switch.c \
+		-cpu i960base -infile $(srcdir)/mloop.in
+	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
+	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
+	touch stamp-mloop
+#	$(SHELL) $(srccom)/genmloop.sh \
+#		-mono -scache -fast i960base $(srcdir)/mloop.in \
+#		| sed -e 's/@cpu@/i960base/' -e 's/@CPU@/I960BASE/' >mloop.c
+mloop.o: mloop.c sem-switch.c $(I960BASE_INCLUDE_DEPS)
+
+cpu.o: cpu.c $(I960BASE_INCLUDE_DEPS)
+decode.o: decode.c $(I960BASE_INCLUDE_DEPS)
+sem.o: sem.c $(I960BASE_INCLUDE_DEPS)
+model.o: model.c $(I960BASE_INCLUDE_DEPS)
+
+i960-clean:
+	rm -f mloop.c eng.h stamp-mloop
+	rm -f tmp-*
+
diff --git a/sim/i960/README b/sim/i960/README
new file mode 100644
index 00000000000..f337558c9f5
--- /dev/null
+++ b/sim/i960/README
@@ -0,0 +1,14 @@
+This is the i960 simulator directory.
+
+It is still work-in-progress.  The current sources are reasonably
+well tested and lots of features are in.  However, there's lots
+more yet to come.
+
+There are lots of machine generated files in the source directory!
+They are only generated if you configure with --enable-cgen-maint,
+similar in behaviour to Makefile.in, configure under automake/autoconf.
+
+For details on the generator, see ../../cgen.
+
+devo/cgen isn't part of the comp-tools module yet.
+You'll need to check it out manually (also akin to automake/autoconf).
diff --git a/sim/i960/TODO b/sim/i960/TODO
new file mode 100644
index 00000000000..263daacbbab
--- /dev/null
+++ b/sim/i960/TODO
@@ -0,0 +1,9 @@
+- header file dependencies revisit
+- hooks cleanup
+- testsuites
+- FIXME's
+- memory accesses still test if profiling is on even in fast mode
+- fill nop counting done even in fast mode
+- have semantic code use G/SET_H_FOO if not default [incl fun-access]
+- have G/SET_H_FOO macros call function if fun-access
+- --> can always use G/S_H_FOO macros
diff --git a/sim/i960/acconfig.h b/sim/i960/acconfig.h
new file mode 100644
index 00000000000..f9b87a10c60
--- /dev/null
+++ b/sim/i960/acconfig.h
@@ -0,0 +1,15 @@
+
+/* Define to 1 if NLS is requested.  */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have catgets and don't want to use GNU gettext.  */
+#undef HAVE_CATGETS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES.  */
+#undef HAVE_LC_MESSAGES
diff --git a/sim/i960/arch.c b/sim/i960/arch.c
new file mode 100644
index 00000000000..5d3ab846209
--- /dev/null
+++ b/sim/i960/arch.c
@@ -0,0 +1,164 @@
+/* Simulator support for i960.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_I960BASE
+  & i960_ka_sa_mach,
+#endif
+#ifdef HAVE_CPU_I960BASE
+  & i960_ca_mach,
+#endif
+  0
+};
+
+/* Get the value of h-pc.  */
+
+USI
+a_i960_h_pc_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ka_sa : 
+      return i960base_h_pc_get (current_cpu);
+#endif
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ca : 
+      return i960base_h_pc_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-pc.  */
+
+void
+a_i960_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ka_sa : 
+      i960base_h_pc_set (current_cpu, newval);
+      break;
+#endif
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ca : 
+      i960base_h_pc_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-gr.  */
+
+SI
+a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ka_sa : 
+      return i960base_h_gr_get (current_cpu, regno);
+#endif
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ca : 
+      return i960base_h_gr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-gr.  */
+
+void
+a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ka_sa : 
+      i960base_h_gr_set (current_cpu, regno, newval);
+      break;
+#endif
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ca : 
+      i960base_h_gr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-cc.  */
+
+SI
+a_i960_h_cc_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ka_sa : 
+      return i960base_h_cc_get (current_cpu);
+#endif
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ca : 
+      return i960base_h_cc_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-cc.  */
+
+void
+a_i960_h_cc_set (SIM_CPU *current_cpu, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ka_sa : 
+      i960base_h_cc_set (current_cpu, newval);
+      break;
+#endif
+#ifdef HAVE_CPU_I960BASE
+    case bfd_mach_i960_ca : 
+      i960base_h_cc_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
diff --git a/sim/i960/arch.h b/sim/i960/arch.h
new file mode 100644
index 00000000000..26dcfd659c4
--- /dev/null
+++ b/sim/i960/arch.h
@@ -0,0 +1,52 @@
+/* Simulator header for i960.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef I960_ARCH_H
+#define I960_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Cover fns for register access.  */
+USI a_i960_h_pc_get (SIM_CPU *);
+void a_i960_h_pc_set (SIM_CPU *, USI);
+SI a_i960_h_gr_get (SIM_CPU *, UINT);
+void a_i960_h_gr_set (SIM_CPU *, UINT, SI);
+SI a_i960_h_cc_get (SIM_CPU *);
+void a_i960_h_cc_set (SIM_CPU *, SI);
+
+/* Enum declaration for model types.  */
+typedef enum model_type {
+  MODEL_I960KA, MODEL_I960CA, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types.  */
+typedef enum unit_type {
+  UNIT_NONE, UNIT_I960KA_U_EXEC, UNIT_I960CA_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+#endif /* I960_ARCH_H */
diff --git a/sim/i960/config.in b/sim/i960/config.in
new file mode 100644
index 00000000000..9723b8662c9
--- /dev/null
+++ b/sim/i960/config.in
@@ -0,0 +1,162 @@
+/* config.in.  Generated automatically from configure.in by autoheader.  */
+
+/* Define if using alloca.c.  */
+#undef C_ALLOCA
+
+/* Define to empty if the keyword does not work.  */
+#undef const
+
+/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
+   This function is required for alloca.c support on those systems.  */
+#undef CRAY_STACKSEG_END
+
+/* Define if you have alloca, as a function or macro.  */
+#undef HAVE_ALLOCA
+
+/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
+#undef HAVE_ALLOCA_H
+
+/* Define if you have a working `mmap' system call.  */
+#undef HAVE_MMAP
+
+/* Define as __inline if that's what the C compiler calls it.  */
+#undef inline
+
+/* Define to `long' if <sys/types.h> doesn't define.  */
+#undef off_t
+
+/* Define if you need to in order for stat and other things to work.  */
+#undef _POSIX_SOURCE
+
+/* Define as the return type of signal handlers (int or void).  */
+#undef RETSIGTYPE
+
+/* Define to `unsigned' if <sys/types.h> doesn't define.  */
+#undef size_t
+
+/* If using the C implementation of alloca, define if you know the
+   direction of stack growth for your system; otherwise it will be
+   automatically deduced at run-time.
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown
+ */
+#undef STACK_DIRECTION
+
+/* Define if you have the ANSI C header files.  */
+#undef STDC_HEADERS
+
+/* Define if your processor stores words with the most significant
+   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
+#undef WORDS_BIGENDIAN
+
+/* Define to 1 if NLS is requested.  */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES.  */
+#undef HAVE_LC_MESSAGES
+
+/* Define if you have the __argz_count function.  */
+#undef HAVE___ARGZ_COUNT
+
+/* Define if you have the __argz_next function.  */
+#undef HAVE___ARGZ_NEXT
+
+/* Define if you have the __argz_stringify function.  */
+#undef HAVE___ARGZ_STRINGIFY
+
+/* Define if you have the __setfpucw function.  */
+#undef HAVE___SETFPUCW
+
+/* Define if you have the dcgettext function.  */
+#undef HAVE_DCGETTEXT
+
+/* Define if you have the getcwd function.  */
+#undef HAVE_GETCWD
+
+/* Define if you have the getpagesize function.  */
+#undef HAVE_GETPAGESIZE
+
+/* Define if you have the getrusage function.  */
+#undef HAVE_GETRUSAGE
+
+/* Define if you have the munmap function.  */
+#undef HAVE_MUNMAP
+
+/* Define if you have the putenv function.  */
+#undef HAVE_PUTENV
+
+/* Define if you have the setenv function.  */
+#undef HAVE_SETENV
+
+/* Define if you have the setlocale function.  */
+#undef HAVE_SETLOCALE
+
+/* Define if you have the sigaction function.  */
+#undef HAVE_SIGACTION
+
+/* Define if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if you have the strcasecmp function.  */
+#undef HAVE_STRCASECMP
+
+/* Define if you have the strchr function.  */
+#undef HAVE_STRCHR
+
+/* Define if you have the time function.  */
+#undef HAVE_TIME
+
+/* Define if you have the <argz.h> header file.  */
+#undef HAVE_ARGZ_H
+
+/* Define if you have the <fcntl.h> header file.  */
+#undef HAVE_FCNTL_H
+
+/* Define if you have the <fpu_control.h> header file.  */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define if you have the <limits.h> header file.  */
+#undef HAVE_LIMITS_H
+
+/* Define if you have the <locale.h> header file.  */
+#undef HAVE_LOCALE_H
+
+/* Define if you have the <malloc.h> header file.  */
+#undef HAVE_MALLOC_H
+
+/* Define if you have the <nl_types.h> header file.  */
+#undef HAVE_NL_TYPES_H
+
+/* Define if you have the <stdlib.h> header file.  */
+#undef HAVE_STDLIB_H
+
+/* Define if you have the <string.h> header file.  */
+#undef HAVE_STRING_H
+
+/* Define if you have the <strings.h> header file.  */
+#undef HAVE_STRINGS_H
+
+/* Define if you have the <sys/param.h> header file.  */
+#undef HAVE_SYS_PARAM_H
+
+/* Define if you have the <sys/resource.h> header file.  */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define if you have the <sys/time.h> header file.  */
+#undef HAVE_SYS_TIME_H
+
+/* Define if you have the <time.h> header file.  */
+#undef HAVE_TIME_H
+
+/* Define if you have the <unistd.h> header file.  */
+#undef HAVE_UNISTD_H
+
+/* Define if you have the <values.h> header file.  */
+#undef HAVE_VALUES_H
diff --git a/sim/i960/configure b/sim/i960/configure
new file mode 100755
index 00000000000..a0f084790ca
--- /dev/null
+++ b/sim/i960/configure
@@ -0,0 +1,4222 @@
+#! /bin/sh
+
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+sim_inline="-DDEFAULT_INLINE=0"
+
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+# This file is derived from `gettext.m4'.  The difference is that the
+# included macros assume Cygnus-style source and build trees.
+
+# Macro to add for using GNU gettext.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 3
+
+
+
+
+
+# Search path for a program which passes the given test.
+# Ulrich Drepper <drepper@cygnus.com>, 1996.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+# Check whether LC_MESSAGES is available in <locale.h>.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+# Check to see if we're running under Cygwin32, without using
+# AC_CANONICAL_*.  If so, set output variable CYGWIN32 to "yes".
+# Otherwise set it to "no".
+
+
+
+# Check to see if we're running under Win32, without using
+# AC_CANONICAL_*.  If so, set output variable EXEEXT to ".exe".
+# Otherwise set it to "".
+
+
+
+
+
+
+# Guess values for system-dependent variables and create Makefiles.
+# Generated automatically using autoconf version 2.13 
+# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+
+# Defaults:
+ac_help=
+ac_default_prefix=/usr/local
+# Any additions from configure.in:
+ac_help="$ac_help
+  --disable-nls           do not use Native Language Support"
+ac_help="$ac_help
+  --with-included-gettext use the GNU gettext library included here"
+ac_help="$ac_help
+  --enable-maintainer-mode		Enable developer functionality."
+ac_help="$ac_help
+  --enable-sim-bswap			Use Host specific BSWAP instruction."
+ac_help="$ac_help
+  --enable-sim-cflags=opts		Extra CFLAGS for use in building simulator"
+ac_help="$ac_help
+  --enable-sim-debug=opts		Enable debugging flags"
+ac_help="$ac_help
+  --enable-sim-stdio			Specify whether to use stdio for console input/output."
+ac_help="$ac_help
+  --enable-sim-trace=opts		Enable tracing flags"
+ac_help="$ac_help
+  --enable-sim-profile=opts		Enable profiling flags"
+ac_help="$ac_help
+  --enable-sim-endian=endian		Specify target byte endian orientation."
+ac_help="$ac_help
+  --enable-sim-alignment=align		Specify strict,  nonstrict or forced alignment of memory accesses."
+ac_help="$ac_help
+  --enable-sim-hostendian=end		Specify host byte endian orientation."
+ac_help="$ac_help
+  --enable-sim-scache=size		Specify simulator execution cache size."
+ac_help="$ac_help
+  --enable-sim-default-model=model	Specify default model to simulate."
+ac_help="$ac_help
+  --enable-sim-environment=environment	Specify mixed, user, virtual or operating environment."
+ac_help="$ac_help
+  --enable-cgen-maint[=DIR]    build cgen generated files"
+
+# Initialize some variables set by options.
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+build=NONE
+cache_file=./config.cache
+exec_prefix=NONE
+host=NONE
+no_create=
+nonopt=NONE
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+target=NONE
+verbose=
+x_includes=NONE
+x_libraries=NONE
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
+mandir='${prefix}/man'
+
+# Initialize some other variables.
+subdirs=
+MFLAGS= MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+# Maximum number of lines to put in a shell here document.
+ac_max_here_lines=12
+
+ac_prev=
+for ac_option
+do
+
+  # If the previous option needs an argument, assign it.
+  if test -n "$ac_prev"; then
+    eval "$ac_prev=\$ac_option"
+    ac_prev=
+    continue
+  fi
+
+  case "$ac_option" in
+  -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
+  *) ac_optarg= ;;
+  esac
+
+  # Accept the important Cygnus configure options, so we can diagnose typos.
+
+  case "$ac_option" in
+
+  -bindir | --bindir | --bindi | --bind | --bin | --bi)
+    ac_prev=bindir ;;
+  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+    bindir="$ac_optarg" ;;
+
+  -build | --build | --buil | --bui | --bu)
+    ac_prev=build ;;
+  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+    build="$ac_optarg" ;;
+
+  -cache-file | --cache-file | --cache-fil | --cache-fi \
+  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+    ac_prev=cache_file ;;
+  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+    cache_file="$ac_optarg" ;;
+
+  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+    ac_prev=datadir ;;
+  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
+  | --da=*)
+    datadir="$ac_optarg" ;;
+
+  -disable-* | --disable-*)
+    ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
+      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+    fi
+    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+    eval "enable_${ac_feature}=no" ;;
+
+  -enable-* | --enable-*)
+    ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
+      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+    fi
+    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+    case "$ac_option" in
+      *=*) ;;
+      *) ac_optarg=yes ;;
+    esac
+    eval "enable_${ac_feature}='$ac_optarg'" ;;
+
+  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+  | --exec | --exe | --ex)
+    ac_prev=exec_prefix ;;
+  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+  | --exec=* | --exe=* | --ex=*)
+    exec_prefix="$ac_optarg" ;;
+
+  -gas | --gas | --ga | --g)
+    # Obsolete; use --with-gas.
+    with_gas=yes ;;
+
+  -help | --help | --hel | --he)
+    # Omit some internal or obsolete options to make the list less imposing.
+    # This message is too long to be a string in the A/UX 3.1 sh.
+    cat << EOF
+Usage: configure [options] [host]
+Options: [defaults in brackets after descriptions]
+Configuration:
+  --cache-file=FILE       cache test results in FILE
+  --help                  print this message
+  --no-create             do not create output files
+  --quiet, --silent       do not print \`checking...' messages
+  --version               print the version of autoconf that created configure
+Directory and file names:
+  --prefix=PREFIX         install architecture-independent files in PREFIX
+                          [$ac_default_prefix]
+  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
+                          [same as prefix]
+  --bindir=DIR            user executables in DIR [EPREFIX/bin]
+  --sbindir=DIR           system admin executables in DIR [EPREFIX/sbin]
+  --libexecdir=DIR        program executables in DIR [EPREFIX/libexec]
+  --datadir=DIR           read-only architecture-independent data in DIR
+                          [PREFIX/share]
+  --sysconfdir=DIR        read-only single-machine data in DIR [PREFIX/etc]
+  --sharedstatedir=DIR    modifiable architecture-independent data in DIR
+                          [PREFIX/com]
+  --localstatedir=DIR     modifiable single-machine data in DIR [PREFIX/var]
+  --libdir=DIR            object code libraries in DIR [EPREFIX/lib]
+  --includedir=DIR        C header files in DIR [PREFIX/include]
+  --oldincludedir=DIR     C header files for non-gcc in DIR [/usr/include]
+  --infodir=DIR           info documentation in DIR [PREFIX/info]
+  --mandir=DIR            man documentation in DIR [PREFIX/man]
+  --srcdir=DIR            find the sources in DIR [configure dir or ..]
+  --program-prefix=PREFIX prepend PREFIX to installed program names
+  --program-suffix=SUFFIX append SUFFIX to installed program names
+  --program-transform-name=PROGRAM
+                          run sed PROGRAM on installed program names
+EOF
+    cat << EOF
+Host type:
+  --build=BUILD           configure for building on BUILD [BUILD=HOST]
+  --host=HOST             configure for HOST [guessed]
+  --target=TARGET         configure for TARGET [TARGET=HOST]
+Features and packages:
+  --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
+  --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
+  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
+  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
+  --x-includes=DIR        X include files are in DIR
+  --x-libraries=DIR       X library files are in DIR
+EOF
+    if test -n "$ac_help"; then
+      echo "--enable and --with options recognized:$ac_help"
+    fi
+    exit 0 ;;
+
+  -host | --host | --hos | --ho)
+    ac_prev=host ;;
+  -host=* | --host=* | --hos=* | --ho=*)
+    host="$ac_optarg" ;;
+
+  -includedir | --includedir | --includedi | --included | --include \
+  | --includ | --inclu | --incl | --inc)
+    ac_prev=includedir ;;
+  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+  | --includ=* | --inclu=* | --incl=* | --inc=*)
+    includedir="$ac_optarg" ;;
+
+  -infodir | --infodir | --infodi | --infod | --info | --inf)
+    ac_prev=infodir ;;
+  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+    infodir="$ac_optarg" ;;
+
+  -libdir | --libdir | --libdi | --libd)
+    ac_prev=libdir ;;
+  -libdir=* | --libdir=* | --libdi=* | --libd=*)
+    libdir="$ac_optarg" ;;
+
+  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+  | --libexe | --libex | --libe)
+    ac_prev=libexecdir ;;
+  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+  | --libexe=* | --libex=* | --libe=*)
+    libexecdir="$ac_optarg" ;;
+
+  -localstatedir | --localstatedir | --localstatedi | --localstated \
+  | --localstate | --localstat | --localsta | --localst \
+  | --locals | --local | --loca | --loc | --lo)
+    ac_prev=localstatedir ;;
+  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+  | --localstate=* | --localstat=* | --localsta=* | --localst=* \
+  | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+    localstatedir="$ac_optarg" ;;
+
+  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+    ac_prev=mandir ;;
+  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+    mandir="$ac_optarg" ;;
+
+  -nfp | --nfp | --nf)
+    # Obsolete; use --without-fp.
+    with_fp=no ;;
+
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c)
+    no_create=yes ;;
+
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+    no_recursion=yes ;;
+
+  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+  | --oldin | --oldi | --old | --ol | --o)
+    ac_prev=oldincludedir ;;
+  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+    oldincludedir="$ac_optarg" ;;
+
+  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+    ac_prev=prefix ;;
+  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+    prefix="$ac_optarg" ;;
+
+  -program-prefix | --program-prefix | --program-prefi | --program-pref \
+  | --program-pre | --program-pr | --program-p)
+    ac_prev=program_prefix ;;
+  -program-prefix=* | --program-prefix=* | --program-prefi=* \
+  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+    program_prefix="$ac_optarg" ;;
+
+  -program-suffix | --program-suffix | --program-suffi | --program-suff \
+  | --program-suf | --program-su | --program-s)
+    ac_prev=program_suffix ;;
+  -program-suffix=* | --program-suffix=* | --program-suffi=* \
+  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+    program_suffix="$ac_optarg" ;;
+
+  -program-transform-name | --program-transform-name \
+  | --program-transform-nam | --program-transform-na \
+  | --program-transform-n | --program-transform- \
+  | --program-transform | --program-transfor \
+  | --program-transfo | --program-transf \
+  | --program-trans | --program-tran \
+  | --progr-tra | --program-tr | --program-t)
+    ac_prev=program_transform_name ;;
+  -program-transform-name=* | --program-transform-name=* \
+  | --program-transform-nam=* | --program-transform-na=* \
+  | --program-transform-n=* | --program-transform-=* \
+  | --program-transform=* | --program-transfor=* \
+  | --program-transfo=* | --program-transf=* \
+  | --program-trans=* | --program-tran=* \
+  | --progr-tra=* | --program-tr=* | --program-t=*)
+    program_transform_name="$ac_optarg" ;;
+
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil)
+    silent=yes ;;
+
+  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+    ac_prev=sbindir ;;
+  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+  | --sbi=* | --sb=*)
+    sbindir="$ac_optarg" ;;
+
+  -sharedstatedir | --sharedstatedir | --sharedstatedi \
+  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+  | --sharedst | --shareds | --shared | --share | --shar \
+  | --sha | --sh)
+    ac_prev=sharedstatedir ;;
+  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+  | --sha=* | --sh=*)
+    sharedstatedir="$ac_optarg" ;;
+
+  -site | --site | --sit)
+    ac_prev=site ;;
+  -site=* | --site=* | --sit=*)
+    site="$ac_optarg" ;;
+
+  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+    ac_prev=srcdir ;;
+  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+    srcdir="$ac_optarg" ;;
+
+  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+  | --syscon | --sysco | --sysc | --sys | --sy)
+    ac_prev=sysconfdir ;;
+  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+    sysconfdir="$ac_optarg" ;;
+
+  -target | --target | --targe | --targ | --tar | --ta | --t)
+    ac_prev=target ;;
+  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+    target="$ac_optarg" ;;
+
+  -v | -verbose | --verbose | --verbos | --verbo | --verb)
+    verbose=yes ;;
+
+  -version | --version | --versio | --versi | --vers)
+    echo "configure generated by autoconf version 2.13"
+    exit 0 ;;
+
+  -with-* | --with-*)
+    ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then
+      { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+    fi
+    ac_package=`echo $ac_package| sed 's/-/_/g'`
+    case "$ac_option" in
+      *=*) ;;
+      *) ac_optarg=yes ;;
+    esac
+    eval "with_${ac_package}='$ac_optarg'" ;;
+
+  -without-* | --without-*)
+    ac_package=`echo $ac_option|sed -e 's/-*without-//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then
+      { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+    fi
+    ac_package=`echo $ac_package| sed 's/-/_/g'`
+    eval "with_${ac_package}=no" ;;
+
+  --x)
+    # Obsolete; use --with-x.
+    with_x=yes ;;
+
+  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+  | --x-incl | --x-inc | --x-in | --x-i)
+    ac_prev=x_includes ;;
+  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+    x_includes="$ac_optarg" ;;
+
+  -x-libraries | --x-libraries | --x-librarie | --x-librari \
+  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+    ac_prev=x_libraries ;;
+  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+    x_libraries="$ac_optarg" ;;
+
+  -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; }
+    ;;
+
+  *)
+    if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then
+      echo "configure: warning: $ac_option: invalid host type" 1>&2
+    fi
+    if test "x$nonopt" != xNONE; then
+      { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; }
+    fi
+    nonopt="$ac_option"
+    ;;
+
+  esac
+done
+
+if test -n "$ac_prev"; then
+  { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; }
+fi
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+# File descriptor usage:
+# 0 standard input
+# 1 file creation
+# 2 errors and warnings
+# 3 some systems may open it to /dev/tty
+# 4 used on the Kubota Titan
+# 6 checking for... messages and results
+# 5 compiler messages saved in config.log
+if test "$silent" = yes; then
+  exec 6>/dev/null
+else
+  exec 6>&1
+fi
+exec 5>./config.log
+
+echo "\
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+" 1>&5
+
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Also quote any args containing shell metacharacters.
+ac_configure_args=
+for ac_arg
+do
+  case "$ac_arg" in
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c) ;;
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;;
+  *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*)
+  ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+  *) ac_configure_args="$ac_configure_args $ac_arg" ;;
+  esac
+done
+
+# NLS nuisances.
+# Only set these to C if already set.  These must not be set unconditionally
+# because not all systems understand e.g. LANG=C (notably SCO).
+# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!
+# Non-C LC_CTYPE values break the ctype check.
+if test "${LANG+set}"   = set; then LANG=C;   export LANG;   fi
+if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi
+if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi
+if test "${LC_CTYPE+set}"    = set; then LC_CTYPE=C;    export LC_CTYPE;    fi
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -rf conftest* confdefs.h
+# AIX cpp loses on an empty file, so make sure it contains at least a newline.
+echo > confdefs.h
+
+# A filename unique to this package, relative to the directory that
+# configure is in, which we can look for to find out if srcdir is correct.
+ac_unique_file=Makefile.in
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+  ac_srcdir_defaulted=yes
+  # Try the directory containing this script, then its parent.
+  ac_prog=$0
+  ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
+  test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
+  srcdir=$ac_confdir
+  if test ! -r $srcdir/$ac_unique_file; then
+    srcdir=..
+  fi
+else
+  ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+  if test "$ac_srcdir_defaulted" = yes; then
+    { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
+  else
+    { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
+  fi
+fi
+srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
+
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$CONFIG_SITE"; then
+  if test "x$prefix" != xNONE; then
+    CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+  else
+    CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+  fi
+fi
+for ac_site_file in $CONFIG_SITE; do
+  if test -r "$ac_site_file"; then
+    echo "loading site script $ac_site_file"
+    . "$ac_site_file"
+  fi
+done
+
+if test -r "$cache_file"; then
+  echo "loading cache $cache_file"
+  . $cache_file
+else
+  echo "creating cache $cache_file"
+  > $cache_file
+fi
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+ac_exeext=
+ac_objext=o
+if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
+  # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
+  if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
+    ac_n= ac_c='
+' ac_t='	'
+  else
+    ac_n=-n ac_c= ac_t=
+  fi
+else
+  ac_n= ac_c='\c' ac_t=
+fi
+
+
+
+echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
+echo "configure:693: checking how to run the C preprocessor" >&5
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+  CPP=
+fi
+if test -z "$CPP"; then
+if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+    # This must be in double quotes, not single quotes, because CPP may get
+  # substituted into the Makefile and "${CC-cc}" will confuse make.
+  CPP="${CC-cc} -E"
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp.
+  cat > conftest.$ac_ext <<EOF
+#line 708 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:714: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP="${CC-cc} -E -traditional-cpp"
+  cat > conftest.$ac_ext <<EOF
+#line 725 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:731: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP="${CC-cc} -nologo -E"
+  cat > conftest.$ac_ext <<EOF
+#line 742 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:748: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP=/lib/cpp
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+  ac_cv_prog_CPP="$CPP"
+fi
+  CPP="$ac_cv_prog_CPP"
+else
+  ac_cv_prog_CPP="$CPP"
+fi
+echo "$ac_t""$CPP" 1>&6
+
+echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6
+echo "configure:773: checking whether ${MAKE-make} sets \${MAKE}" >&5
+set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftestmake <<\EOF
+all:
+	@echo 'ac_maketemp="${MAKE}"'
+EOF
+# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
+eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=`
+if test -n "$ac_maketemp"; then
+  eval ac_cv_prog_make_${ac_make}_set=yes
+else
+  eval ac_cv_prog_make_${ac_make}_set=no
+fi
+rm -f conftestmake
+fi
+if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  SET_MAKE=
+else
+  echo "$ac_t""no" 1>&6
+  SET_MAKE="MAKE=${MAKE-make}"
+fi
+
+echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6
+echo "configure:800: checking for POSIXized ISC" >&5
+if test -d /etc/conf/kconfig.d &&
+  grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1
+then
+  echo "$ac_t""yes" 1>&6
+  ISC=yes # If later tests want to check for ISC.
+  cat >> confdefs.h <<\EOF
+#define _POSIX_SOURCE 1
+EOF
+
+  if test "$GCC" = yes; then
+    CC="$CC -posix"
+  else
+    CC="$CC -Xp"
+  fi
+else
+  echo "$ac_t""no" 1>&6
+  ISC=
+fi
+
+echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
+echo "configure:821: checking for ANSI C header files" >&5
+if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 826 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:834: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  ac_cv_header_stdc=yes
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+if test $ac_cv_header_stdc = yes; then
+  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 851 "configure"
+#include "confdefs.h"
+#include <string.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "memchr" >/dev/null 2>&1; then
+  :
+else
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 869 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "free" >/dev/null 2>&1; then
+  :
+else
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+if test "$cross_compiling" = yes; then
+  :
+else
+  cat > conftest.$ac_ext <<EOF
+#line 890 "configure"
+#include "confdefs.h"
+#include <ctype.h>
+#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int main () { int i; for (i = 0; i < 256; i++)
+if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
+exit (0); }
+
+EOF
+if { (eval echo configure:901: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  :
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_header_stdc=no
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_header_stdc" 1>&6
+if test $ac_cv_header_stdc = yes; then
+  cat >> confdefs.h <<\EOF
+#define STDC_HEADERS 1
+EOF
+
+fi
+
+echo $ac_n "checking for working const""... $ac_c" 1>&6
+echo "configure:925: checking for working const" >&5
+if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 930 "configure"
+#include "confdefs.h"
+
+int main() {
+
+/* Ultrix mips cc rejects this.  */
+typedef int charset[2]; const charset x;
+/* SunOS 4.1.1 cc rejects this.  */
+char const *const *ccp;
+char **p;
+/* NEC SVR4.0.2 mips cc rejects this.  */
+struct point {int x, y;};
+static struct point const zero = {0,0};
+/* AIX XL C 1.02.0.0 rejects this.
+   It does not let you subtract one const X* pointer from another in an arm
+   of an if-expression whose if-part is not a constant expression */
+const char *g = "string";
+ccp = &g + (g ? g-g : 0);
+/* HPUX 7.0 cc rejects these. */
+++ccp;
+p = (char**) ccp;
+ccp = (char const *const *) p;
+{ /* SCO 3.2v4 cc rejects this.  */
+  char *t;
+  char const *s = 0 ? (char *) 0 : (char const *) 0;
+
+  *t++ = 0;
+}
+{ /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
+  int x[] = {25, 17};
+  const int *foo = &x[0];
+  ++foo;
+}
+{ /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
+  typedef const int *iptr;
+  iptr p = 0;
+  ++p;
+}
+{ /* AIX XL C 1.02.0.0 rejects this saying
+     "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
+  struct s { int j; const int *ap[3]; };
+  struct s *b; b->j = 5;
+}
+{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
+  const int foo = 10;
+}
+
+; return 0; }
+EOF
+if { (eval echo configure:979: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_const=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_c_const=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_c_const" 1>&6
+if test $ac_cv_c_const = no; then
+  cat >> confdefs.h <<\EOF
+#define const 
+EOF
+
+fi
+
+echo $ac_n "checking for inline""... $ac_c" 1>&6
+echo "configure:1000: checking for inline" >&5
+if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_cv_c_inline=no
+for ac_kw in inline __inline__ __inline; do
+  cat > conftest.$ac_ext <<EOF
+#line 1007 "configure"
+#include "confdefs.h"
+
+int main() {
+} $ac_kw foo() {
+; return 0; }
+EOF
+if { (eval echo configure:1014: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_inline=$ac_kw; break
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+done
+
+fi
+
+echo "$ac_t""$ac_cv_c_inline" 1>&6
+case "$ac_cv_c_inline" in
+  inline | yes) ;;
+  no) cat >> confdefs.h <<\EOF
+#define inline 
+EOF
+ ;;
+  *)  cat >> confdefs.h <<EOF
+#define inline $ac_cv_c_inline
+EOF
+ ;;
+esac
+
+echo $ac_n "checking for off_t""... $ac_c" 1>&6
+echo "configure:1040: checking for off_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1045 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_type_off_t=yes
+else
+  rm -rf conftest*
+  ac_cv_type_off_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_off_t" 1>&6
+if test $ac_cv_type_off_t = no; then
+  cat >> confdefs.h <<\EOF
+#define off_t long
+EOF
+
+fi
+
+echo $ac_n "checking for size_t""... $ac_c" 1>&6
+echo "configure:1073: checking for size_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1078 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_type_size_t=yes
+else
+  rm -rf conftest*
+  ac_cv_type_size_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_size_t" 1>&6
+if test $ac_cv_type_size_t = no; then
+  cat >> confdefs.h <<\EOF
+#define size_t unsigned
+EOF
+
+fi
+
+# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
+# for constant arguments.  Useless!
+echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
+echo "configure:1108: checking for working alloca.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1113 "configure"
+#include "confdefs.h"
+#include <alloca.h>
+int main() {
+char *p = alloca(2 * sizeof(int));
+; return 0; }
+EOF
+if { (eval echo configure:1120: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  ac_cv_header_alloca_h=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_header_alloca_h=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_header_alloca_h" 1>&6
+if test $ac_cv_header_alloca_h = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA_H 1
+EOF
+
+fi
+
+echo $ac_n "checking for alloca""... $ac_c" 1>&6
+echo "configure:1141: checking for alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1146 "configure"
+#include "confdefs.h"
+
+#ifdef __GNUC__
+# define alloca __builtin_alloca
+#else
+# ifdef _MSC_VER
+#  include <malloc.h>
+#  define alloca _alloca
+# else
+#  if HAVE_ALLOCA_H
+#   include <alloca.h>
+#  else
+#   ifdef _AIX
+ #pragma alloca
+#   else
+#    ifndef alloca /* predefined by HP cc +Olibcalls */
+char *alloca ();
+#    endif
+#   endif
+#  endif
+# endif
+#endif
+
+int main() {
+char *p = (char *) alloca(1);
+; return 0; }
+EOF
+if { (eval echo configure:1174: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  ac_cv_func_alloca_works=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_func_alloca_works=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_func_alloca_works" 1>&6
+if test $ac_cv_func_alloca_works = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA 1
+EOF
+
+fi
+
+if test $ac_cv_func_alloca_works = no; then
+  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
+  # that cause trouble.  Some versions do not even contain alloca or
+  # contain a buggy version.  If you still want to use their alloca,
+  # use ar to extract alloca.o from them instead of compiling alloca.c.
+  ALLOCA=alloca.${ac_objext}
+  cat >> confdefs.h <<\EOF
+#define C_ALLOCA 1
+EOF
+
+
+echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
+echo "configure:1206: checking whether alloca needs Cray hooks" >&5
+if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1211 "configure"
+#include "confdefs.h"
+#if defined(CRAY) && ! defined(CRAY2)
+webecray
+#else
+wenotbecray
+#endif
+
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "webecray" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_os_cray=yes
+else
+  rm -rf conftest*
+  ac_cv_os_cray=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_os_cray" 1>&6
+if test $ac_cv_os_cray = yes; then
+for ac_func in _getb67 GETB67 getb67; do
+  echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1236: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1241 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1264: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  cat >> confdefs.h <<EOF
+#define CRAY_STACKSEG_END $ac_func
+EOF
+
+  break
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+done
+fi
+
+echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
+echo "configure:1291: checking stack direction for C alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$cross_compiling" = yes; then
+  ac_cv_c_stack_direction=0
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1299 "configure"
+#include "confdefs.h"
+find_stack_direction ()
+{
+  static char *addr = 0;
+  auto char dummy;
+  if (addr == 0)
+    {
+      addr = &dummy;
+      return find_stack_direction ();
+    }
+  else
+    return (&dummy > addr) ? 1 : -1;
+}
+main ()
+{
+  exit (find_stack_direction() < 0);
+}
+EOF
+if { (eval echo configure:1318: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_c_stack_direction=1
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_c_stack_direction=-1
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_c_stack_direction" 1>&6
+cat >> confdefs.h <<EOF
+#define STACK_DIRECTION $ac_cv_c_stack_direction
+EOF
+
+fi
+
+for ac_hdr in unistd.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:1343: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1348 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1353: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getpagesize
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1382: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1387 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1410: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+echo $ac_n "checking for working mmap""... $ac_c" 1>&6
+echo "configure:1435: checking for working mmap" >&5
+if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$cross_compiling" = yes; then
+  ac_cv_func_mmap_fixed_mapped=no
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1443 "configure"
+#include "confdefs.h"
+
+/* Thanks to Mike Haertel and Jim Avera for this test.
+   Here is a matrix of mmap possibilities:
+	mmap private not fixed
+	mmap private fixed at somewhere currently unmapped
+	mmap private fixed at somewhere already mapped
+	mmap shared not fixed
+	mmap shared fixed at somewhere currently unmapped
+	mmap shared fixed at somewhere already mapped
+   For private mappings, we should verify that changes cannot be read()
+   back from the file, nor mmap's back from the file at a different
+   address.  (There have been systems where private was not correctly
+   implemented like the infamous i386 svr4.0, and systems where the
+   VM page cache was not coherent with the filesystem buffer cache
+   like early versions of FreeBSD and possibly contemporary NetBSD.)
+   For shared mappings, we should conversely verify that changes get
+   propogated back to all the places they're supposed to be.
+
+   Grep wants private fixed already mapped.
+   The main things grep needs to know about mmap are:
+   * does it exist and is it safe to write into the mmap'd area
+   * how to use it (BSD variants)  */
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+/* This mess was copied from the GNU getpagesize.h.  */
+#ifndef HAVE_GETPAGESIZE
+# ifdef HAVE_UNISTD_H
+#  include <unistd.h>
+# endif
+
+/* Assume that all systems that can run configure have sys/param.h.  */
+# ifndef HAVE_SYS_PARAM_H
+#  define HAVE_SYS_PARAM_H 1
+# endif
+
+# ifdef _SC_PAGESIZE
+#  define getpagesize() sysconf(_SC_PAGESIZE)
+# else /* no _SC_PAGESIZE */
+#  ifdef HAVE_SYS_PARAM_H
+#   include <sys/param.h>
+#   ifdef EXEC_PAGESIZE
+#    define getpagesize() EXEC_PAGESIZE
+#   else /* no EXEC_PAGESIZE */
+#    ifdef NBPG
+#     define getpagesize() NBPG * CLSIZE
+#     ifndef CLSIZE
+#      define CLSIZE 1
+#     endif /* no CLSIZE */
+#    else /* no NBPG */
+#     ifdef NBPC
+#      define getpagesize() NBPC
+#     else /* no NBPC */
+#      ifdef PAGESIZE
+#       define getpagesize() PAGESIZE
+#      endif /* PAGESIZE */
+#     endif /* no NBPC */
+#    endif /* no NBPG */
+#   endif /* no EXEC_PAGESIZE */
+#  else /* no HAVE_SYS_PARAM_H */
+#   define getpagesize() 8192	/* punt totally */
+#  endif /* no HAVE_SYS_PARAM_H */
+# endif /* no _SC_PAGESIZE */
+
+#endif /* no HAVE_GETPAGESIZE */
+
+#ifdef __cplusplus
+extern "C" { void *malloc(unsigned); }
+#else
+char *malloc();
+#endif
+
+int
+main()
+{
+	char *data, *data2, *data3;
+	int i, pagesize;
+	int fd;
+
+	pagesize = getpagesize();
+
+	/*
+	 * First, make a file with some known garbage in it.
+	 */
+	data = malloc(pagesize);
+	if (!data)
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		*(data + i) = rand();
+	umask(0);
+	fd = creat("conftestmmap", 0600);
+	if (fd < 0)
+		exit(1);
+	if (write(fd, data, pagesize) != pagesize)
+		exit(1);
+	close(fd);
+
+	/*
+	 * Next, try to mmap the file at a fixed address which
+	 * already has something else allocated at it.  If we can,
+	 * also make sure that we see the same garbage.
+	 */
+	fd = open("conftestmmap", O_RDWR);
+	if (fd < 0)
+		exit(1);
+	data2 = malloc(2 * pagesize);
+	if (!data2)
+		exit(1);
+	data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1);
+	if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE,
+	    MAP_PRIVATE | MAP_FIXED, fd, 0L))
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		if (*(data + i) != *(data2 + i))
+			exit(1);
+
+	/*
+	 * Finally, make sure that changes to the mapped area
+	 * do not percolate back to the file as seen by read().
+	 * (This is a bug on some variants of i386 svr4.0.)
+	 */
+	for (i = 0; i < pagesize; ++i)
+		*(data2 + i) = *(data2 + i) + 1;
+	data3 = malloc(pagesize);
+	if (!data3)
+		exit(1);
+	if (read(fd, data3, pagesize) != pagesize)
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		if (*(data + i) != *(data3 + i))
+			exit(1);
+	close(fd);
+	unlink("conftestmmap");
+	exit(0);
+}
+
+EOF
+if { (eval echo configure:1583: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_func_mmap_fixed_mapped=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_func_mmap_fixed_mapped=no
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6
+if test $ac_cv_func_mmap_fixed_mapped = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_MMAP 1
+EOF
+
+fi
+
+
+# autoconf.info says this should be called right after AC_INIT.
+
+
+ac_aux_dir=
+for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do
+  if test -f $ac_dir/install-sh; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install-sh -c"
+    break
+  elif test -f $ac_dir/install.sh; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install.sh -c"
+    break
+  fi
+done
+if test -z "$ac_aux_dir"; then
+  { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; }
+fi
+ac_config_guess=$ac_aux_dir/config.guess
+ac_config_sub=$ac_aux_dir/config.sub
+ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
+
+
+# Do some error checking and defaulting for the host and target type.
+# The inputs are:
+#    configure --host=HOST --target=TARGET --build=BUILD NONOPT
+#
+# The rules are:
+# 1. You are not allowed to specify --host, --target, and nonopt at the
+#    same time.
+# 2. Host defaults to nonopt.
+# 3. If nonopt is not specified, then host defaults to the current host,
+#    as determined by config.guess.
+# 4. Target and build default to nonopt.
+# 5. If nonopt is not specified, then target and build default to host.
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+case $host---$target---$nonopt in
+NONE---*---* | *---NONE---* | *---*---NONE) ;;
+*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;;
+esac
+
+
+# Make sure we can run config.sub.
+if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then :
+else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking host system type""... $ac_c" 1>&6
+echo "configure:1656: checking host system type" >&5
+
+host_alias=$host
+case "$host_alias" in
+NONE)
+  case $nonopt in
+  NONE)
+    if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then :
+    else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
+    fi ;;
+  *) host_alias=$nonopt ;;
+  esac ;;
+esac
+
+host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias`
+host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$host" 1>&6
+
+echo $ac_n "checking target system type""... $ac_c" 1>&6
+echo "configure:1677: checking target system type" >&5
+
+target_alias=$target
+case "$target_alias" in
+NONE)
+  case $nonopt in
+  NONE) target_alias=$host_alias ;;
+  *) target_alias=$nonopt ;;
+  esac ;;
+esac
+
+target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias`
+target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$target" 1>&6
+
+echo $ac_n "checking build system type""... $ac_c" 1>&6
+echo "configure:1695: checking build system type" >&5
+
+build_alias=$build
+case "$build_alias" in
+NONE)
+  case $nonopt in
+  NONE) build_alias=$host_alias ;;
+  *) build_alias=$nonopt ;;
+  esac ;;
+esac
+
+build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias`
+build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$build" 1>&6
+
+test "$host_alias" != "$target_alias" &&
+  test "$program_prefix$program_suffix$program_transform_name" = \
+    NONENONEs,x,x, &&
+  program_prefix=${target_alias}-
+
+if test "$program_transform_name" = s,x,x,; then
+  program_transform_name=
+else
+  # Double any \ or $.  echo might interpret backslashes.
+  cat <<\EOF_SED > conftestsed
+s,\\,\\\\,g; s,\$,$$,g
+EOF_SED
+  program_transform_name="`echo $program_transform_name|sed -f conftestsed`"
+  rm -f conftestsed
+fi
+test "$program_prefix" != NONE &&
+  program_transform_name="s,^,${program_prefix},; $program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+  program_transform_name="s,\$\$,${program_suffix},; $program_transform_name"
+
+# sed with no file args requires a program.
+test "$program_transform_name" = "" && program_transform_name="s,x,x,"
+
+# Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1739: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_CC="gcc"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+if test -z "$CC"; then
+  # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1769: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_prog_rejected=no
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
+        ac_prog_rejected=yes
+	continue
+      fi
+      ac_cv_prog_CC="cc"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+if test $ac_prog_rejected = yes; then
+  # We found a bogon in the path, so make sure we never use it.
+  set dummy $ac_cv_prog_CC
+  shift
+  if test $# -gt 0; then
+    # We chose a different compiler from the bogus one.
+    # However, it has the same basename, so the bogon will be chosen
+    # first if we set CC to just the basename; use the full file name.
+    shift
+    set dummy "$ac_dir/$ac_word" "$@"
+    shift
+    ac_cv_prog_CC="$@"
+  fi
+fi
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+  if test -z "$CC"; then
+    case "`uname -s`" in
+    *win32* | *WIN32*)
+      # Extract the first word of "cl", so it can be a program name with args.
+set dummy cl; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1820: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_CC="cl"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+ ;;
+    esac
+  fi
+  test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
+echo "configure:1852: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+cat > conftest.$ac_ext << EOF
+
+#line 1863 "configure"
+#include "confdefs.h"
+
+main(){return(0);}
+EOF
+if { (eval echo configure:1868: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  ac_cv_prog_cc_works=yes
+  # If we can't run a trivial program, we are probably using a cross compiler.
+  if (./conftest; exit) 2>/dev/null; then
+    ac_cv_prog_cc_cross=no
+  else
+    ac_cv_prog_cc_cross=yes
+  fi
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  ac_cv_prog_cc_works=no
+fi
+rm -fr conftest*
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
+if test $ac_cv_prog_cc_works = no; then
+  { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
+fi
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
+echo "configure:1894: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
+echo "configure:1899: checking whether we are using GNU C" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.c <<EOF
+#ifdef __GNUC__
+  yes;
+#endif
+EOF
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1908: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+  ac_cv_prog_gcc=yes
+else
+  ac_cv_prog_gcc=no
+fi
+fi
+
+echo "$ac_t""$ac_cv_prog_gcc" 1>&6
+
+if test $ac_cv_prog_gcc = yes; then
+  GCC=yes
+else
+  GCC=
+fi
+
+ac_test_CFLAGS="${CFLAGS+set}"
+ac_save_CFLAGS="$CFLAGS"
+CFLAGS=
+echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
+echo "configure:1927: checking whether ${CC-cc} accepts -g" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  echo 'void f(){}' > conftest.c
+if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
+  ac_cv_prog_cc_g=yes
+else
+  ac_cv_prog_cc_g=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
+if test "$ac_test_CFLAGS" = set; then
+  CFLAGS="$ac_save_CFLAGS"
+elif test $ac_cv_prog_cc_g = yes; then
+  if test "$GCC" = yes; then
+    CFLAGS="-g -O2"
+  else
+    CFLAGS="-g"
+  fi
+else
+  if test "$GCC" = yes; then
+    CFLAGS="-O2"
+  else
+    CFLAGS=
+  fi
+fi
+
+# Find a good install program.  We prefer a C program (faster),
+# so one script is as good as another.  But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# ./install, which can be erroneously created by make from ./install.sh.
+echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
+echo "configure:1970: checking for a BSD compatible install" >&5
+if test -z "$INSTALL"; then
+if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+    IFS="${IFS= 	}"; ac_save_IFS="$IFS"; IFS=":"
+  for ac_dir in $PATH; do
+    # Account for people who put trailing slashes in PATH elements.
+    case "$ac_dir/" in
+    /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
+    *)
+      # OSF1 and SCO ODT 3.0 have their own names for install.
+      # Don't use installbsd from OSF since it installs stuff as root
+      # by default.
+      for ac_prog in ginstall scoinst install; do
+        if test -f $ac_dir/$ac_prog; then
+	  if test $ac_prog = install &&
+            grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
+	    # AIX install.  It has an incompatible calling convention.
+	    :
+	  else
+	    ac_cv_path_install="$ac_dir/$ac_prog -c"
+	    break 2
+	  fi
+	fi
+      done
+      ;;
+    esac
+  done
+  IFS="$ac_save_IFS"
+
+fi
+  if test "${ac_cv_path_install+set}" = set; then
+    INSTALL="$ac_cv_path_install"
+  else
+    # As a last resort, use the slow shell script.  We don't cache a
+    # path for INSTALL within a source directory, because that will
+    # break other packages using the cache if that directory is
+    # removed, or if the path is relative.
+    INSTALL="$ac_install_sh"
+  fi
+fi
+echo "$ac_t""$INSTALL" 1>&6
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+  CC_FOR_BUILD='$(CC)'
+else
+  CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+# Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2038: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_RANLIB="ranlib"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
+fi
+fi
+RANLIB="$ac_cv_prog_RANLIB"
+if test -n "$RANLIB"; then
+  echo "$ac_t""$RANLIB" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+ALL_LINGUAS=
+                              
+   for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \
+unistd.h values.h sys/param.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2073: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2078 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2083: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+   for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
+__argz_count __argz_stringify __argz_next
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2113: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2118 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2141: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+
+   if test "${ac_cv_func_stpcpy+set}" != "set"; then
+     for ac_func in stpcpy
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2170: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2175 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2198: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+   fi
+   if test "${ac_cv_func_stpcpy}" = "yes"; then
+     cat >> confdefs.h <<\EOF
+#define HAVE_STPCPY 1
+EOF
+
+   fi
+
+   if test $ac_cv_header_locale_h = yes; then
+    echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
+echo "configure:2232: checking for LC_MESSAGES" >&5
+if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2237 "configure"
+#include "confdefs.h"
+#include <locale.h>
+int main() {
+return LC_MESSAGES
+; return 0; }
+EOF
+if { (eval echo configure:2244: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  am_cv_val_LC_MESSAGES=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  am_cv_val_LC_MESSAGES=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6
+    if test $am_cv_val_LC_MESSAGES = yes; then
+      cat >> confdefs.h <<\EOF
+#define HAVE_LC_MESSAGES 1
+EOF
+
+    fi
+  fi
+   echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
+echo "configure:2265: checking whether NLS is requested" >&5
+        # Check whether --enable-nls or --disable-nls was given.
+if test "${enable_nls+set}" = set; then
+  enableval="$enable_nls"
+  USE_NLS=$enableval
+else
+  USE_NLS=yes
+fi
+
+    echo "$ac_t""$USE_NLS" 1>&6
+    
+
+    USE_INCLUDED_LIBINTL=no
+
+        if test "$USE_NLS" = "yes"; then
+      cat >> confdefs.h <<\EOF
+#define ENABLE_NLS 1
+EOF
+
+      echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
+echo "configure:2285: checking whether included gettext is requested" >&5
+      # Check whether --with-included-gettext or --without-included-gettext was given.
+if test "${with_included_gettext+set}" = set; then
+  withval="$with_included_gettext"
+  nls_cv_force_use_gnu_gettext=$withval
+else
+  nls_cv_force_use_gnu_gettext=no
+fi
+
+      echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6
+
+      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
+      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
+                        		nls_cv_header_intl=
+	nls_cv_header_libgt=
+	CATOBJEXT=NONE
+
+	ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
+echo "configure:2304: checking for libintl.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2309 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2314: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
+echo "configure:2331: checking for gettext in libc" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2336 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2343: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  gt_cv_func_gettext_libc=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  gt_cv_func_gettext_libc=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
+
+	   if test "$gt_cv_func_gettext_libc" != "yes"; then
+	     echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
+echo "configure:2359: checking for bindtextdomain in -lintl" >&5
+ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lintl  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 2367 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char bindtextdomain();
+
+int main() {
+bindtextdomain()
+; return 0; }
+EOF
+if { (eval echo configure:2378: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
+echo "configure:2394: checking for gettext in libintl" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2399 "configure"
+#include "confdefs.h"
+
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2406: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  gt_cv_func_gettext_libintl=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  gt_cv_func_gettext_libintl=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+	   fi
+
+	   if test "$gt_cv_func_gettext_libc" = "yes" \
+	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
+	      cat >> confdefs.h <<\EOF
+#define HAVE_GETTEXT 1
+EOF
+
+	      # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2434: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MSGFMT" in
+  /*)
+  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
+  ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+  echo "$ac_t""$MSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+	      if test "$MSGFMT" != "no"; then
+		for ac_func in dcgettext
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2468: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2473 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2496: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+		# Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2523: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$GMSGFMT" in
+  /*)
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+  ;;
+  ?:/*)			 
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do 
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+  ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+  echo "$ac_t""$GMSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+		# Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2559: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$XGETTEXT" in
+  /*)
+  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+  ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+  echo "$ac_t""$XGETTEXT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+		cat > conftest.$ac_ext <<EOF
+#line 2591 "configure"
+#include "confdefs.h"
+
+int main() {
+extern int _nl_msg_cat_cntr;
+			       return _nl_msg_cat_cntr
+; return 0; }
+EOF
+if { (eval echo configure:2599: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  CATOBJEXT=.gmo
+		   DATADIRNAME=share
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CATOBJEXT=.mo
+		   DATADIRNAME=lib
+fi
+rm -f conftest*
+		INSTOBJEXT=.mo
+	      fi
+	    fi
+	
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+	        
+        if test "$CATOBJEXT" = "NONE"; then
+	  	  	  nls_cv_use_gnu_gettext=yes
+        fi
+      fi
+
+      if test "$nls_cv_use_gnu_gettext" = "yes"; then
+                INTLOBJS="\$(GETTOBJS)"
+        # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2631: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MSGFMT" in
+  /*)
+  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
+  ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+  echo "$ac_t""$MSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        # Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2665: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$GMSGFMT" in
+  /*)
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+  ;;
+  ?:/*)			 
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do 
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+  ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+  echo "$ac_t""$GMSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        # Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2701: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$XGETTEXT" in
+  /*)
+  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+  ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+  echo "$ac_t""$XGETTEXT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        
+	USE_INCLUDED_LIBINTL=yes
+        CATOBJEXT=.gmo
+        INSTOBJEXT=.mo
+        DATADIRNAME=share
+	INTLDEPS='$(top_builddir)/../intl/libintl.a'
+	INTLLIBS=$INTLDEPS
+	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
+        nls_cv_header_intl=libintl.h
+        nls_cv_header_libgt=libgettext.h
+      fi
+
+            if test "$XGETTEXT" != ":"; then
+			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
+	  : ;
+	else
+	  echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6
+	  XGETTEXT=":"
+	fi
+      fi
+
+      # We need to process the po/ directory.
+      POSUB=po
+    else
+      DATADIRNAME=share
+      nls_cv_header_intl=libintl.h
+      nls_cv_header_libgt=libgettext.h
+    fi
+
+    # If this is used in GNU gettext we have to set USE_NLS to `yes'
+    # because some of the sources are only built for this goal.
+    if test "$PACKAGE" = gettext; then
+      USE_NLS=yes
+      USE_INCLUDED_LIBINTL=yes
+    fi
+
+                for lang in $ALL_LINGUAS; do
+      GMOFILES="$GMOFILES $lang.gmo"
+      POFILES="$POFILES $lang.po"
+    done
+
+        
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+
+   if test "x$CATOBJEXT" != "x"; then
+     if test "x$ALL_LINGUAS" = "x"; then
+       LINGUAS=
+     else
+       echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
+echo "configure:2791: checking for catalogs to be installed" >&5
+       NEW_LINGUAS=
+       for lang in ${LINGUAS=$ALL_LINGUAS}; do
+         case "$ALL_LINGUAS" in
+          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
+         esac
+       done
+       LINGUAS=$NEW_LINGUAS
+       echo "$ac_t""$LINGUAS" 1>&6
+     fi
+
+          if test -n "$LINGUAS"; then
+       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
+     fi
+   fi
+
+            if test $ac_cv_header_locale_h = yes; then
+     INCLUDE_LOCALE_H="#include <locale.h>"
+   else
+     INCLUDE_LOCALE_H="\
+/* The system does not provide the header <locale.h>.  Take care yourself.  */"
+   fi
+   
+
+            if test -f $srcdir/po2tbl.sed.in; then
+      if test "$CATOBJEXT" = ".cat"; then
+	 ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
+echo "configure:2819: checking for linux/version.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2824 "configure"
+#include "confdefs.h"
+#include <linux/version.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2829: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  msgformat=linux
+else
+  echo "$ac_t""no" 1>&6
+msgformat=xopen
+fi
+
+
+	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
+      fi
+            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
+	 $srcdir/po2tbl.sed.in > po2tbl.sed
+   fi
+
+            if test "$PACKAGE" = "gettext"; then
+     GT_NO="#NO#"
+     GT_YES=
+   else
+     GT_NO=
+     GT_YES="#YES#"
+   fi
+   
+   
+
+   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
+   
+
+      l=
+   
+
+            if test -d $srcdir/po; then
+      test -d po || mkdir po
+      if test "x$srcdir" != "x."; then
+	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
+	    posrcprefix="$srcdir/"
+	 else
+	    posrcprefix="../$srcdir/"
+	 fi
+      else
+	 posrcprefix="../"
+      fi
+      rm -f po/POTFILES
+      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
+	 < $srcdir/po/POTFILES.in > po/POTFILES
+   fi
+  
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+for ac_hdr in stdlib.h string.h strings.h unistd.h time.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2898: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2903 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2908: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in sys/time.h sys/resource.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2938: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2943 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2948: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in fcntl.h fpu_control.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2978: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2983 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2988: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in dlfcn.h errno.h sys/stat.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3018: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3023 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3028: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getrusage time sigaction __setfpucw
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:3057: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3062 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:3085: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+
+# Check for socket libraries
+echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6
+echo "configure:3112: checking for bind in -lsocket" >&5
+ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lsocket  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3120 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char bind();
+
+int main() {
+bind()
+; return 0; }
+EOF
+if { (eval echo configure:3131: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+  LIBS="-lsocket $LIBS"
+
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6
+echo "configure:3159: checking for gethostbyname in -lnsl" >&5
+ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lnsl  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3167 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char gethostbyname();
+
+int main() {
+gethostbyname()
+; return 0; }
+EOF
+if { (eval echo configure:3178: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+  LIBS="-lnsl $LIBS"
+
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then
+  enableval="$enable_maintainer_mode"
+  case "${enableval}" in
+  yes)	MAINT="" USE_MAINTAINER_MODE=yes ;;
+  no)	MAINT="#" ;;
+  *)	{ echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+  echo "Setting maintainer mode" 6>&1
+fi
+else
+  MAINT="#"
+fi
+
+
+
+# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then
+  enableval="$enable_sim_bswap"
+  case "${enableval}" in
+  yes)	sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+  no)	sim_bswap="-DWITH_BSWAP=0";;
+  *)	{ echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+  echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+  sim_bswap=""
+fi
+
+
+
+# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then
+  enableval="$enable_sim_cflags"
+  case "${enableval}" in
+  yes)	 sim_cflags="-O2 -fomit-frame-pointer";;
+  trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";;
+  no)	 sim_cflags="";;
+  *)	 sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+  echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+  sim_cflags=""
+fi
+
+
+
+# Check whether --enable-sim-debug or --disable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then
+  enableval="$enable_sim_debug"
+  case "${enableval}" in
+  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+  echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+  sim_debug=""
+fi
+
+
+
+# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then
+  enableval="$enable_sim_stdio"
+  case "${enableval}" in
+  yes)	sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+  no)	sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+  *)	{ echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+  echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+  sim_stdio=""
+fi
+
+
+
+# Check whether --enable-sim-trace or --disable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then
+  enableval="$enable_sim_trace"
+  case "${enableval}" in
+  yes)	sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+  no)	sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+  [-0-9]*)
+	sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+  [a-z]*)
+	sim_trace=""
+	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+	  if test x"$sim_trace" = x; then
+	    sim_trace="-DWITH_TRACE='(TRACE_$x"
+	  else
+	    sim_trace="${sim_trace}|TRACE_$x"
+	  fi
+	done
+	sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+  echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+  sim_trace=""
+fi
+
+
+
+# Check whether --enable-sim-profile or --disable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then
+  enableval="$enable_sim_profile"
+  case "${enableval}" in
+  yes)	sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+  no)	sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+  [-0-9]*)
+	sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+  [a-z]*)
+	sim_profile=""
+	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+	  if test x"$sim_profile" = x; then
+	    sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+	  else
+	    sim_profile="${sim_profile}|PROFILE_$x"
+	  fi
+	done
+	sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+  echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+  sim_profile=""
+fi
+
+
+
+echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6
+echo "configure:3354: checking return type of signal handlers" >&5
+if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3359 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <signal.h>
+#ifdef signal
+#undef signal
+#endif
+#ifdef __cplusplus
+extern "C" void (*signal (int, void (*)(int)))(int);
+#else
+void (*signal ()) ();
+#endif
+
+int main() {
+int i;
+; return 0; }
+EOF
+if { (eval echo configure:3376: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_type_signal=void
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_type_signal=int
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_type_signal" 1>&6
+cat >> confdefs.h <<EOF
+#define RETSIGTYPE $ac_cv_type_signal
+EOF
+
+
+
+echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
+echo "configure:3396: checking for executable suffix" >&5
+if eval "test \"`echo '$''{'am_cv_exeext'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$CYGWIN32" = yes; then
+am_cv_exeext=.exe
+else
+cat > am_c_test.c << 'EOF'
+int main() {
+/* Nothing needed here */
+}
+EOF
+${CC-cc} -o am_c_test $CFLAGS $CPPFLAGS $LDFLAGS am_c_test.c $LIBS 1>&5
+am_cv_exeext=`ls am_c_test.* | grep -v am_c_test.c | sed -e s/am_c_test//`
+rm -f am_c_test*
+fi
+
+test x"${am_cv_exeext}" = x && am_cv_exeext=no
+fi
+EXEEXT=""
+test x"${am_cv_exeext}" != xno && EXEEXT=${am_cv_exeext}
+echo "$ac_t""${am_cv_exeext}" 1>&6
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+  sim_link_files=tconfig.in
+else
+  sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+
+
+wire_endian="LITTLE_ENDIAN"
+default_endian=""
+# Check whether --enable-sim-endian or --disable-sim-endian was given.
+if test "${enable_sim_endian+set}" = set; then
+  enableval="$enable_sim_endian"
+  case "${enableval}" in
+  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
+  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
+  yes)	 if test x"$wire_endian" != x; then
+	   sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+	 else
+           if test x"$default_endian" != x; then
+	     sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
+	   else
+	     echo "No hard-wired endian for target $target" 1>&6
+	     sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
+	   fi
+	 fi;;
+  no)	 if test x"$default_endian" != x; then
+	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+	 else
+	   if test x"$wire_endian" != x; then
+	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
+	   else
+	     echo "No default endian for target $target" 1>&6
+	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
+	   fi
+	 fi;;
+  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
+  echo "Setting endian flags = $sim_endian" 6>&1
+fi
+else
+  if test x"$default_endian" != x; then
+  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+else
+  if test x"$wire_endian" != x; then
+    sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+  else
+    sim_endian=
+  fi
+fi
+fi
+
+wire_alignment="NONSTRICT_ALIGNMENT"
+default_alignment=""
+
+# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
+if test "${enable_sim_alignment+set}" = set; then
+  enableval="$enable_sim_alignment"
+  case "${enableval}" in
+  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
+  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
+  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
+  yes) if test x"$wire_alignment" != x; then
+	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+       else
+         if test x"$default_alignment" != x; then
+           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
+         else
+	   echo "No hard-wired alignment for target $target" 1>&6
+	   sim_alignment="-DWITH_ALIGNMENT=0"
+         fi
+       fi;;
+  no)  if test x"$default_alignment" != x; then
+	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+       else
+         if test x"$wire_alignment" != x; then
+	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
+         else
+           echo "No default alignment for target $target" 1>&6
+           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
+         fi
+       fi;;
+  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
+  echo "Setting alignment flags = $sim_alignment" 6>&1
+fi
+else
+  if test x"$default_alignment" != x; then
+  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+else
+  if test x"$wire_alignment" != x; then
+    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+  else
+    sim_alignment=
+  fi
+fi
+fi
+
+
+# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
+if test "${enable_sim_hostendian+set}" = set; then
+  enableval="$enable_sim_hostendian"
+  case "${enableval}" in
+  no)	 sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
+  b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
+  l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
+  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
+  echo "Setting hostendian flags = $sim_hostendian" 6>&1
+fi
+else
+  
+if test "x$cross_compiling" = "xno"; then
+  echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
+echo "configure:3550: checking whether byte ordering is bigendian" >&5
+if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_cv_c_bigendian=unknown
+# See if sys/param.h defines the BYTE_ORDER macro.
+cat > conftest.$ac_ext <<EOF
+#line 3557 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
+ bogus endian macros
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3568: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  # It does; now see whether it defined to BIG_ENDIAN or not.
+cat > conftest.$ac_ext <<EOF
+#line 3572 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3583: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_bigendian=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_c_bigendian=no
+fi
+rm -f conftest*
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+if test $ac_cv_c_bigendian = unknown; then
+if test "$cross_compiling" = yes; then
+    { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3603 "configure"
+#include "confdefs.h"
+main () {
+  /* Are we little or big endian?  From Harbison&Steele.  */
+  union
+  {
+    long l;
+    char c[sizeof (long)];
+  } u;
+  u.l = 1;
+  exit (u.c[sizeof (long) - 1] == 1);
+}
+EOF
+if { (eval echo configure:3616: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_c_bigendian=no
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_c_bigendian=yes
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_c_bigendian" 1>&6
+if test $ac_cv_c_bigendian = yes; then
+  cat >> confdefs.h <<\EOF
+#define WORDS_BIGENDIAN 1
+EOF
+
+fi
+
+  if test $ac_cv_c_bigendian = yes; then
+    sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
+  else
+    sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
+  fi
+else
+  sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
+fi
+fi
+
+
+default_sim_scache="1024"
+# Check whether --enable-sim-scache or --disable-sim-scache was given.
+if test "${enable_sim_scache+set}" = set; then
+  enableval="$enable_sim_scache"
+  case "${enableval}" in
+  yes)	sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
+  no)	sim_scache="-DWITH_SCACHE=0" ;;
+  [0-9]*) sim_cache=${enableval};;
+  *)	{ echo "configure: error: "Bad value $enableval passed to --enable-sim-scache"" 1>&2; exit 1; };
+	sim_scache="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
+  echo "Setting scache size = $sim_scache" 6>&1
+fi
+else
+  sim_scache="-DWITH_SCACHE=${default_sim_scache}"
+fi
+
+
+
+default_sim_default_model="i960KA"
+# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
+if test "${enable_sim_default_model+set}" = set; then
+  enableval="$enable_sim_default_model"
+  case "${enableval}" in
+  yes|no) { echo "configure: error: "Missing argument to --enable-sim-default-model"" 1>&2; exit 1; };;
+  *)	sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
+  echo "Setting default model = $sim_default_model" 6>&1
+fi
+else
+  sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
+fi
+
+
+
+# Check whether --enable-sim-environment or --disable-sim-environment was given.
+if test "${enable_sim_environment+set}" = set; then
+  enableval="$enable_sim_environment"
+  case "${enableval}" in
+  all | ALL)             sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
+  user | USER)           sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
+  virtual | VIRTUAL)     sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
+  operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
+  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-environment"" 1>&2; exit 1; };
+       sim_environment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
+  echo "Setting sim environment = $sim_environment" 6>&1
+fi
+else
+  sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
+fi
+
+
+cgen_maint=no
+cgen=../../cgen/cgen
+cgendir='$(srcdir)/../../cgen'
+# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
+if test "${enable_cgen_maint+set}" = set; then
+  enableval="$enable_cgen_maint"
+  case "${enableval}" in
+  yes)	cgen_maint=yes ;;
+  no)	cgen_maint=no ;;
+  *)
+	# argument is cgen install directory (not implemented yet).
+	# Having a `share' directory might be more appropriate for the .scm,
+	# .cpu, etc. files.
+	cgendir=${cgen_maint}/lib/cgen
+	cgen=${cgendir}/bin/cgen
+	;;
+esac
+fi
+if test x${cgen_maint} != xno ; then
+  CGEN_MAINT=''
+else
+  CGEN_MAINT='#'
+fi
+
+
+
+
+
+
+
+trap '' 1 2 15
+cat > confcache <<\EOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs.  It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already.  You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+EOF
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(set) 2>&1 |
+  case `(ac_space=' '; set | grep ac_space) 2>&1` in
+  *ac_space=\ *)
+    # `set' does not quote correctly, so add quotes (double-quote substitution
+    # turns \\\\ into \\, and sed turns \\ into \).
+    sed -n \
+      -e "s/'/'\\\\''/g" \
+      -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
+    ;;
+  *)
+    # `set' quotes correctly as required by POSIX, so do not add quotes.
+    sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
+    ;;
+  esac >> confcache
+if cmp -s $cache_file confcache; then
+  :
+else
+  if test -w $cache_file; then
+    echo "updating cache $cache_file"
+    cat confcache > $cache_file
+  else
+    echo "not updating unwritable cache $cache_file"
+  fi
+fi
+rm -f confcache
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# Any assignment to VPATH causes Sun make to only execute
+# the first set of double-colon rules, so remove it if not needed.
+# If there is a colon in the path, we need to keep it.
+if test "x$srcdir" = x.; then
+  ac_vpsub='/^[ 	]*VPATH[ 	]*=[^:]*$/d'
+fi
+
+trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
+
+DEFS=-DHAVE_CONFIG_H
+
+# Without the "./", some shells look in PATH for config.status.
+: ${CONFIG_STATUS=./config.status}
+
+echo creating $CONFIG_STATUS
+rm -f $CONFIG_STATUS
+cat > $CONFIG_STATUS <<EOF
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+#
+# $0 $ac_configure_args
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
+for ac_option
+do
+  case "\$ac_option" in
+  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+    echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
+    exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
+  -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+    echo "$CONFIG_STATUS generated by autoconf version 2.13"
+    exit 0 ;;
+  -help | --help | --hel | --he | --h)
+    echo "\$ac_cs_usage"; exit 0 ;;
+  *) echo "\$ac_cs_usage"; exit 1 ;;
+  esac
+done
+
+ac_given_srcdir=$srcdir
+ac_given_INSTALL="$INSTALL"
+
+trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
+$ac_vpsub
+$extrasub
+s%@sim_environment@%$sim_environment%g
+s%@sim_alignment@%$sim_alignment%g
+s%@sim_assert@%$sim_assert%g
+s%@sim_bitsize@%$sim_bitsize%g
+s%@sim_endian@%$sim_endian%g
+s%@sim_hostendian@%$sim_hostendian%g
+s%@sim_float@%$sim_float%g
+s%@sim_scache@%$sim_scache%g
+s%@sim_default_model@%$sim_default_model%g
+s%@sim_hw_cflags@%$sim_hw_cflags%g
+s%@sim_hw_objs@%$sim_hw_objs%g
+s%@sim_hw@%$sim_hw%g
+s%@sim_inline@%$sim_inline%g
+s%@sim_packages@%$sim_packages%g
+s%@sim_regparm@%$sim_regparm%g
+s%@sim_reserved_bits@%$sim_reserved_bits%g
+s%@sim_smp@%$sim_smp%g
+s%@sim_stdcall@%$sim_stdcall%g
+s%@sim_xor_endian@%$sim_xor_endian%g
+s%@build_warnings@%$build_warnings%g
+s%@SHELL@%$SHELL%g
+s%@CFLAGS@%$CFLAGS%g
+s%@CPPFLAGS@%$CPPFLAGS%g
+s%@CXXFLAGS@%$CXXFLAGS%g
+s%@FFLAGS@%$FFLAGS%g
+s%@DEFS@%$DEFS%g
+s%@LDFLAGS@%$LDFLAGS%g
+s%@LIBS@%$LIBS%g
+s%@exec_prefix@%$exec_prefix%g
+s%@prefix@%$prefix%g
+s%@program_transform_name@%$program_transform_name%g
+s%@bindir@%$bindir%g
+s%@sbindir@%$sbindir%g
+s%@libexecdir@%$libexecdir%g
+s%@datadir@%$datadir%g
+s%@sysconfdir@%$sysconfdir%g
+s%@sharedstatedir@%$sharedstatedir%g
+s%@localstatedir@%$localstatedir%g
+s%@libdir@%$libdir%g
+s%@includedir@%$includedir%g
+s%@oldincludedir@%$oldincludedir%g
+s%@infodir@%$infodir%g
+s%@mandir@%$mandir%g
+s%@host@%$host%g
+s%@host_alias@%$host_alias%g
+s%@host_cpu@%$host_cpu%g
+s%@host_vendor@%$host_vendor%g
+s%@host_os@%$host_os%g
+s%@target@%$target%g
+s%@target_alias@%$target_alias%g
+s%@target_cpu@%$target_cpu%g
+s%@target_vendor@%$target_vendor%g
+s%@target_os@%$target_os%g
+s%@build@%$build%g
+s%@build_alias@%$build_alias%g
+s%@build_cpu@%$build_cpu%g
+s%@build_vendor@%$build_vendor%g
+s%@build_os@%$build_os%g
+s%@CC@%$CC%g
+s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
+s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g
+s%@INSTALL_DATA@%$INSTALL_DATA%g
+s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g
+s%@HDEFINES@%$HDEFINES%g
+s%@AR@%$AR%g
+s%@RANLIB@%$RANLIB%g
+s%@SET_MAKE@%$SET_MAKE%g
+s%@CPP@%$CPP%g
+s%@ALLOCA@%$ALLOCA%g
+s%@USE_NLS@%$USE_NLS%g
+s%@MSGFMT@%$MSGFMT%g
+s%@GMSGFMT@%$GMSGFMT%g
+s%@XGETTEXT@%$XGETTEXT%g
+s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g
+s%@CATALOGS@%$CATALOGS%g
+s%@CATOBJEXT@%$CATOBJEXT%g
+s%@DATADIRNAME@%$DATADIRNAME%g
+s%@GMOFILES@%$GMOFILES%g
+s%@INSTOBJEXT@%$INSTOBJEXT%g
+s%@INTLDEPS@%$INTLDEPS%g
+s%@INTLLIBS@%$INTLLIBS%g
+s%@INTLOBJS@%$INTLOBJS%g
+s%@POFILES@%$POFILES%g
+s%@POSUB@%$POSUB%g
+s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g
+s%@GT_NO@%$GT_NO%g
+s%@GT_YES@%$GT_YES%g
+s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g
+s%@l@%$l%g
+s%@MAINT@%$MAINT%g
+s%@sim_bswap@%$sim_bswap%g
+s%@sim_cflags@%$sim_cflags%g
+s%@sim_debug@%$sim_debug%g
+s%@sim_stdio@%$sim_stdio%g
+s%@sim_trace@%$sim_trace%g
+s%@sim_profile@%$sim_profile%g
+s%@EXEEXT@%$EXEEXT%g
+s%@CGEN_MAINT@%$CGEN_MAINT%g
+s%@cgendir@%$cgendir%g
+s%@cgen@%$cgen%g
+
+CEOF
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+  if test $ac_beg -gt 1; then
+    sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+  else
+    sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+  fi
+  if test ! -s conftest.s$ac_file; then
+    ac_more_lines=false
+    rm -f conftest.s$ac_file
+  else
+    if test -z "$ac_sed_cmds"; then
+      ac_sed_cmds="sed -f conftest.s$ac_file"
+    else
+      ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+    fi
+    ac_file=`expr $ac_file + 1`
+    ac_beg=$ac_end
+    ac_end=`expr $ac_end + $ac_max_sed_cmds`
+  fi
+done
+if test -z "$ac_sed_cmds"; then
+  ac_sed_cmds=cat
+fi
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+
+CONFIG_FILES=\${CONFIG_FILES-"Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in"}
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+  case "$ac_file" in
+  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+  *) ac_file_in="${ac_file}.in" ;;
+  esac
+
+  # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+  # Remove last slash and all that follows it.  Not all systems have dirname.
+  ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+  if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+    # The file is in a subdirectory.
+    test ! -d "$ac_dir" && mkdir "$ac_dir"
+    ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+    # A "../" for each directory in $ac_dir_suffix.
+    ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+  else
+    ac_dir_suffix= ac_dots=
+  fi
+
+  case "$ac_given_srcdir" in
+  .)  srcdir=.
+      if test -z "$ac_dots"; then top_srcdir=.
+      else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+  /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+  *) # Relative path.
+    srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+    top_srcdir="$ac_dots$ac_given_srcdir" ;;
+  esac
+
+  case "$ac_given_INSTALL" in
+  [/$]*) INSTALL="$ac_given_INSTALL" ;;
+  *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
+  esac
+
+  echo creating "$ac_file"
+  rm -f "$ac_file"
+  configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+  case "$ac_file" in
+  *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+  *) ac_comsub= ;;
+  esac
+
+  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+  sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+s%@INSTALL@%$INSTALL%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s%^\([ 	]*\)#\([ 	]*define[ 	][ 	]*\)'
+ac_dB='\([ 	][ 	]*\)[^ 	]*%\1#\2'
+ac_dC='\3'
+ac_dD='%g'
+# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
+ac_uA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
+ac_uB='\([ 	]\)%\1#\2define\3'
+ac_uC=' '
+ac_uD='\4%g'
+# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_eA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
+ac_eB='$%\1#\2define\3'
+ac_eC=' '
+ac_eD='%g'
+
+if test "${CONFIG_HEADERS+set}" != set; then
+EOF
+cat >> $CONFIG_STATUS <<EOF
+  CONFIG_HEADERS="config.h:config.in"
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+fi
+for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
+  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+  case "$ac_file" in
+  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+  *) ac_file_in="${ac_file}.in" ;;
+  esac
+
+  echo creating $ac_file
+
+  rm -f conftest.frag conftest.in conftest.out
+  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+  cat $ac_file_inputs > conftest.in
+
+EOF
+
+# Transform confdefs.h into a sed script conftest.vals that substitutes
+# the proper values into config.h.in to produce config.h.  And first:
+# Protect against being on the right side of a sed subst in config.status.
+# Protect against being in an unquoted here document in config.status.
+rm -f conftest.vals
+cat > conftest.hdr <<\EOF
+s/[\\&%]/\\&/g
+s%[\\$`]%\\&%g
+s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp
+s%ac_d%ac_u%gp
+s%ac_u%ac_e%gp
+EOF
+sed -n -f conftest.hdr confdefs.h > conftest.vals
+rm -f conftest.hdr
+
+# This sed command replaces #undef with comments.  This is necessary, for
+# example, in the case of _POSIX_SOURCE, which is predefined and required
+# on some systems where configure will not decide to define it.
+cat >> conftest.vals <<\EOF
+s%^[ 	]*#[ 	]*undef[ 	][ 	]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
+EOF
+
+# Break up conftest.vals because some shells have a limit on
+# the size of here documents, and old seds have small limits too.
+
+rm -f conftest.tail
+while :
+do
+  ac_lines=`grep -c . conftest.vals`
+  # grep -c gives empty output for an empty file on some AIX systems.
+  if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi
+  # Write a limited-size here document to conftest.frag.
+  echo '  cat > conftest.frag <<CEOF' >> $CONFIG_STATUS
+  sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS
+  echo 'CEOF
+  sed -f conftest.frag conftest.in > conftest.out
+  rm -f conftest.in
+  mv conftest.out conftest.in
+' >> $CONFIG_STATUS
+  sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail
+  rm -f conftest.vals
+  mv conftest.tail conftest.vals
+done
+rm -f conftest.vals
+
+cat >> $CONFIG_STATUS <<\EOF
+  rm -f conftest.frag conftest.h
+  echo "/* $ac_file.  Generated automatically by configure.  */" > conftest.h
+  cat conftest.in >> conftest.h
+  rm -f conftest.in
+  if cmp -s $ac_file conftest.h 2>/dev/null; then
+    echo "$ac_file is unchanged"
+    rm -f conftest.h
+  else
+    # Remove last slash and all that follows it.  Not all systems have dirname.
+      ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+      if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+      # The file is in a subdirectory.
+      test ! -d "$ac_dir" && mkdir "$ac_dir"
+    fi
+    rm -f $ac_file
+    mv conftest.h $ac_file
+  fi
+fi; done
+
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+srcdir=$ac_given_srcdir
+while test -n "$ac_sources"; do
+  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+  set $ac_sources; ac_source=$1; shift; ac_sources=$*
+
+  echo "linking $srcdir/$ac_source to $ac_dest"
+
+  if test ! -r $srcdir/$ac_source; then
+    { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; }
+  fi
+  rm -f $ac_dest
+
+  # Make relative symlinks.
+  # Remove last slash and all that follows it.  Not all systems have dirname.
+  ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'`
+  if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then
+    # The dest file is in a subdirectory.
+    test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir"
+    ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`"
+    # A "../" for each directory in $ac_dest_dir_suffix.
+    ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'`
+  else
+    ac_dest_dir_suffix= ac_dots=
+  fi
+
+  case "$srcdir" in
+  [/$]*) ac_rel_source="$srcdir/$ac_source" ;;
+  *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;;
+  esac
+
+  # Make a symlink if possible; otherwise try a hard link.
+  if ln -s $ac_rel_source $ac_dest 2>/dev/null ||
+    ln $srcdir/$ac_source $ac_dest; then :
+  else
+    { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; }
+  fi
+done
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+case "x$CONFIG_FILES" in
+ xMakefile*)
+   echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+   rm -f Makesim1.tmp Makesim2.tmp Makefile
+   sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
+   sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
+   sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
+	<Makefile.sim >Makefile
+   rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+   ;;
+ esac
+ case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac
+
+exit 0
+EOF
+chmod +x $CONFIG_STATUS
+rm -fr confdefs* $ac_clean_files
+test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
+
+
diff --git a/sim/i960/configure.in b/sim/i960/configure.in
new file mode 100644
index 00000000000..7c5587512d6
--- /dev/null
+++ b/sim/i960/configure.in
@@ -0,0 +1,16 @@
+dnl Process this file with autoconf to produce a configure script.
+sinclude(../common/aclocal.m4)
+AC_PREREQ(2.5)dnl
+AC_INIT(Makefile.in)
+
+SIM_AC_COMMON
+
+SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(1024)
+SIM_AC_OPTION_DEFAULT_MODEL(i960KA)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_CGEN_MAINT
+
+SIM_AC_OUTPUT
diff --git a/sim/i960/cpu.c b/sim/i960/cpu.c
new file mode 100644
index 00000000000..aec6a06ee73
--- /dev/null
+++ b/sim/i960/cpu.c
@@ -0,0 +1,84 @@
+/* Misc. support for CPU family i960base.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU i960base
+#define WANT_CPU_I960BASE
+
+#include "sim-main.h"
+
+/* Get the value of h-pc.  */
+
+USI
+i960base_h_pc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pc);
+}
+
+/* Set a value for h-pc.  */
+
+void
+i960base_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_pc) = newval;
+}
+
+/* Get the value of h-gr.  */
+
+SI
+i960base_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_gr[regno]);
+}
+
+/* Set a value for h-gr.  */
+
+void
+i960base_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_gr[regno]) = newval;
+}
+
+/* Get the value of h-cc.  */
+
+SI
+i960base_h_cc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_cc);
+}
+
+/* Set a value for h-cc.  */
+
+void
+i960base_h_cc_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_cc) = newval;
+}
+
+/* Record trace results for INSN.  */
+
+void
+i960base_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/i960/cpu.h b/sim/i960/cpu.h
new file mode 100644
index 00000000000..42532b0888d
--- /dev/null
+++ b/sim/i960/cpu.h
@@ -0,0 +1,1860 @@
+/* CPU family header for i960base.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_I960BASE_H
+#define CPU_I960BASE_H
+
+/* Maximum number of instructions that are fetched at a time.
+   This is for LIW type instructions sets (e.g. m32r).  */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel.  */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information.  */
+typedef struct {
+  /* Hardware elements.  */
+  struct {
+  /* program counter */
+  USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+  /* general registers */
+  SI h_gr[32];
+#define GET_H_GR(a1) CPU (h_gr)[a1]
+#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
+  /* condition code */
+  SI h_cc;
+#define GET_H_CC() CPU (h_cc)
+#define SET_H_CC(x) (CPU (h_cc) = (x))
+  } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} I960BASE_CPU_DATA;
+
+/* Cover fns for register access.  */
+USI i960base_h_pc_get (SIM_CPU *);
+void i960base_h_pc_set (SIM_CPU *, USI);
+SI i960base_h_gr_get (SIM_CPU *, UINT);
+void i960base_h_gr_set (SIM_CPU *, UINT, SI);
+SI i960base_h_cc_get (SIM_CPU *);
+void i960base_h_cc_set (SIM_CPU *, SI);
+
+/* These must be hand-written.  */
+extern CPUREG_FETCH_FN i960base_fetch_register;
+extern CPUREG_STORE_FN i960base_store_register;
+
+typedef struct {
+  int empty;
+} MODEL_I960KA_DATA;
+
+typedef struct {
+  int empty;
+} MODEL_I960CA_DATA;
+
+union sem_fields {
+    struct { /* empty sformat for unspecified field list */
+      int empty;
+    } fmt_empty;
+    struct { /* e.g. mulo $src1, $src2, $dst */
+      SI * i_src1;
+      SI * i_src2;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char in_src2;
+      unsigned char out_dst;
+    } fmt_mulo;
+    struct { /* e.g. mulo $lit1, $src2, $dst */
+      UINT f_src1;
+      SI * i_src2;
+      SI * i_dst;
+      unsigned char in_src2;
+      unsigned char out_dst;
+    } fmt_mulo1;
+    struct { /* e.g. mulo $src1, $lit2, $dst */
+      UINT f_src2;
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char out_dst;
+    } fmt_mulo2;
+    struct { /* e.g. mulo $lit1, $lit2, $dst */
+      UINT f_src1;
+      UINT f_src2;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_mulo3;
+    struct { /* e.g. notbit $src1, $src2, $dst */
+      SI * i_src1;
+      SI * i_src2;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char in_src2;
+      unsigned char out_dst;
+    } fmt_notbit;
+    struct { /* e.g. notbit $lit1, $src2, $dst */
+      UINT f_src1;
+      SI * i_src2;
+      SI * i_dst;
+      unsigned char in_src2;
+      unsigned char out_dst;
+    } fmt_notbit1;
+    struct { /* e.g. notbit $src1, $lit2, $dst */
+      UINT f_src2;
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char out_dst;
+    } fmt_notbit2;
+    struct { /* e.g. notbit $lit1, $lit2, $dst */
+      UINT f_src1;
+      UINT f_src2;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_notbit3;
+    struct { /* e.g. not $src1, $src2, $dst */
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char out_dst;
+    } fmt_not;
+    struct { /* e.g. not $lit1, $src2, $dst */
+      UINT f_src1;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_not1;
+    struct { /* e.g. not $src1, $lit2, $dst */
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char out_dst;
+    } fmt_not2;
+    struct { /* e.g. not $lit1, $lit2, $dst */
+      UINT f_src1;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_not3;
+    struct { /* e.g. emul $src1, $src2, $dst */
+      UINT f_srcdst;
+      SI * i_src1;
+      SI * i_src2;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char in_src2;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_emul;
+    struct { /* e.g. emul $lit1, $src2, $dst */
+      UINT f_srcdst;
+      UINT f_src1;
+      SI * i_src2;
+      SI * i_dst;
+      unsigned char in_src2;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_emul1;
+    struct { /* e.g. emul $src1, $lit2, $dst */
+      UINT f_srcdst;
+      UINT f_src2;
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_src1;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_emul2;
+    struct { /* e.g. emul $lit1, $lit2, $dst */
+      UINT f_srcdst;
+      UINT f_src1;
+      UINT f_src2;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_emul3;
+    struct { /* e.g. movl $src1, $dst */
+      UINT f_src1;
+      UINT f_srcdst;
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
+      unsigned char in_src1;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_movl;
+    struct { /* e.g. movl $lit1, $dst */
+      UINT f_srcdst;
+      UINT f_src1;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_movl1;
+    struct { /* e.g. movt $src1, $dst */
+      UINT f_src1;
+      UINT f_srcdst;
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2;
+      unsigned char in_src1;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_movt;
+    struct { /* e.g. movt $lit1, $dst */
+      UINT f_srcdst;
+      UINT f_src1;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_movt1;
+    struct { /* e.g. movq $src1, $dst */
+      UINT f_src1;
+      UINT f_srcdst;
+      SI * i_src1;
+      SI * i_dst;
+      unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_src1_const__WI_3;
+      unsigned char in_src1;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_movq;
+    struct { /* e.g. movq $lit1, $dst */
+      UINT f_srcdst;
+      UINT f_src1;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_movq1;
+    struct { /* e.g. modpc $src1, $src2, $dst */
+      SI * i_src2;
+      SI * i_dst;
+      unsigned char in_src2;
+      unsigned char out_dst;
+    } fmt_modpc;
+    struct { /* e.g. lda $offset, $dst */
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_lda_offset;
+    struct { /* e.g. lda $offset($abase), $dst */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_lda_indirect_offset;
+    struct { /* e.g. lda ($abase), $dst */
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_lda_indirect;
+    struct { /* e.g. lda ($abase)[$index*S$scale], $dst */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_lda_indirect_index;
+    struct { /* e.g. lda $optdisp, $dst */
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_lda_disp;
+    struct { /* e.g. lda $optdisp($abase), $dst */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_lda_indirect_disp;
+    struct { /* e.g. lda $optdisp[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_lda_index_disp;
+    struct { /* e.g. lda $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_lda_indirect_index_disp;
+    struct { /* e.g. ld $offset, $dst */
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ld_offset;
+    struct { /* e.g. ld $offset($abase), $dst */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ld_indirect_offset;
+    struct { /* e.g. ld ($abase), $dst */
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ld_indirect;
+    struct { /* e.g. ld ($abase)[$index*S$scale], $dst */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ld_indirect_index;
+    struct { /* e.g. ld $optdisp, $dst */
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ld_disp;
+    struct { /* e.g. ld $optdisp($abase), $dst */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ld_indirect_disp;
+    struct { /* e.g. ld $optdisp[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ld_index_disp;
+    struct { /* e.g. ld $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ld_indirect_index_disp;
+    struct { /* e.g. ldob $offset, $dst */
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldob_offset;
+    struct { /* e.g. ldob $offset($abase), $dst */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldob_indirect_offset;
+    struct { /* e.g. ldob ($abase), $dst */
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldob_indirect;
+    struct { /* e.g. ldob ($abase)[$index*S$scale], $dst */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldob_indirect_index;
+    struct { /* e.g. ldob $optdisp, $dst */
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldob_disp;
+    struct { /* e.g. ldob $optdisp($abase), $dst */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldob_indirect_disp;
+    struct { /* e.g. ldob $optdisp[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldob_index_disp;
+    struct { /* e.g. ldob $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldob_indirect_index_disp;
+    struct { /* e.g. ldos $offset, $dst */
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldos_offset;
+    struct { /* e.g. ldos $offset($abase), $dst */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldos_indirect_offset;
+    struct { /* e.g. ldos ($abase), $dst */
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldos_indirect;
+    struct { /* e.g. ldos ($abase)[$index*S$scale], $dst */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldos_indirect_index;
+    struct { /* e.g. ldos $optdisp, $dst */
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldos_disp;
+    struct { /* e.g. ldos $optdisp($abase), $dst */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldos_indirect_disp;
+    struct { /* e.g. ldos $optdisp[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldos_index_disp;
+    struct { /* e.g. ldos $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldos_indirect_index_disp;
+    struct { /* e.g. ldib $offset, $dst */
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldib_offset;
+    struct { /* e.g. ldib $offset($abase), $dst */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldib_indirect_offset;
+    struct { /* e.g. ldib ($abase), $dst */
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldib_indirect;
+    struct { /* e.g. ldib ($abase)[$index*S$scale], $dst */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldib_indirect_index;
+    struct { /* e.g. ldib $optdisp, $dst */
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldib_disp;
+    struct { /* e.g. ldib $optdisp($abase), $dst */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldib_indirect_disp;
+    struct { /* e.g. ldib $optdisp[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldib_index_disp;
+    struct { /* e.g. ldib $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldib_indirect_index_disp;
+    struct { /* e.g. ldis $offset, $dst */
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldis_offset;
+    struct { /* e.g. ldis $offset($abase), $dst */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldis_indirect_offset;
+    struct { /* e.g. ldis ($abase), $dst */
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldis_indirect;
+    struct { /* e.g. ldis ($abase)[$index*S$scale], $dst */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldis_indirect_index;
+    struct { /* e.g. ldis $optdisp, $dst */
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+    } fmt_ldis_disp;
+    struct { /* e.g. ldis $optdisp($abase), $dst */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+    } fmt_ldis_indirect_disp;
+    struct { /* e.g. ldis $optdisp[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldis_index_disp;
+    struct { /* e.g. ldis $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+    } fmt_ldis_indirect_index_disp;
+    struct { /* e.g. ldl $offset, $dst */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_offset;
+    struct { /* e.g. ldl $offset($abase), $dst */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_indirect_offset;
+    struct { /* e.g. ldl ($abase), $dst */
+      UINT f_srcdst;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_indirect;
+    struct { /* e.g. ldl ($abase)[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_indirect_index;
+    struct { /* e.g. ldl $optdisp, $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_disp;
+    struct { /* e.g. ldl $optdisp($abase), $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_indirect_disp;
+    struct { /* e.g. ldl $optdisp[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_index_disp;
+    struct { /* e.g. ldl $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+    } fmt_ldl_indirect_index_disp;
+    struct { /* e.g. ldt $offset, $dst */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_offset;
+    struct { /* e.g. ldt $offset($abase), $dst */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_indirect_offset;
+    struct { /* e.g. ldt ($abase), $dst */
+      UINT f_srcdst;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_indirect;
+    struct { /* e.g. ldt ($abase)[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_indirect_index;
+    struct { /* e.g. ldt $optdisp, $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_disp;
+    struct { /* e.g. ldt $optdisp($abase), $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_indirect_disp;
+    struct { /* e.g. ldt $optdisp[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_index_disp;
+    struct { /* e.g. ldt $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+    } fmt_ldt_indirect_index_disp;
+    struct { /* e.g. ldq $offset, $dst */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_offset;
+    struct { /* e.g. ldq $offset($abase), $dst */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_indirect_offset;
+    struct { /* e.g. ldq ($abase), $dst */
+      UINT f_srcdst;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_indirect;
+    struct { /* e.g. ldq ($abase)[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_indirect_index;
+    struct { /* e.g. ldq $optdisp, $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_dst;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_disp;
+    struct { /* e.g. ldq $optdisp($abase), $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_indirect_disp;
+    struct { /* e.g. ldq $optdisp[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_index_disp;
+    struct { /* e.g. ldq $optdisp($abase)[$index*S$scale], $dst */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_dst;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char out_dst;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+      unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+    } fmt_ldq_indirect_index_disp;
+    struct { /* e.g. st $st_src, $offset */
+      UINT f_offset;
+      SI * i_st_src;
+      unsigned char in_st_src;
+    } fmt_st_offset;
+    struct { /* e.g. st $st_src, $offset($abase) */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_st_indirect_offset;
+    struct { /* e.g. st $st_src, ($abase) */
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_st_indirect;
+    struct { /* e.g. st $st_src, ($abase)[$index*S$scale] */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_st_indirect_index;
+    struct { /* e.g. st $st_src, $optdisp */
+      UINT f_optdisp;
+      SI * i_st_src;
+      unsigned char in_st_src;
+    } fmt_st_disp;
+    struct { /* e.g. st $st_src, $optdisp($abase) */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_st_indirect_disp;
+    struct { /* e.g. st $st_src, $optdisp[$index*S$scale */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_st_index_disp;
+    struct { /* e.g. st $st_src, $optdisp($abase)[$index*S$scale] */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_st_indirect_index_disp;
+    struct { /* e.g. stob $st_src, $offset */
+      UINT f_offset;
+      SI * i_st_src;
+      unsigned char in_st_src;
+    } fmt_stob_offset;
+    struct { /* e.g. stob $st_src, $offset($abase) */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_stob_indirect_offset;
+    struct { /* e.g. stob $st_src, ($abase) */
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_stob_indirect;
+    struct { /* e.g. stob $st_src, ($abase)[$index*S$scale] */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stob_indirect_index;
+    struct { /* e.g. stob $st_src, $optdisp */
+      UINT f_optdisp;
+      SI * i_st_src;
+      unsigned char in_st_src;
+    } fmt_stob_disp;
+    struct { /* e.g. stob $st_src, $optdisp($abase) */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_stob_indirect_disp;
+    struct { /* e.g. stob $st_src, $optdisp[$index*S$scale */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stob_index_disp;
+    struct { /* e.g. stob $st_src, $optdisp($abase)[$index*S$scale] */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stob_indirect_index_disp;
+    struct { /* e.g. stos $st_src, $offset */
+      UINT f_offset;
+      SI * i_st_src;
+      unsigned char in_st_src;
+    } fmt_stos_offset;
+    struct { /* e.g. stos $st_src, $offset($abase) */
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_stos_indirect_offset;
+    struct { /* e.g. stos $st_src, ($abase) */
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_stos_indirect;
+    struct { /* e.g. stos $st_src, ($abase)[$index*S$scale] */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stos_indirect_index;
+    struct { /* e.g. stos $st_src, $optdisp */
+      UINT f_optdisp;
+      SI * i_st_src;
+      unsigned char in_st_src;
+    } fmt_stos_disp;
+    struct { /* e.g. stos $st_src, $optdisp($abase) */
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_st_src;
+    } fmt_stos_indirect_disp;
+    struct { /* e.g. stos $st_src, $optdisp[$index*S$scale */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stos_index_disp;
+    struct { /* e.g. stos $st_src, $optdisp($abase)[$index*S$scale] */
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stos_indirect_index_disp;
+    struct { /* e.g. stl $st_src, $offset */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_st_src;
+    } fmt_stl_offset;
+    struct { /* e.g. stl $st_src, $offset($abase) */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_st_src;
+    } fmt_stl_indirect_offset;
+    struct { /* e.g. stl $st_src, ($abase) */
+      UINT f_srcdst;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_st_src;
+    } fmt_stl_indirect;
+    struct { /* e.g. stl $st_src, ($abase)[$index*S$scale] */
+      UINT f_srcdst;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stl_indirect_index;
+    struct { /* e.g. stl $st_src, $optdisp */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_st_src;
+    } fmt_stl_disp;
+    struct { /* e.g. stl $st_src, $optdisp($abase) */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_st_src;
+    } fmt_stl_indirect_disp;
+    struct { /* e.g. stl $st_src, $optdisp[$index*S$scale */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stl_index_disp;
+    struct { /* e.g. stl $st_src, $optdisp($abase)[$index*S$scale] */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stl_indirect_index_disp;
+    struct { /* e.g. stt $st_src, $offset */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_st_src;
+    } fmt_stt_offset;
+    struct { /* e.g. stt $st_src, $offset($abase) */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_st_src;
+    } fmt_stt_indirect_offset;
+    struct { /* e.g. stt $st_src, ($abase) */
+      UINT f_srcdst;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_st_src;
+    } fmt_stt_indirect;
+    struct { /* e.g. stt $st_src, ($abase)[$index*S$scale] */
+      UINT f_srcdst;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stt_indirect_index;
+    struct { /* e.g. stt $st_src, $optdisp */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_st_src;
+    } fmt_stt_disp;
+    struct { /* e.g. stt $st_src, $optdisp($abase) */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_st_src;
+    } fmt_stt_indirect_disp;
+    struct { /* e.g. stt $st_src, $optdisp[$index*S$scale */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stt_index_disp;
+    struct { /* e.g. stt $st_src, $optdisp($abase)[$index*S$scale] */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stt_indirect_index_disp;
+    struct { /* e.g. stq $st_src, $offset */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_st_src;
+    } fmt_stq_offset;
+    struct { /* e.g. stq $st_src, $offset($abase) */
+      UINT f_srcdst;
+      UINT f_offset;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_st_src;
+    } fmt_stq_indirect_offset;
+    struct { /* e.g. stq $st_src, ($abase) */
+      UINT f_srcdst;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_st_src;
+    } fmt_stq_indirect;
+    struct { /* e.g. stq $st_src, ($abase)[$index*S$scale] */
+      UINT f_srcdst;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stq_indirect_index;
+    struct { /* e.g. stq $st_src, $optdisp */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_st_src;
+    } fmt_stq_disp;
+    struct { /* e.g. stq $st_src, $optdisp($abase) */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      SI * i_abase;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_st_src;
+    } fmt_stq_indirect_disp;
+    struct { /* e.g. stq $st_src, $optdisp[$index*S$scale */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stq_index_disp;
+    struct { /* e.g. stq $st_src, $optdisp($abase)[$index*S$scale] */
+      UINT f_srcdst;
+      UINT f_optdisp;
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      SI * i_st_src;
+      unsigned char in_abase;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+      unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+      unsigned char in_index;
+      unsigned char in_st_src;
+    } fmt_stq_indirect_index_disp;
+    struct { /* e.g. cmpi $src1, $src2 */
+      SI * i_src1;
+      SI * i_src2;
+      unsigned char in_src1;
+      unsigned char in_src2;
+    } fmt_cmpi;
+    struct { /* e.g. cmpi $lit1, $src2 */
+      UINT f_src1;
+      SI * i_src2;
+      unsigned char in_src2;
+    } fmt_cmpi1;
+    struct { /* e.g. cmpi $src1, $lit2 */
+      UINT f_src2;
+      SI * i_src1;
+      unsigned char in_src1;
+    } fmt_cmpi2;
+    struct { /* e.g. cmpi $lit1, $lit2 */
+      UINT f_src1;
+      UINT f_src2;
+    } fmt_cmpi3;
+    struct { /* e.g. cmpo $src1, $src2 */
+      SI * i_src1;
+      SI * i_src2;
+      unsigned char in_src1;
+      unsigned char in_src2;
+    } fmt_cmpo;
+    struct { /* e.g. cmpo $lit1, $src2 */
+      UINT f_src1;
+      SI * i_src2;
+      unsigned char in_src2;
+    } fmt_cmpo1;
+    struct { /* e.g. cmpo $src1, $lit2 */
+      UINT f_src2;
+      SI * i_src1;
+      unsigned char in_src1;
+    } fmt_cmpo2;
+    struct { /* e.g. cmpo $lit1, $lit2 */
+      UINT f_src1;
+      UINT f_src2;
+    } fmt_cmpo3;
+    struct { /* e.g. testno $br_src1 */
+      SI * i_br_src1;
+      unsigned char out_br_src1;
+    } fmt_testno_reg;
+    struct { /* e.g. flushreg */
+      int empty;
+    } fmt_flushreg;
+  /* cti insns, kept separately so addr_cache is in fixed place */
+  struct {
+    union {
+    struct { /* e.g. cmpobe $br_src1, $br_src2, $br_disp */
+      IADDR i_br_disp;
+      SI * i_br_src1;
+      SI * i_br_src2;
+      unsigned char in_br_src1;
+      unsigned char in_br_src2;
+    } fmt_cmpobe_reg;
+    struct { /* e.g. cmpobe $br_lit1, $br_src2, $br_disp */
+      UINT f_br_src1;
+      IADDR i_br_disp;
+      SI * i_br_src2;
+      unsigned char in_br_src2;
+    } fmt_cmpobe_lit;
+    struct { /* e.g. cmpobl $br_src1, $br_src2, $br_disp */
+      IADDR i_br_disp;
+      SI * i_br_src1;
+      SI * i_br_src2;
+      unsigned char in_br_src1;
+      unsigned char in_br_src2;
+    } fmt_cmpobl_reg;
+    struct { /* e.g. cmpobl $br_lit1, $br_src2, $br_disp */
+      UINT f_br_src1;
+      IADDR i_br_disp;
+      SI * i_br_src2;
+      unsigned char in_br_src2;
+    } fmt_cmpobl_lit;
+    struct { /* e.g. bbc $br_src1, $br_src2, $br_disp */
+      IADDR i_br_disp;
+      SI * i_br_src1;
+      SI * i_br_src2;
+      unsigned char in_br_src1;
+      unsigned char in_br_src2;
+    } fmt_bbc_reg;
+    struct { /* e.g. bbc $br_lit1, $br_src2, $br_disp */
+      UINT f_br_src1;
+      IADDR i_br_disp;
+      SI * i_br_src2;
+      unsigned char in_br_src2;
+    } fmt_bbc_lit;
+    struct { /* e.g. bno $ctrl_disp */
+      IADDR i_ctrl_disp;
+    } fmt_bno;
+    struct { /* e.g. b $ctrl_disp */
+      IADDR i_ctrl_disp;
+    } fmt_b;
+    struct { /* e.g. bx $offset($abase) */
+      UINT f_offset;
+      SI * i_abase;
+      unsigned char in_abase;
+    } fmt_bx_indirect_offset;
+    struct { /* e.g. bx ($abase) */
+      SI * i_abase;
+      unsigned char in_abase;
+    } fmt_bx_indirect;
+    struct { /* e.g. bx ($abase)[$index*S$scale] */
+      UINT f_scale;
+      SI * i_abase;
+      SI * i_index;
+      unsigned char in_abase;
+      unsigned char in_index;
+    } fmt_bx_indirect_index;
+    struct { /* e.g. bx $optdisp */
+      UINT f_optdisp;
+    } fmt_bx_disp;
+    struct { /* e.g. bx $optdisp($abase) */
+      UINT f_optdisp;
+      SI * i_abase;
+      unsigned char in_abase;
+    } fmt_bx_indirect_disp;
+    struct { /* e.g. callx $optdisp */
+      UINT f_optdisp;
+      unsigned char in_h_gr_0;
+      unsigned char in_h_gr_1;
+      unsigned char in_h_gr_10;
+      unsigned char in_h_gr_11;
+      unsigned char in_h_gr_12;
+      unsigned char in_h_gr_13;
+      unsigned char in_h_gr_14;
+      unsigned char in_h_gr_15;
+      unsigned char in_h_gr_2;
+      unsigned char in_h_gr_3;
+      unsigned char in_h_gr_31;
+      unsigned char in_h_gr_4;
+      unsigned char in_h_gr_5;
+      unsigned char in_h_gr_6;
+      unsigned char in_h_gr_7;
+      unsigned char in_h_gr_8;
+      unsigned char in_h_gr_9;
+      unsigned char out_h_gr_0;
+      unsigned char out_h_gr_1;
+      unsigned char out_h_gr_10;
+      unsigned char out_h_gr_11;
+      unsigned char out_h_gr_12;
+      unsigned char out_h_gr_13;
+      unsigned char out_h_gr_14;
+      unsigned char out_h_gr_15;
+      unsigned char out_h_gr_2;
+      unsigned char out_h_gr_3;
+      unsigned char out_h_gr_31;
+      unsigned char out_h_gr_4;
+      unsigned char out_h_gr_5;
+      unsigned char out_h_gr_6;
+      unsigned char out_h_gr_7;
+      unsigned char out_h_gr_8;
+      unsigned char out_h_gr_9;
+    } fmt_callx_disp;
+    struct { /* e.g. callx ($abase) */
+      SI * i_abase;
+      unsigned char in_abase;
+      unsigned char in_h_gr_0;
+      unsigned char in_h_gr_1;
+      unsigned char in_h_gr_10;
+      unsigned char in_h_gr_11;
+      unsigned char in_h_gr_12;
+      unsigned char in_h_gr_13;
+      unsigned char in_h_gr_14;
+      unsigned char in_h_gr_15;
+      unsigned char in_h_gr_2;
+      unsigned char in_h_gr_3;
+      unsigned char in_h_gr_31;
+      unsigned char in_h_gr_4;
+      unsigned char in_h_gr_5;
+      unsigned char in_h_gr_6;
+      unsigned char in_h_gr_7;
+      unsigned char in_h_gr_8;
+      unsigned char in_h_gr_9;
+      unsigned char out_h_gr_0;
+      unsigned char out_h_gr_1;
+      unsigned char out_h_gr_10;
+      unsigned char out_h_gr_11;
+      unsigned char out_h_gr_12;
+      unsigned char out_h_gr_13;
+      unsigned char out_h_gr_14;
+      unsigned char out_h_gr_15;
+      unsigned char out_h_gr_2;
+      unsigned char out_h_gr_3;
+      unsigned char out_h_gr_31;
+      unsigned char out_h_gr_4;
+      unsigned char out_h_gr_5;
+      unsigned char out_h_gr_6;
+      unsigned char out_h_gr_7;
+      unsigned char out_h_gr_8;
+      unsigned char out_h_gr_9;
+    } fmt_callx_indirect;
+    struct { /* e.g. callx $offset($abase) */
+      UINT f_offset;
+      SI * i_abase;
+      unsigned char in_abase;
+      unsigned char in_h_gr_0;
+      unsigned char in_h_gr_1;
+      unsigned char in_h_gr_10;
+      unsigned char in_h_gr_11;
+      unsigned char in_h_gr_12;
+      unsigned char in_h_gr_13;
+      unsigned char in_h_gr_14;
+      unsigned char in_h_gr_15;
+      unsigned char in_h_gr_2;
+      unsigned char in_h_gr_3;
+      unsigned char in_h_gr_31;
+      unsigned char in_h_gr_4;
+      unsigned char in_h_gr_5;
+      unsigned char in_h_gr_6;
+      unsigned char in_h_gr_7;
+      unsigned char in_h_gr_8;
+      unsigned char in_h_gr_9;
+      unsigned char out_h_gr_0;
+      unsigned char out_h_gr_1;
+      unsigned char out_h_gr_10;
+      unsigned char out_h_gr_11;
+      unsigned char out_h_gr_12;
+      unsigned char out_h_gr_13;
+      unsigned char out_h_gr_14;
+      unsigned char out_h_gr_15;
+      unsigned char out_h_gr_2;
+      unsigned char out_h_gr_3;
+      unsigned char out_h_gr_31;
+      unsigned char out_h_gr_4;
+      unsigned char out_h_gr_5;
+      unsigned char out_h_gr_6;
+      unsigned char out_h_gr_7;
+      unsigned char out_h_gr_8;
+      unsigned char out_h_gr_9;
+    } fmt_callx_indirect_offset;
+    struct { /* e.g. ret */
+      int empty;
+      unsigned char in_h_gr_0;
+      unsigned char in_h_gr_2;
+      unsigned char in_h_gr_31;
+      unsigned char out_h_gr_0;
+      unsigned char out_h_gr_1;
+      unsigned char out_h_gr_10;
+      unsigned char out_h_gr_11;
+      unsigned char out_h_gr_12;
+      unsigned char out_h_gr_13;
+      unsigned char out_h_gr_14;
+      unsigned char out_h_gr_15;
+      unsigned char out_h_gr_2;
+      unsigned char out_h_gr_3;
+      unsigned char out_h_gr_31;
+      unsigned char out_h_gr_4;
+      unsigned char out_h_gr_5;
+      unsigned char out_h_gr_6;
+      unsigned char out_h_gr_7;
+      unsigned char out_h_gr_8;
+      unsigned char out_h_gr_9;
+    } fmt_ret;
+    struct { /* e.g. calls $src1 */
+      SI * i_src1;
+      unsigned char in_src1;
+    } fmt_calls;
+    struct { /* e.g. fmark */
+      int empty;
+    } fmt_fmark;
+    } fields;
+#if WITH_SCACHE_PBB
+    SEM_PC addr_cache;
+#endif
+  } cti;
+#if WITH_SCACHE_PBB
+  /* Writeback handler.  */
+  struct {
+    /* Pointer to argbuf entry for insn whose results need writing back.  */
+    const struct argbuf *abuf;
+  } write;
+  /* x-before handler */
+  struct {
+    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+    int first_p;
+  } before;
+  /* x-after handler */
+  struct {
+    int empty;
+  } after;
+  /* This entry is used to terminate each pbb.  */
+  struct {
+    /* Number of insns in pbb.  */
+    int insn_count;
+    /* Next pbb to execute.  */
+    SCACHE *next;
+  } chain;
+#endif
+};
+
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* cpu specific data follows */
+  union sem semantic;
+  int written;
+  union sem_fields fields;
+};
+
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+   These define and assign the local vars that contain the insn's fields.  */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+  /* Instruction fields.  */ \
+  unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+  length = 0; \
+
+#define EXTRACT_IFMT_MULO_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_src2; \
+  UINT f_m3; \
+  UINT f_m2; \
+  UINT f_m1; \
+  UINT f_opcode2; \
+  UINT f_zero; \
+  UINT f_src1; \
+  unsigned int length;
+#define EXTRACT_IFMT_MULO_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \
+  f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \
+  f_zero = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_MULO1_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_src2; \
+  UINT f_m3; \
+  UINT f_m2; \
+  UINT f_m1; \
+  UINT f_opcode2; \
+  UINT f_zero; \
+  UINT f_src1; \
+  unsigned int length;
+#define EXTRACT_IFMT_MULO1_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \
+  f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \
+  f_zero = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_MULO2_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_src2; \
+  UINT f_m3; \
+  UINT f_m2; \
+  UINT f_m1; \
+  UINT f_opcode2; \
+  UINT f_zero; \
+  UINT f_src1; \
+  unsigned int length;
+#define EXTRACT_IFMT_MULO2_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \
+  f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \
+  f_zero = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_MULO3_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_src2; \
+  UINT f_m3; \
+  UINT f_m2; \
+  UINT f_m1; \
+  UINT f_opcode2; \
+  UINT f_zero; \
+  UINT f_src1; \
+  unsigned int length;
+#define EXTRACT_IFMT_MULO3_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \
+  f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \
+  f_zero = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LDA_OFFSET_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_abase; \
+  UINT f_modea; \
+  UINT f_zeroa; \
+  UINT f_offset; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDA_OFFSET_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_abase = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_modea = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_zeroa = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_offset = EXTRACT_UINT (insn, 32, 20, 12); \
+
+#define EXTRACT_IFMT_LDA_INDIRECT_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_abase; \
+  UINT f_modeb; \
+  UINT f_scale; \
+  UINT f_zerob; \
+  UINT f_index; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDA_INDIRECT_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_abase = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \
+  f_scale = EXTRACT_UINT (insn, 32, 22, 3); \
+  f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_index = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_LDA_DISP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_optdisp; \
+  UINT f_srcdst; \
+  UINT f_abase; \
+  UINT f_modeb; \
+  UINT f_scale; \
+  UINT f_zerob; \
+  UINT f_index; \
+  /* Contents of trailing part of insn.  */ \
+  UINT word_1; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDA_DISP_CODE \
+  length = 8; \
+  word_1 = GETIMEMUSI (current_cpu, pc + 4); \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_optdisp = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_abase = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \
+  f_scale = EXTRACT_UINT (insn, 32, 22, 3); \
+  f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_index = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ST_OFFSET_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_abase; \
+  UINT f_modea; \
+  UINT f_zeroa; \
+  UINT f_offset; \
+  unsigned int length;
+#define EXTRACT_IFMT_ST_OFFSET_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_abase = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_modea = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_zeroa = EXTRACT_UINT (insn, 32, 19, 1); \
+  f_offset = EXTRACT_UINT (insn, 32, 20, 12); \
+
+#define EXTRACT_IFMT_ST_INDIRECT_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_srcdst; \
+  UINT f_abase; \
+  UINT f_modeb; \
+  UINT f_scale; \
+  UINT f_zerob; \
+  UINT f_index; \
+  unsigned int length;
+#define EXTRACT_IFMT_ST_INDIRECT_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_abase = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \
+  f_scale = EXTRACT_UINT (insn, 32, 22, 3); \
+  f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_index = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_ST_DISP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_optdisp; \
+  UINT f_srcdst; \
+  UINT f_abase; \
+  UINT f_modeb; \
+  UINT f_scale; \
+  UINT f_zerob; \
+  UINT f_index; \
+  /* Contents of trailing part of insn.  */ \
+  UINT word_1; \
+  unsigned int length;
+#define EXTRACT_IFMT_ST_DISP_CODE \
+  length = 8; \
+  word_1 = GETIMEMUSI (current_cpu, pc + 4); \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_optdisp = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \
+  f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_abase = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \
+  f_scale = EXTRACT_UINT (insn, 32, 22, 3); \
+  f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \
+  f_index = EXTRACT_UINT (insn, 32, 27, 5); \
+
+#define EXTRACT_IFMT_CMPOBE_REG_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_br_src1; \
+  UINT f_br_src2; \
+  UINT f_br_m1; \
+  SI f_br_disp; \
+  UINT f_br_zero; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMPOBE_REG_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_br_src1 = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_br_src2 = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_br_m1 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_br_disp = ((((EXTRACT_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
+  f_br_zero = EXTRACT_UINT (insn, 32, 30, 2); \
+
+#define EXTRACT_IFMT_CMPOBE_LIT_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  UINT f_br_src1; \
+  UINT f_br_src2; \
+  UINT f_br_m1; \
+  SI f_br_disp; \
+  UINT f_br_zero; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMPOBE_LIT_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_br_src1 = EXTRACT_UINT (insn, 32, 8, 5); \
+  f_br_src2 = EXTRACT_UINT (insn, 32, 13, 5); \
+  f_br_m1 = EXTRACT_UINT (insn, 32, 18, 1); \
+  f_br_disp = ((((EXTRACT_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
+  f_br_zero = EXTRACT_UINT (insn, 32, 30, 2); \
+
+#define EXTRACT_IFMT_BNO_VARS \
+  /* Instruction fields.  */ \
+  UINT f_opcode; \
+  SI f_ctrl_disp; \
+  UINT f_ctrl_zero; \
+  unsigned int length;
+#define EXTRACT_IFMT_BNO_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \
+  f_ctrl_disp = ((((EXTRACT_INT (insn, 32, 8, 22)) << (2))) + (pc)); \
+  f_ctrl_zero = EXTRACT_UINT (insn, 32, 30, 2); \
+
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  IADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_I960BASE_H */
diff --git a/sim/i960/cpuall.h b/sim/i960/cpuall.h
new file mode 100644
index 00000000000..a22e55932b9
--- /dev/null
+++ b/sim/i960/cpuall.h
@@ -0,0 +1,64 @@
+/* Simulator CPU header for i960.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef I960_CPUALL_H
+#define I960_CPUALL_H
+
+/* Include files for each cpu family.  */
+
+#ifdef WANT_CPU_I960BASE
+#include "eng.h"
+#include "cgen-engine.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const MACH i960_ka_sa_mach;
+extern const MACH i960_ca_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+#endif
+
+#endif /* I960_CPUALL_H */
diff --git a/sim/i960/decode.c b/sim/i960/decode.c
new file mode 100644
index 00000000000..2bb81eec04f
--- /dev/null
+++ b/sim/i960/decode.c
@@ -0,0 +1,6644 @@
+/* Simulator instruction decoder for i960base.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU i960base
+#define WANT_CPU_I960BASE
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* FIXME: Need to review choices for the following.  */
+
+#if WITH_SEM_SWITCH_FULL
+#define FULL(fn)
+#else
+#define FULL(fn) CONCAT3 (i960base,_sem_,fn) ,
+#endif
+
+#if WITH_FAST
+#if WITH_SEM_SWITCH_FAST
+#define FAST(fn)
+#else
+#define FAST(fn) CONCAT3 (i960base,_semf_,fn) , /* f for fast */
+#endif
+#else
+#define FAST(fn)
+#endif
+
+/* The instruction descriptor array.
+   This is computed at runtime.  Space for it is not malloc'd to save a
+   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
+   but won't be done until necessary (we don't currently support the runtime
+   addition of instructions nor an SMP machine with different cpus).  */
+static IDESC i960base_insn_data[I960BASE_INSN_MAX];
+
+/* The INSN_ prefix is not here and is instead part of the `insn' argument
+   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
+#define IDX(insn) CONCAT2 (I960BASE_,insn)
+#define TYPE(insn) CONCAT2 (I960_,insn)
+
+/* Commas between elements are contained in the macros.
+   Some of these are conditionally compiled out.  */
+
+static const struct insn_sem i960base_insn_sem[] =
+{
+  { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) },
+  { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) },
+  { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) },
+  { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) },
+  { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) },
+  { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) },
+  { TYPE (INSN_MULO), IDX (INSN_MULO), FULL (mulo) FAST (mulo) },
+  { TYPE (INSN_MULO1), IDX (INSN_MULO1), FULL (mulo1) FAST (mulo1) },
+  { TYPE (INSN_MULO2), IDX (INSN_MULO2), FULL (mulo2) FAST (mulo2) },
+  { TYPE (INSN_MULO3), IDX (INSN_MULO3), FULL (mulo3) FAST (mulo3) },
+  { TYPE (INSN_REMO), IDX (INSN_REMO), FULL (remo) FAST (remo) },
+  { TYPE (INSN_REMO1), IDX (INSN_REMO1), FULL (remo1) FAST (remo1) },
+  { TYPE (INSN_REMO2), IDX (INSN_REMO2), FULL (remo2) FAST (remo2) },
+  { TYPE (INSN_REMO3), IDX (INSN_REMO3), FULL (remo3) FAST (remo3) },
+  { TYPE (INSN_DIVO), IDX (INSN_DIVO), FULL (divo) FAST (divo) },
+  { TYPE (INSN_DIVO1), IDX (INSN_DIVO1), FULL (divo1) FAST (divo1) },
+  { TYPE (INSN_DIVO2), IDX (INSN_DIVO2), FULL (divo2) FAST (divo2) },
+  { TYPE (INSN_DIVO3), IDX (INSN_DIVO3), FULL (divo3) FAST (divo3) },
+  { TYPE (INSN_REMI), IDX (INSN_REMI), FULL (remi) FAST (remi) },
+  { TYPE (INSN_REMI1), IDX (INSN_REMI1), FULL (remi1) FAST (remi1) },
+  { TYPE (INSN_REMI2), IDX (INSN_REMI2), FULL (remi2) FAST (remi2) },
+  { TYPE (INSN_REMI3), IDX (INSN_REMI3), FULL (remi3) FAST (remi3) },
+  { TYPE (INSN_DIVI), IDX (INSN_DIVI), FULL (divi) FAST (divi) },
+  { TYPE (INSN_DIVI1), IDX (INSN_DIVI1), FULL (divi1) FAST (divi1) },
+  { TYPE (INSN_DIVI2), IDX (INSN_DIVI2), FULL (divi2) FAST (divi2) },
+  { TYPE (INSN_DIVI3), IDX (INSN_DIVI3), FULL (divi3) FAST (divi3) },
+  { TYPE (INSN_ADDO), IDX (INSN_ADDO), FULL (addo) FAST (addo) },
+  { TYPE (INSN_ADDO1), IDX (INSN_ADDO1), FULL (addo1) FAST (addo1) },
+  { TYPE (INSN_ADDO2), IDX (INSN_ADDO2), FULL (addo2) FAST (addo2) },
+  { TYPE (INSN_ADDO3), IDX (INSN_ADDO3), FULL (addo3) FAST (addo3) },
+  { TYPE (INSN_SUBO), IDX (INSN_SUBO), FULL (subo) FAST (subo) },
+  { TYPE (INSN_SUBO1), IDX (INSN_SUBO1), FULL (subo1) FAST (subo1) },
+  { TYPE (INSN_SUBO2), IDX (INSN_SUBO2), FULL (subo2) FAST (subo2) },
+  { TYPE (INSN_SUBO3), IDX (INSN_SUBO3), FULL (subo3) FAST (subo3) },
+  { TYPE (INSN_NOTBIT), IDX (INSN_NOTBIT), FULL (notbit) FAST (notbit) },
+  { TYPE (INSN_NOTBIT1), IDX (INSN_NOTBIT1), FULL (notbit1) FAST (notbit1) },
+  { TYPE (INSN_NOTBIT2), IDX (INSN_NOTBIT2), FULL (notbit2) FAST (notbit2) },
+  { TYPE (INSN_NOTBIT3), IDX (INSN_NOTBIT3), FULL (notbit3) FAST (notbit3) },
+  { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) },
+  { TYPE (INSN_AND1), IDX (INSN_AND1), FULL (and1) FAST (and1) },
+  { TYPE (INSN_AND2), IDX (INSN_AND2), FULL (and2) FAST (and2) },
+  { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) },
+  { TYPE (INSN_ANDNOT), IDX (INSN_ANDNOT), FULL (andnot) FAST (andnot) },
+  { TYPE (INSN_ANDNOT1), IDX (INSN_ANDNOT1), FULL (andnot1) FAST (andnot1) },
+  { TYPE (INSN_ANDNOT2), IDX (INSN_ANDNOT2), FULL (andnot2) FAST (andnot2) },
+  { TYPE (INSN_ANDNOT3), IDX (INSN_ANDNOT3), FULL (andnot3) FAST (andnot3) },
+  { TYPE (INSN_SETBIT), IDX (INSN_SETBIT), FULL (setbit) FAST (setbit) },
+  { TYPE (INSN_SETBIT1), IDX (INSN_SETBIT1), FULL (setbit1) FAST (setbit1) },
+  { TYPE (INSN_SETBIT2), IDX (INSN_SETBIT2), FULL (setbit2) FAST (setbit2) },
+  { TYPE (INSN_SETBIT3), IDX (INSN_SETBIT3), FULL (setbit3) FAST (setbit3) },
+  { TYPE (INSN_NOTAND), IDX (INSN_NOTAND), FULL (notand) FAST (notand) },
+  { TYPE (INSN_NOTAND1), IDX (INSN_NOTAND1), FULL (notand1) FAST (notand1) },
+  { TYPE (INSN_NOTAND2), IDX (INSN_NOTAND2), FULL (notand2) FAST (notand2) },
+  { TYPE (INSN_NOTAND3), IDX (INSN_NOTAND3), FULL (notand3) FAST (notand3) },
+  { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) },
+  { TYPE (INSN_XOR1), IDX (INSN_XOR1), FULL (xor1) FAST (xor1) },
+  { TYPE (INSN_XOR2), IDX (INSN_XOR2), FULL (xor2) FAST (xor2) },
+  { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) },
+  { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) },
+  { TYPE (INSN_OR1), IDX (INSN_OR1), FULL (or1) FAST (or1) },
+  { TYPE (INSN_OR2), IDX (INSN_OR2), FULL (or2) FAST (or2) },
+  { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) },
+  { TYPE (INSN_NOR), IDX (INSN_NOR), FULL (nor) FAST (nor) },
+  { TYPE (INSN_NOR1), IDX (INSN_NOR1), FULL (nor1) FAST (nor1) },
+  { TYPE (INSN_NOR2), IDX (INSN_NOR2), FULL (nor2) FAST (nor2) },
+  { TYPE (INSN_NOR3), IDX (INSN_NOR3), FULL (nor3) FAST (nor3) },
+  { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) },
+  { TYPE (INSN_NOT1), IDX (INSN_NOT1), FULL (not1) FAST (not1) },
+  { TYPE (INSN_NOT2), IDX (INSN_NOT2), FULL (not2) FAST (not2) },
+  { TYPE (INSN_NOT3), IDX (INSN_NOT3), FULL (not3) FAST (not3) },
+  { TYPE (INSN_CLRBIT), IDX (INSN_CLRBIT), FULL (clrbit) FAST (clrbit) },
+  { TYPE (INSN_CLRBIT1), IDX (INSN_CLRBIT1), FULL (clrbit1) FAST (clrbit1) },
+  { TYPE (INSN_CLRBIT2), IDX (INSN_CLRBIT2), FULL (clrbit2) FAST (clrbit2) },
+  { TYPE (INSN_CLRBIT3), IDX (INSN_CLRBIT3), FULL (clrbit3) FAST (clrbit3) },
+  { TYPE (INSN_SHLO), IDX (INSN_SHLO), FULL (shlo) FAST (shlo) },
+  { TYPE (INSN_SHLO1), IDX (INSN_SHLO1), FULL (shlo1) FAST (shlo1) },
+  { TYPE (INSN_SHLO2), IDX (INSN_SHLO2), FULL (shlo2) FAST (shlo2) },
+  { TYPE (INSN_SHLO3), IDX (INSN_SHLO3), FULL (shlo3) FAST (shlo3) },
+  { TYPE (INSN_SHRO), IDX (INSN_SHRO), FULL (shro) FAST (shro) },
+  { TYPE (INSN_SHRO1), IDX (INSN_SHRO1), FULL (shro1) FAST (shro1) },
+  { TYPE (INSN_SHRO2), IDX (INSN_SHRO2), FULL (shro2) FAST (shro2) },
+  { TYPE (INSN_SHRO3), IDX (INSN_SHRO3), FULL (shro3) FAST (shro3) },
+  { TYPE (INSN_SHLI), IDX (INSN_SHLI), FULL (shli) FAST (shli) },
+  { TYPE (INSN_SHLI1), IDX (INSN_SHLI1), FULL (shli1) FAST (shli1) },
+  { TYPE (INSN_SHLI2), IDX (INSN_SHLI2), FULL (shli2) FAST (shli2) },
+  { TYPE (INSN_SHLI3), IDX (INSN_SHLI3), FULL (shli3) FAST (shli3) },
+  { TYPE (INSN_SHRI), IDX (INSN_SHRI), FULL (shri) FAST (shri) },
+  { TYPE (INSN_SHRI1), IDX (INSN_SHRI1), FULL (shri1) FAST (shri1) },
+  { TYPE (INSN_SHRI2), IDX (INSN_SHRI2), FULL (shri2) FAST (shri2) },
+  { TYPE (INSN_SHRI3), IDX (INSN_SHRI3), FULL (shri3) FAST (shri3) },
+  { TYPE (INSN_EMUL), IDX (INSN_EMUL), FULL (emul) FAST (emul) },
+  { TYPE (INSN_EMUL1), IDX (INSN_EMUL1), FULL (emul1) FAST (emul1) },
+  { TYPE (INSN_EMUL2), IDX (INSN_EMUL2), FULL (emul2) FAST (emul2) },
+  { TYPE (INSN_EMUL3), IDX (INSN_EMUL3), FULL (emul3) FAST (emul3) },
+  { TYPE (INSN_MOV), IDX (INSN_MOV), FULL (mov) FAST (mov) },
+  { TYPE (INSN_MOV1), IDX (INSN_MOV1), FULL (mov1) FAST (mov1) },
+  { TYPE (INSN_MOVL), IDX (INSN_MOVL), FULL (movl) FAST (movl) },
+  { TYPE (INSN_MOVL1), IDX (INSN_MOVL1), FULL (movl1) FAST (movl1) },
+  { TYPE (INSN_MOVT), IDX (INSN_MOVT), FULL (movt) FAST (movt) },
+  { TYPE (INSN_MOVT1), IDX (INSN_MOVT1), FULL (movt1) FAST (movt1) },
+  { TYPE (INSN_MOVQ), IDX (INSN_MOVQ), FULL (movq) FAST (movq) },
+  { TYPE (INSN_MOVQ1), IDX (INSN_MOVQ1), FULL (movq1) FAST (movq1) },
+  { TYPE (INSN_MODPC), IDX (INSN_MODPC), FULL (modpc) FAST (modpc) },
+  { TYPE (INSN_MODAC), IDX (INSN_MODAC), FULL (modac) FAST (modac) },
+  { TYPE (INSN_LDA_OFFSET), IDX (INSN_LDA_OFFSET), FULL (lda_offset) FAST (lda_offset) },
+  { TYPE (INSN_LDA_INDIRECT_OFFSET), IDX (INSN_LDA_INDIRECT_OFFSET), FULL (lda_indirect_offset) FAST (lda_indirect_offset) },
+  { TYPE (INSN_LDA_INDIRECT), IDX (INSN_LDA_INDIRECT), FULL (lda_indirect) FAST (lda_indirect) },
+  { TYPE (INSN_LDA_INDIRECT_INDEX), IDX (INSN_LDA_INDIRECT_INDEX), FULL (lda_indirect_index) FAST (lda_indirect_index) },
+  { TYPE (INSN_LDA_DISP), IDX (INSN_LDA_DISP), FULL (lda_disp) FAST (lda_disp) },
+  { TYPE (INSN_LDA_INDIRECT_DISP), IDX (INSN_LDA_INDIRECT_DISP), FULL (lda_indirect_disp) FAST (lda_indirect_disp) },
+  { TYPE (INSN_LDA_INDEX_DISP), IDX (INSN_LDA_INDEX_DISP), FULL (lda_index_disp) FAST (lda_index_disp) },
+  { TYPE (INSN_LDA_INDIRECT_INDEX_DISP), IDX (INSN_LDA_INDIRECT_INDEX_DISP), FULL (lda_indirect_index_disp) FAST (lda_indirect_index_disp) },
+  { TYPE (INSN_LD_OFFSET), IDX (INSN_LD_OFFSET), FULL (ld_offset) FAST (ld_offset) },
+  { TYPE (INSN_LD_INDIRECT_OFFSET), IDX (INSN_LD_INDIRECT_OFFSET), FULL (ld_indirect_offset) FAST (ld_indirect_offset) },
+  { TYPE (INSN_LD_INDIRECT), IDX (INSN_LD_INDIRECT), FULL (ld_indirect) FAST (ld_indirect) },
+  { TYPE (INSN_LD_INDIRECT_INDEX), IDX (INSN_LD_INDIRECT_INDEX), FULL (ld_indirect_index) FAST (ld_indirect_index) },
+  { TYPE (INSN_LD_DISP), IDX (INSN_LD_DISP), FULL (ld_disp) FAST (ld_disp) },
+  { TYPE (INSN_LD_INDIRECT_DISP), IDX (INSN_LD_INDIRECT_DISP), FULL (ld_indirect_disp) FAST (ld_indirect_disp) },
+  { TYPE (INSN_LD_INDEX_DISP), IDX (INSN_LD_INDEX_DISP), FULL (ld_index_disp) FAST (ld_index_disp) },
+  { TYPE (INSN_LD_INDIRECT_INDEX_DISP), IDX (INSN_LD_INDIRECT_INDEX_DISP), FULL (ld_indirect_index_disp) FAST (ld_indirect_index_disp) },
+  { TYPE (INSN_LDOB_OFFSET), IDX (INSN_LDOB_OFFSET), FULL (ldob_offset) FAST (ldob_offset) },
+  { TYPE (INSN_LDOB_INDIRECT_OFFSET), IDX (INSN_LDOB_INDIRECT_OFFSET), FULL (ldob_indirect_offset) FAST (ldob_indirect_offset) },
+  { TYPE (INSN_LDOB_INDIRECT), IDX (INSN_LDOB_INDIRECT), FULL (ldob_indirect) FAST (ldob_indirect) },
+  { TYPE (INSN_LDOB_INDIRECT_INDEX), IDX (INSN_LDOB_INDIRECT_INDEX), FULL (ldob_indirect_index) FAST (ldob_indirect_index) },
+  { TYPE (INSN_LDOB_DISP), IDX (INSN_LDOB_DISP), FULL (ldob_disp) FAST (ldob_disp) },
+  { TYPE (INSN_LDOB_INDIRECT_DISP), IDX (INSN_LDOB_INDIRECT_DISP), FULL (ldob_indirect_disp) FAST (ldob_indirect_disp) },
+  { TYPE (INSN_LDOB_INDEX_DISP), IDX (INSN_LDOB_INDEX_DISP), FULL (ldob_index_disp) FAST (ldob_index_disp) },
+  { TYPE (INSN_LDOB_INDIRECT_INDEX_DISP), IDX (INSN_LDOB_INDIRECT_INDEX_DISP), FULL (ldob_indirect_index_disp) FAST (ldob_indirect_index_disp) },
+  { TYPE (INSN_LDOS_OFFSET), IDX (INSN_LDOS_OFFSET), FULL (ldos_offset) FAST (ldos_offset) },
+  { TYPE (INSN_LDOS_INDIRECT_OFFSET), IDX (INSN_LDOS_INDIRECT_OFFSET), FULL (ldos_indirect_offset) FAST (ldos_indirect_offset) },
+  { TYPE (INSN_LDOS_INDIRECT), IDX (INSN_LDOS_INDIRECT), FULL (ldos_indirect) FAST (ldos_indirect) },
+  { TYPE (INSN_LDOS_INDIRECT_INDEX), IDX (INSN_LDOS_INDIRECT_INDEX), FULL (ldos_indirect_index) FAST (ldos_indirect_index) },
+  { TYPE (INSN_LDOS_DISP), IDX (INSN_LDOS_DISP), FULL (ldos_disp) FAST (ldos_disp) },
+  { TYPE (INSN_LDOS_INDIRECT_DISP), IDX (INSN_LDOS_INDIRECT_DISP), FULL (ldos_indirect_disp) FAST (ldos_indirect_disp) },
+  { TYPE (INSN_LDOS_INDEX_DISP), IDX (INSN_LDOS_INDEX_DISP), FULL (ldos_index_disp) FAST (ldos_index_disp) },
+  { TYPE (INSN_LDOS_INDIRECT_INDEX_DISP), IDX (INSN_LDOS_INDIRECT_INDEX_DISP), FULL (ldos_indirect_index_disp) FAST (ldos_indirect_index_disp) },
+  { TYPE (INSN_LDIB_OFFSET), IDX (INSN_LDIB_OFFSET), FULL (ldib_offset) FAST (ldib_offset) },
+  { TYPE (INSN_LDIB_INDIRECT_OFFSET), IDX (INSN_LDIB_INDIRECT_OFFSET), FULL (ldib_indirect_offset) FAST (ldib_indirect_offset) },
+  { TYPE (INSN_LDIB_INDIRECT), IDX (INSN_LDIB_INDIRECT), FULL (ldib_indirect) FAST (ldib_indirect) },
+  { TYPE (INSN_LDIB_INDIRECT_INDEX), IDX (INSN_LDIB_INDIRECT_INDEX), FULL (ldib_indirect_index) FAST (ldib_indirect_index) },
+  { TYPE (INSN_LDIB_DISP), IDX (INSN_LDIB_DISP), FULL (ldib_disp) FAST (ldib_disp) },
+  { TYPE (INSN_LDIB_INDIRECT_DISP), IDX (INSN_LDIB_INDIRECT_DISP), FULL (ldib_indirect_disp) FAST (ldib_indirect_disp) },
+  { TYPE (INSN_LDIB_INDEX_DISP), IDX (INSN_LDIB_INDEX_DISP), FULL (ldib_index_disp) FAST (ldib_index_disp) },
+  { TYPE (INSN_LDIB_INDIRECT_INDEX_DISP), IDX (INSN_LDIB_INDIRECT_INDEX_DISP), FULL (ldib_indirect_index_disp) FAST (ldib_indirect_index_disp) },
+  { TYPE (INSN_LDIS_OFFSET), IDX (INSN_LDIS_OFFSET), FULL (ldis_offset) FAST (ldis_offset) },
+  { TYPE (INSN_LDIS_INDIRECT_OFFSET), IDX (INSN_LDIS_INDIRECT_OFFSET), FULL (ldis_indirect_offset) FAST (ldis_indirect_offset) },
+  { TYPE (INSN_LDIS_INDIRECT), IDX (INSN_LDIS_INDIRECT), FULL (ldis_indirect) FAST (ldis_indirect) },
+  { TYPE (INSN_LDIS_INDIRECT_INDEX), IDX (INSN_LDIS_INDIRECT_INDEX), FULL (ldis_indirect_index) FAST (ldis_indirect_index) },
+  { TYPE (INSN_LDIS_DISP), IDX (INSN_LDIS_DISP), FULL (ldis_disp) FAST (ldis_disp) },
+  { TYPE (INSN_LDIS_INDIRECT_DISP), IDX (INSN_LDIS_INDIRECT_DISP), FULL (ldis_indirect_disp) FAST (ldis_indirect_disp) },
+  { TYPE (INSN_LDIS_INDEX_DISP), IDX (INSN_LDIS_INDEX_DISP), FULL (ldis_index_disp) FAST (ldis_index_disp) },
+  { TYPE (INSN_LDIS_INDIRECT_INDEX_DISP), IDX (INSN_LDIS_INDIRECT_INDEX_DISP), FULL (ldis_indirect_index_disp) FAST (ldis_indirect_index_disp) },
+  { TYPE (INSN_LDL_OFFSET), IDX (INSN_LDL_OFFSET), FULL (ldl_offset) FAST (ldl_offset) },
+  { TYPE (INSN_LDL_INDIRECT_OFFSET), IDX (INSN_LDL_INDIRECT_OFFSET), FULL (ldl_indirect_offset) FAST (ldl_indirect_offset) },
+  { TYPE (INSN_LDL_INDIRECT), IDX (INSN_LDL_INDIRECT), FULL (ldl_indirect) FAST (ldl_indirect) },
+  { TYPE (INSN_LDL_INDIRECT_INDEX), IDX (INSN_LDL_INDIRECT_INDEX), FULL (ldl_indirect_index) FAST (ldl_indirect_index) },
+  { TYPE (INSN_LDL_DISP), IDX (INSN_LDL_DISP), FULL (ldl_disp) FAST (ldl_disp) },
+  { TYPE (INSN_LDL_INDIRECT_DISP), IDX (INSN_LDL_INDIRECT_DISP), FULL (ldl_indirect_disp) FAST (ldl_indirect_disp) },
+  { TYPE (INSN_LDL_INDEX_DISP), IDX (INSN_LDL_INDEX_DISP), FULL (ldl_index_disp) FAST (ldl_index_disp) },
+  { TYPE (INSN_LDL_INDIRECT_INDEX_DISP), IDX (INSN_LDL_INDIRECT_INDEX_DISP), FULL (ldl_indirect_index_disp) FAST (ldl_indirect_index_disp) },
+  { TYPE (INSN_LDT_OFFSET), IDX (INSN_LDT_OFFSET), FULL (ldt_offset) FAST (ldt_offset) },
+  { TYPE (INSN_LDT_INDIRECT_OFFSET), IDX (INSN_LDT_INDIRECT_OFFSET), FULL (ldt_indirect_offset) FAST (ldt_indirect_offset) },
+  { TYPE (INSN_LDT_INDIRECT), IDX (INSN_LDT_INDIRECT), FULL (ldt_indirect) FAST (ldt_indirect) },
+  { TYPE (INSN_LDT_INDIRECT_INDEX), IDX (INSN_LDT_INDIRECT_INDEX), FULL (ldt_indirect_index) FAST (ldt_indirect_index) },
+  { TYPE (INSN_LDT_DISP), IDX (INSN_LDT_DISP), FULL (ldt_disp) FAST (ldt_disp) },
+  { TYPE (INSN_LDT_INDIRECT_DISP), IDX (INSN_LDT_INDIRECT_DISP), FULL (ldt_indirect_disp) FAST (ldt_indirect_disp) },
+  { TYPE (INSN_LDT_INDEX_DISP), IDX (INSN_LDT_INDEX_DISP), FULL (ldt_index_disp) FAST (ldt_index_disp) },
+  { TYPE (INSN_LDT_INDIRECT_INDEX_DISP), IDX (INSN_LDT_INDIRECT_INDEX_DISP), FULL (ldt_indirect_index_disp) FAST (ldt_indirect_index_disp) },
+  { TYPE (INSN_LDQ_OFFSET), IDX (INSN_LDQ_OFFSET), FULL (ldq_offset) FAST (ldq_offset) },
+  { TYPE (INSN_LDQ_INDIRECT_OFFSET), IDX (INSN_LDQ_INDIRECT_OFFSET), FULL (ldq_indirect_offset) FAST (ldq_indirect_offset) },
+  { TYPE (INSN_LDQ_INDIRECT), IDX (INSN_LDQ_INDIRECT), FULL (ldq_indirect) FAST (ldq_indirect) },
+  { TYPE (INSN_LDQ_INDIRECT_INDEX), IDX (INSN_LDQ_INDIRECT_INDEX), FULL (ldq_indirect_index) FAST (ldq_indirect_index) },
+  { TYPE (INSN_LDQ_DISP), IDX (INSN_LDQ_DISP), FULL (ldq_disp) FAST (ldq_disp) },
+  { TYPE (INSN_LDQ_INDIRECT_DISP), IDX (INSN_LDQ_INDIRECT_DISP), FULL (ldq_indirect_disp) FAST (ldq_indirect_disp) },
+  { TYPE (INSN_LDQ_INDEX_DISP), IDX (INSN_LDQ_INDEX_DISP), FULL (ldq_index_disp) FAST (ldq_index_disp) },
+  { TYPE (INSN_LDQ_INDIRECT_INDEX_DISP), IDX (INSN_LDQ_INDIRECT_INDEX_DISP), FULL (ldq_indirect_index_disp) FAST (ldq_indirect_index_disp) },
+  { TYPE (INSN_ST_OFFSET), IDX (INSN_ST_OFFSET), FULL (st_offset) FAST (st_offset) },
+  { TYPE (INSN_ST_INDIRECT_OFFSET), IDX (INSN_ST_INDIRECT_OFFSET), FULL (st_indirect_offset) FAST (st_indirect_offset) },
+  { TYPE (INSN_ST_INDIRECT), IDX (INSN_ST_INDIRECT), FULL (st_indirect) FAST (st_indirect) },
+  { TYPE (INSN_ST_INDIRECT_INDEX), IDX (INSN_ST_INDIRECT_INDEX), FULL (st_indirect_index) FAST (st_indirect_index) },
+  { TYPE (INSN_ST_DISP), IDX (INSN_ST_DISP), FULL (st_disp) FAST (st_disp) },
+  { TYPE (INSN_ST_INDIRECT_DISP), IDX (INSN_ST_INDIRECT_DISP), FULL (st_indirect_disp) FAST (st_indirect_disp) },
+  { TYPE (INSN_ST_INDEX_DISP), IDX (INSN_ST_INDEX_DISP), FULL (st_index_disp) FAST (st_index_disp) },
+  { TYPE (INSN_ST_INDIRECT_INDEX_DISP), IDX (INSN_ST_INDIRECT_INDEX_DISP), FULL (st_indirect_index_disp) FAST (st_indirect_index_disp) },
+  { TYPE (INSN_STOB_OFFSET), IDX (INSN_STOB_OFFSET), FULL (stob_offset) FAST (stob_offset) },
+  { TYPE (INSN_STOB_INDIRECT_OFFSET), IDX (INSN_STOB_INDIRECT_OFFSET), FULL (stob_indirect_offset) FAST (stob_indirect_offset) },
+  { TYPE (INSN_STOB_INDIRECT), IDX (INSN_STOB_INDIRECT), FULL (stob_indirect) FAST (stob_indirect) },
+  { TYPE (INSN_STOB_INDIRECT_INDEX), IDX (INSN_STOB_INDIRECT_INDEX), FULL (stob_indirect_index) FAST (stob_indirect_index) },
+  { TYPE (INSN_STOB_DISP), IDX (INSN_STOB_DISP), FULL (stob_disp) FAST (stob_disp) },
+  { TYPE (INSN_STOB_INDIRECT_DISP), IDX (INSN_STOB_INDIRECT_DISP), FULL (stob_indirect_disp) FAST (stob_indirect_disp) },
+  { TYPE (INSN_STOB_INDEX_DISP), IDX (INSN_STOB_INDEX_DISP), FULL (stob_index_disp) FAST (stob_index_disp) },
+  { TYPE (INSN_STOB_INDIRECT_INDEX_DISP), IDX (INSN_STOB_INDIRECT_INDEX_DISP), FULL (stob_indirect_index_disp) FAST (stob_indirect_index_disp) },
+  { TYPE (INSN_STOS_OFFSET), IDX (INSN_STOS_OFFSET), FULL (stos_offset) FAST (stos_offset) },
+  { TYPE (INSN_STOS_INDIRECT_OFFSET), IDX (INSN_STOS_INDIRECT_OFFSET), FULL (stos_indirect_offset) FAST (stos_indirect_offset) },
+  { TYPE (INSN_STOS_INDIRECT), IDX (INSN_STOS_INDIRECT), FULL (stos_indirect) FAST (stos_indirect) },
+  { TYPE (INSN_STOS_INDIRECT_INDEX), IDX (INSN_STOS_INDIRECT_INDEX), FULL (stos_indirect_index) FAST (stos_indirect_index) },
+  { TYPE (INSN_STOS_DISP), IDX (INSN_STOS_DISP), FULL (stos_disp) FAST (stos_disp) },
+  { TYPE (INSN_STOS_INDIRECT_DISP), IDX (INSN_STOS_INDIRECT_DISP), FULL (stos_indirect_disp) FAST (stos_indirect_disp) },
+  { TYPE (INSN_STOS_INDEX_DISP), IDX (INSN_STOS_INDEX_DISP), FULL (stos_index_disp) FAST (stos_index_disp) },
+  { TYPE (INSN_STOS_INDIRECT_INDEX_DISP), IDX (INSN_STOS_INDIRECT_INDEX_DISP), FULL (stos_indirect_index_disp) FAST (stos_indirect_index_disp) },
+  { TYPE (INSN_STL_OFFSET), IDX (INSN_STL_OFFSET), FULL (stl_offset) FAST (stl_offset) },
+  { TYPE (INSN_STL_INDIRECT_OFFSET), IDX (INSN_STL_INDIRECT_OFFSET), FULL (stl_indirect_offset) FAST (stl_indirect_offset) },
+  { TYPE (INSN_STL_INDIRECT), IDX (INSN_STL_INDIRECT), FULL (stl_indirect) FAST (stl_indirect) },
+  { TYPE (INSN_STL_INDIRECT_INDEX), IDX (INSN_STL_INDIRECT_INDEX), FULL (stl_indirect_index) FAST (stl_indirect_index) },
+  { TYPE (INSN_STL_DISP), IDX (INSN_STL_DISP), FULL (stl_disp) FAST (stl_disp) },
+  { TYPE (INSN_STL_INDIRECT_DISP), IDX (INSN_STL_INDIRECT_DISP), FULL (stl_indirect_disp) FAST (stl_indirect_disp) },
+  { TYPE (INSN_STL_INDEX_DISP), IDX (INSN_STL_INDEX_DISP), FULL (stl_index_disp) FAST (stl_index_disp) },
+  { TYPE (INSN_STL_INDIRECT_INDEX_DISP), IDX (INSN_STL_INDIRECT_INDEX_DISP), FULL (stl_indirect_index_disp) FAST (stl_indirect_index_disp) },
+  { TYPE (INSN_STT_OFFSET), IDX (INSN_STT_OFFSET), FULL (stt_offset) FAST (stt_offset) },
+  { TYPE (INSN_STT_INDIRECT_OFFSET), IDX (INSN_STT_INDIRECT_OFFSET), FULL (stt_indirect_offset) FAST (stt_indirect_offset) },
+  { TYPE (INSN_STT_INDIRECT), IDX (INSN_STT_INDIRECT), FULL (stt_indirect) FAST (stt_indirect) },
+  { TYPE (INSN_STT_INDIRECT_INDEX), IDX (INSN_STT_INDIRECT_INDEX), FULL (stt_indirect_index) FAST (stt_indirect_index) },
+  { TYPE (INSN_STT_DISP), IDX (INSN_STT_DISP), FULL (stt_disp) FAST (stt_disp) },
+  { TYPE (INSN_STT_INDIRECT_DISP), IDX (INSN_STT_INDIRECT_DISP), FULL (stt_indirect_disp) FAST (stt_indirect_disp) },
+  { TYPE (INSN_STT_INDEX_DISP), IDX (INSN_STT_INDEX_DISP), FULL (stt_index_disp) FAST (stt_index_disp) },
+  { TYPE (INSN_STT_INDIRECT_INDEX_DISP), IDX (INSN_STT_INDIRECT_INDEX_DISP), FULL (stt_indirect_index_disp) FAST (stt_indirect_index_disp) },
+  { TYPE (INSN_STQ_OFFSET), IDX (INSN_STQ_OFFSET), FULL (stq_offset) FAST (stq_offset) },
+  { TYPE (INSN_STQ_INDIRECT_OFFSET), IDX (INSN_STQ_INDIRECT_OFFSET), FULL (stq_indirect_offset) FAST (stq_indirect_offset) },
+  { TYPE (INSN_STQ_INDIRECT), IDX (INSN_STQ_INDIRECT), FULL (stq_indirect) FAST (stq_indirect) },
+  { TYPE (INSN_STQ_INDIRECT_INDEX), IDX (INSN_STQ_INDIRECT_INDEX), FULL (stq_indirect_index) FAST (stq_indirect_index) },
+  { TYPE (INSN_STQ_DISP), IDX (INSN_STQ_DISP), FULL (stq_disp) FAST (stq_disp) },
+  { TYPE (INSN_STQ_INDIRECT_DISP), IDX (INSN_STQ_INDIRECT_DISP), FULL (stq_indirect_disp) FAST (stq_indirect_disp) },
+  { TYPE (INSN_STQ_INDEX_DISP), IDX (INSN_STQ_INDEX_DISP), FULL (stq_index_disp) FAST (stq_index_disp) },
+  { TYPE (INSN_STQ_INDIRECT_INDEX_DISP), IDX (INSN_STQ_INDIRECT_INDEX_DISP), FULL (stq_indirect_index_disp) FAST (stq_indirect_index_disp) },
+  { TYPE (INSN_CMPOBE_REG), IDX (INSN_CMPOBE_REG), FULL (cmpobe_reg) FAST (cmpobe_reg) },
+  { TYPE (INSN_CMPOBE_LIT), IDX (INSN_CMPOBE_LIT), FULL (cmpobe_lit) FAST (cmpobe_lit) },
+  { TYPE (INSN_CMPOBNE_REG), IDX (INSN_CMPOBNE_REG), FULL (cmpobne_reg) FAST (cmpobne_reg) },
+  { TYPE (INSN_CMPOBNE_LIT), IDX (INSN_CMPOBNE_LIT), FULL (cmpobne_lit) FAST (cmpobne_lit) },
+  { TYPE (INSN_CMPOBL_REG), IDX (INSN_CMPOBL_REG), FULL (cmpobl_reg) FAST (cmpobl_reg) },
+  { TYPE (INSN_CMPOBL_LIT), IDX (INSN_CMPOBL_LIT), FULL (cmpobl_lit) FAST (cmpobl_lit) },
+  { TYPE (INSN_CMPOBLE_REG), IDX (INSN_CMPOBLE_REG), FULL (cmpoble_reg) FAST (cmpoble_reg) },
+  { TYPE (INSN_CMPOBLE_LIT), IDX (INSN_CMPOBLE_LIT), FULL (cmpoble_lit) FAST (cmpoble_lit) },
+  { TYPE (INSN_CMPOBG_REG), IDX (INSN_CMPOBG_REG), FULL (cmpobg_reg) FAST (cmpobg_reg) },
+  { TYPE (INSN_CMPOBG_LIT), IDX (INSN_CMPOBG_LIT), FULL (cmpobg_lit) FAST (cmpobg_lit) },
+  { TYPE (INSN_CMPOBGE_REG), IDX (INSN_CMPOBGE_REG), FULL (cmpobge_reg) FAST (cmpobge_reg) },
+  { TYPE (INSN_CMPOBGE_LIT), IDX (INSN_CMPOBGE_LIT), FULL (cmpobge_lit) FAST (cmpobge_lit) },
+  { TYPE (INSN_CMPIBE_REG), IDX (INSN_CMPIBE_REG), FULL (cmpibe_reg) FAST (cmpibe_reg) },
+  { TYPE (INSN_CMPIBE_LIT), IDX (INSN_CMPIBE_LIT), FULL (cmpibe_lit) FAST (cmpibe_lit) },
+  { TYPE (INSN_CMPIBNE_REG), IDX (INSN_CMPIBNE_REG), FULL (cmpibne_reg) FAST (cmpibne_reg) },
+  { TYPE (INSN_CMPIBNE_LIT), IDX (INSN_CMPIBNE_LIT), FULL (cmpibne_lit) FAST (cmpibne_lit) },
+  { TYPE (INSN_CMPIBL_REG), IDX (INSN_CMPIBL_REG), FULL (cmpibl_reg) FAST (cmpibl_reg) },
+  { TYPE (INSN_CMPIBL_LIT), IDX (INSN_CMPIBL_LIT), FULL (cmpibl_lit) FAST (cmpibl_lit) },
+  { TYPE (INSN_CMPIBLE_REG), IDX (INSN_CMPIBLE_REG), FULL (cmpible_reg) FAST (cmpible_reg) },
+  { TYPE (INSN_CMPIBLE_LIT), IDX (INSN_CMPIBLE_LIT), FULL (cmpible_lit) FAST (cmpible_lit) },
+  { TYPE (INSN_CMPIBG_REG), IDX (INSN_CMPIBG_REG), FULL (cmpibg_reg) FAST (cmpibg_reg) },
+  { TYPE (INSN_CMPIBG_LIT), IDX (INSN_CMPIBG_LIT), FULL (cmpibg_lit) FAST (cmpibg_lit) },
+  { TYPE (INSN_CMPIBGE_REG), IDX (INSN_CMPIBGE_REG), FULL (cmpibge_reg) FAST (cmpibge_reg) },
+  { TYPE (INSN_CMPIBGE_LIT), IDX (INSN_CMPIBGE_LIT), FULL (cmpibge_lit) FAST (cmpibge_lit) },
+  { TYPE (INSN_BBC_REG), IDX (INSN_BBC_REG), FULL (bbc_reg) FAST (bbc_reg) },
+  { TYPE (INSN_BBC_LIT), IDX (INSN_BBC_LIT), FULL (bbc_lit) FAST (bbc_lit) },
+  { TYPE (INSN_BBS_REG), IDX (INSN_BBS_REG), FULL (bbs_reg) FAST (bbs_reg) },
+  { TYPE (INSN_BBS_LIT), IDX (INSN_BBS_LIT), FULL (bbs_lit) FAST (bbs_lit) },
+  { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) },
+  { TYPE (INSN_CMPI1), IDX (INSN_CMPI1), FULL (cmpi1) FAST (cmpi1) },
+  { TYPE (INSN_CMPI2), IDX (INSN_CMPI2), FULL (cmpi2) FAST (cmpi2) },
+  { TYPE (INSN_CMPI3), IDX (INSN_CMPI3), FULL (cmpi3) FAST (cmpi3) },
+  { TYPE (INSN_CMPO), IDX (INSN_CMPO), FULL (cmpo) FAST (cmpo) },
+  { TYPE (INSN_CMPO1), IDX (INSN_CMPO1), FULL (cmpo1) FAST (cmpo1) },
+  { TYPE (INSN_CMPO2), IDX (INSN_CMPO2), FULL (cmpo2) FAST (cmpo2) },
+  { TYPE (INSN_CMPO3), IDX (INSN_CMPO3), FULL (cmpo3) FAST (cmpo3) },
+  { TYPE (INSN_TESTNO_REG), IDX (INSN_TESTNO_REG), FULL (testno_reg) FAST (testno_reg) },
+  { TYPE (INSN_TESTG_REG), IDX (INSN_TESTG_REG), FULL (testg_reg) FAST (testg_reg) },
+  { TYPE (INSN_TESTE_REG), IDX (INSN_TESTE_REG), FULL (teste_reg) FAST (teste_reg) },
+  { TYPE (INSN_TESTGE_REG), IDX (INSN_TESTGE_REG), FULL (testge_reg) FAST (testge_reg) },
+  { TYPE (INSN_TESTL_REG), IDX (INSN_TESTL_REG), FULL (testl_reg) FAST (testl_reg) },
+  { TYPE (INSN_TESTNE_REG), IDX (INSN_TESTNE_REG), FULL (testne_reg) FAST (testne_reg) },
+  { TYPE (INSN_TESTLE_REG), IDX (INSN_TESTLE_REG), FULL (testle_reg) FAST (testle_reg) },
+  { TYPE (INSN_TESTO_REG), IDX (INSN_TESTO_REG), FULL (testo_reg) FAST (testo_reg) },
+  { TYPE (INSN_BNO), IDX (INSN_BNO), FULL (bno) FAST (bno) },
+  { TYPE (INSN_BG), IDX (INSN_BG), FULL (bg) FAST (bg) },
+  { TYPE (INSN_BE), IDX (INSN_BE), FULL (be) FAST (be) },
+  { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) },
+  { TYPE (INSN_BL), IDX (INSN_BL), FULL (bl) FAST (bl) },
+  { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) },
+  { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) },
+  { TYPE (INSN_BO), IDX (INSN_BO), FULL (bo) FAST (bo) },
+  { TYPE (INSN_B), IDX (INSN_B), FULL (b) FAST (b) },
+  { TYPE (INSN_BX_INDIRECT_OFFSET), IDX (INSN_BX_INDIRECT_OFFSET), FULL (bx_indirect_offset) FAST (bx_indirect_offset) },
+  { TYPE (INSN_BX_INDIRECT), IDX (INSN_BX_INDIRECT), FULL (bx_indirect) FAST (bx_indirect) },
+  { TYPE (INSN_BX_INDIRECT_INDEX), IDX (INSN_BX_INDIRECT_INDEX), FULL (bx_indirect_index) FAST (bx_indirect_index) },
+  { TYPE (INSN_BX_DISP), IDX (INSN_BX_DISP), FULL (bx_disp) FAST (bx_disp) },
+  { TYPE (INSN_BX_INDIRECT_DISP), IDX (INSN_BX_INDIRECT_DISP), FULL (bx_indirect_disp) FAST (bx_indirect_disp) },
+  { TYPE (INSN_CALLX_DISP), IDX (INSN_CALLX_DISP), FULL (callx_disp) FAST (callx_disp) },
+  { TYPE (INSN_CALLX_INDIRECT), IDX (INSN_CALLX_INDIRECT), FULL (callx_indirect) FAST (callx_indirect) },
+  { TYPE (INSN_CALLX_INDIRECT_OFFSET), IDX (INSN_CALLX_INDIRECT_OFFSET), FULL (callx_indirect_offset) FAST (callx_indirect_offset) },
+  { TYPE (INSN_RET), IDX (INSN_RET), FULL (ret) FAST (ret) },
+  { TYPE (INSN_CALLS), IDX (INSN_CALLS), FULL (calls) FAST (calls) },
+  { TYPE (INSN_FMARK), IDX (INSN_FMARK), FULL (fmark) FAST (fmark) },
+  { TYPE (INSN_FLUSHREG), IDX (INSN_FLUSHREG), FULL (flushreg) FAST (flushreg) },
+};
+
+static const struct insn_sem i960base_insn_sem_invalid =
+{
+  VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
+};
+
+#undef IDX
+#undef TYPE
+
+/* Initialize an IDESC from the compile-time computable parts.  */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+  id->num = t->index;
+  if ((int) t->type <= 0)
+    id->idata = & cgen_virtual_insn_table[- (int) t->type];
+  else
+    id->idata = & insn_table[t->type];
+  id->attrs = CGEN_INSN_ATTRS (id->idata);
+  /* Oh my god, a magic number.  */
+  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+#if ! WITH_SEM_SWITCH_FULL
+  id->sem_full = t->sem_full;
+#endif
+#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
+  id->sem_fast = t->sem_fast;
+#endif
+#if WITH_PROFILE_MODEL_P
+  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+  {
+    SIM_DESC sd = CPU_STATE (cpu);
+    SIM_ASSERT (t->index == id->timing->num);
+  }
+#endif
+}
+
+/* Initialize the instruction descriptor table.  */
+
+void
+i960base_init_idesc_table (SIM_CPU *cpu)
+{
+  IDESC *id,*tabend;
+  const struct insn_sem *t,*tend;
+  int tabsize = I960BASE_INSN_MAX;
+  IDESC *table = i960base_insn_data;
+
+  memset (table, 0, tabsize * sizeof (IDESC));
+
+  /* First set all entries to the `invalid insn'.  */
+  t = & i960base_insn_sem_invalid;
+  for (id = table, tabend = table + tabsize; id < tabend; ++id)
+    init_idesc (cpu, id, t);
+
+  /* Now fill in the values for the chosen cpu.  */
+  for (t = i960base_insn_sem, tend = t + sizeof (i960base_insn_sem) / sizeof (*t);
+       t != tend; ++t)
+    {
+      init_idesc (cpu, & table[t->index], t);
+    }
+
+  /* Link the IDESC table into the cpu.  */
+  CPU_IDESC (cpu) = table;
+}
+
+/* Enum declaration for all instruction semantic formats.  */
+typedef enum sfmt {
+  FMT_EMPTY, FMT_MULO, FMT_MULO1, FMT_MULO2
+ , FMT_MULO3, FMT_NOTBIT, FMT_NOTBIT1, FMT_NOTBIT2
+ , FMT_NOTBIT3, FMT_NOT, FMT_NOT1, FMT_NOT2
+ , FMT_NOT3, FMT_EMUL, FMT_EMUL1, FMT_EMUL2
+ , FMT_EMUL3, FMT_MOVL, FMT_MOVL1, FMT_MOVT
+ , FMT_MOVT1, FMT_MOVQ, FMT_MOVQ1, FMT_MODPC
+ , FMT_LDA_OFFSET, FMT_LDA_INDIRECT_OFFSET, FMT_LDA_INDIRECT, FMT_LDA_INDIRECT_INDEX
+ , FMT_LDA_DISP, FMT_LDA_INDIRECT_DISP, FMT_LDA_INDEX_DISP, FMT_LDA_INDIRECT_INDEX_DISP
+ , FMT_LD_OFFSET, FMT_LD_INDIRECT_OFFSET, FMT_LD_INDIRECT, FMT_LD_INDIRECT_INDEX
+ , FMT_LD_DISP, FMT_LD_INDIRECT_DISP, FMT_LD_INDEX_DISP, FMT_LD_INDIRECT_INDEX_DISP
+ , FMT_LDOB_OFFSET, FMT_LDOB_INDIRECT_OFFSET, FMT_LDOB_INDIRECT, FMT_LDOB_INDIRECT_INDEX
+ , FMT_LDOB_DISP, FMT_LDOB_INDIRECT_DISP, FMT_LDOB_INDEX_DISP, FMT_LDOB_INDIRECT_INDEX_DISP
+ , FMT_LDOS_OFFSET, FMT_LDOS_INDIRECT_OFFSET, FMT_LDOS_INDIRECT, FMT_LDOS_INDIRECT_INDEX
+ , FMT_LDOS_DISP, FMT_LDOS_INDIRECT_DISP, FMT_LDOS_INDEX_DISP, FMT_LDOS_INDIRECT_INDEX_DISP
+ , FMT_LDIB_OFFSET, FMT_LDIB_INDIRECT_OFFSET, FMT_LDIB_INDIRECT, FMT_LDIB_INDIRECT_INDEX
+ , FMT_LDIB_DISP, FMT_LDIB_INDIRECT_DISP, FMT_LDIB_INDEX_DISP, FMT_LDIB_INDIRECT_INDEX_DISP
+ , FMT_LDIS_OFFSET, FMT_LDIS_INDIRECT_OFFSET, FMT_LDIS_INDIRECT, FMT_LDIS_INDIRECT_INDEX
+ , FMT_LDIS_DISP, FMT_LDIS_INDIRECT_DISP, FMT_LDIS_INDEX_DISP, FMT_LDIS_INDIRECT_INDEX_DISP
+ , FMT_LDL_OFFSET, FMT_LDL_INDIRECT_OFFSET, FMT_LDL_INDIRECT, FMT_LDL_INDIRECT_INDEX
+ , FMT_LDL_DISP, FMT_LDL_INDIRECT_DISP, FMT_LDL_INDEX_DISP, FMT_LDL_INDIRECT_INDEX_DISP
+ , FMT_LDT_OFFSET, FMT_LDT_INDIRECT_OFFSET, FMT_LDT_INDIRECT, FMT_LDT_INDIRECT_INDEX
+ , FMT_LDT_DISP, FMT_LDT_INDIRECT_DISP, FMT_LDT_INDEX_DISP, FMT_LDT_INDIRECT_INDEX_DISP
+ , FMT_LDQ_OFFSET, FMT_LDQ_INDIRECT_OFFSET, FMT_LDQ_INDIRECT, FMT_LDQ_INDIRECT_INDEX
+ , FMT_LDQ_DISP, FMT_LDQ_INDIRECT_DISP, FMT_LDQ_INDEX_DISP, FMT_LDQ_INDIRECT_INDEX_DISP
+ , FMT_ST_OFFSET, FMT_ST_INDIRECT_OFFSET, FMT_ST_INDIRECT, FMT_ST_INDIRECT_INDEX
+ , FMT_ST_DISP, FMT_ST_INDIRECT_DISP, FMT_ST_INDEX_DISP, FMT_ST_INDIRECT_INDEX_DISP
+ , FMT_STOB_OFFSET, FMT_STOB_INDIRECT_OFFSET, FMT_STOB_INDIRECT, FMT_STOB_INDIRECT_INDEX
+ , FMT_STOB_DISP, FMT_STOB_INDIRECT_DISP, FMT_STOB_INDEX_DISP, FMT_STOB_INDIRECT_INDEX_DISP
+ , FMT_STOS_OFFSET, FMT_STOS_INDIRECT_OFFSET, FMT_STOS_INDIRECT, FMT_STOS_INDIRECT_INDEX
+ , FMT_STOS_DISP, FMT_STOS_INDIRECT_DISP, FMT_STOS_INDEX_DISP, FMT_STOS_INDIRECT_INDEX_DISP
+ , FMT_STL_OFFSET, FMT_STL_INDIRECT_OFFSET, FMT_STL_INDIRECT, FMT_STL_INDIRECT_INDEX
+ , FMT_STL_DISP, FMT_STL_INDIRECT_DISP, FMT_STL_INDEX_DISP, FMT_STL_INDIRECT_INDEX_DISP
+ , FMT_STT_OFFSET, FMT_STT_INDIRECT_OFFSET, FMT_STT_INDIRECT, FMT_STT_INDIRECT_INDEX
+ , FMT_STT_DISP, FMT_STT_INDIRECT_DISP, FMT_STT_INDEX_DISP, FMT_STT_INDIRECT_INDEX_DISP
+ , FMT_STQ_OFFSET, FMT_STQ_INDIRECT_OFFSET, FMT_STQ_INDIRECT, FMT_STQ_INDIRECT_INDEX
+ , FMT_STQ_DISP, FMT_STQ_INDIRECT_DISP, FMT_STQ_INDEX_DISP, FMT_STQ_INDIRECT_INDEX_DISP
+ , FMT_CMPOBE_REG, FMT_CMPOBE_LIT, FMT_CMPOBL_REG, FMT_CMPOBL_LIT
+ , FMT_BBC_REG, FMT_BBC_LIT, FMT_CMPI, FMT_CMPI1
+ , FMT_CMPI2, FMT_CMPI3, FMT_CMPO, FMT_CMPO1
+ , FMT_CMPO2, FMT_CMPO3, FMT_TESTNO_REG, FMT_BNO
+ , FMT_B, FMT_BX_INDIRECT_OFFSET, FMT_BX_INDIRECT, FMT_BX_INDIRECT_INDEX
+ , FMT_BX_DISP, FMT_BX_INDIRECT_DISP, FMT_CALLX_DISP, FMT_CALLX_INDIRECT
+ , FMT_CALLX_INDIRECT_OFFSET, FMT_RET, FMT_CALLS, FMT_FMARK
+ , FMT_FLUSHREG
+} SFMT;
+
+/* The decoder uses this to record insns and direct extraction handling.  */
+
+typedef struct {
+  const IDESC *idesc;
+#ifdef __GNUC__
+  void *sfmt;
+#else
+  enum sfmt sfmt;
+#endif
+} DECODE_DESC;
+
+/* Macro to go from decode phase to extraction phase.  */
+
+#ifdef __GNUC__
+#define GOTO_EXTRACT(id) goto *(id)->sfmt
+#else
+#define GOTO_EXTRACT(id) goto extract
+#endif
+
+/* The decoder needs a slightly different computed goto switch control.  */
+#ifdef __GNUC__
+#define DECODE_SWITCH(N, X) goto *labels_##N[X];
+#else
+#define DECODE_SWITCH(N, X) switch (X)
+#endif
+
+/* Given an instruction, return a pointer to its IDESC entry.  */
+
+const IDESC *
+i960base_decode (SIM_CPU *current_cpu, IADDR pc,
+              CGEN_INSN_INT base_insn,
+              ARGBUF *abuf)
+{
+  /* Result of decoder, used by extractor.  */
+  const DECODE_DESC *idecode;
+
+  /* First decode the instruction.  */
+
+  {
+#define I(insn) & i960base_insn_data[CONCAT2 (I960BASE_,insn)]
+#ifdef __GNUC__
+#define E(fmt) && case_ex_##fmt
+#else
+#define E(fmt) fmt
+#endif
+    CGEN_INSN_INT insn = base_insn;
+    static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
+
+    {
+#ifdef __GNUC__
+      static const void *labels_0[256] = {
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_48, && case_0_49, && case_0_50, && case_0_51, 
+        && case_0_52, && case_0_53, && case_0_54, && case_0_55, 
+        && default_0, && case_0_57, && case_0_58, && case_0_59, 
+        && case_0_60, && case_0_61, && case_0_62, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_88, && case_0_89, && case_0_90, && default_0, 
+        && case_0_92, && case_0_93, && case_0_94, && case_0_95, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && case_0_102, && case_0_103, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_112, && default_0, && default_0, && default_0, 
+        && case_0_116, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_128, && default_0, && case_0_130, && default_0, 
+        && case_0_132, && default_0, && case_0_134, && default_0, 
+        && case_0_136, && default_0, && case_0_138, && default_0, 
+        && case_0_140, && default_0, && default_0, && default_0, 
+        && case_0_144, && default_0, && case_0_146, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_152, && default_0, && case_0_154, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_160, && default_0, && case_0_162, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_176, && default_0, && case_0_178, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_192, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_200, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+      };
+#endif
+      static const DECODE_DESC insns[256] = {
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_B), E (FMT_B) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_RET), E (FMT_RET) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_BNO), E (FMT_BNO) }, { I (INSN_BG), E (FMT_BNO) }, 
+        { I (INSN_BE), E (FMT_BNO) }, { I (INSN_BGE), E (FMT_BNO) }, 
+        { I (INSN_BL), E (FMT_BNO) }, { I (INSN_BNE), E (FMT_BNO) }, 
+        { I (INSN_BLE), E (FMT_BNO) }, { I (INSN_BO), E (FMT_BNO) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_TESTNO_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTG_REG), E (FMT_TESTNO_REG) }, 
+        { I (INSN_TESTE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTGE_REG), E (FMT_TESTNO_REG) }, 
+        { I (INSN_TESTL_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTNE_REG), E (FMT_TESTNO_REG) }, 
+        { I (INSN_TESTLE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTO_REG), E (FMT_TESTNO_REG) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { 0 }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_MODAC), E (FMT_MODPC) }, { I (INSN_MODPC), E (FMT_MODPC) }, 
+        { 0 }, { 0 }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+      };
+      unsigned int val;
+      val = (((insn >> 24) & (255 << 0)));
+      DECODE_SWITCH (0, val)
+        {
+        CASE (0, 48) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_BBC_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BBC_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 49) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPOBG_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPOBG_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 50) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPOBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPOBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 51) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPOBGE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPOBGE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 52) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPOBL_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPOBL_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 53) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPOBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPOBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 54) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPOBLE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPOBLE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 55) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_BBS_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BBS_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 57) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPIBG_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPIBG_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 58) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPIBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPIBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 59) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPIBGE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPIBGE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 60) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPIBL_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPIBL_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 61) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPIBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPIBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 62) :
+          {
+            static const DECODE_DESC insns[8] = {
+              { I (INSN_CMPIBLE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CMPIBLE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 88) :
+          {
+#ifdef __GNUC__
+            static const void *labels_0_88[16] = {
+              && case_0_88_0, && case_0_88_1, && case_0_88_2, && case_0_88_3, 
+              && case_0_88_4, && case_0_88_5, && case_0_88_6, && case_0_88_7, 
+              && default_0_88, && default_0_88, && default_0_88, && default_0_88, 
+              && default_0_88, && default_0_88, && default_0_88, && default_0_88, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { 0 }, { 0 }, 
+              { 0 }, { 0 }, 
+              { 0 }, { 0 }, 
+              { 0 }, { 0 }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val;
+            val = (((insn >> 10) & (15 << 0)));
+            DECODE_SWITCH (0_88, val)
+              {
+              CASE (0_88, 0) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOTBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_AND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_ANDNOT), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SETBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOTAND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_XOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_OR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_88, 1) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOT), E (FMT_NOT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CLRBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_88, 2) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOTBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_AND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_ANDNOT1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SETBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOTAND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_XOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_OR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_88, 3) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOT1), E (FMT_NOT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CLRBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_88, 4) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOTBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_AND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_ANDNOT2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SETBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOTAND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_XOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_OR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_88, 5) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOT2), E (FMT_NOT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CLRBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_88, 6) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOTBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_AND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_ANDNOT3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SETBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOTAND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_XOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_OR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_88, 7) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_NOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_NOT3), E (FMT_NOT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CLRBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              DEFAULT (0_88) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
+              }
+            ENDSWITCH (0_88)
+          }
+        CASE (0, 89) :
+          {
+#ifdef __GNUC__
+            static const void *labels_0_89[16] = {
+              && case_0_89_0, && case_0_89_1, && case_0_89_2, && case_0_89_3, 
+              && case_0_89_4, && case_0_89_5, && case_0_89_6, && case_0_89_7, 
+              && default_0_89, && default_0_89, && default_0_89, && default_0_89, 
+              && default_0_89, && default_0_89, && default_0_89, && default_0_89, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { 0 }, { 0 }, 
+              { 0 }, { 0 }, 
+              { 0 }, { 0 }, 
+              { 0 }, { 0 }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val;
+            val = (((insn >> 10) & (15 << 0)));
+            DECODE_SWITCH (0_89, val)
+              {
+              CASE (0_89, 0) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_ADDO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SUBO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_89, 1) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_SHRO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHRI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_89, 2) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_ADDO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SUBO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_89, 3) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_SHRO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHRI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_89, 4) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_ADDO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SUBO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_89, 5) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_SHRO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHRI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_89, 6) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_ADDO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SUBO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_89, 7) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_SHRO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHRI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SHLI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              DEFAULT (0_89) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
+              }
+            ENDSWITCH (0_89)
+          }
+        CASE (0, 90) :
+          {
+#ifdef __GNUC__
+            static const void *labels_0_90[16] = {
+              && default_0_90, && default_0_90, && default_0_90, && default_0_90, 
+              && default_0_90, && default_0_90, && default_0_90, && default_0_90, 
+              && case_0_90_8, && default_0_90, && case_0_90_10, && default_0_90, 
+              && case_0_90_12, && default_0_90, && case_0_90_14, && default_0_90, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val;
+            val = (((insn >> 10) & (15 << 0)));
+            DECODE_SWITCH (0_90, val)
+              {
+              CASE (0_90, 8) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_CMPO), E (FMT_CMPO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_90, 10) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_CMPO1), E (FMT_CMPO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CMPI1), E (FMT_CMPI1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_90, 12) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_CMPO2), E (FMT_CMPO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CMPI2), E (FMT_CMPI2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_90, 14) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_CMPO3), E (FMT_CMPO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_CMPI3), E (FMT_CMPI3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              DEFAULT (0_90) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
+              }
+            ENDSWITCH (0_90)
+          }
+        CASE (0, 92) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV), E (FMT_NOT2) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV1), E (FMT_NOT3) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 93) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL), E (FMT_MOVL) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL1), E (FMT_MOVL1) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 94) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT), E (FMT_MOVT) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT1), E (FMT_MOVT1) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 95) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ), E (FMT_MOVQ) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ1), E (FMT_MOVQ1) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 102) :
+          {
+#ifdef __GNUC__
+            static const void *labels_0_102[16] = {
+              && default_0_102, && default_0_102, && default_0_102, && default_0_102, 
+              && default_0_102, && default_0_102, && default_0_102, && default_0_102, 
+              && default_0_102, && default_0_102, && default_0_102, && default_0_102, 
+              && default_0_102, && default_0_102, && default_0_102, && case_0_102_15, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CALLS), E (FMT_CALLS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+            };
+            unsigned int val;
+            val = (((insn >> 10) & (15 << 0)));
+            DECODE_SWITCH (0_102, val)
+              {
+              CASE (0_102, 15) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_FMARK), E (FMT_FMARK) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_FLUSHREG), E (FMT_FLUSHREG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              DEFAULT (0_102) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
+              }
+            ENDSWITCH (0_102)
+          }
+        CASE (0, 103) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_EMUL), E (FMT_EMUL) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_EMUL1), E (FMT_EMUL1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_EMUL2), E (FMT_EMUL2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_EMUL3), E (FMT_EMUL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 112) :
+          {
+#ifdef __GNUC__
+            static const void *labels_0_112[16] = {
+              && default_0_112, && case_0_112_1, && default_0_112, && case_0_112_3, 
+              && default_0_112, && case_0_112_5, && default_0_112, && case_0_112_7, 
+              && default_0_112, && default_0_112, && default_0_112, && default_0_112, 
+              && default_0_112, && default_0_112, && default_0_112, && default_0_112, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_MULO), E (FMT_MULO) }, { 0 }, 
+              { I (INSN_MULO1), E (FMT_MULO1) }, { 0 }, 
+              { I (INSN_MULO2), E (FMT_MULO2) }, { 0 }, 
+              { I (INSN_MULO3), E (FMT_MULO3) }, { 0 }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val;
+            val = (((insn >> 10) & (15 << 0)));
+            DECODE_SWITCH (0_112, val)
+              {
+              CASE (0_112, 1) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_112, 3) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_112, 5) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_112, 7) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              DEFAULT (0_112) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
+              }
+            ENDSWITCH (0_112)
+          }
+        CASE (0, 116) :
+          {
+#ifdef __GNUC__
+            static const void *labels_0_116[16] = {
+              && default_0_116, && case_0_116_1, && default_0_116, && case_0_116_3, 
+              && default_0_116, && case_0_116_5, && default_0_116, && case_0_116_7, 
+              && default_0_116, && default_0_116, && default_0_116, && default_0_116, 
+              && default_0_116, && default_0_116, && default_0_116, && default_0_116, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val;
+            val = (((insn >> 10) & (15 << 0)));
+            DECODE_SWITCH (0_116, val)
+              {
+              CASE (0_116, 1) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_116, 3) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_116, 5) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              CASE (0_116, 7) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_REMI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_DIVI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 6) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              DEFAULT (0_116) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
+              }
+            ENDSWITCH (0_116)
+          }
+        CASE (0, 128) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, 
+              { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, 
+              { I (INSN_LDOB_INDIRECT), E (FMT_LDOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOB_INDIRECT_INDEX), E (FMT_LDOB_INDIRECT_INDEX) }, 
+              { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, 
+              { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, 
+              { I (INSN_LDOB_DISP), E (FMT_LDOB_DISP) }, { I (INSN_LDOB_INDIRECT_DISP), E (FMT_LDOB_INDIRECT_DISP) }, 
+              { I (INSN_LDOB_INDEX_DISP), E (FMT_LDOB_INDEX_DISP) }, { I (INSN_LDOB_INDIRECT_INDEX_DISP), E (FMT_LDOB_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 130) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, 
+              { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, 
+              { I (INSN_STOB_INDIRECT), E (FMT_STOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOB_INDIRECT_INDEX), E (FMT_STOB_INDIRECT_INDEX) }, 
+              { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, 
+              { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, 
+              { I (INSN_STOB_DISP), E (FMT_STOB_DISP) }, { I (INSN_STOB_INDIRECT_DISP), E (FMT_STOB_INDIRECT_DISP) }, 
+              { I (INSN_STOB_INDEX_DISP), E (FMT_STOB_INDEX_DISP) }, { I (INSN_STOB_INDIRECT_INDEX_DISP), E (FMT_STOB_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 132) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BX_INDIRECT), E (FMT_BX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_BX_INDIRECT_INDEX), E (FMT_BX_INDIRECT_INDEX) }, 
+              { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, 
+              { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, 
+              { I (INSN_BX_DISP), E (FMT_BX_DISP) }, { I (INSN_BX_INDIRECT_DISP), E (FMT_BX_INDIRECT_DISP) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 134) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CALLX_INDIRECT), E (FMT_CALLX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, 
+              { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, 
+              { I (INSN_CALLX_DISP), E (FMT_CALLX_DISP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 136) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, 
+              { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, 
+              { I (INSN_LDOS_INDIRECT), E (FMT_LDOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOS_INDIRECT_INDEX), E (FMT_LDOS_INDIRECT_INDEX) }, 
+              { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, 
+              { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, 
+              { I (INSN_LDOS_DISP), E (FMT_LDOS_DISP) }, { I (INSN_LDOS_INDIRECT_DISP), E (FMT_LDOS_INDIRECT_DISP) }, 
+              { I (INSN_LDOS_INDEX_DISP), E (FMT_LDOS_INDEX_DISP) }, { I (INSN_LDOS_INDIRECT_INDEX_DISP), E (FMT_LDOS_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 138) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, 
+              { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, 
+              { I (INSN_STOS_INDIRECT), E (FMT_STOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOS_INDIRECT_INDEX), E (FMT_STOS_INDIRECT_INDEX) }, 
+              { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, 
+              { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, 
+              { I (INSN_STOS_DISP), E (FMT_STOS_DISP) }, { I (INSN_STOS_INDIRECT_DISP), E (FMT_STOS_INDIRECT_DISP) }, 
+              { I (INSN_STOS_INDEX_DISP), E (FMT_STOS_INDEX_DISP) }, { I (INSN_STOS_INDIRECT_INDEX_DISP), E (FMT_STOS_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 140) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, 
+              { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, 
+              { I (INSN_LDA_INDIRECT), E (FMT_LDA_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDA_INDIRECT_INDEX), E (FMT_LDA_INDIRECT_INDEX) }, 
+              { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, 
+              { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, 
+              { I (INSN_LDA_DISP), E (FMT_LDA_DISP) }, { I (INSN_LDA_INDIRECT_DISP), E (FMT_LDA_INDIRECT_DISP) }, 
+              { I (INSN_LDA_INDEX_DISP), E (FMT_LDA_INDEX_DISP) }, { I (INSN_LDA_INDIRECT_INDEX_DISP), E (FMT_LDA_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 144) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, 
+              { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, 
+              { I (INSN_LD_INDIRECT), E (FMT_LD_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LD_INDIRECT_INDEX), E (FMT_LD_INDIRECT_INDEX) }, 
+              { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, 
+              { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, 
+              { I (INSN_LD_DISP), E (FMT_LD_DISP) }, { I (INSN_LD_INDIRECT_DISP), E (FMT_LD_INDIRECT_DISP) }, 
+              { I (INSN_LD_INDEX_DISP), E (FMT_LD_INDEX_DISP) }, { I (INSN_LD_INDIRECT_INDEX_DISP), E (FMT_LD_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 146) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, 
+              { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, 
+              { I (INSN_ST_INDIRECT), E (FMT_ST_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_ST_INDIRECT_INDEX), E (FMT_ST_INDIRECT_INDEX) }, 
+              { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, 
+              { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, 
+              { I (INSN_ST_DISP), E (FMT_ST_DISP) }, { I (INSN_ST_INDIRECT_DISP), E (FMT_ST_INDIRECT_DISP) }, 
+              { I (INSN_ST_INDEX_DISP), E (FMT_ST_INDEX_DISP) }, { I (INSN_ST_INDIRECT_INDEX_DISP), E (FMT_ST_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 152) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, 
+              { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, 
+              { I (INSN_LDL_INDIRECT), E (FMT_LDL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDL_INDIRECT_INDEX), E (FMT_LDL_INDIRECT_INDEX) }, 
+              { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, 
+              { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, 
+              { I (INSN_LDL_DISP), E (FMT_LDL_DISP) }, { I (INSN_LDL_INDIRECT_DISP), E (FMT_LDL_INDIRECT_DISP) }, 
+              { I (INSN_LDL_INDEX_DISP), E (FMT_LDL_INDEX_DISP) }, { I (INSN_LDL_INDIRECT_INDEX_DISP), E (FMT_LDL_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 154) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, 
+              { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, 
+              { I (INSN_STL_INDIRECT), E (FMT_STL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STL_INDIRECT_INDEX), E (FMT_STL_INDIRECT_INDEX) }, 
+              { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, 
+              { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, 
+              { I (INSN_STL_DISP), E (FMT_STL_DISP) }, { I (INSN_STL_INDIRECT_DISP), E (FMT_STL_INDIRECT_DISP) }, 
+              { I (INSN_STL_INDEX_DISP), E (FMT_STL_INDEX_DISP) }, { I (INSN_STL_INDIRECT_INDEX_DISP), E (FMT_STL_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 160) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, 
+              { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, 
+              { I (INSN_LDT_INDIRECT), E (FMT_LDT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDT_INDIRECT_INDEX), E (FMT_LDT_INDIRECT_INDEX) }, 
+              { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, 
+              { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, 
+              { I (INSN_LDT_DISP), E (FMT_LDT_DISP) }, { I (INSN_LDT_INDIRECT_DISP), E (FMT_LDT_INDIRECT_DISP) }, 
+              { I (INSN_LDT_INDEX_DISP), E (FMT_LDT_INDEX_DISP) }, { I (INSN_LDT_INDIRECT_INDEX_DISP), E (FMT_LDT_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 162) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, 
+              { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, 
+              { I (INSN_STT_INDIRECT), E (FMT_STT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STT_INDIRECT_INDEX), E (FMT_STT_INDIRECT_INDEX) }, 
+              { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, 
+              { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, 
+              { I (INSN_STT_DISP), E (FMT_STT_DISP) }, { I (INSN_STT_INDIRECT_DISP), E (FMT_STT_INDIRECT_DISP) }, 
+              { I (INSN_STT_INDEX_DISP), E (FMT_STT_INDEX_DISP) }, { I (INSN_STT_INDIRECT_INDEX_DISP), E (FMT_STT_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 176) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, 
+              { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, 
+              { I (INSN_LDQ_INDIRECT), E (FMT_LDQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDQ_INDIRECT_INDEX), E (FMT_LDQ_INDIRECT_INDEX) }, 
+              { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, 
+              { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, 
+              { I (INSN_LDQ_DISP), E (FMT_LDQ_DISP) }, { I (INSN_LDQ_INDIRECT_DISP), E (FMT_LDQ_INDIRECT_DISP) }, 
+              { I (INSN_LDQ_INDEX_DISP), E (FMT_LDQ_INDEX_DISP) }, { I (INSN_LDQ_INDIRECT_INDEX_DISP), E (FMT_LDQ_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 178) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, 
+              { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, 
+              { I (INSN_STQ_INDIRECT), E (FMT_STQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STQ_INDIRECT_INDEX), E (FMT_STQ_INDIRECT_INDEX) }, 
+              { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, 
+              { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, 
+              { I (INSN_STQ_DISP), E (FMT_STQ_DISP) }, { I (INSN_STQ_INDIRECT_DISP), E (FMT_STQ_INDIRECT_DISP) }, 
+              { I (INSN_STQ_INDEX_DISP), E (FMT_STQ_INDEX_DISP) }, { I (INSN_STQ_INDIRECT_INDEX_DISP), E (FMT_STQ_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 192) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, 
+              { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, 
+              { I (INSN_LDIB_INDIRECT), E (FMT_LDIB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIB_INDIRECT_INDEX), E (FMT_LDIB_INDIRECT_INDEX) }, 
+              { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, 
+              { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, 
+              { I (INSN_LDIB_DISP), E (FMT_LDIB_DISP) }, { I (INSN_LDIB_INDIRECT_DISP), E (FMT_LDIB_INDIRECT_DISP) }, 
+              { I (INSN_LDIB_INDEX_DISP), E (FMT_LDIB_INDEX_DISP) }, { I (INSN_LDIB_INDIRECT_INDEX_DISP), E (FMT_LDIB_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 200) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, 
+              { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, 
+              { I (INSN_LDIS_INDIRECT), E (FMT_LDIS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIS_INDIRECT_INDEX), E (FMT_LDIS_INDIRECT_INDEX) }, 
+              { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, 
+              { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, 
+              { I (INSN_LDIS_DISP), E (FMT_LDIS_DISP) }, { I (INSN_LDIS_INDIRECT_DISP), E (FMT_LDIS_INDIRECT_DISP) }, 
+              { I (INSN_LDIS_INDEX_DISP), E (FMT_LDIS_INDEX_DISP) }, { I (INSN_LDIS_INDIRECT_INDEX_DISP), E (FMT_LDIS_INDIRECT_INDEX_DISP) }, 
+            };
+            unsigned int val = (((insn >> 10) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        DEFAULT (0) :
+          idecode = &insns[val];
+          GOTO_EXTRACT (idecode);
+        }
+      ENDSWITCH (0)
+    }
+#undef I
+#undef E
+  }
+
+  /* The instruction has been decoded, now extract the fields.  */
+
+ extract:
+  {
+#ifndef __GNUC__
+    switch (idecode->sfmt)
+#endif
+      {
+
+  CASE (ex, FMT_EMPTY) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+  EXTRACT_IFMT_EMPTY_VARS /* */
+
+  EXTRACT_IFMT_EMPTY_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULO) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mulo.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (in_src2) = f_src2;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULO1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_src2;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULO2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src2) = f_src2;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULO3) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (f_src2) = f_src2;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOTBIT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_notbit.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (in_src2) = f_src2;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOTBIT1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_src2;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOTBIT2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src2) = f_src2;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOTBIT3) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (f_src2) = f_src2;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_not.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not", "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOT1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_not1.f
+  EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not1", "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOT2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_not2.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not2", "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOT3) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_not3.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not3", "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EMUL) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_emul.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul", "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (in_src2) = f_src2;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EMUL1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_emul1.f
+  EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_src1) = f_src1;
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_src2;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EMUL2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_emul2.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_src2) = f_src2;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul2", "f_srcdst 0x%x", 'x', f_srcdst, "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_EMUL3) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_emul3.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_src1) = f_src1;
+  FLD (f_src2) = f_src2;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul3", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVL) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movl.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movl", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1));
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVL1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movl1.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_src1) = f_src1;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movl1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movt.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movt", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1));
+      FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2));
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVT1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movt1.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_src1) = f_src1;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movt1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVQ) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movq.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movq", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1));
+      FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2));
+      FLD (in_h_gr_add__VM_index_of_src1_const__WI_3) = ((FLD (f_src1)) + (3));
+      FLD (in_src1) = f_src1;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MOVQ1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_movq1.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_src1) = f_src1;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movq1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MODPC) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_modpc.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_modpc", "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_src2;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDA_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOB_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDOS_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIB_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDIS_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDL_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDT_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDQ_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (out_dst) = f_srcdst;
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_indirect_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_indirect.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_indirect_index.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_indirect_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_indirect.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_indirect_index.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOB_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_indirect.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_indirect_index.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STOS_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_indirect.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_indirect_index.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STL_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_indirect.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_indirect_index.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STT_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f
+  EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_ST_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_indirect.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_indirect_index.f
+  EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STQ_INDIRECT_INDEX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f
+  EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_ST_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_srcdst) = f_srcdst;
+  FLD (f_optdisp) = f_optdisp;
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  FLD (i_st_src) = & CPU (h_gr)[f_srcdst];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+      FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+      FLD (in_index) = f_index;
+      FLD (in_st_src) = f_srcdst;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPOBE_REG) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
+
+  EXTRACT_IFMT_CMPOBE_REG_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_br_disp) = f_br_disp;
+  FLD (i_br_src1) = & CPU (h_gr)[f_br_src1];
+  FLD (i_br_src2) = & CPU (h_gr)[f_br_src2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobe_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_br_src1) = f_br_src1;
+      FLD (in_br_src2) = f_br_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPOBE_LIT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
+
+  EXTRACT_IFMT_CMPOBE_LIT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_br_src1) = f_br_src1;
+  FLD (i_br_disp) = f_br_disp;
+  FLD (i_br_src2) = & CPU (h_gr)[f_br_src2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobe_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_br_src2) = f_br_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPOBL_REG) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
+
+  EXTRACT_IFMT_CMPOBE_REG_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_br_disp) = f_br_disp;
+  FLD (i_br_src1) = & CPU (h_gr)[f_br_src1];
+  FLD (i_br_src2) = & CPU (h_gr)[f_br_src2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobl_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_br_src1) = f_br_src1;
+      FLD (in_br_src2) = f_br_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPOBL_LIT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
+
+  EXTRACT_IFMT_CMPOBE_LIT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_br_src1) = f_br_src1;
+  FLD (i_br_disp) = f_br_disp;
+  FLD (i_br_src2) = & CPU (h_gr)[f_br_src2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobl_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_br_src2) = f_br_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BBC_REG) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
+
+  EXTRACT_IFMT_CMPOBE_REG_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_br_disp) = f_br_disp;
+  FLD (i_br_src1) = & CPU (h_gr)[f_br_src1];
+  FLD (i_br_src2) = & CPU (h_gr)[f_br_src2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bbc_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_br_src1) = f_br_src1;
+      FLD (in_br_src2) = f_br_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BBC_LIT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
+
+  EXTRACT_IFMT_CMPOBE_LIT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_br_src1) = f_br_src1;
+  FLD (i_br_disp) = f_br_disp;
+  FLD (i_br_src2) = & CPU (h_gr)[f_br_src2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bbc_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_br_src2) = f_br_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPI) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (in_src2) = f_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPI1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpi1.f
+  EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPI2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpi2.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src2) = f_src2;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPI3) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpi3.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (f_src2) = f_src2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPO) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpo.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+      FLD (in_src2) = f_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPO1) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpo1.f
+  EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (i_src2) = & CPU (h_gr)[f_src2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_src2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPO2) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpo2.f
+  EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO2_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src2) = f_src2;
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPO3) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_cmpo3.f
+  EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_src1) = f_src1;
+  FLD (f_src2) = f_src2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_TESTNO_REG) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
+
+  EXTRACT_IFMT_CMPOBE_REG_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_br_src1) = & CPU (h_gr)[f_br_src1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_testno_reg", "br_src1 0x%x", 'x', f_br_src1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_br_src1) = f_br_src1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BNO) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */
+
+  EXTRACT_IFMT_BNO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_ctrl_disp) = f_ctrl_disp;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bno", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_B) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_b.f
+  EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */
+
+  EXTRACT_IFMT_BNO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_ctrl_disp) = f_ctrl_disp;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_b", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BX_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BX_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BX_INDIRECT_INDEX) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_scale) = f_scale;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  FLD (i_index) = & CPU (h_gr)[f_index];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_index) = f_index;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BX_INDIRECT_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CALLX_DISP) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f
+  EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_DISP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_optdisp) = f_optdisp;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_0) = 0;
+      FLD (in_h_gr_1) = 1;
+      FLD (in_h_gr_10) = 10;
+      FLD (in_h_gr_11) = 11;
+      FLD (in_h_gr_12) = 12;
+      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_2) = 2;
+      FLD (in_h_gr_3) = 3;
+      FLD (in_h_gr_31) = 31;
+      FLD (in_h_gr_4) = 4;
+      FLD (in_h_gr_5) = 5;
+      FLD (in_h_gr_6) = 6;
+      FLD (in_h_gr_7) = 7;
+      FLD (in_h_gr_8) = 8;
+      FLD (in_h_gr_9) = 9;
+      FLD (out_h_gr_0) = 0;
+      FLD (out_h_gr_1) = 1;
+      FLD (out_h_gr_10) = 10;
+      FLD (out_h_gr_11) = 11;
+      FLD (out_h_gr_12) = 12;
+      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_15) = 15;
+      FLD (out_h_gr_2) = 2;
+      FLD (out_h_gr_3) = 3;
+      FLD (out_h_gr_31) = 31;
+      FLD (out_h_gr_4) = 4;
+      FLD (out_h_gr_5) = 5;
+      FLD (out_h_gr_6) = 6;
+      FLD (out_h_gr_7) = 7;
+      FLD (out_h_gr_8) = 8;
+      FLD (out_h_gr_9) = 9;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CALLX_INDIRECT) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f
+  EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
+
+  EXTRACT_IFMT_LDA_INDIRECT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_0) = 0;
+      FLD (in_h_gr_1) = 1;
+      FLD (in_h_gr_10) = 10;
+      FLD (in_h_gr_11) = 11;
+      FLD (in_h_gr_12) = 12;
+      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_2) = 2;
+      FLD (in_h_gr_3) = 3;
+      FLD (in_h_gr_31) = 31;
+      FLD (in_h_gr_4) = 4;
+      FLD (in_h_gr_5) = 5;
+      FLD (in_h_gr_6) = 6;
+      FLD (in_h_gr_7) = 7;
+      FLD (in_h_gr_8) = 8;
+      FLD (in_h_gr_9) = 9;
+      FLD (out_h_gr_0) = 0;
+      FLD (out_h_gr_1) = 1;
+      FLD (out_h_gr_10) = 10;
+      FLD (out_h_gr_11) = 11;
+      FLD (out_h_gr_12) = 12;
+      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_15) = 15;
+      FLD (out_h_gr_2) = 2;
+      FLD (out_h_gr_3) = 3;
+      FLD (out_h_gr_31) = 31;
+      FLD (out_h_gr_4) = 4;
+      FLD (out_h_gr_5) = 5;
+      FLD (out_h_gr_6) = 6;
+      FLD (out_h_gr_7) = 7;
+      FLD (out_h_gr_8) = 8;
+      FLD (out_h_gr_9) = 9;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CALLX_INDIRECT_OFFSET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f
+  EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
+
+  EXTRACT_IFMT_LDA_OFFSET_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_offset) = f_offset;
+  FLD (i_abase) = & CPU (h_gr)[f_abase];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_abase) = f_abase;
+      FLD (in_h_gr_0) = 0;
+      FLD (in_h_gr_1) = 1;
+      FLD (in_h_gr_10) = 10;
+      FLD (in_h_gr_11) = 11;
+      FLD (in_h_gr_12) = 12;
+      FLD (in_h_gr_13) = 13;
+      FLD (in_h_gr_14) = 14;
+      FLD (in_h_gr_15) = 15;
+      FLD (in_h_gr_2) = 2;
+      FLD (in_h_gr_3) = 3;
+      FLD (in_h_gr_31) = 31;
+      FLD (in_h_gr_4) = 4;
+      FLD (in_h_gr_5) = 5;
+      FLD (in_h_gr_6) = 6;
+      FLD (in_h_gr_7) = 7;
+      FLD (in_h_gr_8) = 8;
+      FLD (in_h_gr_9) = 9;
+      FLD (out_h_gr_0) = 0;
+      FLD (out_h_gr_1) = 1;
+      FLD (out_h_gr_10) = 10;
+      FLD (out_h_gr_11) = 11;
+      FLD (out_h_gr_12) = 12;
+      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_15) = 15;
+      FLD (out_h_gr_2) = 2;
+      FLD (out_h_gr_3) = 3;
+      FLD (out_h_gr_31) = 31;
+      FLD (out_h_gr_4) = 4;
+      FLD (out_h_gr_5) = 5;
+      FLD (out_h_gr_6) = 6;
+      FLD (out_h_gr_7) = 7;
+      FLD (out_h_gr_8) = 8;
+      FLD (out_h_gr_9) = 9;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_RET) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */
+
+  EXTRACT_IFMT_BNO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ret", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_gr_0) = 0;
+      FLD (in_h_gr_2) = 2;
+      FLD (in_h_gr_31) = 31;
+      FLD (out_h_gr_0) = 0;
+      FLD (out_h_gr_1) = 1;
+      FLD (out_h_gr_10) = 10;
+      FLD (out_h_gr_11) = 11;
+      FLD (out_h_gr_12) = 12;
+      FLD (out_h_gr_13) = 13;
+      FLD (out_h_gr_14) = 14;
+      FLD (out_h_gr_15) = 15;
+      FLD (out_h_gr_2) = 2;
+      FLD (out_h_gr_3) = 3;
+      FLD (out_h_gr_31) = 31;
+      FLD (out_h_gr_4) = 4;
+      FLD (out_h_gr_5) = 5;
+      FLD (out_h_gr_6) = 6;
+      FLD (out_h_gr_7) = 7;
+      FLD (out_h_gr_8) = 8;
+      FLD (out_h_gr_9) = 9;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CALLS) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_calls.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_src1];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_calls", "src1 0x%x", 'x', f_src1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_src1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_FMARK) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_fmark", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_FLUSHREG) :
+  {
+    CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_flushreg.f
+  EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+  EXTRACT_IFMT_MULO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_flushreg", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+
+      }
+    ENDSWITCH (ex)
+
+  }
+
+  return idecode->idesc;
+}
diff --git a/sim/i960/decode.h b/sim/i960/decode.h
new file mode 100644
index 00000000000..6137217c2a8
--- /dev/null
+++ b/sim/i960/decode.h
@@ -0,0 +1,433 @@
+/* Decode header for i960base.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef I960BASE_DECODE_H
+#define I960BASE_DECODE_H
+
+extern const IDESC *i960base_decode (SIM_CPU *, IADDR,
+                                  CGEN_INSN_INT,
+                                  ARGBUF *);
+extern void i960base_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family i960base.  */
+typedef enum i960base_insn_type {
+  I960BASE_INSN_X_INVALID, I960BASE_INSN_X_AFTER, I960BASE_INSN_X_BEFORE, I960BASE_INSN_X_CTI_CHAIN
+ , I960BASE_INSN_X_CHAIN, I960BASE_INSN_X_BEGIN, I960BASE_INSN_MULO, I960BASE_INSN_MULO1
+ , I960BASE_INSN_MULO2, I960BASE_INSN_MULO3, I960BASE_INSN_REMO, I960BASE_INSN_REMO1
+ , I960BASE_INSN_REMO2, I960BASE_INSN_REMO3, I960BASE_INSN_DIVO, I960BASE_INSN_DIVO1
+ , I960BASE_INSN_DIVO2, I960BASE_INSN_DIVO3, I960BASE_INSN_REMI, I960BASE_INSN_REMI1
+ , I960BASE_INSN_REMI2, I960BASE_INSN_REMI3, I960BASE_INSN_DIVI, I960BASE_INSN_DIVI1
+ , I960BASE_INSN_DIVI2, I960BASE_INSN_DIVI3, I960BASE_INSN_ADDO, I960BASE_INSN_ADDO1
+ , I960BASE_INSN_ADDO2, I960BASE_INSN_ADDO3, I960BASE_INSN_SUBO, I960BASE_INSN_SUBO1
+ , I960BASE_INSN_SUBO2, I960BASE_INSN_SUBO3, I960BASE_INSN_NOTBIT, I960BASE_INSN_NOTBIT1
+ , I960BASE_INSN_NOTBIT2, I960BASE_INSN_NOTBIT3, I960BASE_INSN_AND, I960BASE_INSN_AND1
+ , I960BASE_INSN_AND2, I960BASE_INSN_AND3, I960BASE_INSN_ANDNOT, I960BASE_INSN_ANDNOT1
+ , I960BASE_INSN_ANDNOT2, I960BASE_INSN_ANDNOT3, I960BASE_INSN_SETBIT, I960BASE_INSN_SETBIT1
+ , I960BASE_INSN_SETBIT2, I960BASE_INSN_SETBIT3, I960BASE_INSN_NOTAND, I960BASE_INSN_NOTAND1
+ , I960BASE_INSN_NOTAND2, I960BASE_INSN_NOTAND3, I960BASE_INSN_XOR, I960BASE_INSN_XOR1
+ , I960BASE_INSN_XOR2, I960BASE_INSN_XOR3, I960BASE_INSN_OR, I960BASE_INSN_OR1
+ , I960BASE_INSN_OR2, I960BASE_INSN_OR3, I960BASE_INSN_NOR, I960BASE_INSN_NOR1
+ , I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1
+ , I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1
+ , I960BASE_INSN_CLRBIT2, I960BASE_INSN_CLRBIT3, I960BASE_INSN_SHLO, I960BASE_INSN_SHLO1
+ , I960BASE_INSN_SHLO2, I960BASE_INSN_SHLO3, I960BASE_INSN_SHRO, I960BASE_INSN_SHRO1
+ , I960BASE_INSN_SHRO2, I960BASE_INSN_SHRO3, I960BASE_INSN_SHLI, I960BASE_INSN_SHLI1
+ , I960BASE_INSN_SHLI2, I960BASE_INSN_SHLI3, I960BASE_INSN_SHRI, I960BASE_INSN_SHRI1
+ , I960BASE_INSN_SHRI2, I960BASE_INSN_SHRI3, I960BASE_INSN_EMUL, I960BASE_INSN_EMUL1
+ , I960BASE_INSN_EMUL2, I960BASE_INSN_EMUL3, I960BASE_INSN_MOV, I960BASE_INSN_MOV1
+ , I960BASE_INSN_MOVL, I960BASE_INSN_MOVL1, I960BASE_INSN_MOVT, I960BASE_INSN_MOVT1
+ , I960BASE_INSN_MOVQ, I960BASE_INSN_MOVQ1, I960BASE_INSN_MODPC, I960BASE_INSN_MODAC
+ , I960BASE_INSN_LDA_OFFSET, I960BASE_INSN_LDA_INDIRECT_OFFSET, I960BASE_INSN_LDA_INDIRECT, I960BASE_INSN_LDA_INDIRECT_INDEX
+ , I960BASE_INSN_LDA_DISP, I960BASE_INSN_LDA_INDIRECT_DISP, I960BASE_INSN_LDA_INDEX_DISP, I960BASE_INSN_LDA_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LD_OFFSET, I960BASE_INSN_LD_INDIRECT_OFFSET, I960BASE_INSN_LD_INDIRECT, I960BASE_INSN_LD_INDIRECT_INDEX
+ , I960BASE_INSN_LD_DISP, I960BASE_INSN_LD_INDIRECT_DISP, I960BASE_INSN_LD_INDEX_DISP, I960BASE_INSN_LD_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LDOB_OFFSET, I960BASE_INSN_LDOB_INDIRECT_OFFSET, I960BASE_INSN_LDOB_INDIRECT, I960BASE_INSN_LDOB_INDIRECT_INDEX
+ , I960BASE_INSN_LDOB_DISP, I960BASE_INSN_LDOB_INDIRECT_DISP, I960BASE_INSN_LDOB_INDEX_DISP, I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LDOS_OFFSET, I960BASE_INSN_LDOS_INDIRECT_OFFSET, I960BASE_INSN_LDOS_INDIRECT, I960BASE_INSN_LDOS_INDIRECT_INDEX
+ , I960BASE_INSN_LDOS_DISP, I960BASE_INSN_LDOS_INDIRECT_DISP, I960BASE_INSN_LDOS_INDEX_DISP, I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LDIB_OFFSET, I960BASE_INSN_LDIB_INDIRECT_OFFSET, I960BASE_INSN_LDIB_INDIRECT, I960BASE_INSN_LDIB_INDIRECT_INDEX
+ , I960BASE_INSN_LDIB_DISP, I960BASE_INSN_LDIB_INDIRECT_DISP, I960BASE_INSN_LDIB_INDEX_DISP, I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LDIS_OFFSET, I960BASE_INSN_LDIS_INDIRECT_OFFSET, I960BASE_INSN_LDIS_INDIRECT, I960BASE_INSN_LDIS_INDIRECT_INDEX
+ , I960BASE_INSN_LDIS_DISP, I960BASE_INSN_LDIS_INDIRECT_DISP, I960BASE_INSN_LDIS_INDEX_DISP, I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LDL_OFFSET, I960BASE_INSN_LDL_INDIRECT_OFFSET, I960BASE_INSN_LDL_INDIRECT, I960BASE_INSN_LDL_INDIRECT_INDEX
+ , I960BASE_INSN_LDL_DISP, I960BASE_INSN_LDL_INDIRECT_DISP, I960BASE_INSN_LDL_INDEX_DISP, I960BASE_INSN_LDL_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LDT_OFFSET, I960BASE_INSN_LDT_INDIRECT_OFFSET, I960BASE_INSN_LDT_INDIRECT, I960BASE_INSN_LDT_INDIRECT_INDEX
+ , I960BASE_INSN_LDT_DISP, I960BASE_INSN_LDT_INDIRECT_DISP, I960BASE_INSN_LDT_INDEX_DISP, I960BASE_INSN_LDT_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_LDQ_OFFSET, I960BASE_INSN_LDQ_INDIRECT_OFFSET, I960BASE_INSN_LDQ_INDIRECT, I960BASE_INSN_LDQ_INDIRECT_INDEX
+ , I960BASE_INSN_LDQ_DISP, I960BASE_INSN_LDQ_INDIRECT_DISP, I960BASE_INSN_LDQ_INDEX_DISP, I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_ST_OFFSET, I960BASE_INSN_ST_INDIRECT_OFFSET, I960BASE_INSN_ST_INDIRECT, I960BASE_INSN_ST_INDIRECT_INDEX
+ , I960BASE_INSN_ST_DISP, I960BASE_INSN_ST_INDIRECT_DISP, I960BASE_INSN_ST_INDEX_DISP, I960BASE_INSN_ST_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_STOB_OFFSET, I960BASE_INSN_STOB_INDIRECT_OFFSET, I960BASE_INSN_STOB_INDIRECT, I960BASE_INSN_STOB_INDIRECT_INDEX
+ , I960BASE_INSN_STOB_DISP, I960BASE_INSN_STOB_INDIRECT_DISP, I960BASE_INSN_STOB_INDEX_DISP, I960BASE_INSN_STOB_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_STOS_OFFSET, I960BASE_INSN_STOS_INDIRECT_OFFSET, I960BASE_INSN_STOS_INDIRECT, I960BASE_INSN_STOS_INDIRECT_INDEX
+ , I960BASE_INSN_STOS_DISP, I960BASE_INSN_STOS_INDIRECT_DISP, I960BASE_INSN_STOS_INDEX_DISP, I960BASE_INSN_STOS_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_STL_OFFSET, I960BASE_INSN_STL_INDIRECT_OFFSET, I960BASE_INSN_STL_INDIRECT, I960BASE_INSN_STL_INDIRECT_INDEX
+ , I960BASE_INSN_STL_DISP, I960BASE_INSN_STL_INDIRECT_DISP, I960BASE_INSN_STL_INDEX_DISP, I960BASE_INSN_STL_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_STT_OFFSET, I960BASE_INSN_STT_INDIRECT_OFFSET, I960BASE_INSN_STT_INDIRECT, I960BASE_INSN_STT_INDIRECT_INDEX
+ , I960BASE_INSN_STT_DISP, I960BASE_INSN_STT_INDIRECT_DISP, I960BASE_INSN_STT_INDEX_DISP, I960BASE_INSN_STT_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_STQ_OFFSET, I960BASE_INSN_STQ_INDIRECT_OFFSET, I960BASE_INSN_STQ_INDIRECT, I960BASE_INSN_STQ_INDIRECT_INDEX
+ , I960BASE_INSN_STQ_DISP, I960BASE_INSN_STQ_INDIRECT_DISP, I960BASE_INSN_STQ_INDEX_DISP, I960BASE_INSN_STQ_INDIRECT_INDEX_DISP
+ , I960BASE_INSN_CMPOBE_REG, I960BASE_INSN_CMPOBE_LIT, I960BASE_INSN_CMPOBNE_REG, I960BASE_INSN_CMPOBNE_LIT
+ , I960BASE_INSN_CMPOBL_REG, I960BASE_INSN_CMPOBL_LIT, I960BASE_INSN_CMPOBLE_REG, I960BASE_INSN_CMPOBLE_LIT
+ , I960BASE_INSN_CMPOBG_REG, I960BASE_INSN_CMPOBG_LIT, I960BASE_INSN_CMPOBGE_REG, I960BASE_INSN_CMPOBGE_LIT
+ , I960BASE_INSN_CMPIBE_REG, I960BASE_INSN_CMPIBE_LIT, I960BASE_INSN_CMPIBNE_REG, I960BASE_INSN_CMPIBNE_LIT
+ , I960BASE_INSN_CMPIBL_REG, I960BASE_INSN_CMPIBL_LIT, I960BASE_INSN_CMPIBLE_REG, I960BASE_INSN_CMPIBLE_LIT
+ , I960BASE_INSN_CMPIBG_REG, I960BASE_INSN_CMPIBG_LIT, I960BASE_INSN_CMPIBGE_REG, I960BASE_INSN_CMPIBGE_LIT
+ , I960BASE_INSN_BBC_REG, I960BASE_INSN_BBC_LIT, I960BASE_INSN_BBS_REG, I960BASE_INSN_BBS_LIT
+ , I960BASE_INSN_CMPI, I960BASE_INSN_CMPI1, I960BASE_INSN_CMPI2, I960BASE_INSN_CMPI3
+ , I960BASE_INSN_CMPO, I960BASE_INSN_CMPO1, I960BASE_INSN_CMPO2, I960BASE_INSN_CMPO3
+ , I960BASE_INSN_TESTNO_REG, I960BASE_INSN_TESTG_REG, I960BASE_INSN_TESTE_REG, I960BASE_INSN_TESTGE_REG
+ , I960BASE_INSN_TESTL_REG, I960BASE_INSN_TESTNE_REG, I960BASE_INSN_TESTLE_REG, I960BASE_INSN_TESTO_REG
+ , I960BASE_INSN_BNO, I960BASE_INSN_BG, I960BASE_INSN_BE, I960BASE_INSN_BGE
+ , I960BASE_INSN_BL, I960BASE_INSN_BNE, I960BASE_INSN_BLE, I960BASE_INSN_BO
+ , I960BASE_INSN_B, I960BASE_INSN_BX_INDIRECT_OFFSET, I960BASE_INSN_BX_INDIRECT, I960BASE_INSN_BX_INDIRECT_INDEX
+ , I960BASE_INSN_BX_DISP, I960BASE_INSN_BX_INDIRECT_DISP, I960BASE_INSN_CALLX_DISP, I960BASE_INSN_CALLX_INDIRECT
+ , I960BASE_INSN_CALLX_INDIRECT_OFFSET, I960BASE_INSN_RET, I960BASE_INSN_CALLS, I960BASE_INSN_FMARK
+ , I960BASE_INSN_FLUSHREG, I960BASE_INSN_MAX
+} I960BASE_INSN_TYPE;
+
+#if ! WITH_SEM_SWITCH_FULL
+#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (i960base,_sem_,fn);
+#else
+#define SEMFULL(fn)
+#endif
+
+#if ! WITH_SEM_SWITCH_FAST
+#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (i960base,_semf_,fn);
+#else
+#define SEMFAST(fn)
+#endif
+
+#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
+
+/* The function version of the before/after handlers is always needed,
+   so we always want the SEMFULL declaration of them.  */
+extern SEMANTIC_FN CONCAT3 (i960base,_sem_,x_before);
+extern SEMANTIC_FN CONCAT3 (i960base,_sem_,x_after);
+
+SEM (x_invalid)
+SEM (x_after)
+SEM (x_before)
+SEM (x_cti_chain)
+SEM (x_chain)
+SEM (x_begin)
+SEM (mulo)
+SEM (mulo1)
+SEM (mulo2)
+SEM (mulo3)
+SEM (remo)
+SEM (remo1)
+SEM (remo2)
+SEM (remo3)
+SEM (divo)
+SEM (divo1)
+SEM (divo2)
+SEM (divo3)
+SEM (remi)
+SEM (remi1)
+SEM (remi2)
+SEM (remi3)
+SEM (divi)
+SEM (divi1)
+SEM (divi2)
+SEM (divi3)
+SEM (addo)
+SEM (addo1)
+SEM (addo2)
+SEM (addo3)
+SEM (subo)
+SEM (subo1)
+SEM (subo2)
+SEM (subo3)
+SEM (notbit)
+SEM (notbit1)
+SEM (notbit2)
+SEM (notbit3)
+SEM (and)
+SEM (and1)
+SEM (and2)
+SEM (and3)
+SEM (andnot)
+SEM (andnot1)
+SEM (andnot2)
+SEM (andnot3)
+SEM (setbit)
+SEM (setbit1)
+SEM (setbit2)
+SEM (setbit3)
+SEM (notand)
+SEM (notand1)
+SEM (notand2)
+SEM (notand3)
+SEM (xor)
+SEM (xor1)
+SEM (xor2)
+SEM (xor3)
+SEM (or)
+SEM (or1)
+SEM (or2)
+SEM (or3)
+SEM (nor)
+SEM (nor1)
+SEM (nor2)
+SEM (nor3)
+SEM (not)
+SEM (not1)
+SEM (not2)
+SEM (not3)
+SEM (clrbit)
+SEM (clrbit1)
+SEM (clrbit2)
+SEM (clrbit3)
+SEM (shlo)
+SEM (shlo1)
+SEM (shlo2)
+SEM (shlo3)
+SEM (shro)
+SEM (shro1)
+SEM (shro2)
+SEM (shro3)
+SEM (shli)
+SEM (shli1)
+SEM (shli2)
+SEM (shli3)
+SEM (shri)
+SEM (shri1)
+SEM (shri2)
+SEM (shri3)
+SEM (emul)
+SEM (emul1)
+SEM (emul2)
+SEM (emul3)
+SEM (mov)
+SEM (mov1)
+SEM (movl)
+SEM (movl1)
+SEM (movt)
+SEM (movt1)
+SEM (movq)
+SEM (movq1)
+SEM (modpc)
+SEM (modac)
+SEM (lda_offset)
+SEM (lda_indirect_offset)
+SEM (lda_indirect)
+SEM (lda_indirect_index)
+SEM (lda_disp)
+SEM (lda_indirect_disp)
+SEM (lda_index_disp)
+SEM (lda_indirect_index_disp)
+SEM (ld_offset)
+SEM (ld_indirect_offset)
+SEM (ld_indirect)
+SEM (ld_indirect_index)
+SEM (ld_disp)
+SEM (ld_indirect_disp)
+SEM (ld_index_disp)
+SEM (ld_indirect_index_disp)
+SEM (ldob_offset)
+SEM (ldob_indirect_offset)
+SEM (ldob_indirect)
+SEM (ldob_indirect_index)
+SEM (ldob_disp)
+SEM (ldob_indirect_disp)
+SEM (ldob_index_disp)
+SEM (ldob_indirect_index_disp)
+SEM (ldos_offset)
+SEM (ldos_indirect_offset)
+SEM (ldos_indirect)
+SEM (ldos_indirect_index)
+SEM (ldos_disp)
+SEM (ldos_indirect_disp)
+SEM (ldos_index_disp)
+SEM (ldos_indirect_index_disp)
+SEM (ldib_offset)
+SEM (ldib_indirect_offset)
+SEM (ldib_indirect)
+SEM (ldib_indirect_index)
+SEM (ldib_disp)
+SEM (ldib_indirect_disp)
+SEM (ldib_index_disp)
+SEM (ldib_indirect_index_disp)
+SEM (ldis_offset)
+SEM (ldis_indirect_offset)
+SEM (ldis_indirect)
+SEM (ldis_indirect_index)
+SEM (ldis_disp)
+SEM (ldis_indirect_disp)
+SEM (ldis_index_disp)
+SEM (ldis_indirect_index_disp)
+SEM (ldl_offset)
+SEM (ldl_indirect_offset)
+SEM (ldl_indirect)
+SEM (ldl_indirect_index)
+SEM (ldl_disp)
+SEM (ldl_indirect_disp)
+SEM (ldl_index_disp)
+SEM (ldl_indirect_index_disp)
+SEM (ldt_offset)
+SEM (ldt_indirect_offset)
+SEM (ldt_indirect)
+SEM (ldt_indirect_index)
+SEM (ldt_disp)
+SEM (ldt_indirect_disp)
+SEM (ldt_index_disp)
+SEM (ldt_indirect_index_disp)
+SEM (ldq_offset)
+SEM (ldq_indirect_offset)
+SEM (ldq_indirect)
+SEM (ldq_indirect_index)
+SEM (ldq_disp)
+SEM (ldq_indirect_disp)
+SEM (ldq_index_disp)
+SEM (ldq_indirect_index_disp)
+SEM (st_offset)
+SEM (st_indirect_offset)
+SEM (st_indirect)
+SEM (st_indirect_index)
+SEM (st_disp)
+SEM (st_indirect_disp)
+SEM (st_index_disp)
+SEM (st_indirect_index_disp)
+SEM (stob_offset)
+SEM (stob_indirect_offset)
+SEM (stob_indirect)
+SEM (stob_indirect_index)
+SEM (stob_disp)
+SEM (stob_indirect_disp)
+SEM (stob_index_disp)
+SEM (stob_indirect_index_disp)
+SEM (stos_offset)
+SEM (stos_indirect_offset)
+SEM (stos_indirect)
+SEM (stos_indirect_index)
+SEM (stos_disp)
+SEM (stos_indirect_disp)
+SEM (stos_index_disp)
+SEM (stos_indirect_index_disp)
+SEM (stl_offset)
+SEM (stl_indirect_offset)
+SEM (stl_indirect)
+SEM (stl_indirect_index)
+SEM (stl_disp)
+SEM (stl_indirect_disp)
+SEM (stl_index_disp)
+SEM (stl_indirect_index_disp)
+SEM (stt_offset)
+SEM (stt_indirect_offset)
+SEM (stt_indirect)
+SEM (stt_indirect_index)
+SEM (stt_disp)
+SEM (stt_indirect_disp)
+SEM (stt_index_disp)
+SEM (stt_indirect_index_disp)
+SEM (stq_offset)
+SEM (stq_indirect_offset)
+SEM (stq_indirect)
+SEM (stq_indirect_index)
+SEM (stq_disp)
+SEM (stq_indirect_disp)
+SEM (stq_index_disp)
+SEM (stq_indirect_index_disp)
+SEM (cmpobe_reg)
+SEM (cmpobe_lit)
+SEM (cmpobne_reg)
+SEM (cmpobne_lit)
+SEM (cmpobl_reg)
+SEM (cmpobl_lit)
+SEM (cmpoble_reg)
+SEM (cmpoble_lit)
+SEM (cmpobg_reg)
+SEM (cmpobg_lit)
+SEM (cmpobge_reg)
+SEM (cmpobge_lit)
+SEM (cmpibe_reg)
+SEM (cmpibe_lit)
+SEM (cmpibne_reg)
+SEM (cmpibne_lit)
+SEM (cmpibl_reg)
+SEM (cmpibl_lit)
+SEM (cmpible_reg)
+SEM (cmpible_lit)
+SEM (cmpibg_reg)
+SEM (cmpibg_lit)
+SEM (cmpibge_reg)
+SEM (cmpibge_lit)
+SEM (bbc_reg)
+SEM (bbc_lit)
+SEM (bbs_reg)
+SEM (bbs_lit)
+SEM (cmpi)
+SEM (cmpi1)
+SEM (cmpi2)
+SEM (cmpi3)
+SEM (cmpo)
+SEM (cmpo1)
+SEM (cmpo2)
+SEM (cmpo3)
+SEM (testno_reg)
+SEM (testg_reg)
+SEM (teste_reg)
+SEM (testge_reg)
+SEM (testl_reg)
+SEM (testne_reg)
+SEM (testle_reg)
+SEM (testo_reg)
+SEM (bno)
+SEM (bg)
+SEM (be)
+SEM (bge)
+SEM (bl)
+SEM (bne)
+SEM (ble)
+SEM (bo)
+SEM (b)
+SEM (bx_indirect_offset)
+SEM (bx_indirect)
+SEM (bx_indirect_index)
+SEM (bx_disp)
+SEM (bx_indirect_disp)
+SEM (callx_disp)
+SEM (callx_indirect)
+SEM (callx_indirect_offset)
+SEM (ret)
+SEM (calls)
+SEM (fmark)
+SEM (flushreg)
+
+#undef SEMFULL
+#undef SEMFAST
+#undef SEM
+
+/* Function unit handlers (user written).  */
+
+extern int i960base_model_i960KA_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int i960base_model_i960CA_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void i960base_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void i960base_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* I960BASE_DECODE_H */
diff --git a/sim/i960/devices.c b/sim/i960/devices.c
new file mode 100644
index 00000000000..d34e6720201
--- /dev/null
+++ b/sim/i960/devices.c
@@ -0,0 +1,108 @@
+/* i960 device support
+   Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+
+#ifdef HAVE_DV_SOCKSER
+#include "dv-sockser.h"
+#endif
+
+/* Handling the MSPR register is done by creating a device in the core
+   mapping that winds up here.  */
+
+device i960_devices;
+
+int
+device_io_read_buffer (device *me, void *source, int space,
+		       address_word addr, unsigned nr_bytes,
+		       SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#ifdef HAVE_DV_SOCKSER
+  if (addr == UART_INCHAR_ADDR)
+    {
+      int c = dv_sockser_read (sd);
+      if (c == -1)
+	return 0;
+      *(char *) source = c;
+      return 1;
+    }
+  if (addr == UART_STATUS_ADDR)
+    {
+      int status = dv_sockser_status (sd);
+      unsigned char *p = source;
+      p[0] = 0;
+      p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
+#ifdef UART_INPUT_READY0
+	       ? UART_INPUT_READY : 0)
+#else
+	       ? 0 : UART_INPUT_READY)
+#endif
+	      + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
+      return 2;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+int
+device_io_write_buffer (device *me, const void *source, int space,
+			address_word addr, unsigned nr_bytes,
+			SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+#if WITH_SCACHE
+  /* MSPR support is deprecated but is kept in for upward compatibility
+     with existing overlay support.  */
+  if (addr == MSPR_ADDR)
+    {
+      if ((*(const char *) source & MSPR_PURGE) != 0)
+	scache_flush (sd);
+      return nr_bytes;
+    }
+  if (addr == MCCR_ADDR)
+    {
+      if ((*(const char *) source & MCCR_CP) != 0)
+	scache_flush (sd);
+      return nr_bytes;
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#if HAVE_DV_SOCKSER
+  if (addr == UART_OUTCHAR_ADDR)
+    {
+      int rc = dv_sockser_write (sd, *(char *) source);
+      return rc == 1;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+void device_error () {}
diff --git a/sim/i960/i960-desc.c b/sim/i960/i960-desc.c
new file mode 100644
index 00000000000..6ea8fdc5b3c
--- /dev/null
+++ b/sim/i960/i960-desc.c
@@ -0,0 +1,1784 @@
+/* CPU data for i960.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include <ctype.h>
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "i960-desc.h"
+#include "i960-opc.h"
+#include "opintl.h"
+
+/* Attributes.  */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+  { "#f", 0 },
+  { "#t", 1 },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+  { "base", MACH_BASE },
+  { "i960_ka_sa", MACH_I960_KA_SA },
+  { "i960_ca", MACH_I960_CA },
+  { "max", MACH_MAX },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
+{
+  { "MACH", & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "RESERVED", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
+{
+  { "MACH", & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
+  { "PC", &bool_attr[0], &bool_attr[0] },
+  { "PROFILE", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
+{
+  { "MACH", & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
+{
+  { "MACH", & MACH_attr[0] },
+  { "ALIAS", &bool_attr[0], &bool_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+  { "PBB", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] = 
+{
+  { "fp", 31 },
+  { "sp", 1 },
+  { "r0", 0 },
+  { "r1", 1 },
+  { "r2", 2 },
+  { "r3", 3 },
+  { "r4", 4 },
+  { "r5", 5 },
+  { "r6", 6 },
+  { "r7", 7 },
+  { "r8", 8 },
+  { "r9", 9 },
+  { "r10", 10 },
+  { "r11", 11 },
+  { "r12", 12 },
+  { "r13", 13 },
+  { "r14", 14 },
+  { "r15", 15 },
+  { "g0", 16 },
+  { "g1", 17 },
+  { "g2", 18 },
+  { "g3", 19 },
+  { "g4", 20 },
+  { "g5", 21 },
+  { "g6", 22 },
+  { "g7", 23 },
+  { "g8", 24 },
+  { "g9", 25 },
+  { "g10", 26 },
+  { "g11", 27 },
+  { "g12", 28 },
+  { "g13", 29 },
+  { "g14", 30 },
+  { "g15", 31 }
+};
+
+CGEN_KEYWORD i960_cgen_opval_h_gr = 
+{
+  & i960_cgen_opval_h_gr_entries[0],
+  34
+};
+
+CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] = 
+{
+  { "cc", 0 }
+};
+
+CGEN_KEYWORD i960_cgen_opval_h_cc = 
+{
+  & i960_cgen_opval_h_cc_entries[0],
+  1
+};
+
+
+
+/* The hardware table.  */
+
+#define A(a) (1 << (CONCAT2 (CGEN_HW_,a) - CGEN_ATTR_BOOL_OFFSET))
+#define HW_ENT(n) i960_cgen_hw_table[n]
+
+const CGEN_HW_ENTRY i960_cgen_hw_table[] =
+{
+  { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
+  { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+  { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+  { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+  { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+  { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+  { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { CGEN_HW_NBOOL_ATTRS, 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { 0 }
+};
+
+/* don't undef HW_ENT, used later */
+#undef A
+
+/* The instruction field table.  */
+
+#define A(a) (1 << (CONCAT2 (CGEN_IFLD_,a) - CGEN_ATTR_BOOL_OFFSET))
+
+const CGEN_IFLD i960_cgen_ifld_table[] =
+{
+  { I960_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }  },
+  { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_M3, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_M2, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_M1, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_INDEX, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+  { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+  { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+  { 0 }
+};
+
+#undef A
+
+/* The operand table.  */
+
+#define A(a) (1 << (CONCAT2 (CGEN_OPERAND_,a) - CGEN_ATTR_BOOL_OFFSET))
+#define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
+
+const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
+{
+/* pc: program counter */
+  { "pc", & HW_ENT (HW_H_PC), 0, 0,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* src1: source register 1 */
+  { "src1", & HW_ENT (HW_H_GR), 27, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* src2: source register 2 */
+  { "src2", & HW_ENT (HW_H_GR), 13, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* dst: source/dest register */
+  { "dst", & HW_ENT (HW_H_GR), 8, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* lit1: literal 1 */
+  { "lit1", & HW_ENT (HW_H_UINT), 27, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* lit2: literal 2 */
+  { "lit2", & HW_ENT (HW_H_UINT), 13, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* st_src: store src */
+  { "st_src", & HW_ENT (HW_H_GR), 8, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* abase: abase */
+  { "abase", & HW_ENT (HW_H_GR), 13, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* offset: offset */
+  { "offset", & HW_ENT (HW_H_UINT), 20, 12,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* scale: scale */
+  { "scale", & HW_ENT (HW_H_UINT), 22, 3,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* index: index */
+  { "index", & HW_ENT (HW_H_GR), 27, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* optdisp: optional displacement */
+  { "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* br_src1: branch src1 */
+  { "br_src1", & HW_ENT (HW_H_GR), 8, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* br_src2: branch src2 */
+  { "br_src2", & HW_ENT (HW_H_GR), 13, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* br_disp: branch displacement */
+  { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+/* br_lit1: branch literal 1 */
+  { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } }  },
+/* ctrl_disp: ctrl branch disp */
+  { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
+    { CGEN_OPERAND_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+};
+
+#undef A
+
+#define A(a) (1 << (CONCAT2 (CGEN_INSN_,a) - CGEN_ATTR_BOOL_OFFSET))
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table.  */
+
+static const CGEN_IBASE i960_cgen_insn_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { 0, 0, 0 },
+/* mulo $src1, $src2, $dst */
+  {
+    I960_INSN_MULO, "mulo", "mulo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* mulo $lit1, $src2, $dst */
+  {
+    I960_INSN_MULO1, "mulo1", "mulo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* mulo $src1, $lit2, $dst */
+  {
+    I960_INSN_MULO2, "mulo2", "mulo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* mulo $lit1, $lit2, $dst */
+  {
+    I960_INSN_MULO3, "mulo3", "mulo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remo $src1, $src2, $dst */
+  {
+    I960_INSN_REMO, "remo", "remo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remo $lit1, $src2, $dst */
+  {
+    I960_INSN_REMO1, "remo1", "remo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remo $src1, $lit2, $dst */
+  {
+    I960_INSN_REMO2, "remo2", "remo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remo $lit1, $lit2, $dst */
+  {
+    I960_INSN_REMO3, "remo3", "remo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divo $src1, $src2, $dst */
+  {
+    I960_INSN_DIVO, "divo", "divo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divo $lit1, $src2, $dst */
+  {
+    I960_INSN_DIVO1, "divo1", "divo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divo $src1, $lit2, $dst */
+  {
+    I960_INSN_DIVO2, "divo2", "divo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divo $lit1, $lit2, $dst */
+  {
+    I960_INSN_DIVO3, "divo3", "divo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remi $src1, $src2, $dst */
+  {
+    I960_INSN_REMI, "remi", "remi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remi $lit1, $src2, $dst */
+  {
+    I960_INSN_REMI1, "remi1", "remi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remi $src1, $lit2, $dst */
+  {
+    I960_INSN_REMI2, "remi2", "remi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* remi $lit1, $lit2, $dst */
+  {
+    I960_INSN_REMI3, "remi3", "remi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divi $src1, $src2, $dst */
+  {
+    I960_INSN_DIVI, "divi", "divi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divi $lit1, $src2, $dst */
+  {
+    I960_INSN_DIVI1, "divi1", "divi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divi $src1, $lit2, $dst */
+  {
+    I960_INSN_DIVI2, "divi2", "divi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* divi $lit1, $lit2, $dst */
+  {
+    I960_INSN_DIVI3, "divi3", "divi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* addo $src1, $src2, $dst */
+  {
+    I960_INSN_ADDO, "addo", "addo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* addo $lit1, $src2, $dst */
+  {
+    I960_INSN_ADDO1, "addo1", "addo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* addo $src1, $lit2, $dst */
+  {
+    I960_INSN_ADDO2, "addo2", "addo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* addo $lit1, $lit2, $dst */
+  {
+    I960_INSN_ADDO3, "addo3", "addo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* subo $src1, $src2, $dst */
+  {
+    I960_INSN_SUBO, "subo", "subo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* subo $lit1, $src2, $dst */
+  {
+    I960_INSN_SUBO1, "subo1", "subo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* subo $src1, $lit2, $dst */
+  {
+    I960_INSN_SUBO2, "subo2", "subo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* subo $lit1, $lit2, $dst */
+  {
+    I960_INSN_SUBO3, "subo3", "subo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notbit $src1, $src2, $dst */
+  {
+    I960_INSN_NOTBIT, "notbit", "notbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notbit $lit1, $src2, $dst */
+  {
+    I960_INSN_NOTBIT1, "notbit1", "notbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notbit $src1, $lit2, $dst */
+  {
+    I960_INSN_NOTBIT2, "notbit2", "notbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notbit $lit1, $lit2, $dst */
+  {
+    I960_INSN_NOTBIT3, "notbit3", "notbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* and $src1, $src2, $dst */
+  {
+    I960_INSN_AND, "and", "and", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* and $lit1, $src2, $dst */
+  {
+    I960_INSN_AND1, "and1", "and", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* and $src1, $lit2, $dst */
+  {
+    I960_INSN_AND2, "and2", "and", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* and $lit1, $lit2, $dst */
+  {
+    I960_INSN_AND3, "and3", "and", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* andnot $src1, $src2, $dst */
+  {
+    I960_INSN_ANDNOT, "andnot", "andnot", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* andnot $lit1, $src2, $dst */
+  {
+    I960_INSN_ANDNOT1, "andnot1", "andnot", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* andnot $src1, $lit2, $dst */
+  {
+    I960_INSN_ANDNOT2, "andnot2", "andnot", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* andnot $lit1, $lit2, $dst */
+  {
+    I960_INSN_ANDNOT3, "andnot3", "andnot", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* setbit $src1, $src2, $dst */
+  {
+    I960_INSN_SETBIT, "setbit", "setbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* setbit $lit1, $src2, $dst */
+  {
+    I960_INSN_SETBIT1, "setbit1", "setbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* setbit $src1, $lit2, $dst */
+  {
+    I960_INSN_SETBIT2, "setbit2", "setbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* setbit $lit1, $lit2, $dst */
+  {
+    I960_INSN_SETBIT3, "setbit3", "setbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notand $src1, $src2, $dst */
+  {
+    I960_INSN_NOTAND, "notand", "notand", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notand $lit1, $src2, $dst */
+  {
+    I960_INSN_NOTAND1, "notand1", "notand", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notand $src1, $lit2, $dst */
+  {
+    I960_INSN_NOTAND2, "notand2", "notand", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* notand $lit1, $lit2, $dst */
+  {
+    I960_INSN_NOTAND3, "notand3", "notand", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* xor $src1, $src2, $dst */
+  {
+    I960_INSN_XOR, "xor", "xor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* xor $lit1, $src2, $dst */
+  {
+    I960_INSN_XOR1, "xor1", "xor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* xor $src1, $lit2, $dst */
+  {
+    I960_INSN_XOR2, "xor2", "xor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* xor $lit1, $lit2, $dst */
+  {
+    I960_INSN_XOR3, "xor3", "xor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* or $src1, $src2, $dst */
+  {
+    I960_INSN_OR, "or", "or", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* or $lit1, $src2, $dst */
+  {
+    I960_INSN_OR1, "or1", "or", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* or $src1, $lit2, $dst */
+  {
+    I960_INSN_OR2, "or2", "or", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* or $lit1, $lit2, $dst */
+  {
+    I960_INSN_OR3, "or3", "or", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* nor $src1, $src2, $dst */
+  {
+    I960_INSN_NOR, "nor", "nor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* nor $lit1, $src2, $dst */
+  {
+    I960_INSN_NOR1, "nor1", "nor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* nor $src1, $lit2, $dst */
+  {
+    I960_INSN_NOR2, "nor2", "nor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* nor $lit1, $lit2, $dst */
+  {
+    I960_INSN_NOR3, "nor3", "nor", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* not $src1, $src2, $dst */
+  {
+    I960_INSN_NOT, "not", "not", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* not $lit1, $src2, $dst */
+  {
+    I960_INSN_NOT1, "not1", "not", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* not $src1, $lit2, $dst */
+  {
+    I960_INSN_NOT2, "not2", "not", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* not $lit1, $lit2, $dst */
+  {
+    I960_INSN_NOT3, "not3", "not", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* clrbit $src1, $src2, $dst */
+  {
+    I960_INSN_CLRBIT, "clrbit", "clrbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* clrbit $lit1, $src2, $dst */
+  {
+    I960_INSN_CLRBIT1, "clrbit1", "clrbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* clrbit $src1, $lit2, $dst */
+  {
+    I960_INSN_CLRBIT2, "clrbit2", "clrbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* clrbit $lit1, $lit2, $dst */
+  {
+    I960_INSN_CLRBIT3, "clrbit3", "clrbit", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shlo $src1, $src2, $dst */
+  {
+    I960_INSN_SHLO, "shlo", "shlo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shlo $lit1, $src2, $dst */
+  {
+    I960_INSN_SHLO1, "shlo1", "shlo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shlo $src1, $lit2, $dst */
+  {
+    I960_INSN_SHLO2, "shlo2", "shlo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shlo $lit1, $lit2, $dst */
+  {
+    I960_INSN_SHLO3, "shlo3", "shlo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shro $src1, $src2, $dst */
+  {
+    I960_INSN_SHRO, "shro", "shro", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shro $lit1, $src2, $dst */
+  {
+    I960_INSN_SHRO1, "shro1", "shro", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shro $src1, $lit2, $dst */
+  {
+    I960_INSN_SHRO2, "shro2", "shro", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shro $lit1, $lit2, $dst */
+  {
+    I960_INSN_SHRO3, "shro3", "shro", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shli $src1, $src2, $dst */
+  {
+    I960_INSN_SHLI, "shli", "shli", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shli $lit1, $src2, $dst */
+  {
+    I960_INSN_SHLI1, "shli1", "shli", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shli $src1, $lit2, $dst */
+  {
+    I960_INSN_SHLI2, "shli2", "shli", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shli $lit1, $lit2, $dst */
+  {
+    I960_INSN_SHLI3, "shli3", "shli", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shri $src1, $src2, $dst */
+  {
+    I960_INSN_SHRI, "shri", "shri", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shri $lit1, $src2, $dst */
+  {
+    I960_INSN_SHRI1, "shri1", "shri", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shri $src1, $lit2, $dst */
+  {
+    I960_INSN_SHRI2, "shri2", "shri", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* shri $lit1, $lit2, $dst */
+  {
+    I960_INSN_SHRI3, "shri3", "shri", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* emul $src1, $src2, $dst */
+  {
+    I960_INSN_EMUL, "emul", "emul", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* emul $lit1, $src2, $dst */
+  {
+    I960_INSN_EMUL1, "emul1", "emul", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* emul $src1, $lit2, $dst */
+  {
+    I960_INSN_EMUL2, "emul2", "emul", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* emul $lit1, $lit2, $dst */
+  {
+    I960_INSN_EMUL3, "emul3", "emul", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* mov $src1, $dst */
+  {
+    I960_INSN_MOV, "mov", "mov", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* mov $lit1, $dst */
+  {
+    I960_INSN_MOV1, "mov1", "mov", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* movl $src1, $dst */
+  {
+    I960_INSN_MOVL, "movl", "movl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* movl $lit1, $dst */
+  {
+    I960_INSN_MOVL1, "movl1", "movl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* movt $src1, $dst */
+  {
+    I960_INSN_MOVT, "movt", "movt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* movt $lit1, $dst */
+  {
+    I960_INSN_MOVT1, "movt1", "movt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* movq $src1, $dst */
+  {
+    I960_INSN_MOVQ, "movq", "movq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* movq $lit1, $dst */
+  {
+    I960_INSN_MOVQ1, "movq1", "movq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* modpc $src1, $src2, $dst */
+  {
+    I960_INSN_MODPC, "modpc", "modpc", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* modac $src1, $src2, $dst */
+  {
+    I960_INSN_MODAC, "modac", "modac", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda $offset, $dst */
+  {
+    I960_INSN_LDA_OFFSET, "lda-offset", "lda", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda $offset($abase), $dst */
+  {
+    I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda ($abase), $dst */
+  {
+    I960_INSN_LDA_INDIRECT, "lda-indirect", "lda", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda $optdisp, $dst */
+  {
+    I960_INSN_LDA_DISP, "lda-disp", "lda", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda $optdisp($abase), $dst */
+  {
+    I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* lda $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld $offset, $dst */
+  {
+    I960_INSN_LD_OFFSET, "ld-offset", "ld", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld $offset($abase), $dst */
+  {
+    I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld ($abase), $dst */
+  {
+    I960_INSN_LD_INDIRECT, "ld-indirect", "ld", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld $optdisp, $dst */
+  {
+    I960_INSN_LD_DISP, "ld-disp", "ld", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld $optdisp($abase), $dst */
+  {
+    I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ld $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob $offset, $dst */
+  {
+    I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob $offset($abase), $dst */
+  {
+    I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob ($abase), $dst */
+  {
+    I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob $optdisp, $dst */
+  {
+    I960_INSN_LDOB_DISP, "ldob-disp", "ldob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob $optdisp($abase), $dst */
+  {
+    I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldob $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos $offset, $dst */
+  {
+    I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos $offset($abase), $dst */
+  {
+    I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos ($abase), $dst */
+  {
+    I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos $optdisp, $dst */
+  {
+    I960_INSN_LDOS_DISP, "ldos-disp", "ldos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos $optdisp($abase), $dst */
+  {
+    I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldos $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib $offset, $dst */
+  {
+    I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib $offset($abase), $dst */
+  {
+    I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib ($abase), $dst */
+  {
+    I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib $optdisp, $dst */
+  {
+    I960_INSN_LDIB_DISP, "ldib-disp", "ldib", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib $optdisp($abase), $dst */
+  {
+    I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldib $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis $offset, $dst */
+  {
+    I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis $offset($abase), $dst */
+  {
+    I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis ($abase), $dst */
+  {
+    I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis $optdisp, $dst */
+  {
+    I960_INSN_LDIS_DISP, "ldis-disp", "ldis", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis $optdisp($abase), $dst */
+  {
+    I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldis $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl $offset, $dst */
+  {
+    I960_INSN_LDL_OFFSET, "ldl-offset", "ldl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl $offset($abase), $dst */
+  {
+    I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl ($abase), $dst */
+  {
+    I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl $optdisp, $dst */
+  {
+    I960_INSN_LDL_DISP, "ldl-disp", "ldl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl $optdisp($abase), $dst */
+  {
+    I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldl $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt $offset, $dst */
+  {
+    I960_INSN_LDT_OFFSET, "ldt-offset", "ldt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt $offset($abase), $dst */
+  {
+    I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt ($abase), $dst */
+  {
+    I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt $optdisp, $dst */
+  {
+    I960_INSN_LDT_DISP, "ldt-disp", "ldt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt $optdisp($abase), $dst */
+  {
+    I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldt $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq $offset, $dst */
+  {
+    I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq $offset($abase), $dst */
+  {
+    I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq ($abase), $dst */
+  {
+    I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq ($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq $optdisp, $dst */
+  {
+    I960_INSN_LDQ_DISP, "ldq-disp", "ldq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq $optdisp($abase), $dst */
+  {
+    I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq $optdisp[$index*S$scale], $dst */
+  {
+    I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* ldq $optdisp($abase)[$index*S$scale], $dst */
+  {
+    I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, $offset */
+  {
+    I960_INSN_ST_OFFSET, "st-offset", "st", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, $offset($abase) */
+  {
+    I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, ($abase) */
+  {
+    I960_INSN_ST_INDIRECT, "st-indirect", "st", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, ($abase)[$index*S$scale] */
+  {
+    I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, $optdisp */
+  {
+    I960_INSN_ST_DISP, "st-disp", "st", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, $optdisp($abase) */
+  {
+    I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, $optdisp[$index*S$scale */
+  {
+    I960_INSN_ST_INDEX_DISP, "st-index-disp", "st", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* st $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, $offset */
+  {
+    I960_INSN_STOB_OFFSET, "stob-offset", "stob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, $offset($abase) */
+  {
+    I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, ($abase) */
+  {
+    I960_INSN_STOB_INDIRECT, "stob-indirect", "stob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, ($abase)[$index*S$scale] */
+  {
+    I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, $optdisp */
+  {
+    I960_INSN_STOB_DISP, "stob-disp", "stob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, $optdisp($abase) */
+  {
+    I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, $optdisp[$index*S$scale */
+  {
+    I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stob $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, $offset */
+  {
+    I960_INSN_STOS_OFFSET, "stos-offset", "stos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, $offset($abase) */
+  {
+    I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, ($abase) */
+  {
+    I960_INSN_STOS_INDIRECT, "stos-indirect", "stos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, ($abase)[$index*S$scale] */
+  {
+    I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, $optdisp */
+  {
+    I960_INSN_STOS_DISP, "stos-disp", "stos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, $optdisp($abase) */
+  {
+    I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, $optdisp[$index*S$scale */
+  {
+    I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stos $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, $offset */
+  {
+    I960_INSN_STL_OFFSET, "stl-offset", "stl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, $offset($abase) */
+  {
+    I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, ($abase) */
+  {
+    I960_INSN_STL_INDIRECT, "stl-indirect", "stl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, ($abase)[$index*S$scale] */
+  {
+    I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, $optdisp */
+  {
+    I960_INSN_STL_DISP, "stl-disp", "stl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, $optdisp($abase) */
+  {
+    I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, $optdisp[$index*S$scale */
+  {
+    I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stl $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, $offset */
+  {
+    I960_INSN_STT_OFFSET, "stt-offset", "stt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, $offset($abase) */
+  {
+    I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, ($abase) */
+  {
+    I960_INSN_STT_INDIRECT, "stt-indirect", "stt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, ($abase)[$index*S$scale] */
+  {
+    I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, $optdisp */
+  {
+    I960_INSN_STT_DISP, "stt-disp", "stt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, $optdisp($abase) */
+  {
+    I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, $optdisp[$index*S$scale */
+  {
+    I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stt $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, $offset */
+  {
+    I960_INSN_STQ_OFFSET, "stq-offset", "stq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, $offset($abase) */
+  {
+    I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, ($abase) */
+  {
+    I960_INSN_STQ_INDIRECT, "stq-indirect", "stq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, ($abase)[$index*S$scale] */
+  {
+    I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, $optdisp */
+  {
+    I960_INSN_STQ_DISP, "stq-disp", "stq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, $optdisp($abase) */
+  {
+    I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, $optdisp[$index*S$scale */
+  {
+    I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* stq $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpobe $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobe $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobne $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobne $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobl $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobl $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpoble $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpoble $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobg $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobg $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobge $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpobge $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibe $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibe $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibne $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibne $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibl $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibl $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpible $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpible $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibg $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibg $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibge $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpibge $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bbc $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_BBC_REG, "bbc-reg", "bbc", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bbc $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_BBC_LIT, "bbc-lit", "bbc", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bbs $br_src1, $br_src2, $br_disp */
+  {
+    I960_INSN_BBS_REG, "bbs-reg", "bbs", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bbs $br_lit1, $br_src2, $br_disp */
+  {
+    I960_INSN_BBS_LIT, "bbs-lit", "bbs", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* cmpi $src1, $src2 */
+  {
+    I960_INSN_CMPI, "cmpi", "cmpi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpi $lit1, $src2 */
+  {
+    I960_INSN_CMPI1, "cmpi1", "cmpi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpi $src1, $lit2 */
+  {
+    I960_INSN_CMPI2, "cmpi2", "cmpi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpi $lit1, $lit2 */
+  {
+    I960_INSN_CMPI3, "cmpi3", "cmpi", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpo $src1, $src2 */
+  {
+    I960_INSN_CMPO, "cmpo", "cmpo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpo $lit1, $src2 */
+  {
+    I960_INSN_CMPO1, "cmpo1", "cmpo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpo $src1, $lit2 */
+  {
+    I960_INSN_CMPO2, "cmpo2", "cmpo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* cmpo $lit1, $lit2 */
+  {
+    I960_INSN_CMPO3, "cmpo3", "cmpo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* testno $br_src1 */
+  {
+    I960_INSN_TESTNO_REG, "testno-reg", "testno", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* testg $br_src1 */
+  {
+    I960_INSN_TESTG_REG, "testg-reg", "testg", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* teste $br_src1 */
+  {
+    I960_INSN_TESTE_REG, "teste-reg", "teste", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* testge $br_src1 */
+  {
+    I960_INSN_TESTGE_REG, "testge-reg", "testge", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* testl $br_src1 */
+  {
+    I960_INSN_TESTL_REG, "testl-reg", "testl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* testne $br_src1 */
+  {
+    I960_INSN_TESTNE_REG, "testne-reg", "testne", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* testle $br_src1 */
+  {
+    I960_INSN_TESTLE_REG, "testle-reg", "testle", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* testo $br_src1 */
+  {
+    I960_INSN_TESTO_REG, "testo-reg", "testo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+/* bno $ctrl_disp */
+  {
+    I960_INSN_BNO, "bno", "bno", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bg $ctrl_disp */
+  {
+    I960_INSN_BG, "bg", "bg", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* be $ctrl_disp */
+  {
+    I960_INSN_BE, "be", "be", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bge $ctrl_disp */
+  {
+    I960_INSN_BGE, "bge", "bge", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bl $ctrl_disp */
+  {
+    I960_INSN_BL, "bl", "bl", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bne $ctrl_disp */
+  {
+    I960_INSN_BNE, "bne", "bne", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* ble $ctrl_disp */
+  {
+    I960_INSN_BLE, "ble", "ble", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bo $ctrl_disp */
+  {
+    I960_INSN_BO, "bo", "bo", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+  },
+/* b $ctrl_disp */
+  {
+    I960_INSN_B, "b", "b", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bx $offset($abase) */
+  {
+    I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bx ($abase) */
+  {
+    I960_INSN_BX_INDIRECT, "bx-indirect", "bx", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bx ($abase)[$index*S$scale] */
+  {
+    I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bx $optdisp */
+  {
+    I960_INSN_BX_DISP, "bx-disp", "bx", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* bx $optdisp($abase) */
+  {
+    I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* callx $optdisp */
+  {
+    I960_INSN_CALLX_DISP, "callx-disp", "callx", 64,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* callx ($abase) */
+  {
+    I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* callx $offset($abase) */
+  {
+    I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* ret */
+  {
+    I960_INSN_RET, "ret", "ret", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* calls $src1 */
+  {
+    I960_INSN_CALLS, "calls", "calls", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* fmark */
+  {
+    I960_INSN_FMARK, "fmark", "fmark", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+  },
+/* flushreg */
+  {
+    I960_INSN_FLUSHREG, "flushreg", "flushreg", 32,
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+  },
+};
+
+#undef A
+#undef MNEM
+#undef OP
+
+static void
+init_tables ()
+{
+}
+
+/* Initialize a cpu table and return a descriptor.
+   It's much like opening a file, and must be the first function called.  */
+
+CGEN_CPU_DESC
+i960_cgen_cpu_open (mach, endian)
+     int mach;
+     enum cgen_endian endian;
+{
+  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+  static int init_p;
+
+  if (! init_p)
+    {
+      init_tables ();
+      init_p = 1;
+    }
+
+  memset (cd, 0, sizeof (*cd));
+
+  cd->mach = mach;
+  cd->endian = endian;
+  /* FIXME: for the sparc case we can determine insn-endianness statically.
+     The worry here is where both data and insn endian can be independently
+     chosen, in which case this function will need another argument.
+     Actually, will want to allow for more arguments in the future anyway.  */
+  cd->insn_endian = endian;
+
+  cd->int_insn_p = CGEN_INT_INSN_P;
+
+  cd->max_insn_size = CGEN_MAX_INSN_SIZE;
+
+  cd->hw_list = & i960_cgen_hw_table[0];
+
+  cd->ifld_table = & i960_cgen_ifld_table[0];
+
+  cd->operand_table = & i960_cgen_operand_table[0];
+
+  {
+    int i;
+    const CGEN_IBASE *ib = & i960_cgen_insn_table[0];
+    CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+    memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+    for (i = 0; i < MAX_INSNS; ++i)
+      insns[i].base = &ib[i];
+    cd->insn_table.init_entries = insns;
+  }
+  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+  cd->insn_table.num_init_entries = MAX_INSNS;
+
+  return (CGEN_CPU_DESC) cd;
+}
+
+/* Close a cpu table.  */
+
+void
+i960_cgen_cpu_close (cd)
+     CGEN_CPU_DESC cd;
+{
+  if (cd->insn_table.init_entries)
+    free ((CGEN_INSN *) cd->insn_table.init_entries);
+  free (cd);
+}
+
diff --git a/sim/i960/i960-desc.h b/sim/i960/i960-desc.h
new file mode 100644
index 00000000000..7a3310f5265
--- /dev/null
+++ b/sim/i960/i960-desc.h
@@ -0,0 +1,342 @@
+/* CPU data header for i960.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef I960_CPU_H
+#define I960_CPU_H
+
+#define CGEN_ARCH i960
+
+/* Given symbol S, return i960_cgen_<S>.  */
+#define CGEN_SYM(s) CONCAT3 (i960,_cgen_,s)
+
+/* Selected cpu families.  */
+#define HAVE_CPU_I960BASE
+
+#define CGEN_INSN_LSB0_P 0
+#define CGEN_WORD_BITSIZE 32
+#define CGEN_DEFAULT_INSN_BITSIZE 32
+#define CGEN_BASE_INSN_BITSIZE 32
+#define CGEN_MIN_INSN_BITSIZE 32
+#define CGEN_MAX_INSN_BITSIZE 64
+#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
+#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
+#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
+#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
+#define CGEN_INT_INSN_P 0
+
+/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
+   we can't hash on everything up to the space.  */
+#define CGEN_MNEMONIC_OPERANDS
+/* Maximum number of operands any insn or macro-insn has.  */
+#define CGEN_MAX_INSN_OPERANDS 16
+
+/* Maximum number of fields in an instruction.  */
+#define CGEN_MAX_IFMT_OPERANDS 9
+
+/* Enums.  */
+
+/* Enum declaration for insn opcode enums.  */
+typedef enum insn_opcode {
+  OPCODE_00, OPCODE_01, OPCODE_02, OPCODE_03
+ , OPCODE_04, OPCODE_05, OPCODE_06, OPCODE_07
+ , OPCODE_08, OPCODE_09, OPCODE_0A, OPCODE_0B
+ , OPCODE_0C, OPCODE_0D, OPCODE_0E, OPCODE_0F
+ , OPCODE_10, OPCODE_11, OPCODE_12, OPCODE_13
+ , OPCODE_14, OPCODE_15, OPCODE_16, OPCODE_17
+ , OPCODE_18, OPCODE_19, OPCODE_1A, OPCODE_1B
+ , OPCODE_1C, OPCODE_1D, OPCODE_1E, OPCODE_1F
+ , OPCODE_20, OPCODE_21, OPCODE_22, OPCODE_23
+ , OPCODE_24, OPCODE_25, OPCODE_26, OPCODE_27
+ , OPCODE_28, OPCODE_29, OPCODE_2A, OPCODE_2B
+ , OPCODE_2C, OPCODE_2D, OPCODE_2E, OPCODE_2F
+ , OPCODE_30, OPCODE_31, OPCODE_32, OPCODE_33
+ , OPCODE_34, OPCODE_35, OPCODE_36, OPCODE_37
+ , OPCODE_38, OPCODE_39, OPCODE_3A, OPCODE_3B
+ , OPCODE_3C, OPCODE_3D, OPCODE_3E, OPCODE_3F
+ , OPCODE_40, OPCODE_41, OPCODE_42, OPCODE_43
+ , OPCODE_44, OPCODE_45, OPCODE_46, OPCODE_47
+ , OPCODE_48, OPCODE_49, OPCODE_4A, OPCODE_4B
+ , OPCODE_4C, OPCODE_4D, OPCODE_4E, OPCODE_4F
+ , OPCODE_50, OPCODE_51, OPCODE_52, OPCODE_53
+ , OPCODE_54, OPCODE_55, OPCODE_56, OPCODE_57
+ , OPCODE_58, OPCODE_59, OPCODE_5A, OPCODE_5B
+ , OPCODE_5C, OPCODE_5D, OPCODE_5E, OPCODE_5F
+ , OPCODE_60, OPCODE_61, OPCODE_62, OPCODE_63
+ , OPCODE_64, OPCODE_65, OPCODE_66, OPCODE_67
+ , OPCODE_68, OPCODE_69, OPCODE_6A, OPCODE_6B
+ , OPCODE_6C, OPCODE_6D, OPCODE_6E, OPCODE_6F
+ , OPCODE_70, OPCODE_71, OPCODE_72, OPCODE_73
+ , OPCODE_74, OPCODE_75, OPCODE_76, OPCODE_77
+ , OPCODE_78, OPCODE_79, OPCODE_7A, OPCODE_7B
+ , OPCODE_7C, OPCODE_7D, OPCODE_7E, OPCODE_7F
+ , OPCODE_80, OPCODE_81, OPCODE_82, OPCODE_83
+ , OPCODE_84, OPCODE_85, OPCODE_86, OPCODE_87
+ , OPCODE_88, OPCODE_89, OPCODE_8A, OPCODE_8B
+ , OPCODE_8C, OPCODE_8D, OPCODE_8E, OPCODE_8F
+ , OPCODE_90, OPCODE_91, OPCODE_92, OPCODE_93
+ , OPCODE_94, OPCODE_95, OPCODE_96, OPCODE_97
+ , OPCODE_98, OPCODE_99, OPCODE_9A, OPCODE_9B
+ , OPCODE_9C, OPCODE_9D, OPCODE_9E, OPCODE_9F
+ , OPCODE_A0, OPCODE_A1, OPCODE_A2, OPCODE_A3
+ , OPCODE_A4, OPCODE_A5, OPCODE_A6, OPCODE_A7
+ , OPCODE_A8, OPCODE_A9, OPCODE_AA, OPCODE_AB
+ , OPCODE_AC, OPCODE_AD, OPCODE_AE, OPCODE_AF
+ , OPCODE_B0, OPCODE_B1, OPCODE_B2, OPCODE_B3
+ , OPCODE_B4, OPCODE_B5, OPCODE_B6, OPCODE_B7
+ , OPCODE_B8, OPCODE_B9, OPCODE_BA, OPCODE_BB
+ , OPCODE_BC, OPCODE_BD, OPCODE_BE, OPCODE_BF
+ , OPCODE_C0, OPCODE_C1, OPCODE_C2, OPCODE_C3
+ , OPCODE_C4, OPCODE_C5, OPCODE_C6, OPCODE_C7
+ , OPCODE_C8, OPCODE_C9, OPCODE_CA, OPCODE_CB
+ , OPCODE_CC, OPCODE_CD, OPCODE_CE, OPCODE_CF
+ , OPCODE_D0, OPCODE_D1, OPCODE_D2, OPCODE_D3
+ , OPCODE_D4, OPCODE_D5, OPCODE_D6, OPCODE_D7
+ , OPCODE_D8, OPCODE_D9, OPCODE_DA, OPCODE_DB
+ , OPCODE_DC, OPCODE_DD, OPCODE_DE, OPCODE_DF
+ , OPCODE_E0, OPCODE_E1, OPCODE_E2, OPCODE_E3
+ , OPCODE_E4, OPCODE_E5, OPCODE_E6, OPCODE_E7
+ , OPCODE_E8, OPCODE_E9, OPCODE_EA, OPCODE_EB
+ , OPCODE_EC, OPCODE_ED, OPCODE_EE, OPCODE_EF
+ , OPCODE_F0, OPCODE_F1, OPCODE_F2, OPCODE_F3
+ , OPCODE_F4, OPCODE_F5, OPCODE_F6, OPCODE_F7
+ , OPCODE_F8, OPCODE_F9, OPCODE_FA, OPCODE_FB
+ , OPCODE_FC, OPCODE_FD, OPCODE_FE, OPCODE_FF
+} INSN_OPCODE;
+
+/* Enum declaration for insn opcode2 enums.  */
+typedef enum insn_opcode2 {
+  OPCODE2_0, OPCODE2_1, OPCODE2_2, OPCODE2_3
+ , OPCODE2_4, OPCODE2_5, OPCODE2_6, OPCODE2_7
+ , OPCODE2_8, OPCODE2_9, OPCODE2_A, OPCODE2_B
+ , OPCODE2_C, OPCODE2_D, OPCODE2_E, OPCODE2_F
+} INSN_OPCODE2;
+
+/* Enum declaration for insn m3 enums.  */
+typedef enum insn_m3 {
+  M3_0, M3_1
+} INSN_M3;
+
+/* Enum declaration for insn m3 enums.  */
+typedef enum insn_m2 {
+  M2_0, M2_1
+} INSN_M2;
+
+/* Enum declaration for insn m1 enums.  */
+typedef enum insn_m1 {
+  M1_0, M1_1
+} INSN_M1;
+
+/* Enum declaration for insn zero enums.  */
+typedef enum insn_zero {
+  ZERO_0
+} INSN_ZERO;
+
+/* Enum declaration for insn mode a enums.  */
+typedef enum insn_modea {
+  MODEA_OFFSET, MODEA_INDIRECT_OFFSET
+} INSN_MODEA;
+
+/* Enum declaration for insn zero a enums.  */
+typedef enum insn_zeroa {
+  ZEROA_0
+} INSN_ZEROA;
+
+/* Enum declaration for insn mode b enums.  */
+typedef enum insn_modeb {
+  MODEB_ILL0, MODEB_ILL1, MODEB_ILL2, MODEB_ILL3
+ , MODEB_INDIRECT, MODEB_IP_DISP, MODEB_RES6, MODEB_INDIRECT_INDEX
+ , MODEB_ILL8, MODEB_ILL9, MODEB_ILL10, MODEB_ILL11
+ , MODEB_DISP, MODEB_INDIRECT_DISP, MODEB_INDEX_DISP, MODEB_INDIRECT_INDEX_DISP
+} INSN_MODEB;
+
+/* Enum declaration for insn zero b enums.  */
+typedef enum insn_zerob {
+  ZEROB_0
+} INSN_ZEROB;
+
+/* Enum declaration for insn branch m1 enums.  */
+typedef enum insn_br_m1 {
+  BR_M1_0, BR_M1_1
+} INSN_BR_M1;
+
+/* Enum declaration for insn branch zero enums.  */
+typedef enum insn_br_zero {
+  BR_ZERO_0
+} INSN_BR_ZERO;
+
+/* Enum declaration for insn ctrl zero enums.  */
+typedef enum insn_ctrl_zero {
+  CTRL_ZERO_0
+} INSN_CTRL_ZERO;
+
+/* Enum declaration for general registers.  */
+typedef enum h_gr {
+  H_GR_FP = 31, H_GR_SP = 1, H_GR_R0 = 0, H_GR_R1 = 1
+ , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
+ , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
+ , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
+ , H_GR_R14 = 14, H_GR_R15 = 15, H_GR_G0 = 16, H_GR_G1 = 17
+ , H_GR_G2 = 18, H_GR_G3 = 19, H_GR_G4 = 20, H_GR_G5 = 21
+ , H_GR_G6 = 22, H_GR_G7 = 23, H_GR_G8 = 24, H_GR_G9 = 25
+ , H_GR_G10 = 26, H_GR_G11 = 27, H_GR_G12 = 28, H_GR_G13 = 29
+ , H_GR_G14 = 30, H_GR_G15 = 31
+} H_GR;
+
+/* Enum declaration for condition code.  */
+typedef enum h_cc {
+  H_CC_CC
+} H_CC;
+
+/* Attributes.  */
+
+/* Enum declaration for machine type selection.  */
+typedef enum mach_attr {
+  MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX
+} MACH_ATTR;
+
+/* Number of architecture variants.  */
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support.  */
+
+extern const struct cgen_ifld i960_cgen_ifld_table[];
+
+/* Ifield attribute indices.  */
+
+/* Enum declaration for cgen_ifld attrs.  */
+typedef enum cgen_ifld_attr {
+  CGEN_IFLD_MACH, CGEN_IFLD_NBOOLS, CGEN_IFLD_START_BOOL = 31, CGEN_IFLD_VIRTUAL
+ , CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld.  */
+#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_NBOOLS)
+
+/* Enum declaration for i960 ifield types.  */
+typedef enum ifield_type {
+  I960_F_NIL, I960_F_OPCODE, I960_F_SRCDST, I960_F_SRC2
+ , I960_F_M3, I960_F_M2, I960_F_M1, I960_F_OPCODE2
+ , I960_F_ZERO, I960_F_SRC1, I960_F_ABASE, I960_F_MODEA
+ , I960_F_ZEROA, I960_F_OFFSET, I960_F_MODEB, I960_F_SCALE
+ , I960_F_ZEROB, I960_F_INDEX, I960_F_OPTDISP, I960_F_BR_SRC1
+ , I960_F_BR_SRC2, I960_F_BR_M1, I960_F_BR_DISP, I960_F_BR_ZERO
+ , I960_F_CTRL_DISP, I960_F_CTRL_ZERO, I960_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) I960_F_MAX)
+
+/* Hardware attribute indices.  */
+
+/* Enum declaration for cgen_hw attrs.  */
+typedef enum cgen_hw_attr {
+  CGEN_HW_MACH, CGEN_HW_NBOOLS, CGEN_HW_START_BOOL = 31, CGEN_HW_VIRTUAL
+ , CGEN_HW_UNSIGNED, CGEN_HW_SIGNED, CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS
+ , CGEN_HW_PC, CGEN_HW_PROFILE
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw.  */
+#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_NBOOLS)
+
+/* Enum declaration for i960 hardware types.  */
+typedef enum hw_type {
+  HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
+ , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC
+ , HW_MAX
+} HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices.  */
+
+/* Enum declaration for cgen_operand attrs.  */
+typedef enum cgen_operand_attr {
+  CGEN_OPERAND_MACH, CGEN_OPERAND_NBOOLS, CGEN_OPERAND_START_BOOL = 31, CGEN_OPERAND_VIRTUAL
+ , CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand.  */
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_NBOOLS)
+
+/* Enum declaration for i960 operand types.  */
+typedef enum cgen_operand_type {
+  I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST
+ , I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE
+ , I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP
+ , I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1
+ , I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types.  */
+#define MAX_OPERANDS ((int) I960_OPERAND_MAX)
+
+/* Maximum number of operands referenced by any insn.  */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices.  */
+
+/* Enum declaration for cgen_insn attrs.  */
+typedef enum cgen_insn_attr {
+  CGEN_INSN_MACH, CGEN_INSN_NBOOLS, CGEN_INSN_START_BOOL = 31, CGEN_INSN_ALIAS
+ , CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI
+ , CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX, CGEN_INSN_NO_DIS
+ , CGEN_INSN_PBB
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn.  */
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_NBOOLS)
+
+/* cgen.h uses things we just defined.  */
+#include "opcode/cgen.h"
+
+/* Attributes.  */
+extern const CGEN_ATTR_TABLE i960_cgen_hw_attr_table[];
+extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
+
+/* Hardware decls.  */
+
+extern CGEN_KEYWORD i960_cgen_opval_h_gr;
+extern CGEN_KEYWORD i960_cgen_opval_h_cc;
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+
+#endif /* I960_CPU_H */
diff --git a/sim/i960/i960-opc.h b/sim/i960/i960-opc.h
new file mode 100644
index 00000000000..a454ab371a0
--- /dev/null
+++ b/sim/i960/i960-opc.h
@@ -0,0 +1,156 @@
+/* Instruction opcode header for i960.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef I960_OPC_H
+#define I960_OPC_H
+
+/* -- opc.h */
+
+#undef CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 256
+#undef CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value) ((unsigned char *) (buffer))[3]
+
+/* ??? Until cgen disassembler complete and functioning well, redirect back
+   to old disassembler.  */
+#define CGEN_PRINT_INSN(od, pc, info) print_insn_i960_orig (pc, info)
+
+/* -- */
+/* Enum declaration for i960 instruction types.  */
+typedef enum cgen_insn_type {
+  I960_INSN_INVALID, I960_INSN_MULO, I960_INSN_MULO1, I960_INSN_MULO2
+ , I960_INSN_MULO3, I960_INSN_REMO, I960_INSN_REMO1, I960_INSN_REMO2
+ , I960_INSN_REMO3, I960_INSN_DIVO, I960_INSN_DIVO1, I960_INSN_DIVO2
+ , I960_INSN_DIVO3, I960_INSN_REMI, I960_INSN_REMI1, I960_INSN_REMI2
+ , I960_INSN_REMI3, I960_INSN_DIVI, I960_INSN_DIVI1, I960_INSN_DIVI2
+ , I960_INSN_DIVI3, I960_INSN_ADDO, I960_INSN_ADDO1, I960_INSN_ADDO2
+ , I960_INSN_ADDO3, I960_INSN_SUBO, I960_INSN_SUBO1, I960_INSN_SUBO2
+ , I960_INSN_SUBO3, I960_INSN_NOTBIT, I960_INSN_NOTBIT1, I960_INSN_NOTBIT2
+ , I960_INSN_NOTBIT3, I960_INSN_AND, I960_INSN_AND1, I960_INSN_AND2
+ , I960_INSN_AND3, I960_INSN_ANDNOT, I960_INSN_ANDNOT1, I960_INSN_ANDNOT2
+ , I960_INSN_ANDNOT3, I960_INSN_SETBIT, I960_INSN_SETBIT1, I960_INSN_SETBIT2
+ , I960_INSN_SETBIT3, I960_INSN_NOTAND, I960_INSN_NOTAND1, I960_INSN_NOTAND2
+ , I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2
+ , I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2
+ , I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2
+ , I960_INSN_NOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2
+ , I960_INSN_NOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2
+ , I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2
+ , I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2
+ , I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2
+ , I960_INSN_SHLI3, I960_INSN_SHRI, I960_INSN_SHRI1, I960_INSN_SHRI2
+ , I960_INSN_SHRI3, I960_INSN_EMUL, I960_INSN_EMUL1, I960_INSN_EMUL2
+ , I960_INSN_EMUL3, I960_INSN_MOV, I960_INSN_MOV1, I960_INSN_MOVL
+ , I960_INSN_MOVL1, I960_INSN_MOVT, I960_INSN_MOVT1, I960_INSN_MOVQ
+ , I960_INSN_MOVQ1, I960_INSN_MODPC, I960_INSN_MODAC, I960_INSN_LDA_OFFSET
+ , I960_INSN_LDA_INDIRECT_OFFSET, I960_INSN_LDA_INDIRECT, I960_INSN_LDA_INDIRECT_INDEX, I960_INSN_LDA_DISP
+ , I960_INSN_LDA_INDIRECT_DISP, I960_INSN_LDA_INDEX_DISP, I960_INSN_LDA_INDIRECT_INDEX_DISP, I960_INSN_LD_OFFSET
+ , I960_INSN_LD_INDIRECT_OFFSET, I960_INSN_LD_INDIRECT, I960_INSN_LD_INDIRECT_INDEX, I960_INSN_LD_DISP
+ , I960_INSN_LD_INDIRECT_DISP, I960_INSN_LD_INDEX_DISP, I960_INSN_LD_INDIRECT_INDEX_DISP, I960_INSN_LDOB_OFFSET
+ , I960_INSN_LDOB_INDIRECT_OFFSET, I960_INSN_LDOB_INDIRECT, I960_INSN_LDOB_INDIRECT_INDEX, I960_INSN_LDOB_DISP
+ , I960_INSN_LDOB_INDIRECT_DISP, I960_INSN_LDOB_INDEX_DISP, I960_INSN_LDOB_INDIRECT_INDEX_DISP, I960_INSN_LDOS_OFFSET
+ , I960_INSN_LDOS_INDIRECT_OFFSET, I960_INSN_LDOS_INDIRECT, I960_INSN_LDOS_INDIRECT_INDEX, I960_INSN_LDOS_DISP
+ , I960_INSN_LDOS_INDIRECT_DISP, I960_INSN_LDOS_INDEX_DISP, I960_INSN_LDOS_INDIRECT_INDEX_DISP, I960_INSN_LDIB_OFFSET
+ , I960_INSN_LDIB_INDIRECT_OFFSET, I960_INSN_LDIB_INDIRECT, I960_INSN_LDIB_INDIRECT_INDEX, I960_INSN_LDIB_DISP
+ , I960_INSN_LDIB_INDIRECT_DISP, I960_INSN_LDIB_INDEX_DISP, I960_INSN_LDIB_INDIRECT_INDEX_DISP, I960_INSN_LDIS_OFFSET
+ , I960_INSN_LDIS_INDIRECT_OFFSET, I960_INSN_LDIS_INDIRECT, I960_INSN_LDIS_INDIRECT_INDEX, I960_INSN_LDIS_DISP
+ , I960_INSN_LDIS_INDIRECT_DISP, I960_INSN_LDIS_INDEX_DISP, I960_INSN_LDIS_INDIRECT_INDEX_DISP, I960_INSN_LDL_OFFSET
+ , I960_INSN_LDL_INDIRECT_OFFSET, I960_INSN_LDL_INDIRECT, I960_INSN_LDL_INDIRECT_INDEX, I960_INSN_LDL_DISP
+ , I960_INSN_LDL_INDIRECT_DISP, I960_INSN_LDL_INDEX_DISP, I960_INSN_LDL_INDIRECT_INDEX_DISP, I960_INSN_LDT_OFFSET
+ , I960_INSN_LDT_INDIRECT_OFFSET, I960_INSN_LDT_INDIRECT, I960_INSN_LDT_INDIRECT_INDEX, I960_INSN_LDT_DISP
+ , I960_INSN_LDT_INDIRECT_DISP, I960_INSN_LDT_INDEX_DISP, I960_INSN_LDT_INDIRECT_INDEX_DISP, I960_INSN_LDQ_OFFSET
+ , I960_INSN_LDQ_INDIRECT_OFFSET, I960_INSN_LDQ_INDIRECT, I960_INSN_LDQ_INDIRECT_INDEX, I960_INSN_LDQ_DISP
+ , I960_INSN_LDQ_INDIRECT_DISP, I960_INSN_LDQ_INDEX_DISP, I960_INSN_LDQ_INDIRECT_INDEX_DISP, I960_INSN_ST_OFFSET
+ , I960_INSN_ST_INDIRECT_OFFSET, I960_INSN_ST_INDIRECT, I960_INSN_ST_INDIRECT_INDEX, I960_INSN_ST_DISP
+ , I960_INSN_ST_INDIRECT_DISP, I960_INSN_ST_INDEX_DISP, I960_INSN_ST_INDIRECT_INDEX_DISP, I960_INSN_STOB_OFFSET
+ , I960_INSN_STOB_INDIRECT_OFFSET, I960_INSN_STOB_INDIRECT, I960_INSN_STOB_INDIRECT_INDEX, I960_INSN_STOB_DISP
+ , I960_INSN_STOB_INDIRECT_DISP, I960_INSN_STOB_INDEX_DISP, I960_INSN_STOB_INDIRECT_INDEX_DISP, I960_INSN_STOS_OFFSET
+ , I960_INSN_STOS_INDIRECT_OFFSET, I960_INSN_STOS_INDIRECT, I960_INSN_STOS_INDIRECT_INDEX, I960_INSN_STOS_DISP
+ , I960_INSN_STOS_INDIRECT_DISP, I960_INSN_STOS_INDEX_DISP, I960_INSN_STOS_INDIRECT_INDEX_DISP, I960_INSN_STL_OFFSET
+ , I960_INSN_STL_INDIRECT_OFFSET, I960_INSN_STL_INDIRECT, I960_INSN_STL_INDIRECT_INDEX, I960_INSN_STL_DISP
+ , I960_INSN_STL_INDIRECT_DISP, I960_INSN_STL_INDEX_DISP, I960_INSN_STL_INDIRECT_INDEX_DISP, I960_INSN_STT_OFFSET
+ , I960_INSN_STT_INDIRECT_OFFSET, I960_INSN_STT_INDIRECT, I960_INSN_STT_INDIRECT_INDEX, I960_INSN_STT_DISP
+ , I960_INSN_STT_INDIRECT_DISP, I960_INSN_STT_INDEX_DISP, I960_INSN_STT_INDIRECT_INDEX_DISP, I960_INSN_STQ_OFFSET
+ , I960_INSN_STQ_INDIRECT_OFFSET, I960_INSN_STQ_INDIRECT, I960_INSN_STQ_INDIRECT_INDEX, I960_INSN_STQ_DISP
+ , I960_INSN_STQ_INDIRECT_DISP, I960_INSN_STQ_INDEX_DISP, I960_INSN_STQ_INDIRECT_INDEX_DISP, I960_INSN_CMPOBE_REG
+ , I960_INSN_CMPOBE_LIT, I960_INSN_CMPOBNE_REG, I960_INSN_CMPOBNE_LIT, I960_INSN_CMPOBL_REG
+ , I960_INSN_CMPOBL_LIT, I960_INSN_CMPOBLE_REG, I960_INSN_CMPOBLE_LIT, I960_INSN_CMPOBG_REG
+ , I960_INSN_CMPOBG_LIT, I960_INSN_CMPOBGE_REG, I960_INSN_CMPOBGE_LIT, I960_INSN_CMPIBE_REG
+ , I960_INSN_CMPIBE_LIT, I960_INSN_CMPIBNE_REG, I960_INSN_CMPIBNE_LIT, I960_INSN_CMPIBL_REG
+ , I960_INSN_CMPIBL_LIT, I960_INSN_CMPIBLE_REG, I960_INSN_CMPIBLE_LIT, I960_INSN_CMPIBG_REG
+ , I960_INSN_CMPIBG_LIT, I960_INSN_CMPIBGE_REG, I960_INSN_CMPIBGE_LIT, I960_INSN_BBC_REG
+ , I960_INSN_BBC_LIT, I960_INSN_BBS_REG, I960_INSN_BBS_LIT, I960_INSN_CMPI
+ , I960_INSN_CMPI1, I960_INSN_CMPI2, I960_INSN_CMPI3, I960_INSN_CMPO
+ , I960_INSN_CMPO1, I960_INSN_CMPO2, I960_INSN_CMPO3, I960_INSN_TESTNO_REG
+ , I960_INSN_TESTG_REG, I960_INSN_TESTE_REG, I960_INSN_TESTGE_REG, I960_INSN_TESTL_REG
+ , I960_INSN_TESTNE_REG, I960_INSN_TESTLE_REG, I960_INSN_TESTO_REG, I960_INSN_BNO
+ , I960_INSN_BG, I960_INSN_BE, I960_INSN_BGE, I960_INSN_BL
+ , I960_INSN_BNE, I960_INSN_BLE, I960_INSN_BO, I960_INSN_B
+ , I960_INSN_BX_INDIRECT_OFFSET, I960_INSN_BX_INDIRECT, I960_INSN_BX_INDIRECT_INDEX, I960_INSN_BX_DISP
+ , I960_INSN_BX_INDIRECT_DISP, I960_INSN_CALLX_DISP, I960_INSN_CALLX_INDIRECT, I960_INSN_CALLX_INDIRECT_OFFSET
+ , I960_INSN_RET, I960_INSN_CALLS, I960_INSN_FMARK, I960_INSN_FLUSHREG
+ , I960_INSN_MAX
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder.  */
+#define CGEN_INSN_INVALID I960_INSN_INVALID
+
+/* Total number of insns in table.  */
+#define MAX_INSNS ((int) I960_INSN_MAX)
+
+/* This struct records data prior to insertion or after extraction.  */
+struct cgen_fields
+{
+  int length;
+  long f_nil;
+  long f_opcode;
+  long f_srcdst;
+  long f_src2;
+  long f_m3;
+  long f_m2;
+  long f_m1;
+  long f_opcode2;
+  long f_zero;
+  long f_src1;
+  long f_abase;
+  long f_modea;
+  long f_zeroa;
+  long f_offset;
+  long f_modeb;
+  long f_scale;
+  long f_zerob;
+  long f_index;
+  long f_optdisp;
+  long f_br_src1;
+  long f_br_src2;
+  long f_br_m1;
+  long f_br_disp;
+  long f_br_zero;
+  long f_ctrl_disp;
+  long f_ctrl_zero;
+};
+
+
+
+#endif /* I960_OPC_H */
diff --git a/sim/i960/i960-sim.h b/sim/i960/i960-sim.h
new file mode 100644
index 00000000000..e4794daca31
--- /dev/null
+++ b/sim/i960/i960-sim.h
@@ -0,0 +1,49 @@
+#ifndef I960_SIM_H
+#define I960_SIM_H
+
+/* gdb register numbers */
+/* Copied from gdb/config/i960/tc-i960.h.  */
+#define PCW_REGNUM 32   /* process control word */
+#define ACW_REGNUM 33   /* arithmetic control word */
+#define TCW_REGNUM 34   /* trace control word */
+#define IP_REGNUM  35   /* instruction pointer */
+#define FP0_REGNUM 36   /* First floating point register */
+/* Some registers have more than one name */
+#define PC_REGNUM  IP_REGNUM    /* GDB refers to ip as the Program Counter */
+
+#define GETTWI GETTSI
+#define SETTWI SETTSI
+
+/* Exception, Interrupt, and Trap addresses */
+/* ??? Hack for traps.c.  */
+#define EIT_TRAP_BASE_ADDR	0x40
+
+/* Special purpose traps.  */
+/* ??? Hack for traps.c.  */
+#define TRAP_SYSCALL	0
+#define TRAP_BREAKPOINT	1
+
+/* Cache Purge Control (only exists on early versions of chips) */
+/* ??? Hack for devices.c.  */
+#define MSPR_ADDR 0xfffffff7
+#define MSPR_PURGE 1
+
+/* Cache Control Register */
+/* ??? Hack for devices.c.  */
+#define MCCR_ADDR 0xffffffff
+#define MCCR_CP 0x80
+
+/* Start address and length of all device support.  */
+/* ??? Hack for sim-if.c.  */
+#define I960_DEVICE_ADDR	0xff000000
+#define I960_DEVICE_LEN		0x00ffffff
+
+/* sim_core_attach device argument.  */
+/* ??? Hack for sim-if.c.  */
+extern device i960_devices;
+
+/* FIXME: Temporary, until device support ready.  */
+/* ??? Hack for devices.c.  */
+struct _device { int foo; };
+
+#endif I960_SIM_H
diff --git a/sim/i960/i960.c b/sim/i960/i960.c
new file mode 100644
index 00000000000..9737c521011
--- /dev/null
+++ b/sim/i960/i960.c
@@ -0,0 +1,141 @@
+/* i960 simulator support code
+   Copyright (C) 1998 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_I960BASE
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* The contents of BUF are in target byte order.  */
+
+int
+i960base_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+			 int len)
+{
+  if (rn < 32)
+    SETTWI (buf, a_i960_h_gr_get (current_cpu, rn));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+	SETTWI (buf, a_i960_h_pc_get (current_cpu));
+	break;
+      default :
+	return 0;
+      }
+
+  return -1; /*FIXME*/
+
+}
+
+/* The contents of BUF are in target byte order.  */
+
+int
+i960base_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
+			 int len)
+{
+  if (rn < 32)
+    a_i960_h_gr_set (current_cpu, rn, GETTWI (buf));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+	a_i960_h_pc_set (current_cpu, GETTWI (buf));
+	break;
+      default :
+	return 0;
+      }
+
+  return -1; /*FIXME*/
+}
+
+#if WITH_PROFILE_MODEL_P
+
+/* FIXME: Some of these should be inline or macros.  Later.  */
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+
+void
+i960base_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+
+void
+i960base_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+}
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+
+void
+i960_model_init_insn_cycles (SIM_CPU *cpu, int first_p)
+{
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.  */
+
+void
+i960_model_update_insn_cycles (SIM_CPU *cpu, int last_p)
+{
+}
+
+void
+i960_model_record_cycles (SIM_CPU *cpu, unsigned long cycles)
+{
+}
+
+void
+i960base_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
+{
+}
+
+void
+i960base_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
+{
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+int
+i960base_model_i960KA_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+i960base_model_i960CA_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
diff --git a/sim/i960/mloop.in b/sim/i960/mloop.in
new file mode 100644
index 00000000000..0a3ad4728b6
--- /dev/null
+++ b/sim/i960/mloop.in
@@ -0,0 +1,301 @@
+# Simulator main loop for i960. -*- C -*-
+# Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same.
+# It can't provide more than this, however for illustration's sake the M32R
+# port provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+/*static INLINE*/ const IDESC *
+extract32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+	   ARGBUF *abuf, int fast_p)
+{
+  /* ??? wilson, instructions are 32 bits.  */
+  const IDESC *d = @cpu@_decode (current_cpu, pc, (USI) insn, abuf);
+  @cpu@_fill_argbuf (current_cpu, abuf, d, pc, fast_p);
+  if (! fast_p)
+    {
+      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+    }
+  return d;
+}
+
+#if 0
+/*static INLINE*/ const IDESC *
+/* ??? wilson, Some instructions are 64 bits.  */
+extract64 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn,
+	   ARGBUF *abuf, int fast_p)
+{
+  const IDESC *d = @cpu@_decode (current_cpu, pc, (UDI) insn >> 32, abuf);
+  SEM_SET_CODE (abuf, d, fast_p);
+  abuf->idesc = d;
+  abuf->addr = pc;
+  return d;
+}
+#endif
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+  SEM_PC vpc;
+
+  if (fast_p)
+    {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+    }
+  else
+    {
+#if ! WITH_SEM_SWITCH_FULL
+      ARGBUF *abuf = &sc->argbuf;
+      const IDESC *idesc = abuf->idesc;
+      const CGEN_INSN *insn = idesc->idata;
+#if WITH_SCACHE_PBB
+      int virtual_p = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_VIRTUAL);
+#else
+      int virtual_p = 0;
+#endif
+
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-before */
+	  if (ARGBUF_PROFILE_P (abuf))
+	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
+	  if (PROFILE_MODEL_P (current_cpu))
+	    @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+	  TRACE_INSN_INIT (current_cpu, abuf, 1);
+	  TRACE_INSN (current_cpu, insn,
+		      (const struct argbuf *) abuf, abuf->addr);
+	}
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-after */
+	  if (PROFILE_MODEL_P (current_cpu))
+	    {
+	      int cycles;
+
+	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+	      @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+	    }
+	  TRACE_INSN_FINI (current_cpu, abuf, 1);
+	}
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+    }
+
+  return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+cat <<EOF
+/*xxxinit*/
+EOF
+
+;;
+
+xextract-simple | xextract-scache)
+
+cat <<EOF
+{
+  if ((pc & 3) != 0)
+    {
+      abort ();
+#if 0
+      /* This only occurs when single stepping.
+	 The test is unnecessary otherwise, but the cost is teensy,
+	 compared with decoding/extraction.  */
+      UHI insn = GETIMEMUHI (current_cpu, pc);
+      extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P);
+#endif
+    }
+  else
+    {
+      USI insn = GETIMEMUSI (current_cpu, pc);
+      /* ??? wilson, insns are 32 bits, unless MEMB with displacement, which
+	 has high bit set, bit 12 set, and mode of 5, 12, 13, 14, or 15.  */
+      if (((SI) insn > 0)
+	  || ! (((insn & 0x3000) == 0x3000)
+		|| ((insn & 0x3C00) == 0x1400)))
+	{
+	  extract32 (current_cpu, pc, insn, sc, FAST_P);
+	}
+      else
+	{
+	  UDI llinsn = (((UDI) insn << 32) || GETIMEMUSI (current_cpu, pc+4));
+	  extract64 (current_cpu, pc, llinsn, sc, FAST_P);
+	}
+    }
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+  const IDESC *idesc;
+  int icount = 0;
+
+  if ((pc & 3) != 0)
+    {
+      abort ();
+#if 0
+      /* This only occurs when single stepping.
+	 The test is unnecessary otherwise, but the cost is teensy,
+	 compared with decoding/extraction.  */
+      UHI insn = GETIMEMUHI (current_cpu, pc);
+      idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P);
+      ++sc;
+      --max_insns;
+      ++icount;
+      pc += 2;
+      if (IDESC_CTI_P (idesc))
+	{
+	  SET_CTI_VPC (sc - 1);
+	  goto Finish;
+	}
+#endif
+    }
+
+  while (max_insns > 0)
+    {
+      USI insn = GETIMEMUSI (current_cpu, pc);
+#if 0
+      /* ??? wilson, insns are 32 bits, unless MEMB with displacement, which
+	 has high bit set, bit 12 set, and mode of 5, 12, 13, 14, or 15.  */
+      if (((SI) insn > 0)
+	  || ! (((insn & 0x3000) == 0x3000)
+		|| ((insn & 0x3C00) == 0x1400)))
+	{
+	  idesc = extract32 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+	  ++sc;
+	  --max_insns;
+	  ++icount;
+	  pc += 4;
+	  if (IDESC_CTI_P (idesc))
+	    {
+	      SET_CTI_VPC (sc - 1);
+	      break;
+	    }
+	}
+      else
+	{
+	  idesc = extract64 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+	  ++sc;
+	  --max_insns;
+	  ++icount;
+	  pc += 8;
+	  if (IDESC_CTI_P (idesc))
+	    {
+	      SET_CTI_VPC (sc - 1);
+	      break;
+	    }
+	}
+#else
+      idesc = extract32 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+      ++sc;
+      --max_insns;
+      ++icount;
+      pc += idesc->length;
+      if (IDESC_CTI_P (idesc))
+        {
+          SET_CTI_VPC (sc - 1);
+          break;
+        }
+    }
+#endif
+ Finish:
+  SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, vpc, FAST_P
+# Outputs: vpc
+# vpc is the virtual program counter.
+
+cat <<EOF
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem-switch.c"
+#else
+  vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac
diff --git a/sim/i960/model.c b/sim/i960/model.c
new file mode 100644
index 00000000000..5069eb4e876
--- /dev/null
+++ b/sim/i960/model.c
@@ -0,0 +1,9793 @@
+/* Simulator model support for i960base.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU i960base
+#define WANT_CPU_I960BASE
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+   mechanism.  After all, this is information for profiling.  */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn.  */
+
+static int
+model_i960KA_mulo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_mulo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_mulo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_mulo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remi1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remi2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_remi3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divi1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divi2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_divi3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_addo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_addo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_addo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_addo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_subo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_subo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_subo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_subo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notbit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notbit1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notbit2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notbit3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_and1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_and2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_and3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_andnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_andnot1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_andnot2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_andnot3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_setbit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_setbit1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_setbit2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_setbit3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notand1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notand2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_notand3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_xor1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_xor2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_xor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_or1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_or2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_or3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_nor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_nor1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_nor2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_nor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_not1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_not2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_not3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_clrbit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_clrbit1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_clrbit2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_shri3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_emul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_emul1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_emul2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_emul3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_mov (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_mov1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_movl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_movl1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movl1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_movt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movt.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_movt1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movt1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_movq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_movq1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movq1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_modpc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_modpc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_modac (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_modpc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_lda_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ld_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldib_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldis_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ldq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_st_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_stq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobe_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobe_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobne_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobne_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobl_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobl_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpoble_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpoble_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobg_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobg_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobge_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpobge_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibe_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibe_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibne_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibne_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibl_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibl_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpible_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpible_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibg_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibg_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibge_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpibge_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bbc_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bbc_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bbs_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bbs_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpi1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpi2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpi3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_cmpo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_testno_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_testg_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_teste_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_testge_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_testl_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_testne_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_testle_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_testo_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_be (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_b.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bx_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bx_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bx_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_bx_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_callx_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_callx_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_callx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ret (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_calls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_calls.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_fmark (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_flushreg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_flushreg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_mulo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_mulo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_mulo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_mulo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remi1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remi2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_remi3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divi1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divi2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_divi3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_addo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_addo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_addo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_addo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_subo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_subo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_subo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_subo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notbit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notbit1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notbit2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notbit3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_and1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_and2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_and3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_andnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_andnot1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_andnot2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_andnot3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_setbit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_setbit1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_setbit2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_setbit3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notand1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notand2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_notand3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_xor1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_xor2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_xor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_or1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_or2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_or3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_nor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_nor1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_nor2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_nor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_not1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_not2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_not3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_clrbit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_clrbit1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_clrbit2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_shri3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_emul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_emul1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_emul2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_emul3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_mov (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_mov1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_movl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_movl1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movl1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_movt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movt.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_movt1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movt1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_movq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_movq1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movq1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_modpc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_modpc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_modac (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_modpc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_lda_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ld_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldib_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldis_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ldq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_st_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_stq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobe_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobe_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobne_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobne_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobl_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobl_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpoble_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpoble_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobg_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobg_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobge_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpobge_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibe_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibe_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibne_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibne_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibl_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibl_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpible_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpible_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibg_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibg_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibge_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpibge_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bbc_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bbc_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bbs_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bbs_lit (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpi1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpi2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpi3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpo1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo1.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpo2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo2.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_cmpo3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_testno_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_testg_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_teste_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_testge_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_testl_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_testne_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_testle_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_testo_reg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_be (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_b.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bx_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bx_indirect_index (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bx_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_bx_indirect_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_callx_disp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_callx_indirect (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_callx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ret (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_calls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_calls.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_fmark (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_flushreg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_flushreg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+   entries with it.  */
+
+/* Model timing data for `i960KA'.  */
+
+static const INSN_TIMING i960KA_timing[] = {
+  { I960BASE_INSN_X_INVALID, 0, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_AFTER, 0, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_BEFORE, 0, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_CHAIN, 0, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_BEGIN, 0, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO, model_i960KA_mulo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO1, model_i960KA_mulo1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO2, model_i960KA_mulo2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO3, model_i960KA_mulo3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO, model_i960KA_remo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO1, model_i960KA_remo1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO2, model_i960KA_remo2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO3, model_i960KA_remo3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO, model_i960KA_divo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO1, model_i960KA_divo1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO2, model_i960KA_divo2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO3, model_i960KA_divo3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI, model_i960KA_remi, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI1, model_i960KA_remi1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI2, model_i960KA_remi2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI3, model_i960KA_remi3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI, model_i960KA_divi, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI1, model_i960KA_divi1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI2, model_i960KA_divi2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI3, model_i960KA_divi3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO, model_i960KA_addo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO1, model_i960KA_addo1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO2, model_i960KA_addo2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO3, model_i960KA_addo3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO, model_i960KA_subo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO1, model_i960KA_subo1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO2, model_i960KA_subo2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO3, model_i960KA_subo3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT, model_i960KA_notbit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT1, model_i960KA_notbit1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT2, model_i960KA_notbit2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT3, model_i960KA_notbit3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND, model_i960KA_and, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND1, model_i960KA_and1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND2, model_i960KA_and2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND3, model_i960KA_and3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT, model_i960KA_andnot, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT1, model_i960KA_andnot1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT2, model_i960KA_andnot2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT3, model_i960KA_andnot3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT, model_i960KA_setbit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT1, model_i960KA_setbit1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT2, model_i960KA_setbit2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT3, model_i960KA_setbit3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND, model_i960KA_notand, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND1, model_i960KA_notand1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND2, model_i960KA_notand2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND3, model_i960KA_notand3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR, model_i960KA_xor, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR1, model_i960KA_xor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR2, model_i960KA_xor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR3, model_i960KA_xor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR, model_i960KA_or, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR1, model_i960KA_or1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR2, model_i960KA_or2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR3, model_i960KA_or3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR, model_i960KA_nor, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR1, model_i960KA_nor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR2, model_i960KA_nor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR3, model_i960KA_nor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT, model_i960KA_not, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT1, model_i960KA_not1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT2, model_i960KA_not2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT3, model_i960KA_not3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT, model_i960KA_clrbit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT1, model_i960KA_clrbit1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT2, model_i960KA_clrbit2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT3, model_i960KA_clrbit3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO, model_i960KA_shlo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO1, model_i960KA_shlo1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO2, model_i960KA_shlo2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO3, model_i960KA_shlo3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO, model_i960KA_shro, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO1, model_i960KA_shro1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO2, model_i960KA_shro2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO3, model_i960KA_shro3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI, model_i960KA_shli, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI1, model_i960KA_shli1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI2, model_i960KA_shli2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI3, model_i960KA_shli3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI, model_i960KA_shri, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI1, model_i960KA_shri1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI2, model_i960KA_shri2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI3, model_i960KA_shri3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL, model_i960KA_emul, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL1, model_i960KA_emul1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL2, model_i960KA_emul2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL3, model_i960KA_emul3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOV, model_i960KA_mov, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOV1, model_i960KA_mov1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVL, model_i960KA_movl, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVL1, model_i960KA_movl1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVT, model_i960KA_movt, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVT1, model_i960KA_movt1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVQ, model_i960KA_movq, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVQ1, model_i960KA_movq1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MODPC, model_i960KA_modpc, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MODAC, model_i960KA_modac, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_OFFSET, model_i960KA_lda_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_OFFSET, model_i960KA_lda_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT, model_i960KA_lda_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_INDEX, model_i960KA_lda_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_DISP, model_i960KA_lda_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_DISP, model_i960KA_lda_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDEX_DISP, model_i960KA_lda_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_INDEX_DISP, model_i960KA_lda_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_OFFSET, model_i960KA_ld_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_OFFSET, model_i960KA_ld_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT, model_i960KA_ld_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_INDEX, model_i960KA_ld_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_DISP, model_i960KA_ld_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_DISP, model_i960KA_ld_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDEX_DISP, model_i960KA_ld_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_INDEX_DISP, model_i960KA_ld_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_OFFSET, model_i960KA_ldob_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_OFFSET, model_i960KA_ldob_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT, model_i960KA_ldob_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_INDEX, model_i960KA_ldob_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_DISP, model_i960KA_ldob_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_DISP, model_i960KA_ldob_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDEX_DISP, model_i960KA_ldob_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP, model_i960KA_ldob_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_OFFSET, model_i960KA_ldos_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_OFFSET, model_i960KA_ldos_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT, model_i960KA_ldos_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_INDEX, model_i960KA_ldos_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_DISP, model_i960KA_ldos_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_DISP, model_i960KA_ldos_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDEX_DISP, model_i960KA_ldos_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP, model_i960KA_ldos_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_OFFSET, model_i960KA_ldib_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_OFFSET, model_i960KA_ldib_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT, model_i960KA_ldib_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_INDEX, model_i960KA_ldib_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_DISP, model_i960KA_ldib_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_DISP, model_i960KA_ldib_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDEX_DISP, model_i960KA_ldib_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP, model_i960KA_ldib_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_OFFSET, model_i960KA_ldis_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_OFFSET, model_i960KA_ldis_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT, model_i960KA_ldis_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_INDEX, model_i960KA_ldis_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_DISP, model_i960KA_ldis_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_DISP, model_i960KA_ldis_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDEX_DISP, model_i960KA_ldis_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP, model_i960KA_ldis_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_OFFSET, model_i960KA_ldl_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_OFFSET, model_i960KA_ldl_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT, model_i960KA_ldl_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_INDEX, model_i960KA_ldl_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_DISP, model_i960KA_ldl_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_DISP, model_i960KA_ldl_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDEX_DISP, model_i960KA_ldl_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_INDEX_DISP, model_i960KA_ldl_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_OFFSET, model_i960KA_ldt_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_OFFSET, model_i960KA_ldt_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT, model_i960KA_ldt_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_INDEX, model_i960KA_ldt_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_DISP, model_i960KA_ldt_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_DISP, model_i960KA_ldt_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDEX_DISP, model_i960KA_ldt_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_INDEX_DISP, model_i960KA_ldt_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_OFFSET, model_i960KA_ldq_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_OFFSET, model_i960KA_ldq_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT, model_i960KA_ldq_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_INDEX, model_i960KA_ldq_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_DISP, model_i960KA_ldq_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_DISP, model_i960KA_ldq_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDEX_DISP, model_i960KA_ldq_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP, model_i960KA_ldq_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_OFFSET, model_i960KA_st_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_OFFSET, model_i960KA_st_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT, model_i960KA_st_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_INDEX, model_i960KA_st_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_DISP, model_i960KA_st_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_DISP, model_i960KA_st_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDEX_DISP, model_i960KA_st_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_INDEX_DISP, model_i960KA_st_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_OFFSET, model_i960KA_stob_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_OFFSET, model_i960KA_stob_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT, model_i960KA_stob_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_INDEX, model_i960KA_stob_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_DISP, model_i960KA_stob_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_DISP, model_i960KA_stob_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDEX_DISP, model_i960KA_stob_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_INDEX_DISP, model_i960KA_stob_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_OFFSET, model_i960KA_stos_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_OFFSET, model_i960KA_stos_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT, model_i960KA_stos_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_INDEX, model_i960KA_stos_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_DISP, model_i960KA_stos_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_DISP, model_i960KA_stos_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDEX_DISP, model_i960KA_stos_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_INDEX_DISP, model_i960KA_stos_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_OFFSET, model_i960KA_stl_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_OFFSET, model_i960KA_stl_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT, model_i960KA_stl_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_INDEX, model_i960KA_stl_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_DISP, model_i960KA_stl_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_DISP, model_i960KA_stl_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDEX_DISP, model_i960KA_stl_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_INDEX_DISP, model_i960KA_stl_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_OFFSET, model_i960KA_stt_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_OFFSET, model_i960KA_stt_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT, model_i960KA_stt_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_INDEX, model_i960KA_stt_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_DISP, model_i960KA_stt_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_DISP, model_i960KA_stt_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDEX_DISP, model_i960KA_stt_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_INDEX_DISP, model_i960KA_stt_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_OFFSET, model_i960KA_stq_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_OFFSET, model_i960KA_stq_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT, model_i960KA_stq_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_INDEX, model_i960KA_stq_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_DISP, model_i960KA_stq_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_DISP, model_i960KA_stq_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDEX_DISP, model_i960KA_stq_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_INDEX_DISP, model_i960KA_stq_indirect_index_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBE_REG, model_i960KA_cmpobe_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBE_LIT, model_i960KA_cmpobe_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBNE_REG, model_i960KA_cmpobne_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBNE_LIT, model_i960KA_cmpobne_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBL_REG, model_i960KA_cmpobl_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBL_LIT, model_i960KA_cmpobl_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBLE_REG, model_i960KA_cmpoble_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBLE_LIT, model_i960KA_cmpoble_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBG_REG, model_i960KA_cmpobg_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBG_LIT, model_i960KA_cmpobg_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBGE_REG, model_i960KA_cmpobge_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBGE_LIT, model_i960KA_cmpobge_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBE_REG, model_i960KA_cmpibe_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBE_LIT, model_i960KA_cmpibe_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBNE_REG, model_i960KA_cmpibne_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBNE_LIT, model_i960KA_cmpibne_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBL_REG, model_i960KA_cmpibl_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBL_LIT, model_i960KA_cmpibl_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBLE_REG, model_i960KA_cmpible_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBLE_LIT, model_i960KA_cmpible_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBG_REG, model_i960KA_cmpibg_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBG_LIT, model_i960KA_cmpibg_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBGE_REG, model_i960KA_cmpibge_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBGE_LIT, model_i960KA_cmpibge_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBC_REG, model_i960KA_bbc_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBC_LIT, model_i960KA_bbc_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBS_REG, model_i960KA_bbs_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBS_LIT, model_i960KA_bbs_lit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI, model_i960KA_cmpi, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI1, model_i960KA_cmpi1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI2, model_i960KA_cmpi2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI3, model_i960KA_cmpi3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO, model_i960KA_cmpo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO1, model_i960KA_cmpo1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO2, model_i960KA_cmpo2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO3, model_i960KA_cmpo3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTNO_REG, model_i960KA_testno_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTG_REG, model_i960KA_testg_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTE_REG, model_i960KA_teste_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTGE_REG, model_i960KA_testge_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTL_REG, model_i960KA_testl_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTNE_REG, model_i960KA_testne_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTLE_REG, model_i960KA_testle_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTO_REG, model_i960KA_testo_reg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BNO, model_i960KA_bno, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BG, model_i960KA_bg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BE, model_i960KA_be, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BGE, model_i960KA_bge, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BL, model_i960KA_bl, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BNE, model_i960KA_bne, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BLE, model_i960KA_ble, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BO, model_i960KA_bo, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_B, model_i960KA_b, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT_OFFSET, model_i960KA_bx_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT, model_i960KA_bx_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT_INDEX, model_i960KA_bx_indirect_index, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_DISP, model_i960KA_bx_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT_DISP, model_i960KA_bx_indirect_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLX_DISP, model_i960KA_callx_disp, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLX_INDIRECT, model_i960KA_callx_indirect, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLX_INDIRECT_OFFSET, model_i960KA_callx_indirect_offset, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_RET, model_i960KA_ret, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLS, model_i960KA_calls, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_FMARK, model_i960KA_fmark, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_FLUSHREG, model_i960KA_flushreg, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+};
+
+/* Model timing data for `i960CA'.  */
+
+static const INSN_TIMING i960CA_timing[] = {
+  { I960BASE_INSN_X_INVALID, 0, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_AFTER, 0, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_BEFORE, 0, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_CHAIN, 0, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_X_BEGIN, 0, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO, model_i960CA_mulo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO1, model_i960CA_mulo1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO2, model_i960CA_mulo2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MULO3, model_i960CA_mulo3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO, model_i960CA_remo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO1, model_i960CA_remo1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO2, model_i960CA_remo2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMO3, model_i960CA_remo3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO, model_i960CA_divo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO1, model_i960CA_divo1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO2, model_i960CA_divo2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVO3, model_i960CA_divo3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI, model_i960CA_remi, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI1, model_i960CA_remi1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI2, model_i960CA_remi2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_REMI3, model_i960CA_remi3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI, model_i960CA_divi, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI1, model_i960CA_divi1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI2, model_i960CA_divi2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_DIVI3, model_i960CA_divi3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO, model_i960CA_addo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO1, model_i960CA_addo1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO2, model_i960CA_addo2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ADDO3, model_i960CA_addo3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO, model_i960CA_subo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO1, model_i960CA_subo1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO2, model_i960CA_subo2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SUBO3, model_i960CA_subo3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT, model_i960CA_notbit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT1, model_i960CA_notbit1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT2, model_i960CA_notbit2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTBIT3, model_i960CA_notbit3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND, model_i960CA_and, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND1, model_i960CA_and1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND2, model_i960CA_and2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_AND3, model_i960CA_and3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT, model_i960CA_andnot, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT1, model_i960CA_andnot1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT2, model_i960CA_andnot2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ANDNOT3, model_i960CA_andnot3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT, model_i960CA_setbit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT1, model_i960CA_setbit1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT2, model_i960CA_setbit2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SETBIT3, model_i960CA_setbit3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND, model_i960CA_notand, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND1, model_i960CA_notand1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND2, model_i960CA_notand2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOTAND3, model_i960CA_notand3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR, model_i960CA_xor, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR1, model_i960CA_xor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR2, model_i960CA_xor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_XOR3, model_i960CA_xor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR, model_i960CA_or, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR1, model_i960CA_or1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR2, model_i960CA_or2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_OR3, model_i960CA_or3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR, model_i960CA_nor, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR1, model_i960CA_nor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR2, model_i960CA_nor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOR3, model_i960CA_nor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT, model_i960CA_not, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT1, model_i960CA_not1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT2, model_i960CA_not2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_NOT3, model_i960CA_not3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT, model_i960CA_clrbit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT1, model_i960CA_clrbit1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT2, model_i960CA_clrbit2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CLRBIT3, model_i960CA_clrbit3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO, model_i960CA_shlo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO1, model_i960CA_shlo1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO2, model_i960CA_shlo2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLO3, model_i960CA_shlo3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO, model_i960CA_shro, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO1, model_i960CA_shro1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO2, model_i960CA_shro2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRO3, model_i960CA_shro3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI, model_i960CA_shli, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI1, model_i960CA_shli1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI2, model_i960CA_shli2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHLI3, model_i960CA_shli3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI, model_i960CA_shri, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI1, model_i960CA_shri1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI2, model_i960CA_shri2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_SHRI3, model_i960CA_shri3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL, model_i960CA_emul, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL1, model_i960CA_emul1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL2, model_i960CA_emul2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_EMUL3, model_i960CA_emul3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOV, model_i960CA_mov, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOV1, model_i960CA_mov1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVL, model_i960CA_movl, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVL1, model_i960CA_movl1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVT, model_i960CA_movt, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVT1, model_i960CA_movt1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVQ, model_i960CA_movq, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MOVQ1, model_i960CA_movq1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MODPC, model_i960CA_modpc, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_MODAC, model_i960CA_modac, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_OFFSET, model_i960CA_lda_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_OFFSET, model_i960CA_lda_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT, model_i960CA_lda_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_INDEX, model_i960CA_lda_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_DISP, model_i960CA_lda_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_DISP, model_i960CA_lda_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDEX_DISP, model_i960CA_lda_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDA_INDIRECT_INDEX_DISP, model_i960CA_lda_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_OFFSET, model_i960CA_ld_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_OFFSET, model_i960CA_ld_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT, model_i960CA_ld_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_INDEX, model_i960CA_ld_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_DISP, model_i960CA_ld_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_DISP, model_i960CA_ld_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDEX_DISP, model_i960CA_ld_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LD_INDIRECT_INDEX_DISP, model_i960CA_ld_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_OFFSET, model_i960CA_ldob_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_OFFSET, model_i960CA_ldob_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT, model_i960CA_ldob_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_INDEX, model_i960CA_ldob_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_DISP, model_i960CA_ldob_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_DISP, model_i960CA_ldob_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDEX_DISP, model_i960CA_ldob_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP, model_i960CA_ldob_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_OFFSET, model_i960CA_ldos_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_OFFSET, model_i960CA_ldos_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT, model_i960CA_ldos_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_INDEX, model_i960CA_ldos_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_DISP, model_i960CA_ldos_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_DISP, model_i960CA_ldos_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDEX_DISP, model_i960CA_ldos_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP, model_i960CA_ldos_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_OFFSET, model_i960CA_ldib_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_OFFSET, model_i960CA_ldib_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT, model_i960CA_ldib_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_INDEX, model_i960CA_ldib_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_DISP, model_i960CA_ldib_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_DISP, model_i960CA_ldib_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDEX_DISP, model_i960CA_ldib_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP, model_i960CA_ldib_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_OFFSET, model_i960CA_ldis_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_OFFSET, model_i960CA_ldis_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT, model_i960CA_ldis_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_INDEX, model_i960CA_ldis_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_DISP, model_i960CA_ldis_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_DISP, model_i960CA_ldis_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDEX_DISP, model_i960CA_ldis_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP, model_i960CA_ldis_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_OFFSET, model_i960CA_ldl_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_OFFSET, model_i960CA_ldl_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT, model_i960CA_ldl_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_INDEX, model_i960CA_ldl_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_DISP, model_i960CA_ldl_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_DISP, model_i960CA_ldl_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDEX_DISP, model_i960CA_ldl_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDL_INDIRECT_INDEX_DISP, model_i960CA_ldl_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_OFFSET, model_i960CA_ldt_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_OFFSET, model_i960CA_ldt_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT, model_i960CA_ldt_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_INDEX, model_i960CA_ldt_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_DISP, model_i960CA_ldt_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_DISP, model_i960CA_ldt_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDEX_DISP, model_i960CA_ldt_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDT_INDIRECT_INDEX_DISP, model_i960CA_ldt_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_OFFSET, model_i960CA_ldq_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_OFFSET, model_i960CA_ldq_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT, model_i960CA_ldq_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_INDEX, model_i960CA_ldq_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_DISP, model_i960CA_ldq_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_DISP, model_i960CA_ldq_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDEX_DISP, model_i960CA_ldq_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP, model_i960CA_ldq_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_OFFSET, model_i960CA_st_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_OFFSET, model_i960CA_st_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT, model_i960CA_st_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_INDEX, model_i960CA_st_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_DISP, model_i960CA_st_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_DISP, model_i960CA_st_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDEX_DISP, model_i960CA_st_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_ST_INDIRECT_INDEX_DISP, model_i960CA_st_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_OFFSET, model_i960CA_stob_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_OFFSET, model_i960CA_stob_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT, model_i960CA_stob_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_INDEX, model_i960CA_stob_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_DISP, model_i960CA_stob_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_DISP, model_i960CA_stob_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDEX_DISP, model_i960CA_stob_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOB_INDIRECT_INDEX_DISP, model_i960CA_stob_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_OFFSET, model_i960CA_stos_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_OFFSET, model_i960CA_stos_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT, model_i960CA_stos_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_INDEX, model_i960CA_stos_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_DISP, model_i960CA_stos_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_DISP, model_i960CA_stos_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDEX_DISP, model_i960CA_stos_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STOS_INDIRECT_INDEX_DISP, model_i960CA_stos_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_OFFSET, model_i960CA_stl_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_OFFSET, model_i960CA_stl_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT, model_i960CA_stl_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_INDEX, model_i960CA_stl_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_DISP, model_i960CA_stl_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_DISP, model_i960CA_stl_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDEX_DISP, model_i960CA_stl_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STL_INDIRECT_INDEX_DISP, model_i960CA_stl_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_OFFSET, model_i960CA_stt_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_OFFSET, model_i960CA_stt_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT, model_i960CA_stt_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_INDEX, model_i960CA_stt_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_DISP, model_i960CA_stt_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_DISP, model_i960CA_stt_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDEX_DISP, model_i960CA_stt_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STT_INDIRECT_INDEX_DISP, model_i960CA_stt_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_OFFSET, model_i960CA_stq_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_OFFSET, model_i960CA_stq_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT, model_i960CA_stq_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_INDEX, model_i960CA_stq_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_DISP, model_i960CA_stq_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_DISP, model_i960CA_stq_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDEX_DISP, model_i960CA_stq_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_STQ_INDIRECT_INDEX_DISP, model_i960CA_stq_indirect_index_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBE_REG, model_i960CA_cmpobe_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBE_LIT, model_i960CA_cmpobe_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBNE_REG, model_i960CA_cmpobne_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBNE_LIT, model_i960CA_cmpobne_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBL_REG, model_i960CA_cmpobl_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBL_LIT, model_i960CA_cmpobl_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBLE_REG, model_i960CA_cmpoble_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBLE_LIT, model_i960CA_cmpoble_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBG_REG, model_i960CA_cmpobg_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBG_LIT, model_i960CA_cmpobg_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBGE_REG, model_i960CA_cmpobge_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPOBGE_LIT, model_i960CA_cmpobge_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBE_REG, model_i960CA_cmpibe_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBE_LIT, model_i960CA_cmpibe_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBNE_REG, model_i960CA_cmpibne_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBNE_LIT, model_i960CA_cmpibne_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBL_REG, model_i960CA_cmpibl_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBL_LIT, model_i960CA_cmpibl_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBLE_REG, model_i960CA_cmpible_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBLE_LIT, model_i960CA_cmpible_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBG_REG, model_i960CA_cmpibg_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBG_LIT, model_i960CA_cmpibg_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBGE_REG, model_i960CA_cmpibge_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPIBGE_LIT, model_i960CA_cmpibge_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBC_REG, model_i960CA_bbc_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBC_LIT, model_i960CA_bbc_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBS_REG, model_i960CA_bbs_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BBS_LIT, model_i960CA_bbs_lit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI, model_i960CA_cmpi, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI1, model_i960CA_cmpi1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI2, model_i960CA_cmpi2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPI3, model_i960CA_cmpi3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO, model_i960CA_cmpo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO1, model_i960CA_cmpo1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO2, model_i960CA_cmpo2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CMPO3, model_i960CA_cmpo3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTNO_REG, model_i960CA_testno_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTG_REG, model_i960CA_testg_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTE_REG, model_i960CA_teste_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTGE_REG, model_i960CA_testge_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTL_REG, model_i960CA_testl_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTNE_REG, model_i960CA_testne_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTLE_REG, model_i960CA_testle_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_TESTO_REG, model_i960CA_testo_reg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BNO, model_i960CA_bno, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BG, model_i960CA_bg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BE, model_i960CA_be, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BGE, model_i960CA_bge, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BL, model_i960CA_bl, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BNE, model_i960CA_bne, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BLE, model_i960CA_ble, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BO, model_i960CA_bo, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_B, model_i960CA_b, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT_OFFSET, model_i960CA_bx_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT, model_i960CA_bx_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT_INDEX, model_i960CA_bx_indirect_index, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_DISP, model_i960CA_bx_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_BX_INDIRECT_DISP, model_i960CA_bx_indirect_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLX_DISP, model_i960CA_callx_disp, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLX_INDIRECT, model_i960CA_callx_indirect, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLX_INDIRECT_OFFSET, model_i960CA_callx_indirect_offset, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_RET, model_i960CA_ret, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_CALLS, model_i960CA_calls, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_FMARK, model_i960CA_fmark, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+  { I960BASE_INSN_FLUSHREG, model_i960CA_flushreg, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+i960KA_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_I960KA_DATA));
+}
+
+static void
+i960CA_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_I960CA_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL i960_ka_sa_models[] =
+{
+  { "i960KA", & i960_ka_sa_mach, MODEL_I960KA, TIMING_DATA (& i960KA_timing[0]), i960KA_model_init },
+  { 0 }
+};
+
+static const MODEL i960_ca_models[] =
+{
+  { "i960CA", & i960_ca_mach, MODEL_I960CA, TIMING_DATA (& i960CA_timing[0]), i960CA_model_init },
+  { 0 }
+};
+
+/* The properties of this cpu's implementation.  */
+
+static const MACH_IMP_PROPERTIES i960base_imp_properties =
+{
+  sizeof (SIM_CPU),
+#if WITH_SCACHE
+  sizeof (SCACHE)
+#else
+  0
+#endif
+};
+
+
+static void
+i960base_prepare_run (SIM_CPU *cpu)
+{
+  if (CPU_IDESC (cpu) == NULL)
+    i960base_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+i960base_get_idata (SIM_CPU *cpu, int inum)
+{
+  return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+i960_ka_sa_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = i960base_fetch_register;
+  CPU_REG_STORE (cpu) = i960base_store_register;
+  CPU_PC_FETCH (cpu) = i960base_h_pc_get;
+  CPU_PC_STORE (cpu) = i960base_h_pc_set;
+  CPU_GET_IDATA (cpu) = i960base_get_idata;
+  CPU_MAX_INSNS (cpu) = I960BASE_INSN_MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = i960base_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = i960base_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = i960base_engine_run_full;
+#endif
+}
+
+const MACH i960_ka_sa_mach =
+{
+  "i960:ka_sa", "i960:ka_sa",
+  32, 32, & i960_ka_sa_models[0], & i960base_imp_properties,
+  i960_ka_sa_init_cpu,
+  i960base_prepare_run
+};
+
+static void
+i960_ca_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = i960base_fetch_register;
+  CPU_REG_STORE (cpu) = i960base_store_register;
+  CPU_PC_FETCH (cpu) = i960base_h_pc_get;
+  CPU_PC_STORE (cpu) = i960base_h_pc_set;
+  CPU_GET_IDATA (cpu) = i960base_get_idata;
+  CPU_MAX_INSNS (cpu) = I960BASE_INSN_MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = i960base_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = i960base_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = i960base_engine_run_full;
+#endif
+}
+
+const MACH i960_ca_mach =
+{
+  "i960:ca", "i960:ca",
+  32, 32, & i960_ca_models[0], & i960base_imp_properties,
+  i960_ca_init_cpu,
+  i960base_prepare_run
+};
+
diff --git a/sim/i960/sem-switch.c b/sim/i960/sem-switch.c
new file mode 100644
index 00000000000..2ab52eb0382
--- /dev/null
+++ b/sim/i960/sem-switch.c
@@ -0,0 +1,7181 @@
+/* Simulator instruction semantics for i960base.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+  /* The labels have the case they have because the enum of insn types
+     is all uppercase and in the non-stdc case the insn symbol is built
+     into the enum name.  */
+
+  static struct {
+    int index;
+    void *label;
+  } labels[] = {
+    { I960BASE_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+    { I960BASE_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+    { I960BASE_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+    { I960BASE_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+    { I960BASE_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+    { I960BASE_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+    { I960BASE_INSN_MULO, && case_sem_INSN_MULO },
+    { I960BASE_INSN_MULO1, && case_sem_INSN_MULO1 },
+    { I960BASE_INSN_MULO2, && case_sem_INSN_MULO2 },
+    { I960BASE_INSN_MULO3, && case_sem_INSN_MULO3 },
+    { I960BASE_INSN_REMO, && case_sem_INSN_REMO },
+    { I960BASE_INSN_REMO1, && case_sem_INSN_REMO1 },
+    { I960BASE_INSN_REMO2, && case_sem_INSN_REMO2 },
+    { I960BASE_INSN_REMO3, && case_sem_INSN_REMO3 },
+    { I960BASE_INSN_DIVO, && case_sem_INSN_DIVO },
+    { I960BASE_INSN_DIVO1, && case_sem_INSN_DIVO1 },
+    { I960BASE_INSN_DIVO2, && case_sem_INSN_DIVO2 },
+    { I960BASE_INSN_DIVO3, && case_sem_INSN_DIVO3 },
+    { I960BASE_INSN_REMI, && case_sem_INSN_REMI },
+    { I960BASE_INSN_REMI1, && case_sem_INSN_REMI1 },
+    { I960BASE_INSN_REMI2, && case_sem_INSN_REMI2 },
+    { I960BASE_INSN_REMI3, && case_sem_INSN_REMI3 },
+    { I960BASE_INSN_DIVI, && case_sem_INSN_DIVI },
+    { I960BASE_INSN_DIVI1, && case_sem_INSN_DIVI1 },
+    { I960BASE_INSN_DIVI2, && case_sem_INSN_DIVI2 },
+    { I960BASE_INSN_DIVI3, && case_sem_INSN_DIVI3 },
+    { I960BASE_INSN_ADDO, && case_sem_INSN_ADDO },
+    { I960BASE_INSN_ADDO1, && case_sem_INSN_ADDO1 },
+    { I960BASE_INSN_ADDO2, && case_sem_INSN_ADDO2 },
+    { I960BASE_INSN_ADDO3, && case_sem_INSN_ADDO3 },
+    { I960BASE_INSN_SUBO, && case_sem_INSN_SUBO },
+    { I960BASE_INSN_SUBO1, && case_sem_INSN_SUBO1 },
+    { I960BASE_INSN_SUBO2, && case_sem_INSN_SUBO2 },
+    { I960BASE_INSN_SUBO3, && case_sem_INSN_SUBO3 },
+    { I960BASE_INSN_NOTBIT, && case_sem_INSN_NOTBIT },
+    { I960BASE_INSN_NOTBIT1, && case_sem_INSN_NOTBIT1 },
+    { I960BASE_INSN_NOTBIT2, && case_sem_INSN_NOTBIT2 },
+    { I960BASE_INSN_NOTBIT3, && case_sem_INSN_NOTBIT3 },
+    { I960BASE_INSN_AND, && case_sem_INSN_AND },
+    { I960BASE_INSN_AND1, && case_sem_INSN_AND1 },
+    { I960BASE_INSN_AND2, && case_sem_INSN_AND2 },
+    { I960BASE_INSN_AND3, && case_sem_INSN_AND3 },
+    { I960BASE_INSN_ANDNOT, && case_sem_INSN_ANDNOT },
+    { I960BASE_INSN_ANDNOT1, && case_sem_INSN_ANDNOT1 },
+    { I960BASE_INSN_ANDNOT2, && case_sem_INSN_ANDNOT2 },
+    { I960BASE_INSN_ANDNOT3, && case_sem_INSN_ANDNOT3 },
+    { I960BASE_INSN_SETBIT, && case_sem_INSN_SETBIT },
+    { I960BASE_INSN_SETBIT1, && case_sem_INSN_SETBIT1 },
+    { I960BASE_INSN_SETBIT2, && case_sem_INSN_SETBIT2 },
+    { I960BASE_INSN_SETBIT3, && case_sem_INSN_SETBIT3 },
+    { I960BASE_INSN_NOTAND, && case_sem_INSN_NOTAND },
+    { I960BASE_INSN_NOTAND1, && case_sem_INSN_NOTAND1 },
+    { I960BASE_INSN_NOTAND2, && case_sem_INSN_NOTAND2 },
+    { I960BASE_INSN_NOTAND3, && case_sem_INSN_NOTAND3 },
+    { I960BASE_INSN_XOR, && case_sem_INSN_XOR },
+    { I960BASE_INSN_XOR1, && case_sem_INSN_XOR1 },
+    { I960BASE_INSN_XOR2, && case_sem_INSN_XOR2 },
+    { I960BASE_INSN_XOR3, && case_sem_INSN_XOR3 },
+    { I960BASE_INSN_OR, && case_sem_INSN_OR },
+    { I960BASE_INSN_OR1, && case_sem_INSN_OR1 },
+    { I960BASE_INSN_OR2, && case_sem_INSN_OR2 },
+    { I960BASE_INSN_OR3, && case_sem_INSN_OR3 },
+    { I960BASE_INSN_NOR, && case_sem_INSN_NOR },
+    { I960BASE_INSN_NOR1, && case_sem_INSN_NOR1 },
+    { I960BASE_INSN_NOR2, && case_sem_INSN_NOR2 },
+    { I960BASE_INSN_NOR3, && case_sem_INSN_NOR3 },
+    { I960BASE_INSN_NOT, && case_sem_INSN_NOT },
+    { I960BASE_INSN_NOT1, && case_sem_INSN_NOT1 },
+    { I960BASE_INSN_NOT2, && case_sem_INSN_NOT2 },
+    { I960BASE_INSN_NOT3, && case_sem_INSN_NOT3 },
+    { I960BASE_INSN_CLRBIT, && case_sem_INSN_CLRBIT },
+    { I960BASE_INSN_CLRBIT1, && case_sem_INSN_CLRBIT1 },
+    { I960BASE_INSN_CLRBIT2, && case_sem_INSN_CLRBIT2 },
+    { I960BASE_INSN_CLRBIT3, && case_sem_INSN_CLRBIT3 },
+    { I960BASE_INSN_SHLO, && case_sem_INSN_SHLO },
+    { I960BASE_INSN_SHLO1, && case_sem_INSN_SHLO1 },
+    { I960BASE_INSN_SHLO2, && case_sem_INSN_SHLO2 },
+    { I960BASE_INSN_SHLO3, && case_sem_INSN_SHLO3 },
+    { I960BASE_INSN_SHRO, && case_sem_INSN_SHRO },
+    { I960BASE_INSN_SHRO1, && case_sem_INSN_SHRO1 },
+    { I960BASE_INSN_SHRO2, && case_sem_INSN_SHRO2 },
+    { I960BASE_INSN_SHRO3, && case_sem_INSN_SHRO3 },
+    { I960BASE_INSN_SHLI, && case_sem_INSN_SHLI },
+    { I960BASE_INSN_SHLI1, && case_sem_INSN_SHLI1 },
+    { I960BASE_INSN_SHLI2, && case_sem_INSN_SHLI2 },
+    { I960BASE_INSN_SHLI3, && case_sem_INSN_SHLI3 },
+    { I960BASE_INSN_SHRI, && case_sem_INSN_SHRI },
+    { I960BASE_INSN_SHRI1, && case_sem_INSN_SHRI1 },
+    { I960BASE_INSN_SHRI2, && case_sem_INSN_SHRI2 },
+    { I960BASE_INSN_SHRI3, && case_sem_INSN_SHRI3 },
+    { I960BASE_INSN_EMUL, && case_sem_INSN_EMUL },
+    { I960BASE_INSN_EMUL1, && case_sem_INSN_EMUL1 },
+    { I960BASE_INSN_EMUL2, && case_sem_INSN_EMUL2 },
+    { I960BASE_INSN_EMUL3, && case_sem_INSN_EMUL3 },
+    { I960BASE_INSN_MOV, && case_sem_INSN_MOV },
+    { I960BASE_INSN_MOV1, && case_sem_INSN_MOV1 },
+    { I960BASE_INSN_MOVL, && case_sem_INSN_MOVL },
+    { I960BASE_INSN_MOVL1, && case_sem_INSN_MOVL1 },
+    { I960BASE_INSN_MOVT, && case_sem_INSN_MOVT },
+    { I960BASE_INSN_MOVT1, && case_sem_INSN_MOVT1 },
+    { I960BASE_INSN_MOVQ, && case_sem_INSN_MOVQ },
+    { I960BASE_INSN_MOVQ1, && case_sem_INSN_MOVQ1 },
+    { I960BASE_INSN_MODPC, && case_sem_INSN_MODPC },
+    { I960BASE_INSN_MODAC, && case_sem_INSN_MODAC },
+    { I960BASE_INSN_LDA_OFFSET, && case_sem_INSN_LDA_OFFSET },
+    { I960BASE_INSN_LDA_INDIRECT_OFFSET, && case_sem_INSN_LDA_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDA_INDIRECT, && case_sem_INSN_LDA_INDIRECT },
+    { I960BASE_INSN_LDA_INDIRECT_INDEX, && case_sem_INSN_LDA_INDIRECT_INDEX },
+    { I960BASE_INSN_LDA_DISP, && case_sem_INSN_LDA_DISP },
+    { I960BASE_INSN_LDA_INDIRECT_DISP, && case_sem_INSN_LDA_INDIRECT_DISP },
+    { I960BASE_INSN_LDA_INDEX_DISP, && case_sem_INSN_LDA_INDEX_DISP },
+    { I960BASE_INSN_LDA_INDIRECT_INDEX_DISP, && case_sem_INSN_LDA_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LD_OFFSET, && case_sem_INSN_LD_OFFSET },
+    { I960BASE_INSN_LD_INDIRECT_OFFSET, && case_sem_INSN_LD_INDIRECT_OFFSET },
+    { I960BASE_INSN_LD_INDIRECT, && case_sem_INSN_LD_INDIRECT },
+    { I960BASE_INSN_LD_INDIRECT_INDEX, && case_sem_INSN_LD_INDIRECT_INDEX },
+    { I960BASE_INSN_LD_DISP, && case_sem_INSN_LD_DISP },
+    { I960BASE_INSN_LD_INDIRECT_DISP, && case_sem_INSN_LD_INDIRECT_DISP },
+    { I960BASE_INSN_LD_INDEX_DISP, && case_sem_INSN_LD_INDEX_DISP },
+    { I960BASE_INSN_LD_INDIRECT_INDEX_DISP, && case_sem_INSN_LD_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LDOB_OFFSET, && case_sem_INSN_LDOB_OFFSET },
+    { I960BASE_INSN_LDOB_INDIRECT_OFFSET, && case_sem_INSN_LDOB_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDOB_INDIRECT, && case_sem_INSN_LDOB_INDIRECT },
+    { I960BASE_INSN_LDOB_INDIRECT_INDEX, && case_sem_INSN_LDOB_INDIRECT_INDEX },
+    { I960BASE_INSN_LDOB_DISP, && case_sem_INSN_LDOB_DISP },
+    { I960BASE_INSN_LDOB_INDIRECT_DISP, && case_sem_INSN_LDOB_INDIRECT_DISP },
+    { I960BASE_INSN_LDOB_INDEX_DISP, && case_sem_INSN_LDOB_INDEX_DISP },
+    { I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP, && case_sem_INSN_LDOB_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LDOS_OFFSET, && case_sem_INSN_LDOS_OFFSET },
+    { I960BASE_INSN_LDOS_INDIRECT_OFFSET, && case_sem_INSN_LDOS_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDOS_INDIRECT, && case_sem_INSN_LDOS_INDIRECT },
+    { I960BASE_INSN_LDOS_INDIRECT_INDEX, && case_sem_INSN_LDOS_INDIRECT_INDEX },
+    { I960BASE_INSN_LDOS_DISP, && case_sem_INSN_LDOS_DISP },
+    { I960BASE_INSN_LDOS_INDIRECT_DISP, && case_sem_INSN_LDOS_INDIRECT_DISP },
+    { I960BASE_INSN_LDOS_INDEX_DISP, && case_sem_INSN_LDOS_INDEX_DISP },
+    { I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP, && case_sem_INSN_LDOS_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LDIB_OFFSET, && case_sem_INSN_LDIB_OFFSET },
+    { I960BASE_INSN_LDIB_INDIRECT_OFFSET, && case_sem_INSN_LDIB_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDIB_INDIRECT, && case_sem_INSN_LDIB_INDIRECT },
+    { I960BASE_INSN_LDIB_INDIRECT_INDEX, && case_sem_INSN_LDIB_INDIRECT_INDEX },
+    { I960BASE_INSN_LDIB_DISP, && case_sem_INSN_LDIB_DISP },
+    { I960BASE_INSN_LDIB_INDIRECT_DISP, && case_sem_INSN_LDIB_INDIRECT_DISP },
+    { I960BASE_INSN_LDIB_INDEX_DISP, && case_sem_INSN_LDIB_INDEX_DISP },
+    { I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP, && case_sem_INSN_LDIB_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LDIS_OFFSET, && case_sem_INSN_LDIS_OFFSET },
+    { I960BASE_INSN_LDIS_INDIRECT_OFFSET, && case_sem_INSN_LDIS_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDIS_INDIRECT, && case_sem_INSN_LDIS_INDIRECT },
+    { I960BASE_INSN_LDIS_INDIRECT_INDEX, && case_sem_INSN_LDIS_INDIRECT_INDEX },
+    { I960BASE_INSN_LDIS_DISP, && case_sem_INSN_LDIS_DISP },
+    { I960BASE_INSN_LDIS_INDIRECT_DISP, && case_sem_INSN_LDIS_INDIRECT_DISP },
+    { I960BASE_INSN_LDIS_INDEX_DISP, && case_sem_INSN_LDIS_INDEX_DISP },
+    { I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP, && case_sem_INSN_LDIS_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LDL_OFFSET, && case_sem_INSN_LDL_OFFSET },
+    { I960BASE_INSN_LDL_INDIRECT_OFFSET, && case_sem_INSN_LDL_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDL_INDIRECT, && case_sem_INSN_LDL_INDIRECT },
+    { I960BASE_INSN_LDL_INDIRECT_INDEX, && case_sem_INSN_LDL_INDIRECT_INDEX },
+    { I960BASE_INSN_LDL_DISP, && case_sem_INSN_LDL_DISP },
+    { I960BASE_INSN_LDL_INDIRECT_DISP, && case_sem_INSN_LDL_INDIRECT_DISP },
+    { I960BASE_INSN_LDL_INDEX_DISP, && case_sem_INSN_LDL_INDEX_DISP },
+    { I960BASE_INSN_LDL_INDIRECT_INDEX_DISP, && case_sem_INSN_LDL_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LDT_OFFSET, && case_sem_INSN_LDT_OFFSET },
+    { I960BASE_INSN_LDT_INDIRECT_OFFSET, && case_sem_INSN_LDT_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDT_INDIRECT, && case_sem_INSN_LDT_INDIRECT },
+    { I960BASE_INSN_LDT_INDIRECT_INDEX, && case_sem_INSN_LDT_INDIRECT_INDEX },
+    { I960BASE_INSN_LDT_DISP, && case_sem_INSN_LDT_DISP },
+    { I960BASE_INSN_LDT_INDIRECT_DISP, && case_sem_INSN_LDT_INDIRECT_DISP },
+    { I960BASE_INSN_LDT_INDEX_DISP, && case_sem_INSN_LDT_INDEX_DISP },
+    { I960BASE_INSN_LDT_INDIRECT_INDEX_DISP, && case_sem_INSN_LDT_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_LDQ_OFFSET, && case_sem_INSN_LDQ_OFFSET },
+    { I960BASE_INSN_LDQ_INDIRECT_OFFSET, && case_sem_INSN_LDQ_INDIRECT_OFFSET },
+    { I960BASE_INSN_LDQ_INDIRECT, && case_sem_INSN_LDQ_INDIRECT },
+    { I960BASE_INSN_LDQ_INDIRECT_INDEX, && case_sem_INSN_LDQ_INDIRECT_INDEX },
+    { I960BASE_INSN_LDQ_DISP, && case_sem_INSN_LDQ_DISP },
+    { I960BASE_INSN_LDQ_INDIRECT_DISP, && case_sem_INSN_LDQ_INDIRECT_DISP },
+    { I960BASE_INSN_LDQ_INDEX_DISP, && case_sem_INSN_LDQ_INDEX_DISP },
+    { I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP, && case_sem_INSN_LDQ_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_ST_OFFSET, && case_sem_INSN_ST_OFFSET },
+    { I960BASE_INSN_ST_INDIRECT_OFFSET, && case_sem_INSN_ST_INDIRECT_OFFSET },
+    { I960BASE_INSN_ST_INDIRECT, && case_sem_INSN_ST_INDIRECT },
+    { I960BASE_INSN_ST_INDIRECT_INDEX, && case_sem_INSN_ST_INDIRECT_INDEX },
+    { I960BASE_INSN_ST_DISP, && case_sem_INSN_ST_DISP },
+    { I960BASE_INSN_ST_INDIRECT_DISP, && case_sem_INSN_ST_INDIRECT_DISP },
+    { I960BASE_INSN_ST_INDEX_DISP, && case_sem_INSN_ST_INDEX_DISP },
+    { I960BASE_INSN_ST_INDIRECT_INDEX_DISP, && case_sem_INSN_ST_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_STOB_OFFSET, && case_sem_INSN_STOB_OFFSET },
+    { I960BASE_INSN_STOB_INDIRECT_OFFSET, && case_sem_INSN_STOB_INDIRECT_OFFSET },
+    { I960BASE_INSN_STOB_INDIRECT, && case_sem_INSN_STOB_INDIRECT },
+    { I960BASE_INSN_STOB_INDIRECT_INDEX, && case_sem_INSN_STOB_INDIRECT_INDEX },
+    { I960BASE_INSN_STOB_DISP, && case_sem_INSN_STOB_DISP },
+    { I960BASE_INSN_STOB_INDIRECT_DISP, && case_sem_INSN_STOB_INDIRECT_DISP },
+    { I960BASE_INSN_STOB_INDEX_DISP, && case_sem_INSN_STOB_INDEX_DISP },
+    { I960BASE_INSN_STOB_INDIRECT_INDEX_DISP, && case_sem_INSN_STOB_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_STOS_OFFSET, && case_sem_INSN_STOS_OFFSET },
+    { I960BASE_INSN_STOS_INDIRECT_OFFSET, && case_sem_INSN_STOS_INDIRECT_OFFSET },
+    { I960BASE_INSN_STOS_INDIRECT, && case_sem_INSN_STOS_INDIRECT },
+    { I960BASE_INSN_STOS_INDIRECT_INDEX, && case_sem_INSN_STOS_INDIRECT_INDEX },
+    { I960BASE_INSN_STOS_DISP, && case_sem_INSN_STOS_DISP },
+    { I960BASE_INSN_STOS_INDIRECT_DISP, && case_sem_INSN_STOS_INDIRECT_DISP },
+    { I960BASE_INSN_STOS_INDEX_DISP, && case_sem_INSN_STOS_INDEX_DISP },
+    { I960BASE_INSN_STOS_INDIRECT_INDEX_DISP, && case_sem_INSN_STOS_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_STL_OFFSET, && case_sem_INSN_STL_OFFSET },
+    { I960BASE_INSN_STL_INDIRECT_OFFSET, && case_sem_INSN_STL_INDIRECT_OFFSET },
+    { I960BASE_INSN_STL_INDIRECT, && case_sem_INSN_STL_INDIRECT },
+    { I960BASE_INSN_STL_INDIRECT_INDEX, && case_sem_INSN_STL_INDIRECT_INDEX },
+    { I960BASE_INSN_STL_DISP, && case_sem_INSN_STL_DISP },
+    { I960BASE_INSN_STL_INDIRECT_DISP, && case_sem_INSN_STL_INDIRECT_DISP },
+    { I960BASE_INSN_STL_INDEX_DISP, && case_sem_INSN_STL_INDEX_DISP },
+    { I960BASE_INSN_STL_INDIRECT_INDEX_DISP, && case_sem_INSN_STL_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_STT_OFFSET, && case_sem_INSN_STT_OFFSET },
+    { I960BASE_INSN_STT_INDIRECT_OFFSET, && case_sem_INSN_STT_INDIRECT_OFFSET },
+    { I960BASE_INSN_STT_INDIRECT, && case_sem_INSN_STT_INDIRECT },
+    { I960BASE_INSN_STT_INDIRECT_INDEX, && case_sem_INSN_STT_INDIRECT_INDEX },
+    { I960BASE_INSN_STT_DISP, && case_sem_INSN_STT_DISP },
+    { I960BASE_INSN_STT_INDIRECT_DISP, && case_sem_INSN_STT_INDIRECT_DISP },
+    { I960BASE_INSN_STT_INDEX_DISP, && case_sem_INSN_STT_INDEX_DISP },
+    { I960BASE_INSN_STT_INDIRECT_INDEX_DISP, && case_sem_INSN_STT_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_STQ_OFFSET, && case_sem_INSN_STQ_OFFSET },
+    { I960BASE_INSN_STQ_INDIRECT_OFFSET, && case_sem_INSN_STQ_INDIRECT_OFFSET },
+    { I960BASE_INSN_STQ_INDIRECT, && case_sem_INSN_STQ_INDIRECT },
+    { I960BASE_INSN_STQ_INDIRECT_INDEX, && case_sem_INSN_STQ_INDIRECT_INDEX },
+    { I960BASE_INSN_STQ_DISP, && case_sem_INSN_STQ_DISP },
+    { I960BASE_INSN_STQ_INDIRECT_DISP, && case_sem_INSN_STQ_INDIRECT_DISP },
+    { I960BASE_INSN_STQ_INDEX_DISP, && case_sem_INSN_STQ_INDEX_DISP },
+    { I960BASE_INSN_STQ_INDIRECT_INDEX_DISP, && case_sem_INSN_STQ_INDIRECT_INDEX_DISP },
+    { I960BASE_INSN_CMPOBE_REG, && case_sem_INSN_CMPOBE_REG },
+    { I960BASE_INSN_CMPOBE_LIT, && case_sem_INSN_CMPOBE_LIT },
+    { I960BASE_INSN_CMPOBNE_REG, && case_sem_INSN_CMPOBNE_REG },
+    { I960BASE_INSN_CMPOBNE_LIT, && case_sem_INSN_CMPOBNE_LIT },
+    { I960BASE_INSN_CMPOBL_REG, && case_sem_INSN_CMPOBL_REG },
+    { I960BASE_INSN_CMPOBL_LIT, && case_sem_INSN_CMPOBL_LIT },
+    { I960BASE_INSN_CMPOBLE_REG, && case_sem_INSN_CMPOBLE_REG },
+    { I960BASE_INSN_CMPOBLE_LIT, && case_sem_INSN_CMPOBLE_LIT },
+    { I960BASE_INSN_CMPOBG_REG, && case_sem_INSN_CMPOBG_REG },
+    { I960BASE_INSN_CMPOBG_LIT, && case_sem_INSN_CMPOBG_LIT },
+    { I960BASE_INSN_CMPOBGE_REG, && case_sem_INSN_CMPOBGE_REG },
+    { I960BASE_INSN_CMPOBGE_LIT, && case_sem_INSN_CMPOBGE_LIT },
+    { I960BASE_INSN_CMPIBE_REG, && case_sem_INSN_CMPIBE_REG },
+    { I960BASE_INSN_CMPIBE_LIT, && case_sem_INSN_CMPIBE_LIT },
+    { I960BASE_INSN_CMPIBNE_REG, && case_sem_INSN_CMPIBNE_REG },
+    { I960BASE_INSN_CMPIBNE_LIT, && case_sem_INSN_CMPIBNE_LIT },
+    { I960BASE_INSN_CMPIBL_REG, && case_sem_INSN_CMPIBL_REG },
+    { I960BASE_INSN_CMPIBL_LIT, && case_sem_INSN_CMPIBL_LIT },
+    { I960BASE_INSN_CMPIBLE_REG, && case_sem_INSN_CMPIBLE_REG },
+    { I960BASE_INSN_CMPIBLE_LIT, && case_sem_INSN_CMPIBLE_LIT },
+    { I960BASE_INSN_CMPIBG_REG, && case_sem_INSN_CMPIBG_REG },
+    { I960BASE_INSN_CMPIBG_LIT, && case_sem_INSN_CMPIBG_LIT },
+    { I960BASE_INSN_CMPIBGE_REG, && case_sem_INSN_CMPIBGE_REG },
+    { I960BASE_INSN_CMPIBGE_LIT, && case_sem_INSN_CMPIBGE_LIT },
+    { I960BASE_INSN_BBC_REG, && case_sem_INSN_BBC_REG },
+    { I960BASE_INSN_BBC_LIT, && case_sem_INSN_BBC_LIT },
+    { I960BASE_INSN_BBS_REG, && case_sem_INSN_BBS_REG },
+    { I960BASE_INSN_BBS_LIT, && case_sem_INSN_BBS_LIT },
+    { I960BASE_INSN_CMPI, && case_sem_INSN_CMPI },
+    { I960BASE_INSN_CMPI1, && case_sem_INSN_CMPI1 },
+    { I960BASE_INSN_CMPI2, && case_sem_INSN_CMPI2 },
+    { I960BASE_INSN_CMPI3, && case_sem_INSN_CMPI3 },
+    { I960BASE_INSN_CMPO, && case_sem_INSN_CMPO },
+    { I960BASE_INSN_CMPO1, && case_sem_INSN_CMPO1 },
+    { I960BASE_INSN_CMPO2, && case_sem_INSN_CMPO2 },
+    { I960BASE_INSN_CMPO3, && case_sem_INSN_CMPO3 },
+    { I960BASE_INSN_TESTNO_REG, && case_sem_INSN_TESTNO_REG },
+    { I960BASE_INSN_TESTG_REG, && case_sem_INSN_TESTG_REG },
+    { I960BASE_INSN_TESTE_REG, && case_sem_INSN_TESTE_REG },
+    { I960BASE_INSN_TESTGE_REG, && case_sem_INSN_TESTGE_REG },
+    { I960BASE_INSN_TESTL_REG, && case_sem_INSN_TESTL_REG },
+    { I960BASE_INSN_TESTNE_REG, && case_sem_INSN_TESTNE_REG },
+    { I960BASE_INSN_TESTLE_REG, && case_sem_INSN_TESTLE_REG },
+    { I960BASE_INSN_TESTO_REG, && case_sem_INSN_TESTO_REG },
+    { I960BASE_INSN_BNO, && case_sem_INSN_BNO },
+    { I960BASE_INSN_BG, && case_sem_INSN_BG },
+    { I960BASE_INSN_BE, && case_sem_INSN_BE },
+    { I960BASE_INSN_BGE, && case_sem_INSN_BGE },
+    { I960BASE_INSN_BL, && case_sem_INSN_BL },
+    { I960BASE_INSN_BNE, && case_sem_INSN_BNE },
+    { I960BASE_INSN_BLE, && case_sem_INSN_BLE },
+    { I960BASE_INSN_BO, && case_sem_INSN_BO },
+    { I960BASE_INSN_B, && case_sem_INSN_B },
+    { I960BASE_INSN_BX_INDIRECT_OFFSET, && case_sem_INSN_BX_INDIRECT_OFFSET },
+    { I960BASE_INSN_BX_INDIRECT, && case_sem_INSN_BX_INDIRECT },
+    { I960BASE_INSN_BX_INDIRECT_INDEX, && case_sem_INSN_BX_INDIRECT_INDEX },
+    { I960BASE_INSN_BX_DISP, && case_sem_INSN_BX_DISP },
+    { I960BASE_INSN_BX_INDIRECT_DISP, && case_sem_INSN_BX_INDIRECT_DISP },
+    { I960BASE_INSN_CALLX_DISP, && case_sem_INSN_CALLX_DISP },
+    { I960BASE_INSN_CALLX_INDIRECT, && case_sem_INSN_CALLX_INDIRECT },
+    { I960BASE_INSN_CALLX_INDIRECT_OFFSET, && case_sem_INSN_CALLX_INDIRECT_OFFSET },
+    { I960BASE_INSN_RET, && case_sem_INSN_RET },
+    { I960BASE_INSN_CALLS, && case_sem_INSN_CALLS },
+    { I960BASE_INSN_FMARK, && case_sem_INSN_FMARK },
+    { I960BASE_INSN_FLUSHREG, && case_sem_INSN_FLUSHREG },
+    { 0, 0 }
+  };
+  int i;
+
+  for (i = 0; labels[i].label != 0; ++i)
+#if FAST_P
+    CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+    CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+   off frills like tracing and profiling.  */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+   that can cause it to be optimized out.  Another way would be to emit
+   special handlers into the instruction "stream".  */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop.  */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+    {
+
+  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE
+    /* Update the recorded pc in the cpu state struct.  */
+    SET_H_PC (pc);
+#endif
+    sim_engine_invalid_insn (current_cpu, pc);
+    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
+    /* NOTREACHED */
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+    i960base_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+    i960base_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+#ifdef DEFINE_SWITCH
+    vpc = i960base_pbb_cti_chain (current_cpu, sem_arg,
+			       pbb_br_npc_ptr, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = i960base_pbb_cti_chain (current_cpu, sem_arg,
+			       CPU_PBB_BR_NPC_PTR (current_cpu),
+			       CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+    vpc = i960base_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+#ifdef DEFINE_SWITCH
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = i960base_pbb_begin (current_cpu, FAST_P);
+#else
+    vpc = i960base_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULO) : /* mulo $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULO1) : /* mulo $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULO2) : /* mulo $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULO3) : /* mulo $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMO) : /* remo $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMO1) : /* remo $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMO2) : /* remo $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMO3) : /* remo $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVO) : /* divo $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVO1) : /* divo $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVO2) : /* divo $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVO3) : /* divo $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMI) : /* remi $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMI1) : /* remi $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMI2) : /* remi $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMI3) : /* remi $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVI) : /* divi $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVI1) : /* divi $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVI2) : /* divi $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVI3) : /* divi $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDO) : /* addo $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDO1) : /* addo $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDO2) : /* addo $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDO3) : /* addo $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBO) : /* subo $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBO1) : /* subo $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBO2) : /* subo $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBO3) : /* subo $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTBIT) : /* notbit $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, * FLD (i_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTBIT1) : /* notbit $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, FLD (f_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTBIT2) : /* notbit $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, * FLD (i_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTBIT3) : /* notbit $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, FLD (f_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND) : /* and $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND1) : /* and $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND2) : /* and $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND3) : /* and $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDNOT) : /* andnot $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src2), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDNOT1) : /* andnot $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src2), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDNOT2) : /* andnot $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src2), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ANDNOT3) : /* andnot $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src2), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SETBIT) : /* setbit $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, * FLD (i_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SETBIT1) : /* setbit $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, FLD (f_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SETBIT2) : /* setbit $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, * FLD (i_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SETBIT3) : /* setbit $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, FLD (f_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTAND) : /* notand $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTAND1) : /* notand $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTAND2) : /* notand $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOTAND3) : /* notand $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR) : /* xor $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR1) : /* xor $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR2) : /* xor $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR3) : /* xor $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR) : /* or $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR1) : /* or $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR2) : /* or $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR3) : /* or $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOR) : /* nor $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOR1) : /* nor $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOR2) : /* nor $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOR3) : /* nor $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOT) : /* not $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_not.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (* FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOT1) : /* not $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_not1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOT2) : /* not $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_not2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (* FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOT3) : /* not $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_not3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CLRBIT) : /* clrbit $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, * FLD (i_src1))), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CLRBIT1) : /* clrbit $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, FLD (f_src1))), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CLRBIT2) : /* clrbit $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, * FLD (i_src1))), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CLRBIT3) : /* clrbit $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, FLD (f_src1))), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLO) : /* shlo $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLO1) : /* shlo $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLO2) : /* shlo $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLO3) : /* shlo $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRO) : /* shro $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRO1) : /* shro $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRO2) : /* shro $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRO3) : /* shro $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLI) : /* shli $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLI1) : /* shli $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLI2) : /* shli $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHLI3) : /* shli $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRI) : /* shri $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRI1) : /* shri $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRI2) : /* shri $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SHRI3) : /* shri $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EMUL) : /* emul $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_emul.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (* FLD (i_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EMUL1) : /* emul $lit1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_emul1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (* FLD (i_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EMUL2) : /* emul $src1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_emul2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (FLD (f_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_EMUL3) : /* emul $lit1, $lit2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_emul3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (FLD (f_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOV) : /* mov $src1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_not2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOV1) : /* mov $lit1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_not3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVL) : /* movl $src1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_sregno = FLD (f_src1);
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVL1) : /* movl $lit1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movl1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVT) : /* movt $src1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movt.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_sregno = FLD (f_src1);
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVT1) : /* movt $lit1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movt1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVQ) : /* movq $src1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_sregno = FLD (f_src1);
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (3))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MOVQ1) : /* movq $lit1, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_movq1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MODPC) : /* modpc $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_modpc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src2);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MODAC) : /* modac $src1, $src2, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_modpc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src2);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_OFFSET) : /* lda $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_offset);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_INDIRECT_OFFSET) : /* lda $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (FLD (f_offset), * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_INDIRECT) : /* lda ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_abase);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_INDIRECT_INDEX) : /* lda ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_DISP) : /* lda $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = FLD (f_optdisp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_INDIRECT_DISP) : /* lda $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_INDEX_DISP) : /* lda $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDA_INDIRECT_INDEX_DISP) : /* lda $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_OFFSET) : /* ld $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_INDIRECT_OFFSET) : /* ld $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_INDIRECT) : /* ld ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_INDIRECT_INDEX) : /* ld ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_DISP) : /* ld $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_INDIRECT_DISP) : /* ld $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_INDEX_DISP) : /* ld $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_INDIRECT_INDEX_DISP) : /* ld $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_OFFSET) : /* ldob $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_INDIRECT_OFFSET) : /* ldob $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_INDIRECT) : /* ldob ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_INDIRECT_INDEX) : /* ldob ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_DISP) : /* ldob $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_INDIRECT_DISP) : /* ldob $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_INDEX_DISP) : /* ldob $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOB_INDIRECT_INDEX_DISP) : /* ldob $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_OFFSET) : /* ldos $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_INDIRECT_OFFSET) : /* ldos $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_INDIRECT) : /* ldos ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_INDIRECT_INDEX) : /* ldos ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_DISP) : /* ldos $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_INDIRECT_DISP) : /* ldos $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_INDEX_DISP) : /* ldos $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDOS_INDIRECT_INDEX_DISP) : /* ldos $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_OFFSET) : /* ldib $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_INDIRECT_OFFSET) : /* ldib $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_INDIRECT) : /* ldib ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_INDIRECT_INDEX) : /* ldib ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_DISP) : /* ldib $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_INDIRECT_DISP) : /* ldib $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_INDEX_DISP) : /* ldib $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIB_INDIRECT_INDEX_DISP) : /* ldib $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_OFFSET) : /* ldis $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_INDIRECT_OFFSET) : /* ldis $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_INDIRECT) : /* ldis ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_INDIRECT_INDEX) : /* ldis ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_DISP) : /* ldis $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_INDIRECT_DISP) : /* ldis $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_INDEX_DISP) : /* ldis $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDIS_INDIRECT_INDEX_DISP) : /* ldis $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_OFFSET) : /* ldl $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_offset);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_INDIRECT_OFFSET) : /* ldl $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_INDIRECT) : /* ldl ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = * FLD (i_abase);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_INDIRECT_INDEX) : /* ldl ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_DISP) : /* ldl $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_optdisp);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_INDIRECT_DISP) : /* ldl $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_INDEX_DISP) : /* ldl $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDL_INDIRECT_INDEX_DISP) : /* ldl $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_OFFSET) : /* ldt $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_offset);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_INDIRECT_OFFSET) : /* ldt $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_INDIRECT) : /* ldt ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = * FLD (i_abase);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_INDIRECT_INDEX) : /* ldt ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_DISP) : /* ldt $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_optdisp);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_INDIRECT_DISP) : /* ldt $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_INDEX_DISP) : /* ldt $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDT_INDIRECT_INDEX_DISP) : /* ldt $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_OFFSET) : /* ldq $offset, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_offset);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_INDIRECT_OFFSET) : /* ldq $offset($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_INDIRECT) : /* ldq ($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = * FLD (i_abase);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_INDIRECT_INDEX) : /* ldq ($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_DISP) : /* ldq $optdisp, $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_optdisp);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_INDIRECT_DISP) : /* ldq $optdisp($abase), $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_INDEX_DISP) : /* ldq $optdisp[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDQ_INDIRECT_INDEX_DISP) : /* ldq $optdisp($abase)[$index*S$scale], $dst */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_OFFSET) : /* st $st_src, $offset */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_INDIRECT_OFFSET) : /* st $st_src, $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_INDIRECT) : /* st $st_src, ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_INDIRECT_INDEX) : /* st $st_src, ($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_DISP) : /* st $st_src, $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_INDIRECT_DISP) : /* st $st_src, $optdisp($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_INDEX_DISP) : /* st $st_src, $optdisp[$index*S$scale */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_INDIRECT_INDEX_DISP) : /* st $st_src, $optdisp($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_OFFSET) : /* stob $st_src, $offset */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_INDIRECT_OFFSET) : /* stob $st_src, $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_INDIRECT) : /* stob $st_src, ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_INDIRECT_INDEX) : /* stob $st_src, ($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_DISP) : /* stob $st_src, $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_INDIRECT_DISP) : /* stob $st_src, $optdisp($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_INDEX_DISP) : /* stob $st_src, $optdisp[$index*S$scale */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOB_INDIRECT_INDEX_DISP) : /* stob $st_src, $optdisp($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_OFFSET) : /* stos $st_src, $offset */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_INDIRECT_OFFSET) : /* stos $st_src, $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_INDIRECT) : /* stos $st_src, ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_INDIRECT_INDEX) : /* stos $st_src, ($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_DISP) : /* stos $st_src, $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_INDIRECT_DISP) : /* stos $st_src, $optdisp($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_INDEX_DISP) : /* stos $st_src, $optdisp[$index*S$scale */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STOS_INDIRECT_INDEX_DISP) : /* stos $st_src, $optdisp($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_OFFSET) : /* stl $st_src, $offset */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_INDIRECT_OFFSET) : /* stl $st_src, $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_INDIRECT) : /* stl $st_src, ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_INDIRECT_INDEX) : /* stl $st_src, ($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_DISP) : /* stl $st_src, $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_INDIRECT_DISP) : /* stl $st_src, $optdisp($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_INDEX_DISP) : /* stl $st_src, $optdisp[$index*S$scale */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STL_INDIRECT_INDEX_DISP) : /* stl $st_src, $optdisp($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_OFFSET) : /* stt $st_src, $offset */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_INDIRECT_OFFSET) : /* stt $st_src, $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_INDIRECT) : /* stt $st_src, ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_INDIRECT_INDEX) : /* stt $st_src, ($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_DISP) : /* stt $st_src, $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_INDIRECT_DISP) : /* stt $st_src, $optdisp($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_INDEX_DISP) : /* stt $st_src, $optdisp[$index*S$scale */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STT_INDIRECT_INDEX_DISP) : /* stt $st_src, $optdisp($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_OFFSET) : /* stq $st_src, $offset */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_INDIRECT_OFFSET) : /* stq $st_src, $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_INDIRECT) : /* stq $st_src, ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_INDIRECT_INDEX) : /* stq $st_src, ($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_DISP) : /* stq $st_src, $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_INDIRECT_DISP) : /* stq $st_src, $optdisp($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_INDEX_DISP) : /* stq $st_src, $optdisp[$index*S$scale */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STQ_INDIRECT_INDEX_DISP) : /* stq $st_src, $optdisp($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBE_REG) : /* cmpobe $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBE_LIT) : /* cmpobe $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBNE_REG) : /* cmpobne $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBNE_LIT) : /* cmpobne $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBL_REG) : /* cmpobl $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBL_LIT) : /* cmpobl $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBLE_REG) : /* cmpoble $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBLE_LIT) : /* cmpoble $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LEUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBG_REG) : /* cmpobg $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBG_LIT) : /* cmpobg $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBGE_REG) : /* cmpobge $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPOBGE_LIT) : /* cmpobge $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBE_REG) : /* cmpibe $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBE_LIT) : /* cmpibe $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBNE_REG) : /* cmpibne $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBNE_LIT) : /* cmpibne $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBL_REG) : /* cmpibl $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBL_LIT) : /* cmpibl $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBLE_REG) : /* cmpible $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBLE_LIT) : /* cmpible $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBG_REG) : /* cmpibg $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBG_LIT) : /* cmpibg $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBGE_REG) : /* cmpibge $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPIBGE_LIT) : /* cmpibge $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BBC_REG) : /* bbc $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BBC_LIT) : /* bbc $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BBS_REG) : /* bbs $br_src1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BBS_LIT) : /* bbs $br_lit1, $br_src2, $br_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPI) : /* cmpi $src1, $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPI1) : /* cmpi $lit1, $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpi1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPI2) : /* cmpi $src1, $lit2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpi2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPI3) : /* cmpi $lit1, $lit2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpi3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPO) : /* cmpo $src1, $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPO1) : /* cmpo $lit1, $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpo1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPO2) : /* cmpo $src1, $lit2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpo2.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPO3) : /* cmpo $lit1, $lit2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpo3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTNO_REG) : /* testno $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = EQSI (CPU (h_cc), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTG_REG) : /* testg $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 1), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTE_REG) : /* teste $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 2), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTGE_REG) : /* testge $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 3), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTL_REG) : /* testl $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 4), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTNE_REG) : /* testne $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 5), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTLE_REG) : /* testle $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 6), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TESTO_REG) : /* testo $br_src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 7), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNO) : /* bno $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (CPU (h_cc), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BG) : /* bg $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 1), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BE) : /* be $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 2), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGE) : /* bge $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 3), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BL) : /* bl $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 4), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNE) : /* bne $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 5), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLE) : /* ble $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 6), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BO) : /* bo $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 7), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_B) : /* b $ctrl_disp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_b.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BX_INDIRECT_OFFSET) : /* bx $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = ADDSI (FLD (f_offset), * FLD (i_abase));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BX_INDIRECT) : /* bx ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = * FLD (i_abase);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BX_INDIRECT_INDEX) : /* bx ($abase)[$index*S$scale] */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BX_DISP) : /* bx $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    USI opval = FLD (f_optdisp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BX_INDIRECT_DISP) : /* bx $optdisp($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    USI opval = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALLX_DISP) : /* callx $optdisp */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_temp;
+  tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
+  {
+    SI opval = ADDSI (pc, 8);
+    CPU (h_gr[((UINT) 2)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0), CPU (h_gr[((UINT) 0)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4), CPU (h_gr[((UINT) 1)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8), CPU (h_gr[((UINT) 2)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12), CPU (h_gr[((UINT) 3)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16), CPU (h_gr[((UINT) 4)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20), CPU (h_gr[((UINT) 5)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24), CPU (h_gr[((UINT) 6)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28), CPU (h_gr[((UINT) 7)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32), CPU (h_gr[((UINT) 8)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36), CPU (h_gr[((UINT) 9)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40), CPU (h_gr[((UINT) 10)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44), CPU (h_gr[((UINT) 11)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48), CPU (h_gr[((UINT) 12)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52), CPU (h_gr[((UINT) 13)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT) 14)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)]));
+  {
+    USI opval = FLD (f_optdisp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 1)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 2)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 3)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 4)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 5)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 6)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 7)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 8)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 9)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 10)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 11)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 12)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 13)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 14)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
+  {
+    SI opval = CPU (h_gr[((UINT) 31)]);
+    CPU (h_gr[((UINT) 0)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = tmp_temp;
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (tmp_temp, 64);
+    CPU (h_gr[((UINT) 1)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALLX_INDIRECT) : /* callx ($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_temp;
+  tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 2)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0), CPU (h_gr[((UINT) 0)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4), CPU (h_gr[((UINT) 1)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8), CPU (h_gr[((UINT) 2)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12), CPU (h_gr[((UINT) 3)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16), CPU (h_gr[((UINT) 4)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20), CPU (h_gr[((UINT) 5)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24), CPU (h_gr[((UINT) 6)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28), CPU (h_gr[((UINT) 7)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32), CPU (h_gr[((UINT) 8)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36), CPU (h_gr[((UINT) 9)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40), CPU (h_gr[((UINT) 10)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44), CPU (h_gr[((UINT) 11)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48), CPU (h_gr[((UINT) 12)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52), CPU (h_gr[((UINT) 13)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT) 14)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)]));
+  {
+    USI opval = * FLD (i_abase);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 1)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 2)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 3)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 4)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 5)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 6)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 7)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 8)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 9)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 10)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 11)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 12)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 13)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 14)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
+  {
+    SI opval = CPU (h_gr[((UINT) 31)]);
+    CPU (h_gr[((UINT) 0)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = tmp_temp;
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (tmp_temp, 64);
+    CPU (h_gr[((UINT) 1)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALLX_INDIRECT_OFFSET) : /* callx $offset($abase) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_temp;
+  tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 2)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0), CPU (h_gr[((UINT) 0)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4), CPU (h_gr[((UINT) 1)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8), CPU (h_gr[((UINT) 2)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12), CPU (h_gr[((UINT) 3)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16), CPU (h_gr[((UINT) 4)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20), CPU (h_gr[((UINT) 5)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24), CPU (h_gr[((UINT) 6)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28), CPU (h_gr[((UINT) 7)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32), CPU (h_gr[((UINT) 8)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36), CPU (h_gr[((UINT) 9)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40), CPU (h_gr[((UINT) 10)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44), CPU (h_gr[((UINT) 11)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48), CPU (h_gr[((UINT) 12)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52), CPU (h_gr[((UINT) 13)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT) 14)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)]));
+  {
+    USI opval = ADDSI (FLD (f_offset), * FLD (i_abase));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 1)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 2)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 3)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 4)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 5)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 6)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 7)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 8)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 9)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 10)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 11)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 12)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 13)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 14)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
+  {
+    SI opval = CPU (h_gr[((UINT) 31)]);
+    CPU (h_gr[((UINT) 0)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = tmp_temp;
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (tmp_temp, 64);
+    CPU (h_gr[((UINT) 1)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RET) : /* ret */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  {
+    SI opval = CPU (h_gr[((UINT) 0)]);
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0));
+CPU (h_gr[((UINT) 1)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4));
+CPU (h_gr[((UINT) 2)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8));
+CPU (h_gr[((UINT) 3)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12));
+CPU (h_gr[((UINT) 4)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16));
+CPU (h_gr[((UINT) 5)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20));
+CPU (h_gr[((UINT) 6)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24));
+CPU (h_gr[((UINT) 7)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28));
+CPU (h_gr[((UINT) 8)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32));
+CPU (h_gr[((UINT) 9)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36));
+CPU (h_gr[((UINT) 10)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40));
+CPU (h_gr[((UINT) 11)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44));
+CPU (h_gr[((UINT) 12)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48));
+CPU (h_gr[((UINT) 13)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52));
+CPU (h_gr[((UINT) 14)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56));
+CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60));
+  {
+    USI opval = CPU (h_gr[((UINT) 2)]);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CALLS) : /* calls $src1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_calls.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = i960_trap (current_cpu, pc, * FLD (i_src1));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_FMARK) : /* fmark */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = i960_breakpoint (current_cpu, pc);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_FLUSHREG) : /* flushreg */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_flushreg.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+#undef FLD
+}
+  NEXT (vpc);
+
+
+    }
+  ENDSWITCH (sem) /* End of semantic switch.  */
+
+  /* At this point `vpc' contains the next insn to execute.  */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
diff --git a/sim/i960/sem.c b/sim/i960/sem.c
new file mode 100644
index 00000000000..e0621889de3
--- /dev/null
+++ b/sim/i960/sem.c
@@ -0,0 +1,7406 @@
+/* Simulator instruction semantics for i960base.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU i960base
+#define WANT_CPU_I960BASE
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+/* x-invalid: --invalid-- */
+
+SEM_PC
+SEM_FN_NAME (i960base,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE
+    /* Update the recorded pc in the cpu state struct.  */
+    SET_H_PC (pc);
+#endif
+    sim_engine_invalid_insn (current_cpu, pc);
+    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
+    /* NOTREACHED */
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+SEM_PC
+SEM_FN_NAME (i960base,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+    i960base_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+SEM_PC
+SEM_FN_NAME (i960base,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+    i960base_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+SEM_PC
+SEM_FN_NAME (i960base,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+#ifdef DEFINE_SWITCH
+    vpc = i960base_pbb_cti_chain (current_cpu, sem_arg,
+			       pbb_br_npc_ptr, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = i960base_pbb_cti_chain (current_cpu, sem_arg,
+			       CPU_PBB_BR_NPC_PTR (current_cpu),
+			       CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+SEM_PC
+SEM_FN_NAME (i960base,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+    vpc = i960base_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+SEM_PC
+SEM_FN_NAME (i960base,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_I960BASE
+#ifdef DEFINE_SWITCH
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = i960base_pbb_begin (current_cpu, FAST_P);
+#else
+    vpc = i960base_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mulo: mulo $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,mulo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mulo1: mulo $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,mulo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mulo2: mulo $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,mulo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mulo3: mulo $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,mulo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MULSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remo: remo $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remo1: remo $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remo2: remo $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remo3: remo $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UMODSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divo: divo $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divo1: divo $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divo2: divo $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divo3: divo $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = UDIVSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remi: remi $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remi1: remi $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remi2: remi $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* remi3: remi $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,remi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = MODSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divi: divi $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divi1: divi $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divi2: divi $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* divi3: divi $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,divi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = DIVSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addo: addo $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,addo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addo1: addo $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,addo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addo2: addo $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,addo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addo3: addo $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,addo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* subo: subo $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,subo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* subo1: subo $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,subo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* subo2: subo $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,subo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* subo3: subo $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,subo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notbit: notbit $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, * FLD (i_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notbit1: notbit $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, FLD (f_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notbit2: notbit $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, * FLD (i_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notbit3: notbit $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (SLLSI (1, FLD (f_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* and: and $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* and1: and $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,and1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* and2: and $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,and2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* and3: and $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* andnot: andnot $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,andnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src2), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* andnot1: andnot $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,andnot1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_src2), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* andnot2: andnot $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,andnot2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src2), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* andnot3: andnot $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,andnot3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (FLD (f_src2), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* setbit: setbit $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,setbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, * FLD (i_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* setbit1: setbit $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,setbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, FLD (f_src1)), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* setbit2: setbit $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,setbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, * FLD (i_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* setbit3: setbit $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,setbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (SLLSI (1, FLD (f_src1)), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notand: notand $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notand) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notand1: notand $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notand1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notand2: notand $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notand2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notand3: notand $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,notand3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* xor: xor $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* xor1: xor $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* xor2: xor $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* xor3: xor $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* or: or $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (* FLD (i_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* or1: or $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,or1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (FLD (f_src1), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* or2: or $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,or2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (* FLD (i_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* or3: or $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (FLD (f_src1), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nor: nor $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nor1: nor $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,nor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (* FLD (i_src2)), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nor2: nor $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,nor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), INVSI (* FLD (i_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nor3: nor $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,nor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (FLD (f_src2)), INVSI (FLD (f_src1)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* not: not $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (* FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* not1: not $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,not1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* not2: not $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,not2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (* FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* not3: not $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,not3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* clrbit: clrbit $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,clrbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, * FLD (i_src1))), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* clrbit1: clrbit $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,clrbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, FLD (f_src1))), * FLD (i_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* clrbit2: clrbit $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,clrbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, * FLD (i_src1))), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* clrbit3: clrbit $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,clrbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (INVSI (SLLSI (1, FLD (f_src1))), FLD (f_src2));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shlo: shlo $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shlo1: shlo $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shlo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shlo2: shlo $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shlo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shlo3: shlo $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shlo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shro: shro $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shro) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shro1: shro $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shro1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shro2: shro $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shro2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shro3: shro $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shro3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shli: shli $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shli1: shli $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shli1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shli2: shli $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shli2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shli3: shli $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shli3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shri: shri $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (* FLD (i_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shri1: shri $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shri1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (* FLD (i_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shri2: shri $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shri2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (FLD (f_src2), * FLD (i_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* shri3: shri $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,shri3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_notbit3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (FLD (f_src2), FLD (f_src1));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* emul: emul $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,emul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (* FLD (i_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* emul1: emul $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,emul1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (* FLD (i_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* emul2: emul $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,emul2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (FLD (f_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* emul3: emul $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,emul3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_emul3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  DI tmp_temp;
+  tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (FLD (f_src2)));
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = TRUNCDISI (tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* mov: mov $src1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,mov) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mov1: mov $lit1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,mov1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_not3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* movl: movl $src1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,movl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_sregno = FLD (f_src1);
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* movl1: movl $lit1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,movl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movl1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* movt: movt $src1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,movt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movt.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_sregno = FLD (f_src1);
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* movt1: movt $lit1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,movt1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movt1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* movq: movq $src1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,movq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_sregno = FLD (f_src1);
+  {
+    SI opval = * FLD (i_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_src1)) + (3))]);
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* movq1: movq $lit1, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,movq1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_movq1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  tmp_dregno = FLD (f_srcdst);
+  {
+    SI opval = FLD (f_src1);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = 0;
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* modpc: modpc $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,modpc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_modpc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src2);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* modac: modac $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,modac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_modpc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src2);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-offset: lda $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_offset);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-indirect-offset: lda $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (FLD (f_offset), * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-indirect: lda ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_abase);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-indirect-index: lda ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-disp: lda $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = FLD (f_optdisp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-indirect-disp: lda $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-index-disp: lda $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lda-indirect-index-disp: lda $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,lda_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-offset: ld $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-indirect-offset: ld $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-indirect: ld ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-indirect-index: ld ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-disp: ld $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-indirect-disp: ld $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-index-disp: ld $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld-indirect-index-disp: ld $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ld_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-offset: ldob $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-indirect-offset: ldob $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-indirect: ldob ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-indirect-index: ldob ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-disp: ldob $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-indirect-disp: ldob $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-index-disp: ldob $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldob-indirect-index-disp: ldob $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldob_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-offset: ldos $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-indirect-offset: ldos $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-indirect: ldos ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-indirect-index: ldos ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-disp: ldos $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-indirect-disp: ldos $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-index-disp: ldos $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldos-indirect-index-disp: ldos $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldos_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-offset: ldib $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-indirect-offset: ldib $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-indirect: ldib ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-indirect-index: ldib ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-disp: ldib $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-indirect-disp: ldib $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-index-disp: ldib $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldib-indirect-index-disp: ldib $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldib_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-offset: ldis $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, FLD (f_offset));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-indirect-offset: ldis $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-indirect: ldis ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, * FLD (i_abase));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-indirect-index: ldis ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-disp: ldis $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, FLD (f_optdisp));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-indirect-disp: ldis $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-index-disp: ldis $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldis-indirect-index-disp: ldis $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldis_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = GETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))));
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-offset: ldl $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_offset);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-indirect-offset: ldl $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-indirect: ldl ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = * FLD (i_abase);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-indirect-index: ldl ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-disp: ldl $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_optdisp);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-indirect-disp: ldl $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-index-disp: ldl $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldl-indirect-index-disp: ldl $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-offset: ldt $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_offset);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-indirect-offset: ldt $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-indirect: ldt ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = * FLD (i_abase);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-indirect-index: ldt ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-disp: ldt $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_optdisp);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-indirect-disp: ldt $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-index-disp: ldt $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldt-indirect-index-disp: ldt $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-offset: ldq $offset, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_offset);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-indirect-offset: ldq $offset($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-indirect: ldq ($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = * FLD (i_abase);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-indirect-index: ldq ($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-disp: ldq $optdisp, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = FLD (f_optdisp);
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-indirect-disp: ldq $optdisp($abase), $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-index-disp: ldq $optdisp[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* ldq-indirect-index-disp: ldq $optdisp($abase)[$index*S$scale], $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ldq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_dregno;
+  SI tmp_temp;
+  tmp_dregno = FLD (f_srcdst);
+  tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
+  {
+    SI opval = GETMEMSI (current_cpu, pc, tmp_temp);
+    * FLD (i_dst) = opval;
+    TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
+    CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
+    CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
+    CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* st-offset: st $st_src, $offset */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* st-indirect-offset: st $st_src, $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* st-indirect: st $st_src, ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* st-indirect-index: st $st_src, ($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* st-disp: st $st_src, $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* st-indirect-disp: st $st_src, $optdisp($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* st-index-disp: st $st_src, $optdisp[$index*S$scale */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* st-indirect-index-disp: st $st_src, $optdisp($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,st_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-offset: stob $st_src, $offset */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-indirect-offset: stob $st_src, $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-indirect: stob $st_src, ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-indirect-index: stob $st_src, ($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-disp: stob $st_src, $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-indirect-disp: stob $st_src, $optdisp($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-index-disp: stob $st_src, $optdisp[$index*S$scale */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stob-indirect-index-disp: stob $st_src, $optdisp($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stob_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    QI opval = * FLD (i_st_src);
+    SETMEMQI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-offset: stos $st_src, $offset */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-indirect-offset: stos $st_src, $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-indirect: stos $st_src, ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-indirect-index: stos $st_src, ($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-disp: stos $st_src, $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-indirect-disp: stos $st_src, $optdisp($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-index-disp: stos $st_src, $optdisp[$index*S$scale */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stos-indirect-index-disp: stos $st_src, $optdisp($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stos_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    HI opval = * FLD (i_st_src);
+    SETMEMHI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-offset: stl $st_src, $offset */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-indirect-offset: stl $st_src, $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-indirect: stl $st_src, ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-indirect-index: stl $st_src, ($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-disp: stl $st_src, $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-indirect-disp: stl $st_src, $optdisp($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-index-disp: stl $st_src, $optdisp[$index*S$scale */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stl-indirect-index-disp: stl $st_src, $optdisp($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-offset: stt $st_src, $offset */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-indirect-offset: stt $st_src, $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-indirect: stt $st_src, ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-indirect-index: stt $st_src, ($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-disp: stt $st_src, $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-indirect-disp: stt $st_src, $optdisp($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-index-disp: stt $st_src, $optdisp[$index*S$scale */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stt-indirect-index-disp: stt $st_src, $optdisp($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-offset: stq $st_src, $offset */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_offset), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-indirect-offset: stq $st_src, $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-indirect: stq $st_src, ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, * FLD (i_abase), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-indirect-index: stq $st_src, ($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-disp: stq $st_src, $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, FLD (f_optdisp), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-indirect-disp: stq $st_src, $optdisp($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), * FLD (i_abase)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-index-disp: stq $st_src, $optdisp[$index*S$scale */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* stq-indirect-index-disp: stq $st_src, $optdisp($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,stq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_sregno;
+  tmp_sregno = FLD (f_srcdst);
+  {
+    SI opval = * FLD (i_st_src);
+    SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (1))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (2))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = CPU (h_gr[((FLD (f_srcdst)) + (3))]);
+    SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 12), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+} while (0);
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpobe-reg: cmpobe $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobe_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobe-lit: cmpobe $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobe_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobne-reg: cmpobne $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobne-lit: cmpobne $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobne_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobl-reg: cmpobl $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobl-lit: cmpobl $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobl_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpoble-reg: cmpoble $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpoble_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpoble-lit: cmpoble $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpoble_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LEUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobg-reg: cmpobg $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobg-lit: cmpobg $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobg_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobge-reg: cmpobge $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpobge-lit: cmpobge $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpobge_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEUSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibe-reg: cmpibe $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibe_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibe-lit: cmpibe $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibe_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibne-reg: cmpibne $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibne-lit: cmpibne $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibne_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibl-reg: cmpibl $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibl-lit: cmpibl $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibl_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpible-reg: cmpible $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpible_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpible-lit: cmpible $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpible_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibg-reg: cmpibg $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTSI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibg-lit: cmpibg $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibg_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTSI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibge-reg: cmpibge $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GESI (* FLD (i_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpibge-lit: cmpibge $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpibge_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GESI (FLD (f_br_src1), * FLD (i_br_src2))) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bbc-reg: bbc $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bbc_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bbc-lit: bbc $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bbc_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bbs-reg: bbs $br_src1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bbs_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bbs-lit: bbs $br_lit1, $br_src2, $br_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bbs_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
+  {
+    USI opval = FLD (i_br_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* cmpi: cmpi $src1, $src2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpi1: cmpi $lit1, $src2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpi2: cmpi $src1, $lit2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpi3: cmpi $lit1, $lit2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpi3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpo: cmpo $src1, $src2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpo1: cmpo $lit1, $src2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpo2: cmpo $src1, $lit2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo2.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpo3: cmpo $lit1, $lit2 */
+
+SEM_PC
+SEM_FN_NAME (i960base,cmpo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_cmpo3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (LTUSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
+    CPU (h_cc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* testno-reg: testno $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,testno_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = EQSI (CPU (h_cc), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* testg-reg: testg $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,testg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 1), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* teste-reg: teste $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,teste_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 2), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* testge-reg: testge $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,testge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 3), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* testl-reg: testl $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,testl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 4), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* testne-reg: testne $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,testne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 5), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* testle-reg: testle $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,testle_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 6), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* testo-reg: testo $br_src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,testo_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_testno_reg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = NESI (ANDSI (CPU (h_cc), 7), 0);
+    * FLD (i_br_src1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "br_src1", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* bno: bno $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (CPU (h_cc), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bg: bg $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 1), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* be: be $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 2), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bge: bge $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 3), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bl: bl $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 4), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bne: bne $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 5), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* ble: ble $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 6), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bo: bo $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (ANDSI (CPU (h_cc), 7), 0)) {
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* b: b $ctrl_disp */
+
+SEM_PC
+SEM_FN_NAME (i960base,b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_b.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = FLD (i_ctrl_disp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bx-indirect-offset: bx $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,bx_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = ADDSI (FLD (f_offset), * FLD (i_abase));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bx-indirect: bx ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,bx_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = * FLD (i_abase);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bx-indirect-index: bx ($abase)[$index*S$scale] */
+
+SEM_PC
+SEM_FN_NAME (i960base,bx_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bx-disp: bx $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,bx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    USI opval = FLD (f_optdisp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* bx-indirect-disp: bx $optdisp($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,bx_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+  {
+    USI opval = ADDSI (FLD (f_optdisp), * FLD (i_abase));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* callx-disp: callx $optdisp */
+
+SEM_PC
+SEM_FN_NAME (i960base,callx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+do {
+  SI tmp_temp;
+  tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
+  {
+    SI opval = ADDSI (pc, 8);
+    CPU (h_gr[((UINT) 2)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0), CPU (h_gr[((UINT) 0)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4), CPU (h_gr[((UINT) 1)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8), CPU (h_gr[((UINT) 2)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12), CPU (h_gr[((UINT) 3)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16), CPU (h_gr[((UINT) 4)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20), CPU (h_gr[((UINT) 5)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24), CPU (h_gr[((UINT) 6)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28), CPU (h_gr[((UINT) 7)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32), CPU (h_gr[((UINT) 8)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36), CPU (h_gr[((UINT) 9)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40), CPU (h_gr[((UINT) 10)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44), CPU (h_gr[((UINT) 11)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48), CPU (h_gr[((UINT) 12)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52), CPU (h_gr[((UINT) 13)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT) 14)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)]));
+  {
+    USI opval = FLD (f_optdisp);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 1)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 2)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 3)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 4)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 5)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 6)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 7)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 8)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 9)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 10)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 11)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 12)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 13)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 14)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
+  {
+    SI opval = CPU (h_gr[((UINT) 31)]);
+    CPU (h_gr[((UINT) 0)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = tmp_temp;
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (tmp_temp, 64);
+    CPU (h_gr[((UINT) 1)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* callx-indirect: callx ($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,callx_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_temp;
+  tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 2)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0), CPU (h_gr[((UINT) 0)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4), CPU (h_gr[((UINT) 1)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8), CPU (h_gr[((UINT) 2)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12), CPU (h_gr[((UINT) 3)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16), CPU (h_gr[((UINT) 4)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20), CPU (h_gr[((UINT) 5)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24), CPU (h_gr[((UINT) 6)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28), CPU (h_gr[((UINT) 7)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32), CPU (h_gr[((UINT) 8)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36), CPU (h_gr[((UINT) 9)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40), CPU (h_gr[((UINT) 10)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44), CPU (h_gr[((UINT) 11)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48), CPU (h_gr[((UINT) 12)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52), CPU (h_gr[((UINT) 13)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT) 14)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)]));
+  {
+    USI opval = * FLD (i_abase);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 1)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 2)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 3)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 4)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 5)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 6)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 7)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 8)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 9)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 10)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 11)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 12)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 13)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 14)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
+  {
+    SI opval = CPU (h_gr[((UINT) 31)]);
+    CPU (h_gr[((UINT) 0)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = tmp_temp;
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (tmp_temp, 64);
+    CPU (h_gr[((UINT) 1)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* callx-indirect-offset: callx $offset($abase) */
+
+SEM_PC
+SEM_FN_NAME (i960base,callx_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  SI tmp_temp;
+  tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 2)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
+  }
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0), CPU (h_gr[((UINT) 0)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4), CPU (h_gr[((UINT) 1)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8), CPU (h_gr[((UINT) 2)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12), CPU (h_gr[((UINT) 3)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16), CPU (h_gr[((UINT) 4)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20), CPU (h_gr[((UINT) 5)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24), CPU (h_gr[((UINT) 6)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28), CPU (h_gr[((UINT) 7)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32), CPU (h_gr[((UINT) 8)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36), CPU (h_gr[((UINT) 9)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40), CPU (h_gr[((UINT) 10)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44), CPU (h_gr[((UINT) 11)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48), CPU (h_gr[((UINT) 12)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52), CPU (h_gr[((UINT) 13)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT) 14)]));
+SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)]));
+  {
+    USI opval = ADDSI (FLD (f_offset), * FLD (i_abase));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 1)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 2)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 3)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 4)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 5)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 6)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 7)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 8)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 9)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 10)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 11)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 12)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 13)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 14)]) = 0xdeadbeef;
+CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
+  {
+    SI opval = CPU (h_gr[((UINT) 31)]);
+    CPU (h_gr[((UINT) 0)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
+  }
+  {
+    SI opval = tmp_temp;
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+  {
+    SI opval = ADDSI (tmp_temp, 64);
+    CPU (h_gr[((UINT) 1)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* ret: ret */
+
+SEM_PC
+SEM_FN_NAME (i960base,ret) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  {
+    SI opval = CPU (h_gr[((UINT) 0)]);
+    CPU (h_gr[((UINT) 31)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr-31", 'x', opval);
+  }
+CPU (h_gr[((UINT) 0)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 0));
+CPU (h_gr[((UINT) 1)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 4));
+CPU (h_gr[((UINT) 2)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 8));
+CPU (h_gr[((UINT) 3)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 12));
+CPU (h_gr[((UINT) 4)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 16));
+CPU (h_gr[((UINT) 5)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 20));
+CPU (h_gr[((UINT) 6)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 24));
+CPU (h_gr[((UINT) 7)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 28));
+CPU (h_gr[((UINT) 8)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 32));
+CPU (h_gr[((UINT) 9)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 36));
+CPU (h_gr[((UINT) 10)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 40));
+CPU (h_gr[((UINT) 11)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 44));
+CPU (h_gr[((UINT) 12)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 48));
+CPU (h_gr[((UINT) 13)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 52));
+CPU (h_gr[((UINT) 14)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56));
+CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60));
+  {
+    USI opval = CPU (h_gr[((UINT) 2)]);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* calls: calls $src1 */
+
+SEM_PC
+SEM_FN_NAME (i960base,calls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_calls.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = i960_trap (current_cpu, pc, * FLD (i_src1));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* fmark: fmark */
+
+SEM_PC
+SEM_FN_NAME (i960base,fmark) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = i960_breakpoint (current_cpu, pc);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+  return vpc;
+#undef FLD
+}
+
+/* flushreg: flushreg */
+
+SEM_PC
+SEM_FN_NAME (i960base,flushreg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_flushreg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do { } while (0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
diff --git a/sim/i960/sim-if.c b/sim/i960/sim-if.c
new file mode 100644
index 00000000000..3a58548bcbf
--- /dev/null
+++ b/sim/i960/sim-if.c
@@ -0,0 +1,311 @@
+/* Main simulator entry points for the i960.
+   Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "libiberty.h"
+#include "bfd.h"
+#include "sim-main.h"
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "sim-options.h"
+#include "dis-asm.h"
+
+static void free_state (SIM_DESC);
+
+/* Since we don't build the cgen-opcode table, we use the old
+   disassembler.  */
+static CGEN_DISASSEMBLER i960_disassemble_insn;
+
+/* Records simulator descriptor so utilities like m32r_dump_regs can be
+   called from gdb.  */
+SIM_DESC current_state;
+
+/* Cover function of sim_state_free to free the cpu buffers as well.  */
+
+static void
+free_state (SIM_DESC sd)
+{
+  if (STATE_MODULES (sd) != NULL)
+    sim_module_uninstall (sd);
+  sim_cpu_free_all (sd);
+  sim_state_free (sd);
+}
+
+/* Create an instance of the simulator.  */
+
+SIM_DESC
+sim_open (kind, callback, abfd, argv)
+     SIM_OPEN_KIND kind;
+     host_callback *callback;
+     struct _bfd *abfd;
+     char **argv;
+{
+  char c;
+  int i;
+  SIM_DESC sd = sim_state_alloc (kind, callback);
+
+  /* The cpu data is kept in a separately allocated chunk of memory.  */
+  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: pc is in mach-specific struct */
+  /* FIXME: watchpoints code shouldn't need this */
+  {
+    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+    STATE_WATCHPOINTS (sd)->pc = &(PC);
+    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+  }
+#endif
+
+  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: 'twould be nice if we could do this */
+  /* These options override any module options.
+     Obviously ambiguity should be avoided, however the caller may wish to
+     augment the meaning of an option.  */
+  if (extra_options != NULL)
+    sim_add_option_table (sd, extra_options);
+#endif
+
+  /* getopt will print the error message so we just have to exit if this fails.
+     FIXME: Hmmm...  in the case of gdb we need getopt to call
+     print_filtered.  */
+  if (sim_parse_args (sd, argv) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Allocate a handler for the control registers and other devices
+     if no memory for that range has been allocated by the user.
+     All are allocated in one chunk to keep things from being
+     unnecessarily complicated.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, I960_DEVICE_ADDR, 1) == 0)
+    sim_core_attach (sd, NULL,
+		     0 /*level*/,
+		     access_read_write,
+		     0 /*space ???*/,
+		     I960_DEVICE_ADDR, I960_DEVICE_LEN /*nr_bytes*/,
+		     0 /*modulo*/,
+		     &i960_devices,
+		     NULL /*buffer*/);
+
+  /* Allocate core managed memory if none specified by user.
+     Use address 4 here in case the user wanted address 0 unmapped.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
+    /* ??? wilson */
+    sim_do_commandf (sd, "memory region 0x%lx,0x%lx", I960_DEFAULT_MEM_START,
+		     I960_DEFAULT_MEM_SIZE);
+
+  /* check for/establish the reference program image */
+  if (sim_analyze_program (sd,
+			   (STATE_PROG_ARGV (sd) != NULL
+			    ? *STATE_PROG_ARGV (sd)
+			    : NULL),
+			   abfd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Establish any remaining configuration options.  */
+  if (sim_config (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  if (sim_post_argv_init (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Open a copy of the cpu descriptor table.  */
+  {
+    CGEN_CPU_DESC cd = i960_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
+					   CGEN_ENDIAN_LITTLE);
+    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+      {
+	SIM_CPU *cpu = STATE_CPU (sd, i);
+	CPU_CPU_DESC (cpu) = cd;
+	CPU_DISASSEMBLER (cpu) = i960_disassemble_insn;
+      }
+  }
+
+  /* Initialize various cgen things not done by common framework.
+     Must be done after m32r_cgen_cpu_open.  */
+  cgen_init (sd);
+
+  /* Store in a global so things like sparc32_dump_regs can be invoked
+     from the gdb command line.  */
+  current_state = sd;
+
+  return sd;
+}
+
+void
+sim_close (sd, quitting)
+     SIM_DESC sd;
+     int quitting;
+{
+  i960_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+  sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_create_inferior (sd, abfd, argv, envp)
+     SIM_DESC sd;
+     struct _bfd *abfd;
+     char **argv;
+     char **envp;
+{
+  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+  SIM_ADDR addr;
+
+  if (abfd != NULL)
+    addr = bfd_get_start_address (abfd);
+  else
+    addr = 0;
+  sim_pc_set (current_cpu, addr);
+
+#if 0
+  STATE_ARGV (sd) = sim_copy_argv (argv);
+  STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+
+  return SIM_RC_OK;
+}
+
+#if 0
+int
+sim_stop (SIM_DESC sd)
+{
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_i960_ka_sa :
+      return i960base_engine_stop (sd, NULL, NULL_CIA, sim_stopped, SIM_SIGINT);
+    default :
+      abort ();
+    }
+}
+
+/* This isn't part of the official interface.
+   This is just a good place to put this for now.  */
+
+void
+sim_sync_stop (SIM_DESC sd, SIM_CPU *cpu, PCADDR pc, enum sim_stop reason, int sigrc)
+{
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_i960_ka_sa :
+      (void) i960base_engine_stop (sd, cpu, pc, reason, sigrc);
+      break;
+    default :
+      abort ();
+    }
+}
+
+void
+sim_resume (sd, step, siggnal)
+     SIM_DESC sd;
+     int step, siggnal;
+{
+  sim_module_resume (sd);
+
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_i960_ka_sa :
+      i960base_engine_run (sd, step, siggnal);
+      break;
+    default :
+      abort ();
+    }
+
+  sim_module_suspend (sd);
+}
+#endif
+
+/* The contents of BUF are in target byte order.  */
+
+int
+sim_fetch_register (sd, rn, buf, length)
+     SIM_DESC sd;
+     int rn;
+     unsigned char *buf;
+     int length;
+{
+  SIM_CPU *cpu = STATE_CPU (sd, 0);
+
+  return (* CPU_REG_FETCH (cpu)) (cpu, rn, buf, length);
+}
+ 
+/* The contents of BUF are in target byte order.  */
+
+int
+sim_store_register (sd, rn, buf, length)
+     SIM_DESC sd;
+     int rn;
+     unsigned char *buf;
+     int length;
+{
+  SIM_CPU *cpu = STATE_CPU (sd, 0);
+
+  return (* CPU_REG_STORE (cpu)) (cpu, rn, buf, length);
+}
+
+void
+sim_do_command (sd, cmd)
+     SIM_DESC sd;
+     char *cmd;
+{ 
+  if (sim_args_command (sd, cmd) != SIM_RC_OK)
+    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+}
+
+/* Disassemble an instruction.  */
+
+static void
+i960_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
+		       const ARGBUF *abuf, IADDR pc, char *buf)
+{
+  struct disassemble_info disasm_info;
+  SFILE sfile;
+  SIM_DESC sd = CPU_STATE (cpu);
+  int insn_length = CGEN_INSN_BITSIZE (insn) / 8;
+
+  sfile.buffer = sfile.current = buf;
+  INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
+			 (fprintf_ftype) sim_disasm_sprintf);
+  disasm_info.endian =
+    (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
+     : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
+     : BFD_ENDIAN_UNKNOWN);
+  disasm_info.read_memory_func = sim_disasm_read_memory;
+  disasm_info.memory_error_func = sim_disasm_perror_memory;
+  disasm_info.application_data = (PTR) cpu;
+
+  print_insn_i960 (pc, &disasm_info);
+}
diff --git a/sim/i960/sim-main.h b/sim/i960/sim-main.h
new file mode 100644
index 00000000000..abac5fcf2ac
--- /dev/null
+++ b/sim/i960/sim-main.h
@@ -0,0 +1,69 @@
+/* Main header for the i960.  */
+
+#define USING_SIM_BASE_H /* FIXME: quick hack */
+
+struct _sim_cpu; /* FIXME: should be in sim-basics.h */
+typedef struct _sim_cpu SIM_CPU;
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "i960-desc.h"
+#include "i960-opc.h"
+#include "arch.h"
+
+/* These must be defined before sim-base.h.  */
+typedef USI sim_cia;
+#define CIA_GET(cpu)     0 /* FIXME:(CPU_CGEN_HW (cpu)->h_pc) */
+#define CIA_SET(cpu,val) 0 /* FIXME:(CPU_CGEN_HW (cpu)->h_pc = (val)) */
+
+/* FIXME: Shouldn't be required to define these this early.  */
+#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
+#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA)
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "i960-sim.h"
+
+/* The _sim_cpu struct.  */
+
+struct _sim_cpu {
+  sim_cpu_base base;
+
+  /* Static parts of cgen.  */
+  CGEN_CPU cgen_cpu;
+
+  /* CPU specific parts go here.
+     Note that in files that don't need to access these pieces WANT_CPU_FOO
+     won't be defined and thus these parts won't appear.  This is ok.
+     One has to of course be careful to not take the size of this
+     struct and no structure members accessed in non-cpu specific files can
+     go after here.  */
+#if defined (WANT_CPU_I960BASE)
+  I960BASE_CPU_DATA cpu_data;
+#endif
+};
+
+/* The sim_state struct.  */
+
+struct sim_state {
+  sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+  CGEN_STATE cgen_state;
+
+  sim_state_base base;
+};
+
+/* Misc.  */
+
+/* Catch address exceptions.  */
+extern SIM_CORE_SIGNAL_FN i960_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+i960_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+		  (TRANSFER), (ERROR))
+
+/* Default memory size.  */
+/* This value comes from the libgloss/i960/mon960.ld linker script.  */
+#define I960_DEFAULT_MEM_START 0xa0008000
+#define I960_DEFAULT_MEM_SIZE 0x800000 /* 8M */
diff --git a/sim/i960/tconfig.in b/sim/i960/tconfig.in
new file mode 100644
index 00000000000..2acf4567251
--- /dev/null
+++ b/sim/i960/tconfig.in
@@ -0,0 +1,49 @@
+/* I960 target configuration file.  -*- C -*- */
+
+/* See sim-hload.c.  We properly handle LMA.  */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support.  FIXME: revisit.  */
+#define WITH_DEVICES 1
+
+/* FIXME: Revisit.  */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+#endif
+
+#if 0
+/* Enable watchpoints.  */
+#define WITH_WATCHPOINTS 1
+#endif
+
+/* ??? Temporary hack until model support unified.  */
+#define SIM_HAVE_MODEL
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
+   duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 0
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0x10, 0xf1 }
+#define SIM_BREAKPOINT_SIZE 2
+#endif
+
+/* This is a global setting.  Different cpu families can't mix-n-match -scache
+   and -pbb.  However some cpu families may use -simple while others use
+   one of -scache/-pbb.  */
+#define WITH_SCACHE_PBB 1
+
+#if 0
+/* ??? This was obsoleted by the PBB code.  */
+/* The semantic code should probably always use a switch().
+   However, in case that's not possible in some circumstance, we allow
+   the target to choose.  Perhaps this can be autoconf'd on whether the
+   switch is too big?  I can't (yet) think of a reason for allowing the
+   user to choose, though the developer may certainly wish to.  */
+#ifdef WANT_CPU_I960BASE
+#define WITH_FAST 1
+#define WITH_SEM_SWITCH_FULL 0
+#define WITH_SEM_SWITCH_FAST 1
+#endif
+#endif
diff --git a/sim/i960/traps.c b/sim/i960/traps.c
new file mode 100644
index 00000000000..5b62ca15574
--- /dev/null
+++ b/sim/i960/traps.c
@@ -0,0 +1,213 @@
+/* i960 exception, interrupt, and trap (EIT) support
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#include "targ-vals.h"
+
+/* The semantic code invokes this for illegal (unrecognized) instructions.  */
+
+void
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+#if 0
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      h_bsm_set (current_cpu, h_sm_get (current_cpu));
+      h_bie_set (current_cpu, h_ie_get (current_cpu));
+      h_bcond_set (current_cpu, h_cond_get (current_cpu));
+      /* sm not changed */
+      h_ie_set (current_cpu, 0);
+      h_cond_set (current_cpu, 0);
+
+      h_bpc_set (current_cpu, cia);
+
+      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+			  EIT_RSVD_INSN_ADDR);
+    }
+  else
+#endif
+    sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+}
+
+/* Process an address exception.  */
+
+void
+i960_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+		  unsigned int map, int nr_bytes, address_word addr,
+		  transfer_type transfer, sim_core_signals sig)
+{
+#if 0
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      h_bsm_set (current_cpu, h_sm_get (current_cpu));
+      h_bie_set (current_cpu, h_ie_get (current_cpu));
+      h_bcond_set (current_cpu, h_cond_get (current_cpu));
+      /* sm not changed */
+      h_ie_set (current_cpu, 0);
+      h_cond_set (current_cpu, 0);
+
+      h_bpc_set (current_cpu, cia);
+
+      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+			  EIT_ADDR_EXCP_ADDR);
+    }
+  else
+#endif
+    sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
+		     transfer, sig);
+}
+
+/* Read/write functions for system call interface.  */
+
+static int
+syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
+		  unsigned long taddr, char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
+}
+
+static int
+syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
+		   unsigned long taddr, const char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
+}
+
+/* Trap support.
+   The result is the pc address to continue at.
+   Preprocessing like saving the various registers has already been done.  */
+
+USI
+i960_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  host_callback *cb = STATE_CALLBACK (sd);
+
+#ifdef SIM_HAVE_BREAKPOINTS
+  /* Check for breakpoints "owned" by the simulator first, regardless
+     of --environment.  */
+  if (num == TRAP_BREAKPOINT)
+    {
+      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
+	 it doesn't return.  Otherwise it returns and let's us try.  */
+      sim_handle_breakpoint (sd, current_cpu, pc);
+      /* Fall through.  */
+    }
+#endif
+
+#if 0
+  /* ??? wilson, don't know what this does.  */
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      /* The new pc is the trap vector entry.
+	 We assume there's a branch there to some handler.  */
+      USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
+      return new_pc;
+    }
+#endif
+
+  switch (num)
+    {
+    default:
+    case TRAP_SYSCALL :
+      {
+	CB_SYSCALL s;
+
+	CB_SYSCALL_INIT (&s);
+	s.func = num;
+	s.arg1 = a_i960_h_gr_get (current_cpu, 16);
+	s.arg2 = a_i960_h_gr_get (current_cpu, 17);
+	s.arg3 = a_i960_h_gr_get (current_cpu, 18);
+
+	if (s.func == TARGET_SYS_exit)
+	  {
+	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
+	  }
+
+	s.p1 = (PTR) sd;
+	s.p2 = (PTR) current_cpu;
+	s.read_mem = syscall_read_mem;
+	s.write_mem = syscall_write_mem;
+	cb_syscall (cb, &s);
+	/* ??? This stuff is probably wrong, but libgloss doesn't look at
+	   these values, so it shouldn't matter.  */
+	a_i960_h_gr_set (current_cpu, 18, s.errcode);
+	a_i960_h_gr_set (current_cpu, 16, s.result);
+	a_i960_h_gr_set (current_cpu, 17, s.result2);
+	break;
+      }
+
+    case TRAP_BREAKPOINT:
+      sim_engine_halt (sd, current_cpu, NULL, NULL_CIA,
+		       sim_stopped, SIM_SIGTRAP);
+      break;
+
+#if 0
+      /* ??? wilson, don't know what this does.  */
+    default :
+      {
+	USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
+	return new_pc;
+      }
+#endif
+    }
+
+  /* Fake an "rte" insn.  */
+  /* FIXME: Should duplicate all of rte processing.  */
+  return (pc & -4) + 4;
+}
+
+/* Breakpoint support.
+   The result is the pc address to continue at.  */
+/* ??? This is an editted copy of the above.  */
+
+USI
+i960_breakpoint (SIM_CPU *current_cpu, PCADDR pc)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  host_callback *cb = STATE_CALLBACK (sd);
+
+#ifdef SIM_HAVE_BREAKPOINTS
+  /* Check for breakpoints "owned" by the simulator first, regardless
+     of --environment.  */
+  if (num == TRAP_BREAKPOINT)
+    {
+      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
+	 it doesn't return.  Otherwise it returns and let's us try.  */
+      sim_handle_breakpoint (sd, current_cpu, pc);
+      /* Fall through.  */
+    }
+#endif
+
+  sim_engine_halt (sd, current_cpu, NULL, NULL_CIA,
+		   sim_stopped, SIM_SIGTRAP);
+
+  /* Fake an "rte" insn.  */
+  /* FIXME: Should duplicate all of rte processing.  */
+  return (pc & -4) + 4;
+}