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authorJason Molenda <jsm@bugshack.cygnus.com>1999-11-17 02:31:06 +0000
committerJason Molenda <jsm@bugshack.cygnus.com>1999-11-17 02:31:06 +0000
commite49ad2d1d5b90c08b47a628a1e68c591029a5a15 (patch)
tree9114b63ccfe6a79e820431e18c8de6f6d8dbc54d /sim/mips/interp.c
parent5eae3750b9c334b4674593e17df0ac7a09b53ca0 (diff)
downloadgdb-e49ad2d1d5b90c08b47a628a1e68c591029a5a15.tar.gz
import gdb-1999-11-16 snapshot
Diffstat (limited to 'sim/mips/interp.c')
-rw-r--r--sim/mips/interp.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 396a93c1525..ef70ca63c4a 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -13,8 +13,8 @@
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- $Revision: 1.186 $
- $Date: 1999/09/03 19:18:46 $
+ $Revision: 1.187 $
+ $Date: 1999/11/11 18:13:32 $
NOTEs:
@@ -3124,9 +3124,14 @@ decode_coproc (SIM_DESC sd,
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
- if (((code == 0x00) || (code == 0x04)) && tail == 0)
+ if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
+ || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
+ && tail == 0)
{
- /* M[TF]C0 - 32 bit word */
+ /* Clear double/single coprocessor move bit. */
+ code &= ~1;
+
+ /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
switch (rd) /* NOTEs: Standard CP0 registers */
{