diff options
| author | Chris Demetriou <cgd@google.com> | 2002-03-06 06:21:17 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-03-06 06:21:17 +0000 |
| commit | 8d9c2f8f5ef5e6ca13e68a6469d6878d5bc67a8c (patch) | |
| tree | 302c9bded7e83092690ed0264ff8c4bcf475a073 /sim/mips | |
| parent | e36cb76d168b781d957857f37292fb1fb37aca88 (diff) | |
| download | gdb-8d9c2f8f5ef5e6ca13e68a6469d6878d5bc67a8c.tar.gz | |
2002-03-05 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (status_UX, status_SX, status_KX, status_TS)
(status_PX, status_MX, status_CU0, status_CU1, status_CU2)
(status_CU3): New definitions.
* sim-main.h (ExceptionCause): Add new values for MIPS32
and MIPS64: MDMX, MCheck, CacheErr. Update comments
for DebugBreakPoint and NMIReset to note their status in
MIPS32 and MIPS64.
(SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
(SignalExceptionCacheErr): New exception macros.
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 13 | ||||
| -rw-r--r-- | sim/mips/sim-main.h | 23 |
2 files changed, 34 insertions, 2 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 3bcc294859d..25ce89ce86b 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,5 +1,18 @@ 2002-03-05 Chris Demetriou <cgd@broadcom.com> + * sim-main.h (status_UX, status_SX, status_KX, status_TS) + (status_PX, status_MX, status_CU0, status_CU1, status_CU2) + (status_CU3): New definitions. + + * sim-main.h (ExceptionCause): Add new values for MIPS32 + and MIPS64: MDMX, MCheck, CacheErr. Update comments + for DebugBreakPoint and NMIReset to note their status in + MIPS32 and MIPS64. + (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) + (SignalExceptionCacheErr): New exception macros. + +2002-03-05 Chris Demetriou <cgd@broadcom.com> + * mips.igen (check_fpu): Enable check for coprocessor 1 usability. * sim-main.h (COP_Usable): Define, but for now coprocessor 1 is always enabled. diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 1870c965cd0..256dd1f7c96 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -534,6 +534,18 @@ struct sim_state { #define status_NMI (1 << 20) /* NMI */ #define status_NMI (1 << 20) /* NMI */ +/* Status bits used by MIPS32/MIPS64. */ +#define status_UX (1 << 5) /* 64-bit user addrs */ +#define status_SX (1 << 6) /* 64-bit supervisor addrs */ +#define status_KX (1 << 7) /* 64-bit kernel addrs */ +#define status_TS (1 << 21) /* TLB shutdown has occurred */ +#define status_PX (1 << 23) /* Enable 64 bit operations */ +#define status_MX (1 << 24) /* Enable MDMX resources */ +#define status_CU0 (1 << 28) /* Coprocessor 0 usable */ +#define status_CU1 (1 << 29) /* Coprocessor 1 usable */ +#define status_CU2 (1 << 30) /* Coprocessor 2 usable */ +#define status_CU3 (1 << 31) /* Coprocessor 3 usable */ + #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ #define cause_CE_mask 0x30000000 /* Coprocessor exception */ @@ -611,9 +623,12 @@ enum ExceptionCause { IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */ Trap = 13, FPE = 15, - DebugBreakPoint = 16, + DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */ + MDMX = 22, Watch = 23, - NMIReset = 31, + MCheck = 24, + CacheErr = 30, + NMIReset = 31, /* Reserved in MIPS32/MIPS64. */ /* The following exception code is actually private to the simulator @@ -660,6 +675,10 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID) #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID) #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification) +#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX) +#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch) +#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck) +#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr) /* Co-processor accesses */ |