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| author | Andrew Cagney <cagney@redhat.com> | 2003-06-03 20:54:43 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2003-06-03 20:54:43 +0000 |
| commit | 1684382a9110efd6523ce304cb99c869053323c8 (patch) | |
| tree | 40364f6d12e4c278425f9de47c2f4e15c98e8076 /sim/testsuite/sim/arm/xscale/miaph.cgs | |
| parent | 2729fb2483899a9b69e0d73500c79373156f27a7 (diff) | |
| download | gdb-cvs/cagney_writestrings-20030508-branch.tar.gz | |
Snap const char * mess.cvs/cagney_writestrings-20030508-branchcagney_writestrings-20030508-branch
Diffstat (limited to 'sim/testsuite/sim/arm/xscale/miaph.cgs')
| -rw-r--r-- | sim/testsuite/sim/arm/xscale/miaph.cgs | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/sim/testsuite/sim/arm/xscale/miaph.cgs b/sim/testsuite/sim/arm/xscale/miaph.cgs deleted file mode 100644 index 53fb2017f61..00000000000 --- a/sim/testsuite/sim/arm/xscale/miaph.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# XSCALE testcase for MIAPH -# mach: xscale -# as: -mcpu=xscale - - .include "testutils.inc" - - start - - .global miaph -miaph: - # Enable access to CoProcessors 0 & 1 before - # we attempt these instructions. - - mvi_h_gr r1, 3 - mcr p15, 0, r1, cr15, cr1, 0 - - # Test Multilply Accumulate - - mvi_h_gr r0, 0x11223344 - mvi_h_gr r1, 0x55667788 - mvi_h_gr r2, 0x12345678 - mvi_h_gr r3, 0x9abcdef0 - - mar acc0, r0, r1 - - miaph acc0, r2, r3 - - mra r0, r1, acc0 - - test_h_gr r0, 0xfec3f9f4 - test_h_gr r1, 0x55667787 - test_h_gr r2, 0x12345678 - test_h_gr r3, 0x9abcdef0 - - pass |