New sim testsuite for Fujitsu FRV. Contributed by Red Hat.

14 files changed, 979 insertions, 0 deletions

diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp
new file mode 100644
index 00000000000..8f8b7c9d2f3
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/allinsn.exp
@@ -0,0 +1,19 @@
+# FRV simulator testsuite.
+
+if [istarget frv*-*] {
+    # load support procs (none yet)
+    # load_lib cgen.exp
+    # all machines
+    set all_machs "fr400"
+    set cpu_option -mcpu
+
+    # The .cgs suffix is for "cgen .s".
+    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
+	# If we're only testing specific files and this isn't one of them,
+	# skip it.
+	if ![runtest_file_p $runtests $src] {
+	    continue
+	}
+	run_sim_test $src $all_machs
+    }
+}
diff --git a/sim/testsuite/sim/frv/fr400/csdiv.cgs b/sim/testsuite/sim/frv/fr400/csdiv.cgs
new file mode 100644
index 00000000000..9fa6d8c6af9
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/csdiv.cgs
@@ -0,0 +1,187 @@
+# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global csdiv
+csdiv:
+	set_spr_immed	0x1b1b,cccr
+
+	; simple division 12 / 3
+	set_gr_immed   	3,gr3
+	set_gr_immed   	12,gr1
+	csdiv      	gr1,gr3,gr2,cc4,1
+	test_gr_immed  	4,gr2
+
+	; Random example
+	set_gr_limmed  	0x0123,0x4567,gr3
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	csdiv      	gr1,gr3,gr2,cc4,1
+	test_gr_immed  	-1,gr2
+
+	; Special case from the Arch Spec Vol 2
+	and_spr_immed	-33,isr		; turn off isr.edem
+	; set up exception handler
+	set_psr_et	1
+	and_spr_immed	-4081,tbr	; clear tbr.tt
+	set_gr_spr	tbr,gr17
+	inc_gr_immed	0x170,gr17	; address of exception handler
+	set_bctrlr_0_0  gr17
+	set_spr_immed	128,lcr
+	set_gr_immed	0,gr15
+
+	; divide will cause overflow
+	set_spr_addr	ok1,lr
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+e1:	csdiv      	gr1,gr3,gr2,cc4,1
+	test_gr_immed	1,gr15
+	test_gr_limmed 	0x8000,0x0000,gr2
+
+	; Special case from the Arch Spec Vol 2
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc4,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; simple division 12 / 3
+	set_gr_immed   	3,gr3
+	set_gr_immed   	12,gr1
+	csdiv      	gr1,gr3,gr2,cc4,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Random example
+	set_gr_limmed  	0x0123,0x4567,gr3
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	csdiv      	gr1,gr3,gr2,cc4,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Special case from the Arch Spec Vol 2
+	and_spr_immed	-33,isr		; turn off isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc4,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc4,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; simple division 12 / 3
+	set_gr_immed   	3,gr3
+	set_gr_immed   	12,gr1
+	csdiv      	gr1,gr3,gr2,cc5,0
+	test_gr_immed  	4,gr2
+
+	; Random example
+	set_gr_limmed  	0x0123,0x4567,gr3
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	csdiv      	gr1,gr3,gr2,cc5,0
+	test_gr_immed  	-1,gr2
+
+	; Special case from the Arch Spec Vol 2
+	and_spr_immed	-33,isr		; turn off isr.edem
+	; divide will cause overflow
+	set_spr_addr	ok1,lr
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+e2:	csdiv      	gr1,gr3,gr2,cc5,0
+	test_gr_immed	2,gr15
+	test_gr_limmed 	0x8000,0x0000,gr2
+
+	; Special case from the Arch Spec Vol 2
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc5,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; simple division 12 / 3
+	set_gr_immed   	3,gr3
+	set_gr_immed   	12,gr1
+	csdiv      	gr1,gr3,gr2,cc5,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Random example
+	set_gr_limmed  	0x0123,0x4567,gr3
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	csdiv      	gr1,gr3,gr2,cc5,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Special case from the Arch Spec Vol 2
+	and_spr_immed	-33,isr		; turn off isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc5,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc5,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; simple division 12 / 3
+	set_gr_immed   	3,gr3
+	set_gr_immed   	12,gr1
+	csdiv      	gr1,gr3,gr2,cc6,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Random example
+	set_gr_limmed  	0x0123,0x4567,gr3
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	csdiv      	gr1,gr3,gr2,cc6,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Special case from the Arch Spec Vol 2
+	and_spr_immed	-33,isr		; turn off isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc6,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc6,0
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; simple division 12 / 3
+	set_gr_immed   	3,gr3
+	set_gr_immed   	12,gr1
+	csdiv      	gr1,gr3,gr2,cc7,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Random example
+	set_gr_limmed  	0x0123,0x4567,gr3
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	csdiv      	gr1,gr3,gr2,cc7,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	; Special case from the Arch Spec Vol 2
+	and_spr_immed	-33,isr		; turn off isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc7,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	csdiv      	gr1,gr3,gr2,cc7,1
+	test_gr_limmed 	0x7fff,0xffff,gr2
+
+	pass
+
+ok1:	; exception handler for overflow
+	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
+	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
+	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
+	inc_gr_immed	1,gr15
+	rett		0
+	fail
diff --git a/sim/testsuite/sim/frv/fr400/maveh.cgs b/sim/testsuite/sim/frv/fr400/maveh.cgs
new file mode 100644
index 00000000000..445e121daf6
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/maveh.cgs
@@ -0,0 +1,319 @@
+# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global maveh
+maveh:
+	; Test Rounding toward positive infinity via RDAV
+	or_spr_immed	0x20000000,msr0
+	and_spr_immed	0xefffffff,msr0
+
+	set_fr_iimmed	0x0000,0x0000,fr10
+	set_fr_iimmed	0x0000,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0x0000,fr12
+
+	set_fr_iimmed	0x0001,0x0000,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0002,0x0001,fr12
+
+	set_fr_iimmed	0x0000,0xffff,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0xffff,fr12
+
+	set_fr_iimmed	0xdead,0x0000,fr10
+	set_fr_iimmed	0x0000,0xbeef,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xef57,0xdf78,fr12
+
+	set_fr_iimmed	0x0000,0xdead,fr10
+	set_fr_iimmed	0xbeef,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xdf78,0xef57,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0x1111,0x1111,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x11a3,0x33c5,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0xffff,0xffff,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x091a,0x2b3c,fr12
+
+	set_fr_iimmed	0x7ffe,0x7ffe,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x4000,0x4000,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xc000,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xfffe,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xc000,fr12
+
+	set_fr_iimmed	0x8000,0x8000,fr10
+	set_fr_iimmed	0x7fff,0x7fff,fr11
+	maveh.p		fr10,fr10,fr12
+	maveh		fr11,fr11,fr13
+	test_fr_limmed	0x8000,0x8000,fr12
+	test_fr_limmed	0x7fff,0x7fff,fr13
+
+	; Test Rounding toward nearest via RD
+	or_spr_immed	0x10000000,msr0
+	and_spr_immed	0x3fffffff,msr0
+
+	set_fr_iimmed	0x0000,0x0000,fr10
+	set_fr_iimmed	0x0000,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0x0000,fr12
+
+	set_fr_iimmed	0x0001,0x0000,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0002,0x0001,fr12
+
+	set_fr_iimmed	0x0000,0xffff,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xffff,0xfffe,fr12
+
+	set_fr_iimmed	0xdead,0x0000,fr10
+	set_fr_iimmed	0x0000,0xbeef,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xef56,0xdf77,fr12
+
+	set_fr_iimmed	0x0000,0xdead,fr10
+	set_fr_iimmed	0xbeef,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xdf77,0xef56,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0x1111,0x1111,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x11a3,0x33c5,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0xffff,0xffff,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x091a,0x2b3c,fr12
+
+	set_fr_iimmed	0x7ffe,0x7ffe,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x4000,0x4000,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xbfff,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xfffe,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xbfff,0xbfff,fr12
+
+	set_fr_iimmed	0x8000,0x8000,fr10
+	set_fr_iimmed	0x7fff,0x7fff,fr11
+	maveh.p		fr10,fr10,fr12
+	maveh		fr11,fr11,fr13
+	test_fr_limmed	0x8000,0x8000,fr12
+	test_fr_limmed	0x7fff,0x7fff,fr13
+
+	; Test Rounding toward zero via RD
+	or_spr_immed	0x50000000,msr0
+	and_spr_immed	0x7fffffff,msr0
+
+	set_fr_iimmed	0x0000,0x0000,fr10
+	set_fr_iimmed	0x0000,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0x0000,fr12
+
+	set_fr_iimmed	0x0001,0x0000,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0001,0x0000,fr12
+
+	set_fr_iimmed	0x0000,0xffff,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0xffff,fr12
+
+	set_fr_iimmed	0xdead,0x0000,fr10
+	set_fr_iimmed	0x0000,0xbeef,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xef57,0xdf78,fr12
+
+	set_fr_iimmed	0x0000,0xdead,fr10
+	set_fr_iimmed	0xbeef,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xdf78,0xef57,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0x1111,0x1111,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x11a2,0x33c4,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0xffff,0xffff,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0919,0x2b3b,fr12
+
+	set_fr_iimmed	0x7ffe,0x7ffe,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x4000,0x3fff,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xc000,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xfffe,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xc000,fr12
+
+	set_fr_iimmed	0x8000,0x8000,fr10
+	set_fr_iimmed	0x7fff,0x7fff,fr11
+	maveh.p		fr10,fr10,fr12
+	maveh		fr11,fr11,fr13
+	test_fr_limmed	0x8000,0x8000,fr12
+	test_fr_limmed	0x7fff,0x7fff,fr13
+
+	; Test Rounding toward positive infinity via RD
+	or_spr_immed	0x90000000,msr0
+	and_spr_immed	0xbfffffff,msr0
+
+	set_fr_iimmed	0x0000,0x0000,fr10
+	set_fr_iimmed	0x0000,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0x0000,fr12
+
+	set_fr_iimmed	0x0001,0x0000,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0002,0x0001,fr12
+
+	set_fr_iimmed	0x0000,0xffff,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0xffff,fr12
+
+	set_fr_iimmed	0xdead,0x0000,fr10
+	set_fr_iimmed	0x0000,0xbeef,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xef57,0xdf78,fr12
+
+	set_fr_iimmed	0x0000,0xdead,fr10
+	set_fr_iimmed	0xbeef,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xdf78,0xef57,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0x1111,0x1111,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x11a3,0x33c5,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0xffff,0xffff,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x091a,0x2b3c,fr12
+
+	set_fr_iimmed	0x7ffe,0x7ffe,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x4000,0x4000,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xc000,fr12
+
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xfffe,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xc000,fr12
+
+	set_fr_iimmed	0x8000,0x8000,fr10
+	set_fr_iimmed	0x7fff,0x7fff,fr11
+	maveh.p		fr10,fr10,fr12
+	maveh		fr11,fr11,fr13
+	test_fr_limmed	0x8000,0x8000,fr12
+	test_fr_limmed	0x7fff,0x7fff,fr13
+
+	; Test Rounding toward negative infinity via RD
+	or_spr_immed	0xd0000000,msr0
+
+	set_fr_iimmed	0x0000,0x0000,fr10
+	set_fr_iimmed	0x0000,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0000,0x0000,fr12
+
+	set_fr_iimmed	0x0001,0x0000,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0001,0x0000,fr12
+
+	set_fr_iimmed	0x0000,0xffff,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xffff,0xfffe,fr12
+
+	set_fr_iimmed	0xdead,0x0000,fr10
+	set_fr_iimmed	0x0000,0xbeef,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xef56,0xdf77,fr12
+
+	set_fr_iimmed	0x0000,0xdead,fr10
+	set_fr_iimmed	0xbeef,0x0000,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xdf77,0xef56,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0x1111,0x1111,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x11a2,0x33c4,fr12
+
+	set_fr_iimmed	0x1234,0x5678,fr10
+	set_fr_iimmed	0xffff,0xffff,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x0919,0x2b3b,fr12
+
+	set_spr_immed	0,msr0
+	set_fr_iimmed	0x7ffe,0x7ffe,fr10
+	set_fr_iimmed	0x0002,0x0001,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0x4000,0x3fff,fr12
+
+	set_spr_immed	0,msr0
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xffff,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xc000,0xbfff,fr12
+
+	set_spr_immed	0,msr0
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0xfffe,0xfffe,fr11
+	maveh		fr10,fr11,fr12
+	test_fr_limmed	0xbfff,0xbfff,fr12
+
+	set_spr_immed	0,msr0
+	set_spr_immed	0,msr1
+	set_fr_iimmed	0x8000,0x8000,fr10
+	set_fr_iimmed	0x7fff,0x7fff,fr11
+	maveh.p		fr10,fr10,fr12
+	maveh		fr11,fr11,fr13
+	test_fr_limmed	0x8000,0x8000,fr12
+	test_fr_limmed	0x7fff,0x7fff,fr13
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/mclracc.cgs b/sim/testsuite/sim/frv/fr400/mclracc.cgs
new file mode 100644
index 00000000000..02975446be4
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/mclracc.cgs
@@ -0,0 +1,79 @@
+# frv testcase for mclracc $ACC40k,$A
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global mclracc
+mclracc:
+	set_accg_immed	0xff,accg0
+	set_acc_immed	-1,acc0
+	set_accg_immed	0xff,accg1
+	set_acc_immed	-1,acc1
+	set_accg_immed	0xff,accg2
+	set_acc_immed	-1,acc2
+	set_accg_immed	0xff,accg3
+	set_acc_immed	-1,acc3
+
+	mclracc		acc8,0		; nop
+	test_accg_immed	0xff,accg0
+	test_acc_immed	-1,acc0
+	test_accg_immed	0xff,accg1
+	test_acc_immed	-1,acc1
+	test_accg_immed	0xff,accg2
+	test_acc_immed	-1,acc2
+	test_accg_immed	0xff,accg3
+	test_acc_immed	-1,acc3
+
+	mclracc		acc8,1		; nop
+	test_accg_immed	0xff,accg0
+	test_acc_immed	-1,acc0
+	test_accg_immed	0xff,accg1
+	test_acc_immed	-1,acc1
+	test_accg_immed	0xff,accg2
+	test_acc_immed	-1,acc2
+	test_accg_immed	0xff,accg3
+	test_acc_immed	-1,acc3
+
+	mclracc		acc2,0
+	test_accg_immed	0xff,accg0
+	test_acc_immed	-1,acc0
+	test_accg_immed	0xff,accg1
+	test_acc_immed	-1,acc1
+	test_accg_immed	0,accg2
+	test_acc_immed	0,acc2
+	test_accg_immed	0xff,accg3
+	test_acc_immed	-1,acc3
+
+	mclracc		acc3,1
+	test_accg_immed	0xff,accg0
+	test_acc_immed	-1,acc0
+	test_accg_immed	0xff,accg1
+	test_acc_immed	-1,acc1
+	test_accg_immed	0,accg2
+	test_acc_immed	0,acc2
+	test_accg_immed	0,accg3
+	test_acc_immed	0,acc3
+
+	mclracc		acc0,0
+	test_accg_immed	0,accg0
+	test_acc_immed	0,acc0
+	test_accg_immed	0xff,accg1
+	test_acc_immed	-1,acc1
+	test_accg_immed	0,accg2
+	test_acc_immed	0,acc2
+	test_accg_immed	0,accg3
+	test_acc_immed	0,acc3
+
+	mclracc		acc0,1
+	test_accg_immed	0,accg0
+	test_acc_immed	0,acc0
+	test_accg_immed	0,accg1
+	test_acc_immed	0,acc1
+	test_accg_immed	0,accg2
+	test_acc_immed	0,acc2
+	test_accg_immed	0,accg3
+	test_acc_immed	0,acc3
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhdseth.cgs b/sim/testsuite/sim/frv/fr400/mhdseth.cgs
new file mode 100644
index 00000000000..b99c996f78b
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/mhdseth.cgs
@@ -0,0 +1,22 @@
+# frv testcase for mhdseth $s12,$FRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global mhdseth
+mhdseth:
+	set_fr_immed	0,fr1
+	mhdseth		0,fr1
+	test_fr_iimmed	0,fr1
+	mhdseth		1,fr1
+	test_fr_iimmed	0x08000800,fr1 
+	mhdseth		0xf,fr1
+	test_fr_iimmed	0x78007800,fr1
+	mhdseth		-16,fr1
+	test_fr_iimmed	0x80008000,fr1
+	mhdseth		-1,fr1
+	test_fr_iimmed	0xf800f800,fr1
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhdsets.cgs b/sim/testsuite/sim/frv/fr400/mhdsets.cgs
new file mode 100644
index 00000000000..c495cb7130c
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/mhdsets.cgs
@@ -0,0 +1,20 @@
+# frv testcase for mhdsets $s12,$FRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global mhdsets
+mhdsets:
+	set_fr_immed	0,fr1
+	mhdsets		0,fr1
+	test_fr_iimmed	0,fr1
+	mhdsets		1,fr1
+	test_fr_iimmed	0x00010001,fr1
+	mhdsets		0x7ff,fr1
+	test_fr_iimmed	0x07ff07ff,fr1
+	mhdsets		-2048,fr1
+	test_fr_iimmed	0xf800f800,fr1
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsethih.cgs b/sim/testsuite/sim/frv/fr400/mhsethih.cgs
new file mode 100644
index 00000000000..fed9d2335e7
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/mhsethih.cgs
@@ -0,0 +1,22 @@
+# frv testcase for mhsethih $s12,$FRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global mhsethih
+mhsethih:
+	set_fr_immed	0,fr1
+	mhsethih	0,fr1
+	test_fr_iimmed	0,fr1
+	mhsethih	1,fr1
+	test_fr_iimmed	0x08000000,fr1 
+	mhsethih	0xf,fr1
+	test_fr_iimmed	0x78000000,fr1
+	mhsethih	-16,fr1
+	test_fr_iimmed	0x80000000,fr1
+	mhsethih	-1,fr1
+	test_fr_iimmed	0xf8000000,fr1
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsethis.cgs b/sim/testsuite/sim/frv/fr400/mhsethis.cgs
new file mode 100644
index 00000000000..ade9102a5e3
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/mhsethis.cgs
@@ -0,0 +1,25 @@
+# frv testcase for mhsethis $s12,$FRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global mhsethis
+mhsethis:
+	set_fr_immed	0,fr1
+	mhsethis	0,fr1
+	test_fr_iimmed	0,fr1
+	mhsethis	1,fr1
+	test_fr_iimmed	0x00010000,fr1
+	mhsethis	0x7ff,fr1
+	test_fr_iimmed	0x07ff0000,fr1
+	mhsethis	-2048,fr1
+	test_fr_iimmed	0xf8000000,fr1
+
+	; Try parallel set of hi and lo at the same time
+	mhsethis.p	1,fr1
+	mhsetlos	2,fr1
+	test_fr_iimmed	0x00010002,fr1
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs
new file mode 100644
index 00000000000..1dedb836eca
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs
@@ -0,0 +1,27 @@
+# frv testcase for mhsetloh $s12,$FRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global mhsetloh
+mhsetloh:
+	set_fr_immed	0,fr1
+	mhsetloh	0,fr1
+	test_fr_iimmed	0,fr1
+	mhsetloh	1,fr1
+	test_fr_iimmed	0x0000800,fr1 
+	mhsetloh	0xf,fr1
+	test_fr_iimmed	0x00007800,fr1
+	mhsetloh	-16,fr1
+	test_fr_iimmed	0x00008000,fr1
+	mhsetloh	-1,fr1
+	test_fr_iimmed	0x0000f800,fr1
+
+	; Try parallel write to both hi and lo
+	mhsetloh.p	1,fr1
+	mhsethih	0xf,fr1
+	test_fr_iimmed	0x78000800,fr1
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs
new file mode 100644
index 00000000000..8e8839ab6e9
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs
@@ -0,0 +1,25 @@
+# frv testcase for mhsetlos $s12,$FRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global mhsetlos
+mhsetlos:
+	set_fr_immed	0,fr1
+	mhsetlos	0,fr1
+	test_fr_iimmed	0,fr1
+	mhsetlos	1,fr1
+	test_fr_iimmed	0x00000001,fr1
+	mhsetlos	0x7ff,fr1
+	test_fr_iimmed	0x000007ff,fr1
+	mhsetlos	-2048,fr1
+	test_fr_iimmed	0x0000f800,fr1
+
+	; Try parallel set of hi and lo at the same time
+	mhsethis.p	1,fr1
+	mhsetlos	2,fr1
+	test_fr_iimmed	0x00010002,fr1
+
+	pass
diff --git a/sim/testsuite/sim/frv/fr400/sdiv.cgs b/sim/testsuite/sim/frv/fr400/sdiv.cgs
new file mode 100644
index 00000000000..b9c03cfeea3
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/sdiv.cgs
@@ -0,0 +1,71 @@
+# frv testcase for sdiv $GRi,$GRj,$GRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global sdiv
+sdiv:
+	; simple division 12 / 3
+	set_gr_immed   	3,gr3
+	set_gr_immed   	12,gr1
+	sdiv      	gr1,gr3,gr2
+	test_gr_immed  	4,gr2
+
+	; Random example
+	set_gr_limmed  	0x0123,0x4567,gr3
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	sdiv      	gr1,gr3,gr2
+	test_gr_immed  	-1,gr2
+
+	; Special case from the Arch Spec Vol 2
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+	sdiv      	gr1,gr3,gr2
+	test_gr_limmed 	0x7fff,0xffff,gr2
+	test_spr_bits	0x4,2,1,isr	; isr.aexc is set
+
+	and_spr_immed	-33,isr		; turn off isr.edem
+	; set up exception handler
+	set_psr_et	1
+	and_spr_immed	-4081,tbr	; clear tbr.tt
+	set_gr_spr	tbr,gr17
+	inc_gr_immed	0x170,gr17	; address of exception handler
+	set_bctrlr_0_0  gr17
+	set_spr_immed	128,lcr
+	set_gr_immed	0,gr15
+
+	; divide will cause overflow
+	set_spr_addr	ok1,lr
+	set_gr_immed  	-1,gr3
+	set_gr_limmed  	0x8000,0x0000,gr1
+e1:	sdiv      	gr1,gr3,gr2	; overflow
+	test_gr_immed	1,gr15
+	test_gr_limmed 	0x8000,0x0000,gr2; gr2 updated
+
+	; divide by zero
+	set_spr_addr	ok2,lr
+	set_gr_immed	0xdeadbeef,gr2
+e2:	sdiv      	gr1,gr0,gr2	; divide by zero
+	test_gr_immed	2,gr15		; handler called
+	test_gr_immed	0xdeadbeef,gr2	; gr2 not updated.
+
+	pass
+
+ok1:	; exception handler for overflow
+	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
+	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
+	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
+	inc_gr_immed	1,gr15
+	rett		0
+	fail
+
+ok2:	; exception handler for divide by zero
+	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
+	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
+	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
+	inc_gr_immed	1,gr15
+	rett		0
+	fail
diff --git a/sim/testsuite/sim/frv/fr400/sdivi.cgs b/sim/testsuite/sim/frv/fr400/sdivi.cgs
new file mode 100644
index 00000000000..fda573e5842
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/sdivi.cgs
@@ -0,0 +1,70 @@
+# frv testcase for sdivi $GRi,$s12,$GRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global sdivi
+sdivi:
+	; simple division 12 / 3
+	set_gr_immed   	12,gr1
+	sdivi      	gr1,3,gr2
+	test_gr_immed  	4,gr2
+
+	; Random example
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	sdivi      	gr1,0x7ff,gr2
+	test_gr_limmed 	0xffff,0xdb93,gr2
+
+	; Random negative example
+	set_gr_limmed  	0xfedc,0xba98,gr1
+	sdivi      	gr1,-2048,gr2
+	test_gr_immed 	0x2468,gr2
+
+	; Special case from the Arch Spec Vol 2
+	or_spr_immed	0x20,isr	; turn on isr.edem
+	set_gr_limmed  	0x8000,0x0000,gr1
+	sdivi      	gr1,-1,gr2
+	test_gr_limmed 	0x7fff,0xffff,gr2
+	test_spr_bits	0x4,2,1,isr	; isr.aexc is set
+
+	and_spr_immed	-33,isr		; turn off isr.edem
+	; set up exception handler
+	set_psr_et	1
+	and_spr_immed	-4081,tbr	; clear tbr.tt
+	set_gr_spr	tbr,gr17
+	inc_gr_immed	0x170,gr17	; address of exception handler
+	set_bctrlr_0_0  gr17
+	set_spr_immed	128,lcr
+	set_gr_immed	0,gr15
+
+	; divide will cause overflow
+	set_spr_addr	ok1,lr
+	set_gr_limmed  	0x8000,0x0000,gr1
+e1:	sdivi      	gr1,-1,gr2
+	test_gr_immed	1,gr15
+	test_gr_limmed 	0x8000,0x0000,gr2
+
+	; divide by zero
+	set_spr_addr	ok2,lr
+e2:	sdivi      	gr1,0,gr2	; divide by zero
+	test_gr_immed	2,gr15
+
+	pass
+
+ok1:	; exception handler for overflow
+	test_spr_bits	0x18,3,0x2,isr		; isr.dtt is set
+	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
+	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
+	inc_gr_immed	1,gr15
+	rett		0
+	fail
+
+ok2:	; exception handler for divide by zero
+	test_spr_bits	0x18,3,0x3,isr		; isr.dtt is set
+	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
+	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
+	inc_gr_immed	1,gr15
+	rett		0
+	fail
diff --git a/sim/testsuite/sim/frv/fr400/udiv.cgs b/sim/testsuite/sim/frv/fr400/udiv.cgs
new file mode 100644
index 00000000000..25ae7b3bf6b
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/udiv.cgs
@@ -0,0 +1,46 @@
+# frv testcase for udiv $GRi,$GRj,$GRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global udiv
+udiv:
+	; simple division 12 / 3
+	set_gr_immed   	0x00000003,gr2
+	set_gr_immed   	0x0000000c,gr3
+	udiv      	gr3,gr2,gr3
+	test_gr_immed  	0x00000003,gr2
+	test_gr_immed  	0x00000004,gr3
+
+	; example 1 from udiv in the fr30 manual
+	set_gr_limmed  	0x0123,0x4567,gr2
+	set_gr_limmed  	0xfedc,0xba98,gr3
+	udiv      	gr3,gr2,gr3
+	test_gr_limmed 	0x0123,0x4567,gr2
+	test_gr_immed  	0x000000e0,gr3
+
+	; set up exception handler
+	set_psr_et	1
+	and_spr_immed	-4081,tbr	; clear tbr.tt
+	set_gr_spr	tbr,gr17
+	inc_gr_immed	0x170,gr17	; address of exception handler
+	set_bctrlr_0_0  gr17
+	set_spr_immed	128,lcr
+	set_gr_immed	0,gr15
+
+	; divide by zero
+	set_spr_addr	ok1,lr
+e1:	udiv      	gr1,gr0,gr2	; divide by zero
+	test_gr_immed	1,gr15
+
+	pass
+
+ok1:	; exception handler for divide by zero
+	test_spr_bits	0x18,3,0x1,isr		; isr.dtt is set
+	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
+	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
+	inc_gr_immed	1,gr15
+	rett		0
+	fail
diff --git a/sim/testsuite/sim/frv/fr400/udivi.cgs b/sim/testsuite/sim/frv/fr400/udivi.cgs
new file mode 100644
index 00000000000..242952b90d4
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr400/udivi.cgs
@@ -0,0 +1,47 @@
+# frv testcase for udivi $GRi,$s12,$GRk
+# mach: all
+
+	.include "../testutils.inc"
+
+	start
+
+	.global udivi
+udivi:
+	; simple division 12 / 3
+	set_gr_immed   	0x0000000c,gr3
+	udivi      	gr3,3,gr3
+	test_gr_immed  	0x00000004,gr3
+
+	; random example
+	set_gr_limmed  	0xfedc,0xba98,gr3
+	udivi      	gr3,0x7ff,gr3
+	test_gr_limmed 	0x001f,0xdf93,gr3
+
+	; random example
+	set_gr_limmed  	0xffff,0xffff,gr3
+	udivi      	gr3,-2048,gr3
+	test_gr_immed 	1,gr3
+
+	; set up exception handler
+	set_psr_et	1
+	and_spr_immed	-4081,tbr	; clear tbr.tt
+	set_gr_spr	tbr,gr17
+	inc_gr_immed	0x170,gr17	; address of exception handler
+	set_bctrlr_0_0  gr17
+	set_spr_immed	128,lcr
+	set_gr_immed	0,gr15
+
+	; divide by zero
+	set_spr_addr	ok1,lr
+e1:	udivi      	gr1,0,gr2	; divide by zero
+	test_gr_immed	1,gr15
+
+	pass
+
+ok1:	; exception handler for divide by zero
+	test_spr_bits	0x18,3,0x1,isr		; isr.dtt is set
+	test_spr_bits	0x0001,0,0x1,esr0	; esr0 is valid
+	test_spr_bits	0x003e,1,0x13,esr0	; esr0.ec is set
+	inc_gr_immed	1,gr15
+	rett		0
+	fail