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| author | Dave Brolley <brolley@redhat.com> | 2003-08-29 16:41:31 +0000 |
|---|---|---|
| committer | Dave Brolley <brolley@redhat.com> | 2003-08-29 16:41:31 +0000 |
| commit | 29f63e3a7cd1a6196021db84f330cfc5d4277f9f (patch) | |
| tree | 1056bea2e5d045b9afb24a2e6b25081fea1b4fc7 /sim/testsuite/sim/frv/fteq.cgs | |
| parent | 8ada8fd2eed30b6843d326fc6a3606f4e9c6d21f (diff) | |
| download | gdb-29f63e3a7cd1a6196021db84f330cfc5d4277f9f.tar.gz | |
New sim testsuite for Fujitsu FRV. Contributed by Red Hat.
Diffstat (limited to 'sim/testsuite/sim/frv/fteq.cgs')
| -rw-r--r-- | sim/testsuite/sim/frv/fteq.cgs | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/sim/testsuite/sim/frv/fteq.cgs b/sim/testsuite/sim/frv/fteq.cgs new file mode 100644 index 00000000000..020a88712ee --- /dev/null +++ b/sim/testsuite/sim/frv/fteq.cgs @@ -0,0 +1,101 @@ +# frv testcase for fteq $FCCi_2,$GRi,$GRj +# mach: all + + .include "testutils.inc" + + start + + .global fteq +fteq: + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr7 + inc_gr_immed 2112,gr7 ; address of exception handler + set_bctrlr_0_0 gr7 ; bctrlr 0,0 + + set_spr_immed 128,lcr + set_gr_immed 0,gr7 + set_gr_immed 4,gr8 + + set_spr_addr bad,lr + set_fcc 0x0 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x1 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x2 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x3 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x4 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x5 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x6 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_spr_addr bad,lr + set_fcc 0x7 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + + set_psr_et 1 + set_spr_addr ok8,lr + set_fcc 0x8 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok8: + set_psr_et 1 + set_spr_addr ok9,lr + set_fcc 0x9 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +ok9: + set_psr_et 1 + set_spr_addr oka,lr + set_fcc 0xa 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oka: + set_psr_et 1 + set_spr_addr okb,lr + set_fcc 0xb 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okb: + set_psr_et 1 + set_spr_addr okc,lr + set_fcc 0xc 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okc: + set_psr_et 1 + set_spr_addr okd,lr + set_fcc 0xd 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okd: + set_psr_et 1 + set_spr_addr oke,lr + set_fcc 0xe 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +oke: + set_psr_et 1 + set_spr_addr okf,lr + set_fcc 0xf 0 + fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 + fail +okf: + pass +bad: + fail |