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| author | Jim Blandy <jimb@codesourcery.com> | 2004-09-22 18:49:07 +0000 |
|---|---|---|
| committer | Jim Blandy <jimb@codesourcery.com> | 2004-09-22 18:49:07 +0000 |
| commit | c182e1c896482e9645589b7fe00637637f5fd8ee (patch) | |
| tree | f36b5da2ab92cefdda813b59897bd952a9208272 /sim/testsuite/sim/frv/mdsubaccs.cgs | |
| parent | 148551e5315b1908ddedeb35c817900fd915675b (diff) | |
| download | gdb-c182e1c896482e9645589b7fe00637637f5fd8ee.tar.gz | |
* dwarf2loc.c (dwarf2_evaluate_loc_desc): Fix misapplied patch.
Diffstat (limited to 'sim/testsuite/sim/frv/mdsubaccs.cgs')
| -rw-r--r-- | sim/testsuite/sim/frv/mdsubaccs.cgs | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/sim/testsuite/sim/frv/mdsubaccs.cgs b/sim/testsuite/sim/frv/mdsubaccs.cgs new file mode 100644 index 00000000000..73d2e2dc899 --- /dev/null +++ b/sim/testsuite/sim/frv/mdsubaccs.cgs @@ -0,0 +1,102 @@ +# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "testutils.inc" + + start + + .global mdsubaccs +mdsubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0xdead0000,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x0000beef,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x11111111,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x4111,0xdead,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x12345678,acc2 + set_accg_immed 0xff,accg3 + set_acc_immed 0xffffffff,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg2 + test_acc_limmed 0x1234,0x5679,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + set_accg_immed 0x80,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0,accg3 + set_acc_immed 0x00000002,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + mdsubaccs acc0,acc2 + test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf is set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass |