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| author | Ben Elliston <bje@au.ibm.com> | 2002-02-01 11:44:32 +0000 |
|---|---|---|
| committer | Ben Elliston <bje@au.ibm.com> | 2002-02-01 11:44:32 +0000 |
| commit | 3da25b5a2a8931f5143b423021e4e95f57c78c52 (patch) | |
| tree | 8cfe23621092082a7b1f18f9cd5bd7287fe47807 /sim/testsuite/sim/sh64 | |
| parent | a50dc7f4d7e5d1474295a119df0c4ec7c715f277 (diff) | |
| download | gdb-3da25b5a2a8931f5143b423021e4e95f57c78c52.tar.gz | |
* Contribute Hitachi SH5 simulator.
Diffstat (limited to 'sim/testsuite/sim/sh64')
390 files changed, 13495 insertions, 0 deletions
diff --git a/sim/testsuite/sim/sh64/ChangeLog b/sim/testsuite/sim/sh64/ChangeLog new file mode 100644 index 00000000000..8bb2f764ae6 --- /dev/null +++ b/sim/testsuite/sim/sh64/ChangeLog @@ -0,0 +1,21 @@ +2001-01-06 Ben Elliston <bje@redhat.com> + + * misc/fr-dr.s: New test. + +2001-01-03 Ben Elliston <bje@redhat.com> + + * interwork.exp: Match .s files only. + +2000-12-06 Ben Elliston <bje@redhat.com> + + * interwork.exp: New test case. + +2000-11-16 Ben Elliston <bje@redhat.com> + + * allinsn.exp: Rename from this .. + * compact.exp: .. to this. + * media.exp: New test case. + +2000-11-13 Ben Elliston <bje@redhat.com> + + * allinsn.exp: New test case. diff --git a/sim/testsuite/sim/sh64/compact.exp b/sim/testsuite/sim/sh64/compact.exp new file mode 100644 index 00000000000..d3d482acf0f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact.exp @@ -0,0 +1,19 @@ +# SHcompact testsuite. + +if [istarget sh64-*-*] { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "sh5" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/compact/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/sh64/compact/ChangeLog b/sim/testsuite/sim/sh64/compact/ChangeLog new file mode 100644 index 00000000000..99aaec1ff02 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ChangeLog @@ -0,0 +1,26 @@ +2002-01-09 Ben Elliston <bje@redhat.com> + + * macl.cgs: For good measure, clear the S bit at startup. + +2001-01-11 Ben Elliston <bje@redhat.com> + + * fmov.cgs (f13b): Compare R0 with R1, not R2, when testing that + the source register was correctly post-incremented. + +2000-12-01 Ben Elliston <bje@redhat.com> + + * *.cgs (ld): Link tests with -m shelf32. + +2000-11-24 Ben Elliston <bje@redhat.com> + + * fmov.cgs: New test case. + * ftrv.cgs: Populate the matrix with meaningful values. + +2000-11-22 Ben Elliston <bje@redhat.com> + + * *.cgs (as): Assemble tests with -isa=shcompact. + +2000-11-16 Ben Elliston <bje@redhat.com> + + * *.cgs: New test cases. + diff --git a/sim/testsuite/sim/sh64/compact/add.cgs b/sim/testsuite/sim/sh64/compact/add.cgs new file mode 100644 index 00000000000..105e4849069 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/add.cgs @@ -0,0 +1,55 @@ +# sh testcase for add $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +init: + # Initialise some registers with values which help us to verify + # that the correct source registers are used by the ADD instruction. + mov #0, r0 + mov #1, r1 + mov #2, r2 + mov #3, r3 + mov #5, r5 + mov #15, r15 + +add: + # 0 + 0 = 0. + add r0, r0 + assert r0, #0 + + # 0 + 1 = 1. + add r0, r1 + assert r1, #1 + + # 1 + 2 = 3. + add r1, r2 + assert r2, #3 + + # 3 + 5 = 8. + add r3, r5 + assert r5, #8 + + # 8 + 8 = 16. + add r5, r5 + assert r5, #16 + + # 15 + 1 = 16. + add r15, r1 + assert r1, #16 + +neg: + mov #1, r0 + neg r0, r0 + mov #2, r1 + add r0, r1 + assert r1, #1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/addc.cgs b/sim/testsuite/sim/sh64/compact/addc.cgs new file mode 100644 index 00000000000..f6e46e1a969 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/addc.cgs @@ -0,0 +1,90 @@ +# sh testcase for addc $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + # Initialise some registers with values which help us to verify + # that the correct source registers are used by the ADDC instruction. + + .macro init + mov #0, r0 + mov #1, r1 + mov #2, r2 + mov #3, r3 + mov #5, r5 + mov #15, r15 + .endm + + start + + init +add: + clrt + addc r0, r0 + assert r0, #0 + clrt + addc r0, r1 + assert r1, #1 + clrt + addc r1, r2 + assert r2, #3 + clrt + addc r3, r5 + assert r5, #8 + clrt + addc r5, r5 + assert r5, #16 + clrt + addc r15, r1 + assert r1, #16 + + init +addt: + sett + addc r0, r0 + assert r0, #1 + sett + addc r0, r1 + assert r1, #3 + sett + addc r1, r2 + assert r2, #6 + sett + addc r3, r5 + assert r5, #9 + sett + addc r5, r5 + assert r5, #19 + sett + addc r15, r1 + assert r1, #19 + + bra next + nop + +wrong: + fail + +next: + init +large: + clrt + mov #1, r0 + neg r0, r0 + mov #2, r1 + addc r0, r1 + assert r1, #1 + + init +larget: + sett + mov #1, r0 + neg r0, r0 + mov #2, r1 + addc r0, r1 + assert r1, #2 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/addi.cgs b/sim/testsuite/sim/sh64/compact/addi.cgs new file mode 100644 index 00000000000..7c96ddf76d5 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/addi.cgs @@ -0,0 +1,46 @@ +# sh testcase for add #$imm8, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +init: + # Initialise some registers with values which help us to verify + # that the correct source registers are used by the ADD instruction. + mov #0, r0 + mov #1, r1 + mov #2, r2 + mov #3, r3 + mov #5, r5 + mov #15, r15 + +addi: + # 0 + 0 = 0. + add #0, r0 + assert r0, #0 + + # 0 + 1 = 1. + add #0, r1 + assert r1, #1 + + # 2 + 2 = 4. + add #2, r2 + assert r2, #4 + + # 120 + 5 = 125. + add #120, r5 + assert r5, #125 + +large: + mov #1, r0 + neg r0, r0 + add #2, r0 + assert r0, #1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/addv.cgs b/sim/testsuite/sim/sh64/compact/addv.cgs new file mode 100644 index 00000000000..0267e5dfa00 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/addv.cgs @@ -0,0 +1,48 @@ +# sh testcase for addv $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +zero: + mov #0, r0 + mov #0, r1 + addv r0, r1 + # Assert !T and #0. + bt wrong + assert r1, #0 + +one: + mov #0, r0 + mov #1, r1 + addv r0, r1 + # Assert !T and #1. + bt wrong + assert r1, #1 + +large: + # Produce MAXINT in R0. + mov #0, r0 + not r0, r0 + shlr r0 + + # Put #3 into R1. + mov #3, r1 + + # Add them and overflow. + addv r0, r1 + + # Assert T and overflowed value. + bf wrong + mov #1, r7 + rotr r7 + add #2, r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/and.cgs b/sim/testsuite/sim/sh64/compact/and.cgs new file mode 100644 index 00000000000..e1452752ae0 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/and.cgs @@ -0,0 +1,33 @@ +# sh testcase for and $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global and +and: + mov #1, r1 + mov #7, r2 + rotr r2 + rotr r2 + and r1, r2 + + # R1 & R2 = 1. + assert r2, #1 + +another: + mov #192, r1 + mov #0, r2 + and r1, r2 + + # R1 & R2 = 0. + assert r2, #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/andb.cgs b/sim/testsuite/sim/sh64/compact/andb.cgs new file mode 100644 index 00000000000..77e628598b1 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/andb.cgs @@ -0,0 +1,24 @@ +# sh testcase for and.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + and.b #255, @(r0, gbr) + and.b #170, @(r0, gbr) + and.b #255, @(r0, gbr) + and.b #0, @(r0, gbr) + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/andi.cgs b/sim/testsuite/sim/sh64/compact/andi.cgs new file mode 100644 index 00000000000..32d71c5b477 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/andi.cgs @@ -0,0 +1,43 @@ +# sh testcase for and #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global andi +andi: + mov #0, r0 + or #255, r0 + and #0, r0 + assert r0, #0 + +large: + mov #0, r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + +mask: + and #255, r0 + mov r0, r1 + mov #0, r0 + or #255, r0 + cmp/eq r0, r1 + bf wrong + +mask0: + and #0, r0 + assert r0, #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/bf.cgs b/sim/testsuite/sim/sh64/compact/bf.cgs new file mode 100644 index 00000000000..5c361f94b89 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bf.cgs @@ -0,0 +1,24 @@ +# sh testcase for bf $disp8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + clrt + bf ntaken + fail + .global ntaken +ntaken: + sett + bf bad + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bfs.cgs b/sim/testsuite/sim/sh64/compact/bfs.cgs new file mode 100644 index 00000000000..3cad5f6fc73 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bfs.cgs @@ -0,0 +1,28 @@ +# sh testcase for bf/s $disp8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + clrt + bf/s ntaken +slot1: + nop + fail + .global ntaken +ntaken: + sett + bf/s bad +slot2: + nop + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bra.cgs b/sim/testsuite/sim/sh64/compact/bra.cgs new file mode 100644 index 00000000000..77c6da9bdde --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bra.cgs @@ -0,0 +1,23 @@ +# sh testcase for bra $disp12 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global bra +bra: + bra okay +slot: + nop +bad: + fail + fail + fail + .global okay +okay: + pass + fail + diff --git a/sim/testsuite/sim/sh64/compact/braf.cgs b/sim/testsuite/sim/sh64/compact/braf.cgs new file mode 100644 index 00000000000..e761f6d0a6d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/braf.cgs @@ -0,0 +1,24 @@ +# sh testcase for braf $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global braf +braf: + mov #4, r0 + braf r0 +slot: + nop +bad: + fail + fail +okay: + pass +alsobad: + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/brk.cgs b/sim/testsuite/sim/sh64/compact/brk.cgs new file mode 100644 index 00000000000..99080724565 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/brk.cgs @@ -0,0 +1,18 @@ +# sh testcase for brk -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + .global brk +brk: + # If we hit the breakpoint, the sim will stop. + pass + + # FIXME: breakpoint instruction. + # The SH4 assembler doesn't know about "brk". + .word 0x003b +bad: + fail diff --git a/sim/testsuite/sim/sh64/compact/bsr.cgs b/sim/testsuite/sim/sh64/compact/bsr.cgs new file mode 100644 index 00000000000..75a1a2b275e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bsr.cgs @@ -0,0 +1,21 @@ +# sh testcase for bsr $disp12 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global bsr +bsr: + bsr okay +slot: + nop +bad: + fail + fail +okay: + pass +alsobad: + fail diff --git a/sim/testsuite/sim/sh64/compact/bsrf.cgs b/sim/testsuite/sim/sh64/compact/bsrf.cgs new file mode 100644 index 00000000000..9360eaa88b0 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bsrf.cgs @@ -0,0 +1,22 @@ +# sh testcase for bsrf $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +bsrf: + mov #4, r0 + bsrf r0 +slot: + nop +bad: + fail + fail +okay: + pass +alsobad: + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bt.cgs b/sim/testsuite/sim/sh64/compact/bt.cgs new file mode 100644 index 00000000000..65b9d61b885 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bt.cgs @@ -0,0 +1,24 @@ +# sh testcase for bt $disp8 +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + sett + bt ntaken + fail + .global ntaken +ntaken: + clrt + bt bad + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bts.cgs b/sim/testsuite/sim/sh64/compact/bts.cgs new file mode 100644 index 00000000000..3d62e4d822c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bts.cgs @@ -0,0 +1,28 @@ +# sh testcase for bt/s $disp8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + sett + bt/s ntaken +slot1: + nop + fail + .global ntaken +ntaken: + clrt + bt/s bad +slot2: + nop + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/clrmac.cgs b/sim/testsuite/sim/sh64/compact/clrmac.cgs new file mode 100644 index 00000000000..482dc804d62 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/clrmac.cgs @@ -0,0 +1,13 @@ +# sh testcase for clrmac -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global clrmac +clrmac: + clrmac + pass diff --git a/sim/testsuite/sim/sh64/compact/clrs.cgs b/sim/testsuite/sim/sh64/compact/clrs.cgs new file mode 100644 index 00000000000..bed5fd5178e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/clrs.cgs @@ -0,0 +1,14 @@ +# sh testcase for clrs -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global clrs +clrs: + clrs + # Somehow ensure that S is set. + pass diff --git a/sim/testsuite/sim/sh64/compact/clrt.cgs b/sim/testsuite/sim/sh64/compact/clrt.cgs new file mode 100644 index 00000000000..281c2f4243d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/clrt.cgs @@ -0,0 +1,16 @@ +# sh testcase for clrt -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global clrt +clrt: + clrt + bt wrong + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpeq.cgs b/sim/testsuite/sim/sh64/compact/cmpeq.cgs new file mode 100644 index 00000000000..3cc744cf7f7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpeq.cgs @@ -0,0 +1,52 @@ +# sh testcase for cmp/eq $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zeroes: + mov #0, r1 + mov #0, r2 + cmp/eq r1, r2 + bf wrong + +zero1: + mov #0, r1 + mov #1, r2 + cmp/eq r1, r2 + bt wrong + +zero2: + mov #0, r2 + mov #1, r1 + cmp/eq r2, r1 + bt wrong + +equal: + mov #192, r1 + mov #192, r2 + cmp/eq r1, r2 + bf wrong + +noteq: + mov #192, r1 + mov #193, r2 + cmp/eq r1, r2 + bt wrong + +large: + mov #1, r1 + rotr r1 + mov #1, r2 + rotr r2 + cmp/eq r1, r2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpeqi.cgs b/sim/testsuite/sim/sh64/compact/cmpeqi.cgs new file mode 100644 index 00000000000..79900a0cecc --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpeqi.cgs @@ -0,0 +1,39 @@ +# sh testcase for cmp/eq #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zeroes: + mov #0, r0 + cmp/eq #0, r0 + bf wrong + +zero1: + mov #0, r0 + cmp/eq #1, r0 + bt wrong + +zero2: + mov #1, r0 + cmp/eq #0, r0 + bt wrong + +equal: + mov #192, r0 + cmp/eq #192, r0 + bf wrong + +sign: + mov #255, r0 + cmp/eq #255, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpge.cgs b/sim/testsuite/sim/sh64/compact/cmpge.cgs new file mode 100644 index 00000000000..9d4327e35cc --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpge.cgs @@ -0,0 +1,69 @@ +# sh testcase for cmp/ge $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r1 + cmp/ge r0, r1 + bf wrong + +onezero: + mov #1, r0 + mov #0, r1 + cmp/ge r0, r1 + bt wrong + +zeroone: + mov #0, r0 + mov #1, r1 + cmp/ge r0, r1 + bf wrong + +equal: + mov #192, r0 + mov #192, r1 + cmp/ge r0, r1 + bf wrong + +eqlarge: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/ge r0, r1 + bf wrong + +large2: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #84, r1 + cmp/ge r0, r1 + bt wrong + +large3: + mov #1, r0 + rotr r0 + add #84, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/ge r0, r1 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/cmpgt.cgs b/sim/testsuite/sim/sh64/compact/cmpgt.cgs new file mode 100644 index 00000000000..460ca65ae68 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpgt.cgs @@ -0,0 +1,69 @@ +# sh testcase for cmp/gt $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r1 + cmp/gt r0, r1 + bt wrong + +onezero: + mov #1, r0 + mov #0, r1 + cmp/gt r0, r1 + bt wrong + +zeroone: + mov #0, r0 + mov #1, r1 + cmp/gt r0, r1 + bf wrong + +equal: + mov #192, r0 + mov #192, r1 + cmp/gt r0, r1 + bt wrong + +eqlarge: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/gt r0, r1 + bt wrong + +large2: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #84, r1 + cmp/gt r0, r1 + bt wrong + +large3: + mov #1, r0 + rotr r0 + add #84, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/gt r0, r1 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/cmphi.cgs b/sim/testsuite/sim/sh64/compact/cmphi.cgs new file mode 100644 index 00000000000..efbcaa328cd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmphi.cgs @@ -0,0 +1,68 @@ +# sh testcase for cmp/hi $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r0 + cmp/hi r0, r1 + bt wrong + +equal: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hi r0, r1 + bt wrong + +gt: + mov #10, r0 + mov #12, r1 + cmp/hi r0, r1 + bf wrong + +lt: + mov #12, r0 + mov #10, r1 + cmp/hi r0, r1 + bt wrong + +gtneg: + mov #1, r0 + rotr r0 + add #1, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hi r0, r1 + bf wrong + +ltneg: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #1, r1 + + cmp/hi r0, r1 + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmphs.cgs b/sim/testsuite/sim/sh64/compact/cmphs.cgs new file mode 100644 index 00000000000..957f80c0245 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmphs.cgs @@ -0,0 +1,59 @@ +# sh testcase for cmp/hs $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r0 + cmp/hs r0, r1 + +equal: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hs r0, r1 + +gt: + mov #10, r0 + mov #12, r1 + cmp/hs r0, r1 + +lt: + mov #12, r0 + mov #10, r1 + cmp/hs r0, r1 + +gtneg: + mov #1, r0 + rotr r0 + add #1, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hs r0, r1 + +ltneg: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #1, r1 + + cmp/hs r0, r1 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/cmppl.cgs b/sim/testsuite/sim/sh64/compact/cmppl.cgs new file mode 100644 index 00000000000..1c11377f34b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmppl.cgs @@ -0,0 +1,37 @@ +# sh testcase for cmp/pl $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + cmp/pl r0 + bt wrong + +plus: + mov #10, r0 + cmp/pl r0 + bf wrong + +minus: + mov #10, r0 + neg r0, r0 + cmp/pl r0 + bt wrong + +large: + mov #10, r0 + shll8 r0 + add #123, r0 + cmp/pl r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmppz.cgs b/sim/testsuite/sim/sh64/compact/cmppz.cgs new file mode 100644 index 00000000000..2e0bf48e827 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmppz.cgs @@ -0,0 +1,37 @@ +# sh testcase for cmp/pz $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + cmp/pz r0 + bf wrong + +plus: + mov #10, r0 + cmp/pz r0 + bf wrong + +minus: + mov #10, r0 + neg r0, r0 + cmp/pz r0 + bt wrong + +large: + mov #10, r0 + shll8 r0 + add #123, r0 + cmp/pz r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpstr.cgs b/sim/testsuite/sim/sh64/compact/cmpstr.cgs new file mode 100644 index 00000000000..70d90d33c20 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpstr.cgs @@ -0,0 +1,148 @@ +# sh testcase for cmp/str $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + +.macro rot8 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 +.endm + + start + +# Use multiple "wrong" labels because this program is quite long. It's +# likely that some instructions will be too far away from the branch +# target to use PC-relative branches. + +match0: + # No bytes matching. + mov #1, r0 + neg r0, r0 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + mov r0, r1 + mov #1, r0 + neg r0, r0 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + cmp/str r0, r1 + bt wrong0 + + bra match1 + nop +wrong0: + fail + +match1: + # One byte matching. + mov #1, r0 + neg r0, r0 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + mov r0, r1 + mov #1, r0 + neg r0, r0 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + cmp/str r0, r1 + bf wrong1 + + bra match2 + nop +wrong1: + fail + +match2: + # Two bytes matching. + mov #1, r0 + neg r0, r0 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + mov r0, r1 + mov #1, r0 + neg r0, r0 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + cmp/str r0, r1 + bf wrong2 + + bra match3 + nop +wrong2: + fail + +byte0: +match3: + # One byte matching. + # This is also the test for byte 0. + mov #85, r0 + mov #85, r1 + cmp/str r0, r1 + bf wrong3 + +byte1: + # Match in byte position 1. + mov #85, r0 + shll8 r0 + mov #85, r1 + shll8 r1 + cmp/str r0, r1 + bf wrong3 + +byte2: + # Match in byte position 2. + mov #85, r0 + shll16 r0 + mov #85, r1 + shll16 r1 + cmp/str r0, r1 + bf wrong3 + +byte3: + # Match in byte position 3. + mov #85, r0 + shll16 r0 + shll8 r0 + mov #85, r1 + shll16 r1 + shll8 r1 + cmp/str r0, r1 + bf wrong3 + +okay: + pass +wrong3: + fail + diff --git a/sim/testsuite/sim/sh64/compact/div0s.cgs b/sim/testsuite/sim/sh64/compact/div0s.cgs new file mode 100644 index 00000000000..8cd6422bea8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/div0s.cgs @@ -0,0 +1,52 @@ +# sh testcase for div0s $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +init: + mov #0, r0 + mov #3, r1 + mov #4, r2 + neg r1, r3 + neg r2, r4 + +perm1: + div0s r0, r0 + bt wrong + div0s r0, r1 + bt wrong + div0s r1, r0 + bt wrong + +perm2: + div0s r0, r4 + bf wrong + div0s r4, r0 + bf wrong + +perm3: + div0s r1, r2 + bt wrong + div0s r2, r1 + bt wrong + +perm4: + div0s r3, r4 + bt wrong + div0s r4, r3 + bt wrong + +perm5: + div0s r1, r1 + bt wrong + div0s r3, r3 + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/div0u.cgs b/sim/testsuite/sim/sh64/compact/div0u.cgs new file mode 100644 index 00000000000..02f8534d4c4 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/div0u.cgs @@ -0,0 +1,21 @@ +# sh testcase for div0u -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global div0u +div0u: + div0u + # Can't easily test Q and M (other than visually inspecting + # the simulator's trace output). + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/div1.cgs b/sim/testsuite/sim/sh64/compact/div1.cgs new file mode 100644 index 00000000000..63a0e81cb12 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/div1.cgs @@ -0,0 +1,52 @@ +# sh testcase for div1 $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #10, r0 + mov #2, r1 + div0s r0,r1 + + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + + pass diff --git a/sim/testsuite/sim/sh64/compact/dmulsl.cgs b/sim/testsuite/sim/sh64/compact/dmulsl.cgs new file mode 100644 index 00000000000..081ce169955 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/dmulsl.cgs @@ -0,0 +1,115 @@ +# sh testcase for dmuls.l $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #0, r0 + mov #0, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #0 + +test2: + mov #0, r0 + mov #5, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #0 + +test3: + mov #5, r0 + mov #0, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #0 + +test4: + mov #1, r0 + mov #5, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #5 + +test5: + mov #5, r0 + mov #1, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #5 + + bra test6 + nop + +wrong: + fail + +test6: + mov #2, r0 + mov #2, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #4 + +test7: + mov #1, r0 + neg r0, r0 + mov #2, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + + mov #0, r8 + not r8, r9 + not r8, r10 + shll r10 + cmp/eq r3, r9 + bf wrong + cmp/eq r4, r10 + bf wrong + +test8: + mov #1, r0 + neg r0, r0 + mov #1, r1 + neg r1, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #1 + +test9: + mov #1, r0 + neg r0, r0 + shlr r0 + mov #1, r1 + neg r1, r1 + shlr r1 + dmuls.l r0, r1 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/dmulul.cgs b/sim/testsuite/sim/sh64/compact/dmulul.cgs new file mode 100644 index 00000000000..b34b870269d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/dmulul.cgs @@ -0,0 +1,53 @@ +# sh testcase for dmulu.l $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #0, r0 + mov #0, r1 + dmulu.l r0, r1 + + mov #0, r0 + mov #5, r1 + dmulu.l r0, r1 + + mov #5, r0 + mov #0, r1 + dmulu.l r0, r1 + + mov #1, r0 + mov #5, r1 + dmulu.l r0, r1 + + mov #5, r0 + mov #1, r1 + dmulu.l r0, r1 + + mov #2, r0 + mov #2, r1 + dmulu.l r0, r1 + + mov #1, r0 + neg r0, r0 + mov #2, r1 + dmulu.l r0, r1 + + mov #1, r0 + neg r0, r0 + mov #1, r1 + neg r1, r1 + dmulu.l r0, r1 + + mov #1, r0 + neg r0, r0 + shlr r0 + mov #1, r1 + neg r1, r1 + shlr r1 + dmulu.l r0, r1 + + pass diff --git a/sim/testsuite/sim/sh64/compact/dt.cgs b/sim/testsuite/sim/sh64/compact/dt.cgs new file mode 100644 index 00000000000..38e91638bd9 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/dt.cgs @@ -0,0 +1,42 @@ +# sh testcase for dt $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global dt +dt: + mov #3, r0 + dt r0 + bt wrong + assert r0, #2 + + mov #1, r0 + dt r0 + bf wrong + assert r0, #0 + + mov #0, r0 + dt r0 + bt wrong + mov #0, r7 + not r7, r7 + cmp/eq r7, r0 + bf wrong + + mov #1, r0 + neg r0, r0 + dt r0 + mov #1, r7 + not r7, r7 + cmp/eq r7, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/extsb.cgs b/sim/testsuite/sim/sh64/compact/extsb.cgs new file mode 100644 index 00000000000..90878020a28 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extsb.cgs @@ -0,0 +1,29 @@ +# sh testcase for exts.b $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extsb +extsb: + mov #42, r1 + exts.b r1, r2 + assert r2, #42 +signed: + mov #0, r0 + or #255, r0 + exts.b r0, r1 + mov #0, r7 + not r7, r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/extsw.cgs b/sim/testsuite/sim/sh64/compact/extsw.cgs new file mode 100644 index 00000000000..d6257747df7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extsw.cgs @@ -0,0 +1,32 @@ +# sh testcase for exts.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extsw +extsw: + mov #42, r1 + exts.w r1, r2 + assert r2, #42 + +another: + mov #0, r0 + or #255, r0 + shll8 r0 + exts.w r0, r1 + + mov #-1, r7 + shll8 r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/extub.cgs b/sim/testsuite/sim/sh64/compact/extub.cgs new file mode 100644 index 00000000000..51c14ac4359 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extub.cgs @@ -0,0 +1,31 @@ +# sh testcase for extu.b $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extub +extub: + mov #42, r1 + extu.b r1, r2 + assert r2, #42 + +another: + mov #0, r0 + or #255, r0 + extu.b r0, r1 + + mov #0, r0 + or #255, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/extuw.cgs b/sim/testsuite/sim/sh64/compact/extuw.cgs new file mode 100644 index 00000000000..057afe7d949 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extuw.cgs @@ -0,0 +1,31 @@ +# sh testcase for extu.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extuw +extuw: + mov #42, r1 + extu.w r1, r2 + assert r2, #42 + +another: + mov #0, r0 + or #255, r0 + shll8 r0 + extu.w r0, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fabs.cgs b/sim/testsuite/sim/sh64/compact/fabs.cgs new file mode 100644 index 00000000000..6955fa2aa16 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fabs.cgs @@ -0,0 +1,88 @@ +# sh testcase for fabs -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _clrpr + # fabs(0.0) = 0.0. + fldi0 fr0 + fabs fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # fabs(1.0) = 1.0. + fldi1 fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # double precision tests. + # fabs(0.0) = 0.0. + fldi0 fr0 + _s2d fr0, dr0 + _setpr + fabs dr0 + _clrpr + # check. + fldi0 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong + _clrpr + +one: + # fabs(1.0) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + _setpr + fabs dr0 + _clrpr + # check. + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + +minusone: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + _s2d fr0, dr0 + _setpr + fabs dr0 + _clrpr + # check. + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + +okay: + pass +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fadd.cgs b/sim/testsuite/sim/sh64/compact/fadd.cgs new file mode 100644 index 00000000000..b00035308f8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fadd.cgs @@ -0,0 +1,31 @@ +# sh testcase for fadd +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _clrpr + + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + + fldi0 fr0 + fldi1 fr1 + fadd fr0, fr1 + + fldi1 fr0 + fldi0 fr1 + fadd fr0, fr1 + + _setpr +double: + fldi1 fr0 + fldi1 fr1 + _s2d fr0, dr4 + _s2d fr1, dr6 + fadd dr4, dr6 + + pass diff --git a/sim/testsuite/sim/sh64/compact/fcmpeq.cgs b/sim/testsuite/sim/sh64/compact/fcmpeq.cgs new file mode 100644 index 00000000000..151d5e5647a --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcmpeq.cgs @@ -0,0 +1,88 @@ +# sh testcase for fcmpeq -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # 1.0 == 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # 0.0 != 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt wrong + + # 1.0 != 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt wrong + + # 2.0 != 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt wrong + + bra double + # delay slot + nop + +wrong: + fail + +double: + # 1.0 == 1.0 + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong + _clrpr + + # 0.0 != 1.0 + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bt wrong + _clrpr + + # 1.0 != 0.0 + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bt wrong2 + _clrpr + + # 2.0 != 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bt wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fcmpgt.cgs b/sim/testsuite/sim/sh64/compact/fcmpgt.cgs new file mode 100644 index 00000000000..931ae3e2e6c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcmpgt.cgs @@ -0,0 +1,95 @@ +# sh testcase for fcmpgt -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bt wrong + + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf wrong + + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/gt fr0, fr1 + bt wrong + + # 2.0 > 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bt wrong + + bra double + nop + +wrong: + fail + +double: + # double precision tests. + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bt wrong2 + _clrpr + + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bf wrong2 + _clrpr + + bra next + nop + +wrong2: + fail + +next: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bt wrong2 + _clrpr + + # 2.0 > 1.0. + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bt wrong2 + _clrpr + +okay: + pass + +wrong3: + fail diff --git a/sim/testsuite/sim/sh64/compact/fcnvds.cgs b/sim/testsuite/sim/sh64/compact/fcnvds.cgs new file mode 100644 index 00000000000..abf9e704ffb --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcnvds.cgs @@ -0,0 +1,13 @@ +# sh testcase for fcnvds -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _setpr + fcnvds dr0, fpul + _clrpr +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/fcnvsd.cgs b/sim/testsuite/sim/sh64/compact/fcnvsd.cgs new file mode 100644 index 00000000000..699bde55c6e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcnvsd.cgs @@ -0,0 +1,27 @@ +# sh testcase for fcnvsd -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fldi1 fr0 + flds fr0, fpul + _setpr + fcnvsd fpul, dr2 + _clrpr + + # Convert back. + _setpr + fcnvds dr2, fpul + _clrpr + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fdiv.cgs b/sim/testsuite/sim/sh64/compact/fdiv.cgs new file mode 100644 index 00000000000..06d1e93a014 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fdiv.cgs @@ -0,0 +1,83 @@ +# sh testcase for fdiv -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _clrpr + + # 1.0 / 0.0 should be INF + # (and not crash the sim). + fldi0 fr0 + fldi1 fr1 + fdiv fr0, fr1 + + # 0.0 / 1.0 == 0.0. + fldi0 fr0 + fldi1 fr1 + fdiv fr1, fr0 + fldi0 fr2 + fcmp/eq fr0, fr2 + bf wrong + + # 2.0 / 1.0 == 2.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr1, fr2 + # Load 2.0 into fr3. + fldi1 fr3 + fadd fr3, fr3 + fcmp/eq fr2, fr3 + bf wrong + + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr2, fr1 + # fr1 should contain 0.5. + fadd fr1, fr1 + # Load 1.0 into fr3. + fldi1 fr3 + # Compare fr1 with fr3. + fcmp/eq fr1, fr3 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # double test + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + _s2d fr1, dr6 + fldi1 fr2 + fadd fr2, fr2 + _s2d fr2, dr8 + _setpr + fdiv dr8, dr6 + # dr0 should contain 0.5. + # double it, expect 1.0. + fadd dr6, dr6 + _clrpr +foo: + # Load 1.0 into dr4. + fldi1 fr1 + _s2d fr1, dr10 + # Compare dr0 with dr10. + _setpr + fcmp/eq dr6, dr10 + bf wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fipr.cgs b/sim/testsuite/sim/sh64/compact/fipr.cgs new file mode 100644 index 00000000000..092f0f6c066 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fipr.cgs @@ -0,0 +1,44 @@ +# sh testcase for fipr $fvm, $fvn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +initv1: + fldi1 fr0 + # Load 2 into fr2. + fldi1 fr1 + fadd fr1, fr1 + # Load 4 into fr2. + fldi1 fr2 + fadd fr2, fr2 + fadd fr2, fr2 + fldi0 fr3 + +initv2: + fldi1 fr8 + fldi0 fr9 + fldi1 fr10 + fldi0 fr11 + + fipr fv0, fv8 + + # Result will be in fr11. + fldi1 fr0 + fldi1 fr1 + # Two. + fadd fr1, fr0 + # Four. + fadd fr0, fr0 + # Five. + fadd fr1, fr0 + fcmp/eq fr0, fr11 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fldi0.cgs b/sim/testsuite/sim/sh64/compact/fldi0.cgs new file mode 100644 index 00000000000..b0d35e4fb09 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fldi0.cgs @@ -0,0 +1,17 @@ +# sh testcase for fldi0 $frn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fldi0 fr0 + fldi0 fr2 + fldi0 fr4 + fldi0 fr6 + fldi0 fr8 + fldi0 fr10 + fldi0 fr12 + fldi0 fr14 + pass diff --git a/sim/testsuite/sim/sh64/compact/fldi1.cgs b/sim/testsuite/sim/sh64/compact/fldi1.cgs new file mode 100644 index 00000000000..8bd5c521be2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fldi1.cgs @@ -0,0 +1,17 @@ +# sh testcase for fldi1 $frn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fldi1 fr1 + fldi1 fr3 + fldi1 fr5 + fldi1 fr7 + fldi1 fr9 + fldi1 fr11 + fldi1 fr13 + fldi1 fr15 + pass diff --git a/sim/testsuite/sim/sh64/compact/flds.cgs b/sim/testsuite/sim/sh64/compact/flds.cgs new file mode 100644 index 00000000000..797e7cba9ab --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/flds.cgs @@ -0,0 +1,26 @@ +# sh testcase for flds -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + fldi0 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bf wrong + + fldi1 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/float.cgs b/sim/testsuite/sim/sh64/compact/float.cgs new file mode 100644 index 00000000000..8532d7fd651 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/float.cgs @@ -0,0 +1,80 @@ +# sh testcase for float -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +pos: + mov #3, r0 + lds r0, fpul + float fpul, fr7 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fcmp/eq fr1, fr7 + bf wrong + +neg: + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, fr7 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + fcmp/eq fr1, fr7 + bf wrong + + bra double + nop + +wrong: + fail + +double: + mov #3, r0 + lds r0, fpul + _setpr + float fpul, dr8 + _clrpr + # check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + _s2d fr1, dr2 + fcmp/eq dr2, dr8 + bf wrong + +dneg: + mov #3, r0 + neg r0, r0 + lds r0, fpul + _setpr + float fpul, dr8 + _clrpr + # check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + _s2d fr1, dr2 + fcmp/eq dr2, dr8 + bf wrong + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fmac.cgs b/sim/testsuite/sim/sh64/compact/fmac.cgs new file mode 100644 index 00000000000..dbf36ab78c8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fmac.cgs @@ -0,0 +1,78 @@ +# sh testcase for fmac -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # 0.0 * x + y = y. + + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fcmp/eq fr0, fr2 + bf wrong + + # x * y + 0.0 = x * y. + + fldi1 fr0 + fldi1 fr1 + fldi0 fr2 + # double it. + fadd fr1, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bf wrong + + # x * 0.0 + y = y. + + fldi1 fr0 + fldi0 fr1 + fldi1 fr2 + fadd fr2, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + # double fr0. + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bf wrong + + # x * 0.0 + 0.0 = 0.0 + + fldi1 fr0 + fadd fr0, fr0 + fldi0 fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bf wrong + + # 0.0 * x + 0.0 = 0.0. + + fldi0 fr0 + fldi1 fr1 + # double it. + fadd fr1, fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fmov.cgs b/sim/testsuite/sim/sh64/compact/fmov.cgs new file mode 100644 index 00000000000..f4e1fde3c11 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fmov.cgs @@ -0,0 +1,273 @@ +# sh testcase for all fmov instructions +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr2 + .endm + + # Set the SZ (SiZe) bit in the fpscr. + .macro _setsz + sts fpscr, r7 + mov #16, r8 + shll16 r8 + or r8, r7 + lds r7, fpscr + .endm + + # Clear the SZ bit. + .macro _clrsz + sts fpscr, r7 + mov #16, r8 + shll16 r8 + not r8, r8 + and r8, r7 + lds r7, fpscr + .endm + start + +fmov1: # Test fr -> fr. + init + _clrpr + _clrsz + fmov fr0, fr10 + # Ensure fr0 and fr10 are now equal. + fcmp/eq fr0, fr10 + bt fmov2 + fail + +fmov2: # Test dr -> dr. + init + _setpr + _setsz + fmov dr0, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt fmov3 + fail + +fmov3: # Test dr -> xd and xd -> dr. + init + _setsz + fmov dr0, xd0 + # Ensure dr0 and xd0 are now equal. + fmov xd0, dr2 + fcmp/eq dr0, dr2 + bt fmov4 + fail + +fmov4: # Test xd -> xd. + init + _setsz + _setpr + fmov dr0, xd0 + fmov xd0, xd2 + fmov xd2, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt fmov5 + fail + +fmov5: # Test fr -> @rn and @rn -> fr. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + fmov fr0, @r0 + fmov @r0, fr1 + fcmp/eq fr0, fr1 + bt fmov6 + fail + +fmov6: # Test dr -> @rn and @rn -> dr. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + fmov dr0, @r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt fmov7 + fail + +fmov7: # Test xd -> @rn and @rn -> xd. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt fmov8 + fail + +fmov8: # Test fr -> @-rn. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + # Preserve. + mov r0, r1 + fmov fr0, @-r0 + fmov @r0, fr2 + fcmp/eq fr0, fr2 + bt f8b + fail +f8b: # check pre-dec. + add #4, r0 + cmp/eq r0, r1 + bt fmov9 + fail + +fmov9: # Test dr -> @-rn. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, @-r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt f9b + fail +f9b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov10 + fail + +fmov10: # Test xd -> @-rn. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @-r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f10b + fail +f10b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov11 + fail + +fmov11: # Test @rn+ -> fr. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov fr0, @r0 + fmov @r0+, fr2 + fcmp/eq fr0, fr2 + bt f11b + fail +f11b: # check post-inc. + add #4, r1 + cmp/eq r0, r1 + bt fmov12 + fail + +fmov12: # Test @rn+ -> dr. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # preserve r0. + mov r0, r1 + fmov dr0, @r0 + fmov @r0+, dr2 + fcmp/eq dr0, dr2 + bt f12b + fail +f12b: # check post-inc. + add #8, r1 + cmp/eq r0, r1 + bt fmov13 + fail + +fmov13: # Test @rn -> xd. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0+, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f13b + fail +f13b: + add #8, r1 + cmp/eq r0, r1 + bt fmov14 + fail + +fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov fr0, @(r0, r1) + fmov @(r0, r1), fr1 + fcmp/eq fr0, fr1 + bt fmov15 + fail + +fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, @(r0, r1) + fmov @(r0, r1), dr2 + fcmp/eq dr0, dr2 + bt fmov16 + fail + +fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, xd0 + fmov xd0, @(r0, r1) + fmov @(r0, r1), xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt okay + fail + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/fmul.cgs b/sim/testsuite/sim/sh64/compact/fmul.cgs new file mode 100644 index 00000000000..a1325d6395b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fmul.cgs @@ -0,0 +1,121 @@ +# sh testcase for fmul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fldi0 fr7 + fldi1 fr8 + .endm + + start + + # 0.0 * 0.0 = 0.0. + init + fmul fr0, fr0 + fcmp/eq fr7, fr0 + bf wrong + + # 0.0 * 1.0 = 0.0. + init + fmul fr1, fr0 + fcmp/eq fr7, fr0 + bf wrong + + # 1.0 * 0.0 = 0.0. + init + fmul fr0, fr1 + fcmp/eq fr7, fr1 + bf wrong + + # 1.0 * 1.0 = 1.0. + init + fmul fr1, fr1 + fcmp/eq fr8, fr1 + bf wrong + + # 2.0 * 1.0 = 2.0. + init + fmul fr2, fr1 + fcmp/eq fr2, fr1 + bf wrong + + bra double + nop + +wrong: + fail + + .macro dinit + fldi0 fr0 + fldi1 fr2 + fldi1 fr4 + fadd fr4, fr4 + fldi0 fr8 + fldi1 fr10 + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + _s2d fr8, dr8 + _s2d fr10, dr10 + .endm + +double: + # 0.0 * 0.0 = 0.0. + dinit + _setpr + fmul dr0, dr0 + fcmp/eq dr8, dr0 + bf wrong + _clrpr + + # 0.0 * 1.0 = 0.0. + dinit + _setpr + fmul dr2, dr0 + fcmp/eq dr8, dr0 + bf wrong2 + _clrpr + + # 1.0 * 0.0 = 0.0. + dinit + _setpr + fmul dr0, dr2 + fcmp/eq dr8, dr2 + bf wrong2 + _clrpr + + bra next + nop + +wrong2: + fail + +next: + # 1.0 * 1.0 = 1.0. + dinit + _setpr + fmul dr2, dr2 + fcmp/eq dr10, dr2 + bf wrong3 + _clrpr + + # 2.0 * 1.0 = 2.0. + dinit + _setpr + fmul dr4, dr2 + fcmp/eq dr4, dr2 + bf wrong3 + _clrpr + +okay: + pass + +wrong3: + fail diff --git a/sim/testsuite/sim/sh64/compact/fneg.cgs b/sim/testsuite/sim/sh64/compact/fneg.cgs new file mode 100644 index 00000000000..71fc901fb6d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fneg.cgs @@ -0,0 +1,83 @@ +# sh testcase for fneg -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr1 + fneg fr0 + fcmp/eq fr0, fr1 + bf wrong + + # neg(1.0) = fsub(0,1) + fldi1 fr0 + fneg fr0 + fldi0 fr1 + fldi1 fr2 + fsub fr2, fr1 + fcmp/eq fr0, fr1 + bf wrong + + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + fldi1 fr1 + fneg fr0 + fneg fr0 + fcmp/eq fr0, fr1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fneg dr0 + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + + # neg(1.0) = fsub(0,1) + fldi1 fr0 + _s2d fr0, dr0 + _setpr + fneg dr0 + _clrpr + fldi0 fr2 + fldi1 fr3 + fsub fr3, fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq fr0, fr2 + bf wrong2 + _clrpr + + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fneg dr0 + fneg dr2 + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/frchg.cgs b/sim/testsuite/sim/sh64/compact/frchg.cgs new file mode 100644 index 00000000000..6f2e743fc37 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/frchg.cgs @@ -0,0 +1,13 @@ +# sh testcase for frchg +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + frchg + frchg + frchg + frchg + pass diff --git a/sim/testsuite/sim/sh64/compact/fschg.cgs b/sim/testsuite/sim/sh64/compact/fschg.cgs new file mode 100644 index 00000000000..54a1491962b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fschg.cgs @@ -0,0 +1,13 @@ +# sh testcase for fschg +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fschg + fschg + fschg + fschg + pass diff --git a/sim/testsuite/sim/sh64/compact/fsqrt.cgs b/sim/testsuite/sim/sh64/compact/fsqrt.cgs new file mode 100644 index 00000000000..933e112c903 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fsqrt.cgs @@ -0,0 +1,93 @@ +# sh testcase for fsqrt -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # sqrt(0.0) = 0.0. + fldi0 fr0 + fsqrt fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # sqrt(1.0) = 1.0. + fldi1 fr0 + fsqrt fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # sqrt(4.0) = 2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsqrt fr0 + fldi1 fr1 + # Double it. + fadd fr1, fr1 + fcmp/eq fr0, fr1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # sqrt(0.0) = 0.0. + fldi0 fr0 + _s2d fr0, dr0 + _setpr + fsqrt dr0 + _clrpr + fldi0 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + + # sqrt(1.0) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + _setpr + fsqrt dr0 + _clrpr + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq fr0, fr2 + bf wrong2 + _clrpr + + # sqrt(4.0) = 2.0. + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + _s2d fr0, dr0 + _setpr + fsqrt dr0 + _clrpr + fldi1 fr2 + # Double it. + fadd fr2, fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq fr0, fr2 + bf wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fsts.cgs b/sim/testsuite/sim/sh64/compact/fsts.cgs new file mode 100644 index 00000000000..518533db094 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fsts.cgs @@ -0,0 +1,11 @@ +# sh testcase for fsts fpul, $frn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fsts fpul, fr0 + fsts fpul, fr1 + pass diff --git a/sim/testsuite/sim/sh64/compact/fsub.cgs b/sim/testsuite/sim/sh64/compact/fsub.cgs new file mode 100644 index 00000000000..346d01ffcaa --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fsub.cgs @@ -0,0 +1,120 @@ +# sh testcase for fmul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bf wrong + + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi1 fr2 + fcmp/eq fr1, fr2 + bf wrong + + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bf wrong + + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi1 fr2 + fneg fr2 + fcmp/eq fr1, fr2 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi0 fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong + _clrpr + +onezero: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi1 fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong2 + _clrpr + +oneone: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi0 fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong2 + _clrpr + + bra zeroone + nop + +wrong2: + fail + +zeroone: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi1 fr4 + fneg fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong2 + _clrpr + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/ftrc.cgs b/sim/testsuite/sim/sh64/compact/ftrc.cgs new file mode 100644 index 00000000000..6a89744b33e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ftrc.cgs @@ -0,0 +1,132 @@ +# sh testcase for ftrc -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # ftrc(0.0) = 0. + fldi0 fr0 + ftrc fr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong + + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong + + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fneg fr1 + # -1 + -0.5 = -1.5. + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # ftrc(0.0) = 0. + fldi0 fr0 + _s2d fr0, dr0 + _setpr + ftrc dr0, fpul + _clrpr + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 +foo: + bf wrong2 + + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr2 + fldi1 fr4 + # double it. + fadd fr4, fr4 + # form 0.5. + fdiv fr4, fr2 + fadd fr2, fr0 + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + _setpr + ftrc dr0, fpul + _clrpr + + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong2 + + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr2 + fldi1 fr4 + # double it. + fadd fr4, fr4 + # form the fraction. + fdiv fr4, fr2 + fneg fr2 + # -1 + -0.5 = -1.5. + fadd fr2, fr0 + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + _setpr + ftrc dr0, fpul + _clrpr + + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong2 + +okay: + pass +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/ftrv.cgs b/sim/testsuite/sim/sh64/compact/ftrv.cgs new file mode 100644 index 00000000000..9bdf806ba13 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ftrv.cgs @@ -0,0 +1,74 @@ +# sh testcase for ftrv xmtrx, $fvn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + # set the fr bit in the fpscr + .macro _setfr + sts fpscr, r7 + mov #32, r8 + shll16 r8 + or r8, r7 + lds r7, fpscr + .endm + + # clear the fr bit + .macro _clrfr + sts fpscr, r7 + mov #32, r8 + shll16 r8 + not r8, r8 + and r8, r7 + lds r7, fpscr + .endm + + .macro incr old new + fldi1 \new + fadd \old, \new + .endm + + start + _setfr +popmtrx: + # 1.0. + fldi1 fr0 + # 2.0. + fldi1 fr1 + fadd fr1, fr1 + + incr fr1, fr2 + incr fr2, fr3 + incr fr3, fr4 + incr fr4, fr5 + incr fr5, fr6 + incr fr6, fr7 + incr fr7, fr8 + incr fr8, fr9 + incr fr9, fr10 + incr fr10, fr11 + incr fr11, fr12 + incr fr12, fr13 + incr fr13, fr14 + incr fr14, fr15 + +popvect: + # Swtich fp banks. + _clrfr + fldi1 fr4 + fldi1 fr5 + fadd fr5, fr5 + fldi1 fr6 + fadd fr5, fr6 + fldi1 fr7 + fadd fr6, fr7 + +ftrv: + # fr[4,7] should contain the results: + # { 30, 70, 110, 150 }. + ftrv xmtrx, fv4 + +okay: + pass + diff --git a/sim/testsuite/sim/sh64/compact/jmp.cgs b/sim/testsuite/sim/sh64/compact/jmp.cgs new file mode 100644 index 00000000000..e9e99401545 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/jmp.cgs @@ -0,0 +1,29 @@ +# sh testcase for jmp @$rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global jmp +jmp: + # Load 0x1010 into r0. + mov #1, r0 + shll8 r0 + shll2 r0 + shll2 r0 + add #16, r0 + jmp @r0 +slot: + nop +bad: + fail +okay: + pass +alsobad: + fail + fail + fail + diff --git a/sim/testsuite/sim/sh64/compact/jsr.cgs b/sim/testsuite/sim/sh64/compact/jsr.cgs new file mode 100644 index 00000000000..5ad7aefc931 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/jsr.cgs @@ -0,0 +1,29 @@ +# sh testcase for jsr @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global jsr +jsr: + # Load 0x1010 into r0. + mov #1, r0 + shll8 r0 + shll2 r0 + shll2 r0 + add #16, r0 + jsr @r0 +slot: + nop +bad: + fail +okay: + pass +alsobad: + fail + fail + fail + diff --git a/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs new file mode 100644 index 00000000000..b19a3c194fe --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs @@ -0,0 +1,22 @@ +# sh testcase for ldc $rn, gbr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldc +ldc: + mov #40, r0 + shll8 r0 + ldc r0, gbr + stc gbr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs new file mode 100644 index 00000000000..613e58e722c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldc.l @${rn}+, gbr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldcl +ldcl: + mov #40, r0 + shll8 r0 + # Preserve address. + mov r0, r1 + ldc.l @r0+, gbr + + # Add 4 to saved address (r1). + # Then compare with r0. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs b/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs new file mode 100644 index 00000000000..2dce253375d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs @@ -0,0 +1,22 @@ +# sh testcase for lds $rn, fpscr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_fpscr +lds_fpscr: + mov #0, r0 + lds r0, fpscr +readback: + sts fpscr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-fpul.cgs b/sim/testsuite/sim/sh64/compact/lds-fpul.cgs new file mode 100644 index 00000000000..1a80a7032ea --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-fpul.cgs @@ -0,0 +1,17 @@ +# sh testcase for lds $rn, fpul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_fpul +lds_fpul: + mov #63, r0 + shll8 r0 + add #128, r0 + shll16 r0 + lds r0, fpul + pass diff --git a/sim/testsuite/sim/sh64/compact/lds-mach.cgs b/sim/testsuite/sim/sh64/compact/lds-mach.cgs new file mode 100644 index 00000000000..1ffd6566c9a --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-mach.cgs @@ -0,0 +1,23 @@ +# sh testcase for lds $rn, mach +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_mach +lds_mach: + mov #41, r0 + shll8 r0 + lds r0, mach +readback: + sts mach, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-macl.cgs b/sim/testsuite/sim/sh64/compact/lds-macl.cgs new file mode 100644 index 00000000000..f09315abbb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-macl.cgs @@ -0,0 +1,23 @@ +# sh testcase for lds $rn, macl +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_macl +lds_macl: + mov #42, r0 + shll8 r0 + lds r0, macl +readback: + sts macl, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-pr.cgs b/sim/testsuite/sim/sh64/compact/lds-pr.cgs new file mode 100644 index 00000000000..97e3a650767 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-pr.cgs @@ -0,0 +1,23 @@ +# sh testcase for lds $rn, pr +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_pr +lds_pr: + mov #40, r0 + shll8 r0 + lds r0, pr +readback: + sts pr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs new file mode 100644 index 00000000000..642f15dc527 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs @@ -0,0 +1,43 @@ +# sh testcase for lds.l @${rn}+, fpscr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #40, r0 + shll8 r0 + # save address for later examination. + mov r0, r1 + + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + # Store it in memory. + mov.l r2, @r0 + + lds.l @r0+, fpscr + +check: + # Read it back. + sts fpscr, r3 + cmp/eq r2, r3 + bf wrong + +inc: + # Test for proper post-increment. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs new file mode 100644 index 00000000000..428a5b71816 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs @@ -0,0 +1,27 @@ +# sh testcase for lds.l @${rn}+, fpul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_fpul +ldsl_fpul: + mov #40, r0 + shll8 r0 + # remember the address. + mov r0, r1 + lds.l @r0+, fpul + + # ensure post increment occurred. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs b/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs new file mode 100644 index 00000000000..f5ffdec8dce --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs @@ -0,0 +1,26 @@ +# sh testcase for lds.l @${rn}+, mach -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_mach +ldsl_mach: + mov #40, r0 + shll8 r0 + # save address for later examination. + mov r0, r1 + + lds.l @r0+, mach + + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs b/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs new file mode 100644 index 00000000000..4e21bf1942f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs @@ -0,0 +1,26 @@ +# sh testcase for lds.l @${rn}+, macl -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_macl +ldsl_macl: + mov #40, r0 + shll8 r0 + # save address for later examination. + mov r0, r1 + + lds.l @r0+, macl + + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs new file mode 100644 index 00000000000..eb8ee531bd3 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs @@ -0,0 +1,28 @@ +# sh testcase for lds.l @${rn}+, pr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_pr +ldsl_pr: + mov #40, r0 + shll8 r0 + # Preserve address. + mov r0, r1 + lds.l @r0+, pr + + # Add 4 to saved address (r1). + # Then compare with r0. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/macl.cgs b/sim/testsuite/sim/sh64/compact/macl.cgs new file mode 100644 index 00000000000..ef2dfa6e929 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/macl.cgs @@ -0,0 +1,76 @@ +# sh testcase for mac.l @${rm}+, @${rn}+ +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + # force S-bit clear + clrs + + # Store some magic numbers in memory. + mov #40, r1 + shll8 r1 + mov #85, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r10 +store2: + mov #40, r1 + shll8 r1 + add #12, r1 + mov #17, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r11 + +init: + # Set up addresses. + mov #40, r1 + shll8 r1 + mov #40, r2 + shll8 r2 + add #12, r2 + + # Prime {MACL, MACH} to #1. + mov #1, r3 + dmulu.l r3, r3 + +test: + mac.l @r1+, @r2+ + +check: + # Check result. + sts mach, r5 + assert r5, #0 + + mov #5, r0 + shll8 r0 + or #166, r0 + sts macl, r6 + cmp/eq r6, r0 + bf wrong + + # Ensure post-increment occurred. + add #4, r10 + cmp/eq r10, r1 + bf wrong + + add #4, r11 + cmp/eq r11, r2 + bf wrong + +doubleinc: + mov #40, r0 + shll8 r0 + mov r0, r1 + mac.l @r0+, @r0+ + add #16, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/macw.cgs b/sim/testsuite/sim/sh64/compact/macw.cgs new file mode 100644 index 00000000000..f5935f7054d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/macw.cgs @@ -0,0 +1,70 @@ +# sh testcase for mac.w @${rm}+, @${rn}+ +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # Store some magic numbers in memory. + mov #40, r1 + shll8 r1 + mov #85, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r10 +store2: + mov #40, r1 + shll8 r1 + add #12, r1 + mov #17, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r11 + +init: + # Set up addresses. + mov #40, r1 + shll8 r1 + mov #40, r2 + shll8 r2 + add #12, r2 + + # Prime {MACL, MACH} to #1. + mov #1, r3 + dmulu.l r3, r3 + +test: + mac.w @r1+, @r2+ + +check: + # Check result. + sts mach, r5 + assert r5, #0 + + sts macl, r6 + assert r6, #1 + + # Ensure post-increment occurred. + add #2, r10 + cmp/eq r10, r1 + bf wrong + + add #2, r11 + cmp/eq r11, r2 + bf wrong + +doubleinc: + mov #40, r0 + shll8 r0 + mov r0, r1 + mac.w @r0+, @r0+ + add #8, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mov.cgs b/sim/testsuite/sim/sh64/compact/mov.cgs new file mode 100644 index 00000000000..9442388384e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mov.cgs @@ -0,0 +1,40 @@ +# sh testcase for mov $rm64, $rn64 +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global mov +mov: + mov #1, r0 + rotr r0 + mov #0, r15 + mov #10, r0 + + mov r0, r1 + mov r1, r2 + mov r2, r3 + mov r3, r4 + mov r4, r5 + mov r5, r6 + mov r6, r7 + mov r7, r8 + mov r8, r9 + mov r9, r10 + mov r10, r11 + mov r11, r12 + mov r12, r13 + mov r13, r14 + mov r14, r15 + + cmp/eq r0, r15 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mova.cgs b/sim/testsuite/sim/sh64/compact/mova.cgs new file mode 100644 index 00000000000..f555d66e093 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mova.cgs @@ -0,0 +1,29 @@ +# sh testcase for mova @($imm8x4, pc), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global mova +mova: + mova @(40, pc), r0 + mov #16, r1 + shll8 r1 + add #40, r1 + cmp/eq r0, r1 + bf wrong + mova @(12, pc), r0 + mov #16, r1 + shll8 r1 + add #24, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb1.cgs b/sim/testsuite/sim/sh64/compact/movb1.cgs new file mode 100644 index 00000000000..8278e1bbeaa --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb1.cgs @@ -0,0 +1,27 @@ +# sh testcase for mov.b $rm, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #55, r1 + mov #40, r2 + shll8 r2 + mov.b r1, @r2 + + # Load it back into r3. + mov #40, r2 + shll8 r2 + mov.b @r2, r3 + + # Make sure r1 and r3 match. + cmp/eq r1, r3 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb10.cgs b/sim/testsuite/sim/sh64/compact/movb10.cgs new file mode 100644 index 00000000000..0ddb736f868 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb10.cgs @@ -0,0 +1,25 @@ +# sh testcase for mov.b @($imm4, $rm), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r0, @(3, r1) + # Load it back. + mov.b @(3, r1), r0 + and #255, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb2.cgs b/sim/testsuite/sim/sh64/compact/movb2.cgs new file mode 100644 index 00000000000..692c34fb648 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb2.cgs @@ -0,0 +1,34 @@ +# sh testcase for mov.b $rm, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #40, r1 + shll8 r1 + mov #55, r2 + + # Save ADDR, DATA. + mov r1, r7 + mov r2, r8 + + # Do the move. + mov.b r2, @-r1 + + # Load the value back into r3. + mov.b @r1, r3 + cmp/eq r2, r3 + bf wrong + + # Ensure that r1 has been decremented. + mov #1, r0 + sub r0, r7 + cmp/eq r7, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb3.cgs b/sim/testsuite/sim/sh64/compact/movb3.cgs new file mode 100644 index 00000000000..6143562b8c1 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb3.cgs @@ -0,0 +1,30 @@ +# sh testcase for mov.b $rm, @(r0,$rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #40, r2 + shll8 r2 + mov #3, r1 + mov #0, r0 + or #170, r0 + mov r0, r3 + mov r2, r0 + mov.b r3, @(r0, r1) + + # Load the value back into a different register. + mov.b @(r0, r1), r4 + # Check the lowest order byte matches the stored value. + mov r4, r0 + and #255, r0 + cmp/eq r0, r3 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb4.cgs b/sim/testsuite/sim/sh64/compact/movb4.cgs new file mode 100644 index 00000000000..d30a7a8641f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb4.cgs @@ -0,0 +1,28 @@ +# sh testcase for mov.b r0, @($imm8, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #0, r0 + or #170, r0 + mov r0, r3 + mov #30, r2 + ldc r2, gbr + mov.b r0, @(40, gbr) + + # Load the value back into a different register. + mov.b @(40, gbr), r0 + # Check the lowest order byte matches the stored value. + and #255, r0 + cmp/eq r0, r3 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movb5.cgs b/sim/testsuite/sim/sh64/compact/movb5.cgs new file mode 100644 index 00000000000..4f6795a8860 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb5.cgs @@ -0,0 +1,25 @@ +# sh testcase for mov.b r0, @($imm4, rm) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #0, r0 + or #170, r0 + mov r0, r3 + mov #30, r2 + mov.b r0, @(3, r2) + + # Load the value back into a different register. + mov.b @(3, r2), r0 + and #255, r0 + cmp/eq r3, r0 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movb6.cgs b/sim/testsuite/sim/sh64/compact/movb6.cgs new file mode 100644 index 00000000000..9ddebde5ce4 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb6.cgs @@ -0,0 +1,26 @@ +# sh testcase for mov.b @$rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r2 + shll8 r2 + # Store something first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r7, @r2 + # Load it back. + mov.b @r2, r1 + mov r1, r0 + and #255, r0 + cmp/eq r7, r0 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb7.cgs b/sim/testsuite/sim/sh64/compact/movb7.cgs new file mode 100644 index 00000000000..f55a223436b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb7.cgs @@ -0,0 +1,35 @@ +# sh testcase for mov.b @${rm}+, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + # Store addr. + mov r1, r8 + + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r7, @r1 + # Load it back. + mov.b @r1+, r2 + mov r2, r0 + and #255, r0 + cmp/eq r7, r0 + bf wrong + + # Test address for post-incrementing. + add #1, r8 + cmp/eq r8, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movb8.cgs b/sim/testsuite/sim/sh64/compact/movb8.cgs new file mode 100644 index 00000000000..883e4b357ed --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb8.cgs @@ -0,0 +1,27 @@ +# sh testcase for mov.b @(r0, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + mov #14, r1 + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r7, @(r0, r1) + # Load it back. + mov.b @(r0, r1), r2 + mov r2, r0 + and #255, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb9.cgs b/sim/testsuite/sim/sh64/compact/movb9.cgs new file mode 100644 index 00000000000..3ad1b46f2c0 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb9.cgs @@ -0,0 +1,27 @@ +# sh testcase for mov.b @($imm8, gbr), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + ldc r0, gbr + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r0, @(3, gbr) + # Load it back. + mov.b @(3, gbr), r0 + and #255, r0 + cmp/eq r7, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movcal.cgs b/sim/testsuite/sim/sh64/compact/movcal.cgs new file mode 100644 index 00000000000..7aac57e7f43 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movcal.cgs @@ -0,0 +1,28 @@ +# sh testcase for movca.l r0, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global movcal +movcal: + mov #1, r0 + rotr r0 + add #128, r0 + mov #40, r1 + shll8 r1 + movca.l r0, @r1 + + # Load the word back in. + mov.l @r1, r3 + cmp/eq r0, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movi.cgs b/sim/testsuite/sim/sh64/compact/movi.cgs new file mode 100644 index 00000000000..bc72c1b8e63 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movi.cgs @@ -0,0 +1,39 @@ +# sh testcase for mov #$imm8, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global movi +movi: + mov #0, r0 + cmp/eq #0, r0 + bf wrong + + mov #1, r0 + cmp/eq #1, r0 + bf wrong + + mov #255, r0 + cmp/eq #255, r0 + bf wrong + + mov #1, r15 + mov #1, r0 + cmp/eq r0, r15 + bf wrong + + mov #255, r15 + mov r15, r0 + cmp/eq r0, r15 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl1.cgs b/sim/testsuite/sim/sh64/compact/movl1.cgs new file mode 100644 index 00000000000..7d85c380f3e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl1.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.l $rm, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + + mov.l r2, @r1 + + # Load it back. + mov.l @r1, r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl10.cgs b/sim/testsuite/sim/sh64/compact/movl10.cgs new file mode 100644 index 00000000000..5e9cf2d2fbd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl10.cgs @@ -0,0 +1,34 @@ +# sh testcase for mov.l @($imm8x4, pc), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + + # Store to memory. + mov #16, r1 + shll8 r1 + add #32, r1 + mov.l r2, @r1 +check: + # Read it back. + mov.l @(12, pc), r0 + cmp/eq r2, r0 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl11.cgs b/sim/testsuite/sim/sh64/compact/movl11.cgs new file mode 100644 index 00000000000..32c763d8a2e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl11.cgs @@ -0,0 +1,32 @@ +# sh testcase for mov.l @($imm4x4, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + # Store something first. + mov.l r2, @(12, r0) + +check: + # Read it back. + mov.l @(12, r0), r1 + cmp/eq r2, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl2.cgs b/sim/testsuite/sim/sh64/compact/movl2.cgs new file mode 100644 index 00000000000..bb550612cce --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl2.cgs @@ -0,0 +1,43 @@ +# sh testcase for mov.l $rm, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r1 + shll8 r1 + # Save address. + mov r1, r7 + +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + mov.l r2, @-r1 + +check: + # Compare the value loaded into another reg. + mov.l @r1, r3 + cmp/eq r2, r3 + bf wrong + +dec: + # Ensure address is decremented. + mov #4, r6 + sub r6, r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl3.cgs b/sim/testsuite/sim/sh64/compact/movl3.cgs new file mode 100644 index 00000000000..6205de7558d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl3.cgs @@ -0,0 +1,36 @@ +# sh testcase for mov.l $rm, @(r0, $rn) +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +setaddr: + mov #0, r0 + mov #30, r1 + shll8 r1 + +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + + mov.l r2, @(r0, r1) + +check: + # Load it back. + mov.l @(r0, r1), r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl4.cgs b/sim/testsuite/sim/sh64/compact/movl4.cgs new file mode 100644 index 00000000000..44440946365 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl4.cgs @@ -0,0 +1,38 @@ +# sh testcase for mov.l r0, @($imm8x4, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +setaddr: + mov #30, r1 + shll8 r1 + ldc r1, gbr + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + # Preserve. + mov r0, r7 + + mov.l r0, @(4, gbr) +check: + # Load it back. + mov.l @(4, gbr), r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl5.cgs b/sim/testsuite/sim/sh64/compact/movl5.cgs new file mode 100644 index 00000000000..897ebef2367 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl5.cgs @@ -0,0 +1,37 @@ +# sh testcase for mov.l $rm, @($imm4x4, $rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +setaddr: + mov #30, r1 + shll8 r1 + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + # Preserve. + mov r0, r7 + + mov.l r0, @(4, r1) +check: + # Load it back. + mov.l @(4, r1), r0 + cmp/eq r7, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl6.cgs b/sim/testsuite/sim/sh64/compact/movl6.cgs new file mode 100644 index 00000000000..42f63b2a9ac --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl6.cgs @@ -0,0 +1,25 @@ +# sh testcase for mov.l @$rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + # Store something there first. + mov #170, r1 + mov.l r1, @r0 +check: + # Load it back. + mov.l @r0, r3 + cmp/eq r1, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl7.cgs b/sim/testsuite/sim/sh64/compact/movl7.cgs new file mode 100644 index 00000000000..b6c12fc5515 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl7.cgs @@ -0,0 +1,37 @@ +# sh testcase for mov.l @$rm+, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + # Preserve address. + mov r0, r7 + # Store something first. + mov #170, r3 + mov.l r3, @r0 + + mov.l @r0+, r1 +check: + cmp/eq r1, r3 + bf wrong + + # Ensure address is post-incremented. + add #4, r7 + cmp/eq r7, r0 + bf wrong + +equal: + # Test rm = rn. + mov #30, r0 + shll8 r0 + mov.l @r0+, r0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl8.cgs b/sim/testsuite/sim/sh64/compact/movl8.cgs new file mode 100644 index 00000000000..a6cd932d0a2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl8.cgs @@ -0,0 +1,24 @@ +# sh testcase for mov.l @(r0, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #0, r0 + mov #30, r1 + shll8 r1 + # Store something there first. + mov #170, r3 + mov.l r3, @(r0, r1) +check: + # Load it back. + mov.l @(r0, r1), r2 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl9.cgs b/sim/testsuite/sim/sh64/compact/movl9.cgs new file mode 100644 index 00000000000..4fa07b069d8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl9.cgs @@ -0,0 +1,24 @@ +# sh testcase for mov.l @($imm8x4, gbr), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + ldc r1, gbr + # Store something there first. + mov #170, r0 + mov r0, r7 + mov.l r0, @(12, gbr) +check: + # Load it back. + mov.l @(12, gbr), r0 + cmp/eq r0, r7 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movt.cgs b/sim/testsuite/sim/sh64/compact/movt.cgs new file mode 100644 index 00000000000..45539810beb --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movt.cgs @@ -0,0 +1,28 @@ +# sh testcase for movt $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global movt +init: + sett + movt r1 + assert r1, #1 +clear: + clrt + movt r1 + assert r1, #0 +set: + sett + movt r1 + assert r1, #1 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw1.cgs b/sim/testsuite/sim/sh64/compact/movw1.cgs new file mode 100644 index 00000000000..5d55a581ffd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw1.cgs @@ -0,0 +1,29 @@ +# sh testcase for mov.w $rm, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r1 + shll8 r1 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @r1 +check: + # Read it back. + mov.w @r1, r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw10.cgs b/sim/testsuite/sim/sh64/compact/movw10.cgs new file mode 100644 index 00000000000..5bab9117e9e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw10.cgs @@ -0,0 +1,32 @@ +# sh testcase for mov.w @($imm8x2, pc), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + + # Store to memory. + mov #16, r1 + shll8 r1 + add #32, r1 + mov.w r2, @r1 + +check: + # Read it back. + mov.w @(18, pc), r0 + shll16 r0 + shll16 r2 + cmp/eq r0, r2 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw11.cgs b/sim/testsuite/sim/sh64/compact/movw11.cgs new file mode 100644 index 00000000000..df739fa783d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw11.cgs @@ -0,0 +1,35 @@ +# sh testcase for mov.w @($imm4x2, $rm), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + + # Preserve r0. + mov r0, r3 + + # Store something first. + mov.w r0, @(12, r1) + +check: + # Read it back. + mov.w @(12, r1), r0 + shll16 r0 + shll16 r3 + cmp/eq r0, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw2.cgs b/sim/testsuite/sim/sh64/compact/movw2.cgs new file mode 100644 index 00000000000..27c29dc0292 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw2.cgs @@ -0,0 +1,36 @@ +# sh testcase for mov.w $rm, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r1 + shll8 r1 + # Preserve. + mov r1, r7 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 +store: + mov.w r2, @-r1 +check: + # Read it back. + mov.w @r1, r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong +dec: + add #2, r1 + cmp/eq r7, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw3.cgs b/sim/testsuite/sim/sh64/compact/movw3.cgs new file mode 100644 index 00000000000..d7b39c81506 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw3.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.w $rm, @(r0, $rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #0, r0 + mov #30, r1 + shll8 r1 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @(r0, r1) +check: + # Read it back. + mov.w @(r0, r1), r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw4.cgs b/sim/testsuite/sim/sh64/compact/movw4.cgs new file mode 100644 index 00000000000..4853b5019bc --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw4.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.w r0, @($imm8x2, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + ldc r0, gbr + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + # Preserve r0. + mov r0, r7 + mov.w r0, @(12, gbr) +check: + mov.w @(12, gbr), r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw5.cgs b/sim/testsuite/sim/sh64/compact/movw5.cgs new file mode 100644 index 00000000000..9b4f84f6516 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw5.cgs @@ -0,0 +1,32 @@ +# sh testcase for mov.w r0, @($imm4x2, $rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + # Preserve. + mov r0, r7 +move: + mov.w r0, @(12, r1) +check: + mov.w @(12, r1), r0 + shll16 r0 + shll16 r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw6.cgs b/sim/testsuite/sim/sh64/compact/movw6.cgs new file mode 100644 index 00000000000..758497c13e7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw6.cgs @@ -0,0 +1,30 @@ +# sh testcase for mov.w @$rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @r0 + +check: + # Read it back. + mov.w @r0, r1 + cmp/eq r1, r2 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw7.cgs b/sim/testsuite/sim/sh64/compact/movw7.cgs new file mode 100644 index 00000000000..45f5c098e4e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw7.cgs @@ -0,0 +1,36 @@ +# sh testcase for mov.w @${rm}+, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + # Preserve address. + mov r0, r7 + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @r0 +check: + # Read it back. + mov.w @r0+, r3 + cmp/eq r2, r3 + bf wrong + +inc: + # Ensure address is post-incremented. + add #2, r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw8.cgs b/sim/testsuite/sim/sh64/compact/movw8.cgs new file mode 100644 index 00000000000..0a7ce3f346c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw8.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.w @(r0, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + mov #10, r1 + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + + mov.w r2, @(r0, r1) +check: + # Read it back. + mov.w @(r0, r1), r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw9.cgs b/sim/testsuite/sim/sh64/compact/movw9.cgs new file mode 100644 index 00000000000..1872f06afb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw9.cgs @@ -0,0 +1,33 @@ +# sh testcase for mov.w @($imm8x2, gbr), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + ldc r0, gbr + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + # Preserve r0. + mov r0, r7 + mov.w r0, @(12, gbr) + +check: + # Load it back. + mov.w @(12, gbr), r0 + shll16 r0 + shll16 r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mull.cgs b/sim/testsuite/sim/sh64/compact/mull.cgs new file mode 100644 index 00000000000..921141aafd6 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mull.cgs @@ -0,0 +1,64 @@ +# sh testcase for mul.l $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global mull +mull: + mov #3, r0 + mov #5, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #15, r4 + cmp/eq r3, r4 + bf wrong + +lxs: + # Large * small. + mov #255, r0 + mov #0, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + cmp/eq r3, r4 + bf wrong + +sxl: + # Small * large. + mov #0, r0 + mov #255, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + cmp/eq r3, r4 + bf wrong + +lxl: + # Large * large. + mov #1, r0 + neg r0, r0 + mov #2, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #2, r4 + neg r4, r4 + cmp/eq r3, r4 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mulsw.cgs b/sim/testsuite/sim/sh64/compact/mulsw.cgs new file mode 100644 index 00000000000..05c8a3d384c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mulsw.cgs @@ -0,0 +1,91 @@ +# sh testcase for muls.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + sts mach, r7 + + .global mulsw +zero: + mov #0, r0 + mov #1, r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + cmp/eq r3, r4 + bf wrong + +sxs: + # Small * small. + mov #1, r0 + mov #2, r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #2, r4 + cmp/eq r3, r4 + bf wrong + +sxl: + # Small * large. + mov #1, r0 + mov #255, r1 + shll8 r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + not r4, r4 + shll8 r4 + cmp/eq r3, r4 + bf wrong + +lxs: + # Large * small. + mov #255, r0 + shll8 r0 + mov #1, r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + not r4, r4 + shll8 r4 + cmp/eq r3, r4 + bf wrong + +lxl: + # Large * large. + mov #255, r0 + shll8 r0 + mov #255, r1 + shll8 r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #1, r4 + shll16 r4 + cmp/eq r3, r4 + bf wrong + +invariant: + # Ensure MACH is invariant. + sts mach, r8 + cmp/eq r7, r8 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/muluw.cgs b/sim/testsuite/sim/sh64/compact/muluw.cgs new file mode 100644 index 00000000000..fa0a3343332 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/muluw.cgs @@ -0,0 +1,96 @@ +# sh testcase for mulu.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + sts mach, r7 + + .global mulsw +zero: + mov #0, r0 + mov #1, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #0, r0 + cmp/eq r0, r1 + bf wrong + +sxs: + # Small * small. + mov #1, r0 + mov #2, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #2, r0 + cmp/eq r0, r1 + bf wrong + +sxl: + # Small * large. + mov #1, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + mulu.w r1, r0 + + # Check the result. + sts macl, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + cmp/eq r0, r1 + bf wrong + +lxs: + # Large * small. + mov #0, r0 + or #255, r0 + shll8 r0 + mov #1, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + cmp/eq r0, r1 + bf wrong + +lxl: + # Large * large. + mov #0, r0 + or #255, r0 + shll8 r0 + mov r0, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #0, r0 + or #254, r0 + shll8 r0 + or #1, r0 + shll16 r0 + cmp/eq r0, r1 + bf wrong + +invariant: + # Ensure MACH is invariant. + sts mach, r8 + cmp/eq r7, r8 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/neg.cgs b/sim/testsuite/sim/sh64/compact/neg.cgs new file mode 100644 index 00000000000..b6f98d74060 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/neg.cgs @@ -0,0 +1,55 @@ +# sh testcase for neg $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro signbit sign + shlr16 r1 + shlr8 r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + assert r1, \sign + .endm + start + + .global neg +neg: + mov #0, r0 + neg r0, r1 + signbit #0 + + mov #42, r0 + neg r0, r1 + signbit #1 + + mov #0, r0 + or #25, r0 + neg r0, r1 + signbit #1 + + # neg(0) is 0. + mov #0, r0 + neg r0, r1 + signbit #0 + + # neg(neg(x)) = x. + mov #42, r0 + neg r0, r1 + signbit #1 + mov #42, r0 + neg r0, r2 + neg r2, r1 + signbit #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/negc.cgs b/sim/testsuite/sim/sh64/compact/negc.cgs new file mode 100644 index 00000000000..1f5547d9bab --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/negc.cgs @@ -0,0 +1,66 @@ +# sh testcase for negc $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro signbit sign + mov r1, r2 + shlr16 r2 + shlr8 r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + assert r2, \sign + .endm + start + + .global negc +negc: + clrt + mov #1, r0 + negc r0, r1 + signbit #1 + +negc2: + sett + mov #1, r0 + negc r0, r1 + signbit #1 + +negc3: + clrt + mov #0, r0 + negc r0, r1 + signbit #0 + +negc4: + sett + mov #0, r0 + negc r0, r1 + signbit #1 + +negc5: + clrt + mov #0, r0 + or #255, r0 + negc r0, r1 + signbit #1 + +negc6: + sett + mov #0, r0 + or #255, r0 + negc r0, r1 + signbit #1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/nop.cgs b/sim/testsuite/sim/sh64/compact/nop.cgs new file mode 100644 index 00000000000..8ce910c5abd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/nop.cgs @@ -0,0 +1,13 @@ +# sh testcase for nop +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global nop +nop: + nop + pass diff --git a/sim/testsuite/sim/sh64/compact/not.cgs b/sim/testsuite/sim/sh64/compact/not.cgs new file mode 100644 index 00000000000..380808ddb57 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/not.cgs @@ -0,0 +1,47 @@ +# sh testcase for not $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global not +not: + mov #0, r0 + or #192, r0 + not r0, r1 + + mov #0, r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #63, r0 + + cmp/eq r0, r1 + bf wrong + +ones: + mov #0, r1 + not r1, r2 + + mov #0, r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + cmp/eq r0, r2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ocbi.cgs b/sim/testsuite/sim/sh64/compact/ocbi.cgs new file mode 100644 index 00000000000..12fb2a116c4 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ocbi.cgs @@ -0,0 +1,14 @@ +# sh testcase for ocbi @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + .global ocbi +ocbi: + ocbi @r0 + ocbi @r1 + ocbi @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/ocbp.cgs b/sim/testsuite/sim/sh64/compact/ocbp.cgs new file mode 100644 index 00000000000..153aff2eade --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ocbp.cgs @@ -0,0 +1,15 @@ +# sh testcase for ocbp @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ocbp +ocbp: + ocbp @r0 + ocbp @r1 + ocbp @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/ocbwb.cgs b/sim/testsuite/sim/sh64/compact/ocbwb.cgs new file mode 100644 index 00000000000..6b0a741cbca --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ocbwb.cgs @@ -0,0 +1,15 @@ +# sh testcase for ocbwb @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ocbwb +ocbwb: + ocbwb @r0 + ocbwb @r1 + ocbwb @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/or.cgs b/sim/testsuite/sim/sh64/compact/or.cgs new file mode 100644 index 00000000000..a02eee39aaf --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/or.cgs @@ -0,0 +1,43 @@ +# sh testcase for or $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global or +or: + mov #1, r0 + rotr r0 + mov #1, r1 + or r0, r1 + + mov #1, r7 + rotr r7 + add #1, r7 + cmp/eq r7, r1 + bf wrong + + .global or2 +or2: + mov #85, r0 + shll16 r0 + shll8 r0 + mov #85, r1 + shll8 r1 + or r0, r1 + + mov #85, r7 + shll16 r7 + add #85 ,r7 + shll8 r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/orb.cgs b/sim/testsuite/sim/sh64/compact/orb.cgs new file mode 100644 index 00000000000..7e962f6fe69 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/orb.cgs @@ -0,0 +1,24 @@ +# sh testcase for or.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + or.b #0, @(r0, gbr) + or.b #170, @(r0, gbr) + or.b #0, @(r0, gbr) + or.b #255, @(r0, gbr) + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/ori.cgs b/sim/testsuite/sim/sh64/compact/ori.cgs new file mode 100644 index 00000000000..63a5fb58740 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ori.cgs @@ -0,0 +1,40 @@ +# sh testcase for or #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ori +ori: + mov #1, r0 + rotr r0 + or #1, r0 + + mov #1, r7 + rotr r7 + add #1, r7 + cmp/eq r0, r7 + bf wrong + + .global ori2 +ori2: + mov #85, r0 + shll16 r0 + shll8 r0 + or #85, r0 + + mov #85, r7 + shll16 r7 + shll8 r7 + add #85, r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/pref.cgs b/sim/testsuite/sim/sh64/compact/pref.cgs new file mode 100644 index 00000000000..065e0932e6c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/pref.cgs @@ -0,0 +1,15 @@ +# sh testcase for pref @$rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global pref +pref: + pref @r0 + pref @r1 + pref @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/rotcl.cgs b/sim/testsuite/sim/sh64/compact/rotcl.cgs new file mode 100644 index 00000000000..5e1a3b91137 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotcl.cgs @@ -0,0 +1,121 @@ +# sh testcase for rotcl $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotcl + +rotcl: + clrt + mov #1, r1 + rotcl r1 + assert r1, #2 + clrt + rotcl r1 + assert r1, #4 + clrt + rotcl r1 + assert r1, #8 + clrt + rotcl r1 + assert r1, #16 + clrt + rotcl r1 + assert r1, #32 + clrt + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + bf wrong + rotcl r1 + assert r1, #1 + + bra trotcl + nop + +wrong: + fail + +trotcl: + sett + mov #1, r1 + rotcl r1 + assert r1, #3 + clrt + rotcl r1 + assert r1, #6 + clrt + rotcl r1 + assert r1, #12 + clrt + rotcl r1 + assert r1, #24 + clrt + rotcl r1 + assert r1, #48 + clrt + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + bf wrong2 + assert r1, #1 + rotcl r1 + rotcl r1 + +okay: + pass +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/rotcr.cgs b/sim/testsuite/sim/sh64/compact/rotcr.cgs new file mode 100644 index 00000000000..b53300ec54f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotcr.cgs @@ -0,0 +1,103 @@ +# sh testcase for rotcr $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotcr +rotcr: + clrt + mov #1, r1 + rotcr r1 + bf wrong + assert r1, #0 + sett + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + assert r1, #1 + rotcr r1 + bf wrong + +trotcr: + sett + mov #1, r1 + rotcr r1 + bf wrong + sett + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + bf wrong + assert r1, #1 + rotcr r1 + bf wrong + rotcr r1 + +okay: + pass +wrong: + fail + + diff --git a/sim/testsuite/sim/sh64/compact/rotl.cgs b/sim/testsuite/sim/sh64/compact/rotl.cgs new file mode 100644 index 00000000000..e292de7e437 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotl.cgs @@ -0,0 +1,62 @@ +# sh testcase for rotl $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotl +rotl: + mov #1, r1 + rotl r1 + assert r1, #2 + rotl r1 + assert r1, #4 + rotl r1 + assert r1, #8 + rotl r1 + assert r1, #16 + rotl r1 + assert r1, #32 + rotl r1 + assert r1, #64 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + bf wrong + assert r1, #1 + rotl r1 + rotl r1 + rotl r1 + assert r1, #8 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/rotr.cgs b/sim/testsuite/sim/sh64/compact/rotr.cgs new file mode 100644 index 00000000000..7f80f993aea --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotr.cgs @@ -0,0 +1,55 @@ +# sh testcase for rotr $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotr +rotr: + mov #1, r1 + rotr r1 + bf wrong + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + assert r1, #1 + rotr r1 + rotr r1 + rotr r1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/rts.cgs b/sim/testsuite/sim/sh64/compact/rts.cgs new file mode 100644 index 00000000000..eeb8dce9332 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rts.cgs @@ -0,0 +1,24 @@ +# sh testcase for rts -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rts +rts: + bsr subroutine +slot: + nop +return: + pass + fail + +subroutine: + rts +rts_slot: + nop +bad: + fail diff --git a/sim/testsuite/sim/sh64/compact/sets.cgs b/sim/testsuite/sim/sh64/compact/sets.cgs new file mode 100644 index 00000000000..f031701d6ee --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sets.cgs @@ -0,0 +1,13 @@ +# sh testcase for sets -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sets +sets: + sets + pass diff --git a/sim/testsuite/sim/sh64/compact/sett.cgs b/sim/testsuite/sim/sh64/compact/sett.cgs new file mode 100644 index 00000000000..9ae8af536e7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sett.cgs @@ -0,0 +1,16 @@ +# sh testcase for sett -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sett +sett: + sett + bf wrong + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shad.cgs b/sim/testsuite/sim/sh64/compact/shad.cgs new file mode 100644 index 00000000000..340743d8f1f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shad.cgs @@ -0,0 +1,58 @@ +# sh testcase for shad $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global null +null: + mov #1, r0 + mov #0, r1 + shad r1, r0 + # no shift is performed. + assert r0, #1 + + .global gt0 +gt0: + mov #4, r0 + mov #3, r1 + shad r1, r0 + # shift left 3 bits. + assert r0, #32 + + .global lt0 +lt0: + mov #32, r0 + mov #3, r1 + neg r1, r1 + shad r1, r0 + # shift right 3 bits. + assert r0, #4 + + .global fillpos +fillpos: + mov #1, r0 + mov #1, r1 + rotr r1 + shad r1, r0 + # check result. + assert r0, #0 + + .global fillneg +fillneg: + mov #1, r0 + neg r0, r0 + mov #1, r1 + rotr r1 + shad r1, r0 + # check result. + not r0, r0 + assert r0, #0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shal.cgs b/sim/testsuite/sim/sh64/compact/shal.cgs new file mode 100644 index 00000000000..dfea947e856 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shal.cgs @@ -0,0 +1,57 @@ +# sh testcase for shal $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shal +shal: + mov #1, r1 + shal r1 + assert r1, #2 + shal r1 + assert r1, #4 + shal r1 + assert r1, #8 + shal r1 + assert r1, #16 + shal r1 + assert r1, #32 + shal r1 + assert r1, #64 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + assert r1, #0 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/shar.cgs b/sim/testsuite/sim/sh64/compact/shar.cgs new file mode 100644 index 00000000000..e3e92fca080 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shar.cgs @@ -0,0 +1,40 @@ +# sh testcase for shar $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shar +shar: + mov #0, r0 + or #192, r0 + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bf wrong + shar r0 + bf wrong + shar r0 + bt wrong + shar r0 + bt wrong + assert r0, #0 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/shld.cgs b/sim/testsuite/sim/sh64/compact/shld.cgs new file mode 100644 index 00000000000..32e4100259d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shld.cgs @@ -0,0 +1,48 @@ +# sh testcase for shld $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global null +null: + mov #1, r0 + mov #0, r1 + shld r1, r0 + # no shift is performed. + assert r0, #1 + + .global gt0 +gt0: + mov #4, r0 + mov #3, r1 + shld r1, r0 + # shift left 3 bits. + assert r0, #32 + + .global lt0 +lt0: + mov #32, r0 + mov #3, r1 + neg r1, r1 + shld r1, r0 + # shift right 3 bits. + assert r0, #4 + + .global fill +fill: + mov #1, r0 + rotr r0 + mov #1, r1 + rotr r1 + shld r1, r0 + assert r0, #0 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/shll.cgs b/sim/testsuite/sim/sh64/compact/shll.cgs new file mode 100644 index 00000000000..882f2c2e1ef --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll.cgs @@ -0,0 +1,57 @@ +# sh testcase for shll $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll +shll: + mov #1, r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + assert r1, #0 +another: + mov #1, r1 + shll r1 + shll r1 + shll r1 + assert r1, #8 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shll16.cgs b/sim/testsuite/sim/sh64/compact/shll16.cgs new file mode 100644 index 00000000000..0637c3de706 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll16.cgs @@ -0,0 +1,44 @@ +# sh testcase for shll16 $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll16 +shll16: + mov #108, r1 + shll16 r1 + shll16 r1 + assert r1, #0 + +another: + mov #1, r1 + shll16 r1 + mov #1, r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shll2.cgs b/sim/testsuite/sim/sh64/compact/shll2.cgs new file mode 100644 index 00000000000..6e28c664307 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll2.cgs @@ -0,0 +1,40 @@ +# sh testcase for shll2 $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll2 +shll2: + mov #1, r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + assert r1, #0 + +another: + mov #1, r1 + shll2 r1 + assert r1, #4 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shll8.cgs b/sim/testsuite/sim/sh64/compact/shll8.cgs new file mode 100644 index 00000000000..fe455ec753d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll8.cgs @@ -0,0 +1,38 @@ +# sh testcase for shll8 $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll8 +shll8: + mov #1, r1 + shll8 r1 + shll8 r1 + shll8 r1 + shll8 r1 + assert r1, #0 + +another: + mov #1, r1 + shll8 r1 + mov #1, r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shlr.cgs b/sim/testsuite/sim/sh64/compact/shlr.cgs new file mode 100644 index 00000000000..9d86461b959 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr.cgs @@ -0,0 +1,33 @@ +# sh testcase for shlr $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shlr +shlr: + mov #0, r0 + or #192, r0 + shlr r0 + shlr r0 + shlr r0 + shlr r0 + shlr r0 + shlr r0 + # Make sure a bit is shifted into T. + shlr r0 + bf wrong + # Ditto. + shlr r0 + bf wrong + shlr r0 + assert r0, #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shlr16.cgs b/sim/testsuite/sim/sh64/compact/shlr16.cgs new file mode 100644 index 00000000000..7bfc62788f3 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr16.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlr16 $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shrl16 +shrl16: + shlr16 r0 + + pass diff --git a/sim/testsuite/sim/sh64/compact/shlr2.cgs b/sim/testsuite/sim/sh64/compact/shlr2.cgs new file mode 100644 index 00000000000..6f085979443 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr2.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlr2 $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shrl2 +shrl2: + shlr2 r0 + + pass diff --git a/sim/testsuite/sim/sh64/compact/shlr8.cgs b/sim/testsuite/sim/sh64/compact/shlr8.cgs new file mode 100644 index 00000000000..82040b581b8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr8.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlr8 $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shrl8 +shrl8: + shlr8 r0 + + pass diff --git a/sim/testsuite/sim/sh64/compact/stc-gbr.cgs b/sim/testsuite/sim/sh64/compact/stc-gbr.cgs new file mode 100644 index 00000000000..1b84008c9d2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stc-gbr.cgs @@ -0,0 +1,21 @@ +# sh testcase for stc gbr, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stc_gbr +stc_gbr: + stc gbr, r1 + mov #42, r1 + ldc r1, gbr + stc gbr, r2 + cmp/eq r1, r2 + bf wrong +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs new file mode 100644 index 00000000000..3e74cc551de --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs @@ -0,0 +1,27 @@ +# sh testcase for stc.l gbr, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stcl_gbr +stcl_gbr: + mov #42, r0 + ldc r0, gbr + mov #40, r0 + shll8 r0 + # save address + mov r0, r1 + stc.l gbr, @-r0 + + add #4, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs b/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs new file mode 100644 index 00000000000..42724b44fff --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs @@ -0,0 +1,23 @@ +# sh testcase for sts fpscr, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_fpscr +sts_fpscr: + sts fpscr, r0 + mov #42, r0 + lds r0, fpscr + sts fpscr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/sts-fpul.cgs b/sim/testsuite/sim/sh64/compact/sts-fpul.cgs new file mode 100644 index 00000000000..ddbdaf15fb2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-fpul.cgs @@ -0,0 +1,14 @@ +# sh testcase for sts fpul, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_fpul +sts_fpul: + # This is properly exercised by the lds-fpul test case. + sts fpul, r1 + pass diff --git a/sim/testsuite/sim/sh64/compact/sts-mach.cgs b/sim/testsuite/sim/sh64/compact/sts-mach.cgs new file mode 100644 index 00000000000..4d34bc17aa8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-mach.cgs @@ -0,0 +1,22 @@ +# sh testcase for sts mach, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_mach +sts_mach: + mov #42, r0 + lds r0, mach + sts mach, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/sts-macl.cgs b/sim/testsuite/sim/sh64/compact/sts-macl.cgs new file mode 100644 index 00000000000..b805f796e44 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-macl.cgs @@ -0,0 +1,21 @@ +# sh testcase for sts macl, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_macl +sts_macl: + mov #42, r0 + lds r0, macl + sts macl, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/sts-pr.cgs b/sim/testsuite/sim/sh64/compact/sts-pr.cgs new file mode 100644 index 00000000000..3e4f6ee880a --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-pr.cgs @@ -0,0 +1,22 @@ +# sh testcase for sts pr, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_pr +sts_pr: + mov #42, r0 + lds r0, pr + sts pr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs new file mode 100644 index 00000000000..032870dc189 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs @@ -0,0 +1,28 @@ +# sh testcase for sts.l fpscr, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_fpscr +stsl_fpscr: + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r7 + sts.l fpscr, @-r0 + +check: + # Ensure r0 is decremented. + add #4, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs new file mode 100644 index 00000000000..89bd9e73849 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs @@ -0,0 +1,27 @@ +# sh testcase for sts.l fpul, @-$rn -*- Asm -*_ +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_fpul +stsl_fpul: + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r7 + sts.l fpul, @-r0 + +dec: + # Check for proper pre-decrementing. + add #4, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/stsl-mach.cgs b/sim/testsuite/sim/sh64/compact/stsl-mach.cgs new file mode 100644 index 00000000000..e15bddece29 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-mach.cgs @@ -0,0 +1,42 @@ +# sh testcase for sts.l mach, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_mach +stsl_mach: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + + lds r0, mach + mov #40, r2 + shll8 r2 + # Preserve r2. + mov r2, r7 + sts.l mach, @-r2 + + # check results. + mov.l @r2, r3 + cmp/eq r0, r3 + bf wrong + + # Ensure decrement occurred. + add #4, r2 + cmp/eq r2, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-macl.cgs b/sim/testsuite/sim/sh64/compact/stsl-macl.cgs new file mode 100644 index 00000000000..854ef341552 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-macl.cgs @@ -0,0 +1,42 @@ +# sh testcase for sts.l macl, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_macl +stsl_macl: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + + lds r0, macl + mov #40, r2 + shll8 r2 + # Preserve r2. + mov r2, r7 + sts.l macl, @-r2 + + # check results. + mov.l @r2, r3 + cmp/eq r0, r3 + bf wrong + + # Ensure decrement occurred. + add #4, r2 + cmp/eq r2, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-pr.cgs b/sim/testsuite/sim/sh64/compact/stsl-pr.cgs new file mode 100644 index 00000000000..b519c9bb5bd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-pr.cgs @@ -0,0 +1,42 @@ +# sh testcase for sts.l pr, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_pr +stsl_pr: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + + lds r0, pr + mov #40, r2 + shll8 r2 + # Preserve r2. + mov r2, r7 + sts.l pr, @-r2 + + # check results. + mov.l @r2, r3 + cmp/eq r0, r3 + bf wrong + + # Ensure decrement occurred. + add #4, r2 + cmp/eq r2, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/sub.cgs b/sim/testsuite/sim/sh64/compact/sub.cgs new file mode 100644 index 00000000000..3ba29f872aa --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sub.cgs @@ -0,0 +1,68 @@ +# sh testcase for sub $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sub1 +sub1: + # 0 - x. + mov #0, r0 + mov #3, r1 + sub r1, r0 + + mov #2, r7 + not r7, r7 + cmp/eq r7, r0 + bf wrong + + .global sub2 +sub2: + # x - 0. + mov #0, r0 + mov #3, r1 + sub r0, r1 + assert r1, #3 + + .global sub3 +sub3: + # x - y. + mov #4, r0 + mov #3, r1 + sub r0, r1 + + mov #0, r7 + not r7, r7 + cmp/eq r7, r1 + bf wrong + + .global sub4 +sub4: + # y - x. + mov #4, r0 + mov #3, r1 + sub r1, r0 + assert r0, #1 + + .global sub5 +sub5: + # y - y == 0 (where y are in two distinct registers). + mov #4, r0 + mov #4, r1 + sub r1, r0 + assert r0, #0 + + .global sub6 +sub6: + # y - y = 0 (where y is the same register). + mov #4, r1 + sub r1, r1 + assert r1, #0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/subc.cgs b/sim/testsuite/sim/sh64/compact/subc.cgs new file mode 100644 index 00000000000..cda1e84ae9d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/subc.cgs @@ -0,0 +1,109 @@ +# sh testcase for subc $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +zero: + mov #0, r0 + mov #0, r1 + clrt + subc r0, r1 + assert r1, #0 + +zerot: + mov #0, r0 + mov #0, r1 + sett + subc r0, r1 + # Invert all 1's to all 0's for ease of comparison. + not r1, r1 + assert r1, #0 + +null: + mov #0, r0 + mov #10, r1 + clrt + subc r0, r1 + assert r1, #10 + +nullt: + mov #0, r0 + mov #10, r1 + sett + subc r0, r1 + assert r1, #9 + +subc: + mov #10, r0 + mov #0, r1 + clrt + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #9 + +subct: + mov #10, r0 + mov #0, r1 + sett + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #10 + +subc2: + mov #10, r0 + mov #20, r1 + clrt + subc r0, r1 + assert r1, #10 + +subc2t: + mov #20, r0 + mov #10, r1 + sett + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #10 + +subc3: + mov #5, r0 + mov #5, r1 + clrt + subc r0, r1 + assert r1, #0 + +subc3t: + mov #5, r0 + mov #5, r1 + sett + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #0 + +large: + mov #2, r0 + mov #10, r1 + clrt + subc r1, r0 + # Again, invert .. + not r0, r0 + assert r0, #7 + +larget: + mov #2, r0 + mov #10, r1 + sett + subc r0, r1 + assert r1, #7 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/subv.cgs b/sim/testsuite/sim/sh64/compact/subv.cgs new file mode 100644 index 00000000000..ceb8c64e7fd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/subv.cgs @@ -0,0 +1,55 @@ +# sh testcase for subv $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +zero: + mov #0, r0 + mov #0, r1 + subv r0, r1 + bt wrong + assert r1, #0 + +one: + mov #10, r0 + mov #0, r1 + subv r0, r1 + bt wrong + not r1, r1 + assert r1, #9 + +large: + # Produce MAXINT in R0. + mov #0, r0 + not r0, r0 + shlr r0 + + # Put -3 into R1. + mov #3, r1 + neg r1, r1 + + # Subtract them and underflow. + subv r0, r1 + bf wrong + +another: + # Produce MAXINT in R0. + mov #0, r0 + not r0, r0 + shlr r0 + + # Put -3 into R1. + mov #3, r1 + neg r1, r1 + + # Subtract them and overflow. + subv r1, r0 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/swapb.cgs b/sim/testsuite/sim/sh64/compact/swapb.cgs new file mode 100644 index 00000000000..22f6f16a2e1 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/swapb.cgs @@ -0,0 +1,44 @@ +# sh testcase for swap.b $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #70, r0 + +test: + # Swap the lower two bytes into a different register. + swap.b r0, r1 + mov #1, r7 + shll8 r7 + add #12, r7 + shll8 r7 + add #70, r7 + shll8 r7 + add #85, r7 + cmp/eq r1, r7 + bf wrong + +swapback: + # Swap the lower two bytes into the same registers. + # R0 should now equal R1. + swap.b r1, r2 + cmp/eq r0, r2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/swapw.cgs b/sim/testsuite/sim/sh64/compact/swapw.cgs new file mode 100644 index 00000000000..fa1ab697f27 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/swapw.cgs @@ -0,0 +1,43 @@ +# sh testcase for swap.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global swapw +swapw: + # Build up a characteristic bit pattern in R0. + mov #85, r0 + shll16 r0 + add #3, r0 + rotr r0 + rotr r0 + or #170, r0 + # Preserve for later. + mov r0, r8 + +test: + swap.w r0, r1 + mov #64, r0 + shll8 r0 + or #170, r0 + shll8 r0 + or #192, r0 + shll8 r0 + or #21, r0 + cmp/eq r1, r0 + bf wrong + +swapback: + swap.w r1, r2 + cmp/eq r2, r8 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/tasb.cgs b/sim/testsuite/sim/sh64/compact/tasb.cgs new file mode 100644 index 00000000000..cb7f61870d2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tasb.cgs @@ -0,0 +1,26 @@ +# sh testcase for tas.b @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +tasb1: + mov #40, r0 + shll8 r0 + tas.b @r0 + bf wrong + +tasb2: + mov #40, r0 + shll8 r0 + tas.b @r0 + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/testutils.inc b/sim/testsuite/sim/sh64/compact/testutils.inc new file mode 100644 index 00000000000..b1ad830578b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/testutils.inc @@ -0,0 +1,49 @@ +# Support macros for the assembly test cases. + + .macro start + .text + .global start +start: + .endm + + # Perform a single to double precision floating point conversion. + .macro _s2d fpr dpr + flds \fpr, fpul + _setpr + fcnvsd fpul, \dpr + _clrpr + .endm + + # Set the PR (PRecision) bit in the FPSCR. + .macro _setpr + sts fpscr, r7 + mov #8, r8 + shll16 r8 + or r8, r7 + lds r7, fpscr + .endm + + # Clear the PR bit. + .macro _clrpr + sts fpscr, r7 + mov #8, r8 + shll16 r8 + not r8, r8 + and r8, r7 + lds r7, fpscr + .endm + + # nb: this macro clobbers R7. + .macro assert reg value + mov \value, r7 + cmp/eq \reg, r7 + bf wrong + .endm + + .macro pass + trapa #253 + .endm + + .macro fail + trapa #254 + .endm diff --git a/sim/testsuite/sim/sh64/compact/trapa.cgs b/sim/testsuite/sim/sh64/compact/trapa.cgs new file mode 100644 index 00000000000..24f8a6b13ba --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/trapa.cgs @@ -0,0 +1,13 @@ +# sh testcase for trapa #$imm8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global trapa +trapa: + # pass is a macro for "trapa #253". + trapa #253 diff --git a/sim/testsuite/sim/sh64/compact/tst.cgs b/sim/testsuite/sim/sh64/compact/tst.cgs new file mode 100644 index 00000000000..a72b8a9a743 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tst.cgs @@ -0,0 +1,62 @@ +# sh testcase for tst $rm, $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global tst1 +tst1: + mov #0, r0 + mov #0, r1 + tst r0, r0 + bf wrong + +test2: + mov #0, r0 + mov #1, r1 + tst r0, r1 + bf wrong + +test3: + mov #0, r0 + mov #1, r1 + tst r1, r0 + bf wrong + +test4: + mov #1, r0 + mov #1, r1 + tst r0, r1 + bt wrong + +test5: + mov #1, r0 + rotr r0 + add #85, r0 + shll16 r0 + add #12, r0 + mov #1, r1 + rotr r1 + add #85, r1 + shll16 r1 + add #12, r1 + tst r0, r1 + bt wrong + +test6: + mov #1, r0 + rotr r0 + add #85, r0 + shll16 r0 + add #12, r0 + mov #1, r1 + tst r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/tstb.cgs b/sim/testsuite/sim/sh64/compact/tstb.cgs new file mode 100644 index 00000000000..1b3829b1d30 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tstb.cgs @@ -0,0 +1,30 @@ +# sh testcase for tst.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + tst.b #0, @(r0, gbr) + bf wrong + tst.b #170, @(r0, gbr) + bf wrong + tst.b #0, @(r0, gbr) + bf wrong + tst.b #255, @(r0, gbr) + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/tsti.cgs b/sim/testsuite/sim/sh64/compact/tsti.cgs new file mode 100644 index 00000000000..e088029b470 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tsti.cgs @@ -0,0 +1,32 @@ +# sh testcase for tst #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global tsti +tsti: + mov #0, r0 + tst #0, r0 + +tsti2: + mov #0, r0 + tst #1, r0 + +tsti3: + mov #1, r0 + tst #0, r0 + +tsti4: + mov #1, r0 + tst #1, r0 + +tsti5: + mov #255, r0 + tst #255, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/xor.cgs b/sim/testsuite/sim/sh64/compact/xor.cgs new file mode 100644 index 00000000000..d158aaf3713 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xor.cgs @@ -0,0 +1,70 @@ +# sh testcase for xor $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global xor +xor: + # 0 (+) 1 = 1. + mov #0, r0 + mov #1, r1 + xor r0, r1 + assert r1, #1 + +xor2: + # 1 (+) 0 = 0. + mov #1, r0 + mov #0, r1 + xor r0, r1 + assert r1, #1 + +xor3: + # 0 (+) 0 = 0. + mov #0, r0 + mov #0, r1 + xor r0, r1 + assert r1, #0 + +xor4: + # 0 (+) 0 = 0. + mov #0, r0 + xor r0, r0 + assert r0, #0 + +xor5: + mov #0, r0 + or #85, r0 + shll16 r0 + or #170, r0 + mov r0, r1 + mov #0, r0 + or #85, r0 + shll16 r0 + or #170, r0 + xor r1, r0 + assert r0, #0 + +xor6: + mov #0, r0 + or #85, r0 + shll16 r0 + or #170, r0 + mov r0, r1 + mov #0, r0 + or #85, r0 + shll16 r0 + or #12, r0 + xor r0, r1 + mov #0, r0 + or #166, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/xorb.cgs b/sim/testsuite/sim/sh64/compact/xorb.cgs new file mode 100644 index 00000000000..b31464b3c13 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xorb.cgs @@ -0,0 +1,24 @@ +# sh testcase for xor.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + xor.b #0, @(r0, gbr) + xor.b #170, @(r0, gbr) + xor.b #0, @(r0, gbr) + xor.b #255, @(r0, gbr) + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/xori.cgs b/sim/testsuite/sim/sh64/compact/xori.cgs new file mode 100644 index 00000000000..732b9ec5c48 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xori.cgs @@ -0,0 +1,50 @@ +# sh testcase for xor #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global xori +xori: + # 0 (+) 1 = 1. + mov #0, r0 + xor #1, r0 + assert r0, #1 + +xori2: + # 1 (+) 0 = 1. + mov #1, r0 + xor #0, r0 + assert r0, #1 + +xori3: + # 1 (+) 1 = 0. + mov #1, r0 + xor #1, r0 + assert r0, #0 + +xori4: + # 255 (+) 255 = 0. + mov #0, r0 + or #255, r0 + xor #255, r0 + assert r0, #0 + +xori5: + # 0 (+) 255 = 255. + mov #0, r0 + xor #255, r0 + mov r0, r1 + + mov #0, r0 + or #255, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/xtrct.cgs b/sim/testsuite/sim/sh64/compact/xtrct.cgs new file mode 100644 index 00000000000..11dae7cbdec --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xtrct.cgs @@ -0,0 +1,46 @@ +# sh testcase for xtrct $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +init: + mov #170, r0 + shll8 r0 + add #1, r0 + shll8 r0 + add #66, r0 + shll8 r0 + mov r0, r1 + + mov #85, r0 + shll8 r0 + add #2, r0 + shll8 r0 + add #42, r0 + shll8 r0 + add #3, r0 + +copy: + mov r0, r3 + mov r1, r4 + +xtrct: + xtrct r0, r1 + +check: + # Lower r3, upper r4. + shll16 r3 + shlr16 r4 + or r3, r4 + cmp/eq r1, r4 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/interwork.exp b/sim/testsuite/sim/sh64/interwork.exp new file mode 100644 index 00000000000..acd19b3c90c --- /dev/null +++ b/sim/testsuite/sim/sh64/interwork.exp @@ -0,0 +1,20 @@ +# SH64 interworking testsuite. +# In particular, test parts of the instruction set that can be used +# for SHmedia/SHcompact instruction set mode switches. + +if [istarget sh64-*-*] { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "sh5" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/misc/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/sh64/media.exp b/sim/testsuite/sim/sh64/media.exp new file mode 100644 index 00000000000..1a3d9f4c961 --- /dev/null +++ b/sim/testsuite/sim/sh64/media.exp @@ -0,0 +1,19 @@ +# SHmedia testsuite. + +if [istarget sh64-*-*] { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "sh5" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/media/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/sh64/media/ChangeLog b/sim/testsuite/sim/sh64/media/ChangeLog new file mode 100644 index 00000000000..e435dbe5278 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ChangeLog @@ -0,0 +1,102 @@ +2001-01-09 Ben Elliston <bje@redhat.com> + + * nsb.cgs: Test consecutive bits of zeros as well as ones. + * ptb.cgs: Clean up. + +2001-01-08 Ben Elliston <bje@redhat.com> + + * fcmpund.cgs, fcmpuns.cgs: Complete test cases. + * fcnvds.cgs, fcnvsd.cgs, fgetscr.cgs, fiprs.cgs: Ditto. + * floatld.cgs, floatls.cgs, floatqd.cgs, floatqs.cgs: Ditto. + * fmuld.cgs, fmuls.cgs, fputscr.cgs, fstxp.cgs: Ditto. + * fsubd.cgs, fsubs.cgs, ftrcdl.cgs, ftrcdq.cgs: Ditto. + * ftrcsl.cgs, ftrcsq.cgs, ftrvs.cgs: Ditto. + * ldhil.cgs, ldhiq.cgs, ldlol.cgs, ldloq.cgs: Ditto. + * mabsl.cgs, mabsw.cgs, maddl.cgs, maddsl.cgs: Ditto. + * maddsub.cgs, maddsw.cgs, maddw.cgs: Ditto. + * mcmpeqb.cgs, mcmpeql.cgs, mcmpeqw.cgs: Ditto. + * mcmpgtl.cgs, mcmpgtub.cgs, mcmpgtw.cgs: Ditto. + * mcmv.cgs, mcnvslw.cgs, mcnvswb.cgs, mcnvswub.cgs: Ditto. + * mmacfxwl.cgs, mmacnfx-wl.cgs: Ditto. + * mmulfxl.cgs, mmulfxrpw.cgs, mmulfxw.cgs: Ditto. + * mmulhiwl.cgs, mmull.cgs, mmullowl.cgs: Ditto. + * mmulsumwq.cgs, mmulw.cgs, movi.cgs: Ditto. + * mpermw.cgs, msadubq.cgs: Ditto. + * mshaldsl.cgs, mshaldsw.cgs: Ditto. + * mshardl.cgs, mshardsq.cgs, mshardw.cgs: Ditto. + * mshfhib.cgs, mshfhil.cgs, mshfhiw.cgs: Ditto. + * mshflob.cgs, mshflol.cgs, mshflow.cgs: Ditto. + * mshlldl.cgs, mshlldw.cgs, mshlrdl.cgs: Ditto. + * mshlrdw.cgs, msubl.cgs, msubsl.cgs: Ditto. + * msubsub.cgs, msubsw.cgs, msubw.cgs: Ditto. + * mulsl.cgs, mulul.cgs: Ditto. + * ptabs.cgs, ptb.cgs, ptrel.cgs: Ditto. + * shard.cgs, shardl.cgs, shari.cgs, sharil.cgs: Ditto. + * shlld.cgs, shlldl.cgs, shlli.cgs, shllil.cgs: Ditto. + * shlrd.cgs, shlrdl.cgs, shlri.cgs, shlril.cgs: Ditto. + * sthil.cgs, sthiq.cgs, swapq.cgs, trapa.cgs: Ditto. + + * testutils.inc (pass): Pass correct "syscall" number. + (fail): Ditto. + +2000-12-13 Ben Elliston <bje@redhat.com> + + * sub.cgs, subl.cgs: Complete test cases. + * ptrel.cgs: Likewise. + + * shori.cgs: Test for zero extension of immediate operand. + * fcmpged.cgs, fcmpges.cgs, fldd.cgs: Complete test cases. + * fldp.cgs, flds.cgs, fldxd.cgs, fldxp.cgs: Likewise. + * fldxs.cgs, fmacs.cgs, fnegd.cgs, fnegs.cgs: Likewise. + * fsqrtd.cgs, fsqrts.cgs, fstd.cgs, fstp.cgs: Likewise. + * fsts.cgs, fstxd.cgs, fstxs.cgs: Likewise. + +2000-12-12 Ben Elliston <bje@redhat.com> + + * testutils.inc (pass): Use simple syscall mechanism. + (fail): Likewise. + (_packb, _packw, _packl): New macros for packing slices. + + * stb.cgs, stq.cgs, stxb.cgs, stxq.cgs: Complete test cases. + * stl.cgs, stw.cgs, stxl.cgs, stxw.cgs: Likewise. + * ldl.cgs, ldq.cgs, ldub.cgs, lduw.cgs, ldw.cgs: Likewise. + * ldxb.cgs, ldxl.cgs, ldxq.cgs, ldxub.cgs: Likewise. + * ldxuw.cgs, ldxw.cgs, nsb.cgs, trapa.cgs: Likewise. + + * fcmpeqd.cgs, fcmpeqs.cgs, fcmpgtd.cgs: Complete test cases. + * fcmpgts.cgs, fdivd.cgs, fdivs.cgs, fmovd.cgs: Likewise. + * fmovdq.cgs, fmovqd.cgs, fmovls.cgs, fmovs.cgs: Likewise. + * fmovsl.cgs: Likewise. + +2000-12-11 Ben Elliston <bje@redhat.com> + + * fabss.cgs, fabsd.cgs, fadds.cgs, faddd.cgs: Complete test cases. + * getcfg.cgs, getcon.cgs, gettr.cgs, icbi.cgs: Likewise. + * prefi.cgs, pta.cgs, ptabs.cgs, ptb.cgs: Likewise. + * putcon.cgs, putcfg.cgs, rte.cgs: Likewise. + + * add.cgs, addi.cgs, addl.cgs, addil.cgs: Complete test cases. + * addl.cgs, addzl.cgs, alloco.cgs, and.cgs, andc.cgs: Likewise. + * andi.cgs, beq.cgs, beqi.cgs, bge.cgs, bgeu.cgs: Likewise. + * bgt.cgs, bgtu.cgs, blink.cgs, bne.cgs, bnei.cgs: Likewise. + * brk.cgs, byterev.cgs, cmpeq.cgs, cmpgt.cgs: Likewise. + * cmpgtu.cgs, cmveq.cgs, cmvne.cgs: Likewise. + +2000-12-07 Ben Elliston <bje@redhat.com> + + * mextr1.cgs, mextr2.cgs, mextr3.cgs: Complete test cases. + * mextr4.cgs, mextr5.cgs, mextr6.cgs, mextr7.cgs: Likewise. + +2000-12-05 Ben Elliston <bje@redhat.com> + + * nop.cgs, ocbi.cgs, ocbp.cgs, ocbwb.cgs: Complete test cases. + * or.cgs, ori.cgs, xor.cgs, xori.cgs: Ditto. + * sleep.cgs, synci.cgs, synco.cgs: Ditto. + +2000-11-22 Ben Elliston <bje@redhat.com> + + * *.cgs: Include "media/testutils.inc", not "testutils.inc" as + generated test cases do. Miscellaneous fixes. + + * testutils.inc: New file. + * *.cgs: Generate test cases. diff --git a/sim/testsuite/sim/sh64/media/add.cgs b/sim/testsuite/sim/sh64/media/add.cgs new file mode 100644 index 00000000000..9778e8fd62c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/add.cgs @@ -0,0 +1,47 @@ +# sh testcase for add $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global add +init: + pta wrong, tr0 +add: + movi 10, r0 + movi 0, r1 + add r0, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +add0: + movi 1, r63 + add r63, r63, r1 + bnei r1, 0, tr0 + +add2: + movi 0, r0 + movi 10, r1 + add r0, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +add3: + movi 10, r1 + add r63, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +add4: + movi 10, r1 + add r1, r63, r3 + movi 10, r4 + bne r3, r4, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addi.cgs b/sim/testsuite/sim/sh64/media/addi.cgs new file mode 100644 index 00000000000..3d4b49f5995 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addi.cgs @@ -0,0 +1,37 @@ +# sh testcase for addi $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +addi1: + movi 1, r0 + addi r0, 10, r0 + bnei r0, 11, tr0 + +addi2: + movi 10, r0 + addi r0, 1, r0 + bnei r0, 11, tr0 + +addi3: + movi 10, r0 + addi r0, -1, r0 + bnei r0, 9, tr0 + +addi4: + movi 20, r0 + addi r0, -2, r0 + bnei r0, 18, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addil.cgs b/sim/testsuite/sim/sh64/media/addil.cgs new file mode 100644 index 00000000000..5c92e2733a6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addil.cgs @@ -0,0 +1,49 @@ +# sh testcase for addi.l $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +addil0: + movi 1, r63 + addi.l r63, 0, r1 + bnei r1, 0, tr0 + +addil1: + movi 10, r0 + addi.l r0, 0, r3 + bnei r3, 10, tr0 + +addil2: + movi 0, r0 + addi.l r0, 10, r2 + bnei r2, 10, tr0 + +addil3: + addi.l r63, 10, r1 + bnei r1, 10, tr0 + +addil4: + movi 10, r0 + addi.l r0, 0, r1 + bnei r1, 10, tr0 + +addil5: + # Ensure top 32-bits are discarded when adding. + movi 10, r0 + shlli r0, 32, r0 + addi r0, 10, r0 + addi.l r0, 10, r2 + bnei r2, 20, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addl.cgs b/sim/testsuite/sim/sh64/media/addl.cgs new file mode 100644 index 00000000000..7f94b616206 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addl.cgs @@ -0,0 +1,61 @@ +# sh testcase for add.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global addl +init: + pta wrong, tr0 + +addl0: + movi 1, r63 + add.l r63, r63, r1 + bnei r1, 0, tr0 + +addl1: + movi 10, r0 + movi 0, r1 + add.l r0, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +addl2: + movi 0, r0 + movi 10, r1 + add.l r0, r1, r2 + movi 10, r3 + bne r2, r3, tr0 + +addl3: + movi 10, r0 + add.l r63, r0, r1 + movi 10, r2 + bne r1, r2, tr0 + +addl4: + movi 10, r0 + add.l r0, r63, r1 + movi 10, r2 + bne r1, r2, tr0 + +addl5: + # Ensure top 32-bits are discarded when adding. + movi 10, r0 + shlli r0, 32, r0 + addi r0, 10, r0 + movi 10, r1 + shlli r1, 32, r1 + addi r1, 10, r1 + add.l r0, r1, r2 + movi 20, r3 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addzl.cgs b/sim/testsuite/sim/sh64/media/addzl.cgs new file mode 100644 index 00000000000..b7917d377a6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addzl.cgs @@ -0,0 +1,39 @@ +# sh testcase for addz.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +addzl1: + movi 1, r0 + movi 2, r1 + addz.l r0, r1, r2 + bnei r2, 3, tr0 + +addzl2: + movi 1, r0 + shlli r0, 32, r0 + addi r0, 2, r0 + movi 1, r1 + shlli r1, 32, r1 + addi r1, 2, r1 + addz.l r0, r1, r2 + bnei r2, 4, tr0 + +addzl3: + movi 1, r0 + shlli r0, 31, r0 + addi r0, 2, r0 + movi 2, r1 + addz.l r0, r1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/alloco.cgs b/sim/testsuite/sim/sh64/media/alloco.cgs new file mode 100644 index 00000000000..5f27359c3b6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/alloco.cgs @@ -0,0 +1,10 @@ +# sh testcase for alloco $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + alloco r0, 32 + pass diff --git a/sim/testsuite/sim/sh64/media/and.cgs b/sim/testsuite/sim/sh64/media/and.cgs new file mode 100644 index 00000000000..c2d42339bcf --- /dev/null +++ b/sim/testsuite/sim/sh64/media/and.cgs @@ -0,0 +1,68 @@ +# sh testcase for and $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +and0: + # 0 and 0 is 0. + movi 0, r0 + movi 0, r1 + and r0, r1, r2 + bnei r2, 0, tr0 + +and1: + # 0 and 1 is 0. + movi 0, r0 + movi 1, r1 + and r0, r1, r2 + bnei r2, 0, tr0 + +and2: + # 1 and 0 is 0. + movi 1, r0 + movi 0, r1 + and r0, r1, r2 + bnei r2, 0, tr0 + +and3: + # 1 and 1 is 1. + movi 1, r0 + movi 1, r1 + and r0, r1, r2 + bnei r2, 1, tr0 + +and4: + movi 1, r0 + shlli r0, 63, r0 + movi 1, r1 + shlli r1, 63, r1 + and r0, r1, r2 + # Check it. + movi 1, r3 + shlli r3, 63, r3 + bne r2, r3, tr0 + +and5: + movi 1, r0 + shlli r0, 63, r0 + movi 1, r1 + shlli r1, 63, r1 + ori r1, 1, r1 + and r0, r1, r2 + # Check it. + movi 1, r3 + shlli r1, 63, r1 + bne r1, r2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/andc.cgs b/sim/testsuite/sim/sh64/media/andc.cgs new file mode 100644 index 00000000000..60b50ace465 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/andc.cgs @@ -0,0 +1,50 @@ +# sh testcase for andc $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +andc1: + # X . !X = 0. + movi 3, r0 + movi 3, r1 + andc r0, r1, r2 + bnei r2, 0, tr0 + +andc2: + # X . 0 = X. + movi 3, r0 + movi 0, r1 + andc r0, r1, r2 + bnei r2, 3, tr0 + +andc3: + # wide X . 0 = wide X. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + movi 0, r1 + andc r0, r1, r2 + bne r0, r2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/andi.cgs b/sim/testsuite/sim/sh64/media/andi.cgs new file mode 100644 index 00000000000..decfc2fc2ec --- /dev/null +++ b/sim/testsuite/sim/sh64/media/andi.cgs @@ -0,0 +1,46 @@ +# sh testcase for andi $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +andi0: + # 0 and 0 is 0. + movi 0, r0 + andi r0, 0, r2 + bnei r2, 0, tr0 + +and1: + # 0 and 1 is 0. + movi 0, r0 + andi r0, 1, r2 + bnei r2, 0, tr0 + +and2: + # 1 and 0 is 0. + movi 1, r0 + andi r0, 0, r2 + bnei r2, 0, tr0 + +and3: + # 1 and 1 is 1. + movi 1, r0 + andi r0, 1, r2 + bnei r2, 1, tr0 + +and4: + movi 15, r0 + andi r0, 3, r2 + bnei r2, 3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/beq.cgs b/sim/testsuite/sim/sh64/media/beq.cgs new file mode 100644 index 00000000000..6f96ffdf00f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/beq.cgs @@ -0,0 +1,52 @@ +# sh testcase for beq$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global beq +init: + # Load up the branch target registers. + pta beq2, tr0 + pta beq3, tr1 + pta wrong, tr2 + +beq1: + # Compare r0 with itself. + # Always true, so branch likely. + movi 1, r0 + beq/l r0, r0, tr0 + # We should branch over this. + fail + +beq2: + # Ensure high order bits are compared, too. + movi 1, r0 + shlli r0, 35, r0 + addi r0, 10, r0 + movi 1, r1 + shlli r1, 35, r1 + addi r1, 10, r1 + beq r0, r1, tr1 + # We should branch over this, too. + fail + +beq3: + movi 1, r0 + shlli r0, 35, r0 + addi r0, 10, r0 + movi 2, r1 + shlli r1, 35, r1 + addi r1, 9, r1 + # Unlikely we'll branch! + beq/u r0, r1, tr2 + # We should proceed to pass here. + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/beqi.cgs b/sim/testsuite/sim/sh64/media/beqi.cgs new file mode 100644 index 00000000000..c2b4ea8acf5 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/beqi.cgs @@ -0,0 +1,40 @@ +# sh testcase for beqi$likely $rm, $imm6, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global beqi +init: + # Load up the branch target registers. + pta beqi2, tr0 + pta beqi3, tr1 + pta wrong, tr2 + +beqi1: + # Always true, so branch likely. + movi 1, r0 + beqi/l r0, 1, tr0 + # We should branch over this. + fail + +beqi2: + movi 22, r3 + beqi r3, 22, tr1 + # We should branch over this. + fail + +beqi3: + movi 27, r7 + # We shouldn't branch here. + beqi/u r7, 23, tr2 + # We should proceed to pass here. + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bge.cgs b/sim/testsuite/sim/sh64/media/bge.cgs new file mode 100644 index 00000000000..832ff06ac21 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bge.cgs @@ -0,0 +1,40 @@ +# sh testcase for bge$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global bge +init: + pta bge2, tr0 + pta bge3, tr1 + pta wrong, tr2 + movi 0, r0 + +bge1: + # Compare r0 with itself. + bge/l r0, r0, tr0 + # We should branch here. + fail + +bge2: + movi 1, r1 + movi 1, r2 + bge r1, r2, tr1 + # We should branch here. + fail + +bge3: + movi -1, r1 + movi 1, r2 + bge r1, r2, tr2 + # We should not branch here. + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bgeu.cgs b/sim/testsuite/sim/sh64/media/bgeu.cgs new file mode 100644 index 00000000000..da469d0e4ae --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bgeu.cgs @@ -0,0 +1,47 @@ +# sh testcase for bgeu$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global bgeu +init: + movi 0, r0 + +bgeu1: + # Compare r0 with itself. + pta bgeu2, tr0 + bgeu/l r0, r0, tr0 + # We should branch here. + fail + +bgeu2: + movi 1, r1 + movi 1, r2 + pta bge3, tr0 + bgeu r1, r2, tr0 + # We should branch here. + fail + +bge3: + movi -1, r1 + movi 1, r2 + # We SHOULD branch here. + pta bge4, tr0 + bgeu r1, r2, tr0 + fail + +bge4: + movi 1, r1 + movi -1, r2 + # We should not branch here. + pta wrong, tr0 + bgeu r1, r2, tr0 +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bgt.cgs b/sim/testsuite/sim/sh64/media/bgt.cgs new file mode 100644 index 00000000000..8866635b818 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bgt.cgs @@ -0,0 +1,32 @@ +# sh testcase for bgt$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + +init: + pta wrong, tr0 + +bgt1: + movi 1, r0 + movi -1, r1 + bgt r1, r0, tr0 + +bgt2: + bgt r0, r0, tr0 + +bgt3: + pta okay, tr1 + movi -1, r0 + movi 1, r1 + bgt r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bgtu.cgs b/sim/testsuite/sim/sh64/media/bgtu.cgs new file mode 100644 index 00000000000..3cc02696e75 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bgtu.cgs @@ -0,0 +1,36 @@ +# sh testcase for bgtu$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + +init: + pta wrong, tr0 + +bgtu1: + movi 1, r0 + movi -1, r1 + pta bgt2, tr1 + bgtu r1, r0, tr1 + fail + +bgt2: + bgtu r0, r0, tr0 + +bgt3: + pta okay, tr1 + movi -1, r0 + movi 1, r1 + pta okay, tr1 + bgtu r0, r1, tr1 + fail + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/blink.cgs b/sim/testsuite/sim/sh64/media/blink.cgs new file mode 100644 index 00000000000..000d1f597f2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/blink.cgs @@ -0,0 +1,17 @@ +# sh testcase for blink $trb, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +blink: + pta target, tr0 + gettr tr0, r1 + ptabs r1, tr0 + blink tr0, r0 + fail + +target: + pass diff --git a/sim/testsuite/sim/sh64/media/bne.cgs b/sim/testsuite/sim/sh64/media/bne.cgs new file mode 100644 index 00000000000..f574147e3de --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bne.cgs @@ -0,0 +1,23 @@ +# sh testcase for bne$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 1, r0 + pta wrong, tr0 + pta okay, tr1 + +bne1: + bne r63, r63, tr0 +bne2: + bne r0, r63, tr1 +bad: + fail +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bnei.cgs b/sim/testsuite/sim/sh64/media/bnei.cgs new file mode 100644 index 00000000000..5ce33991c0d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bnei.cgs @@ -0,0 +1,23 @@ +# sh testcase for bnei$likely $rm, $imm6, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 1, r0 + pta wrong, tr0 + pta okay, tr1 + +bnei1: + bnei r63, 0, tr0 +bnei2: + bnei r0, 3, tr1 +bad: + fail +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/brk.cgs b/sim/testsuite/sim/sh64/media/brk.cgs new file mode 100644 index 00000000000..073641443ec --- /dev/null +++ b/sim/testsuite/sim/sh64/media/brk.cgs @@ -0,0 +1,11 @@ +# sh testcase for brk -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # brk will cause the sim to trap, so avoid it. + pass + brk diff --git a/sim/testsuite/sim/sh64/media/byterev.cgs b/sim/testsuite/sim/sh64/media/byterev.cgs new file mode 100644 index 00000000000..d97c3adb7b0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/byterev.cgs @@ -0,0 +1,67 @@ +# sh testcase for byterev $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + pta wrong, tr0 +init: + # Put a distinctive pattern in r0. + movi 10, r0 + shlli r0, 8, r0 + ori r0, 20, r0 + shlli r0, 8, r0 + ori r0, 30, r0 + shlli r0, 8, r0 + ori r0, 40, r0 + shlli r0, 8, r0 + ori r0, 50, r0 + shlli r0, 8, r0 + ori r0, 60, r0 + shlli r0, 8, r0 + ori r0, 70, r0 + shlli r0, 8, r0 + ori r0, 80, r0 + +byterev: + byterev r0, r1 + +check: + andi r1, 255, r2 + movi 10, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 20, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 30, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 40, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 50, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 60, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 70, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 80, r3 + bne r2, r3, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmpeq.cgs b/sim/testsuite/sim/sh64/media/cmpeq.cgs new file mode 100644 index 00000000000..78f51f4a65d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmpeq.cgs @@ -0,0 +1,42 @@ +# sh testcase for cmpeq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 2, r3 + movi 3, r4 + +cmpeq1: + cmpeq r2, r2, r7 + bne r7, r1, tr0 + +cmpeq2: + cmpeq r2, r3, r7 + bne r7, r1, tr0 + +cmpeq3: + cmpeq r2, r4, r7 + bne r7, r0, tr0 + +cmpeq4: + movi 1, r2 + shlli r2, 63, r2 + movi 1, r3 + shlli r3, 63, r3 + cmpeq r2, r3, r7 + bne r7, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmpgt.cgs b/sim/testsuite/sim/sh64/media/cmpgt.cgs new file mode 100644 index 00000000000..e4a971bd5ee --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmpgt.cgs @@ -0,0 +1,43 @@ +# sh testcase for cmpgt $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 2, r3 + movi 3, r4 + +cmpgt1: + cmpgt r2, r2, r7 + bne r7, r0, tr0 + +cmpgt2: + cmpgt r2, r3, r7 + bne r7, r0, tr0 + +cmpgt3: + cmpgt r4, r2, r7 + bne r7, r1, tr0 + +cmpgt4: + movi 1, r2 + shlli r2, 63, r2 + movi 1, r3 + shlli r3, 63, r3 + addi r3, 1, r3 + cmpgt r3, r2, r7 + bne r7, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmpgtu.cgs b/sim/testsuite/sim/sh64/media/cmpgtu.cgs new file mode 100644 index 00000000000..b896dfcb9fd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmpgtu.cgs @@ -0,0 +1,43 @@ +# sh testcase for cmpgtu $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 2, r3 + movi 3, r4 + +cmpgt1: + cmpgtu r2, r2, r7 + bne r7, r0, tr0 + +cmpgt2: + cmpgtu r2, r3, r7 + bne r7, r0, tr0 + +cmpgt3: + cmpgtu r4, r2, r7 + bne r7, r1, tr0 + +cmpgt4: + movi 1, r2 + shlli r2, 63, r2 + movi 1, r3 + shlli r3, 63, r3 + addi r3, 1, r3 + cmpgtu r3, r2, r7 + bne r7, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmveq.cgs b/sim/testsuite/sim/sh64/media/cmveq.cgs new file mode 100644 index 00000000000..0f49733de36 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmveq.cgs @@ -0,0 +1,32 @@ +# sh testcase for cmveq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 21, r3 + +cmveq: + # Zap r7. + movi 0, r7 + + cmveq r0, r2, r7 + bne r2, r7, tr0 + + cmveq r1, r3, r7 + # Make sure r7 is still equal to r2. + bne r2, r7, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmvne.cgs b/sim/testsuite/sim/sh64/media/cmvne.cgs new file mode 100644 index 00000000000..909179afc76 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmvne.cgs @@ -0,0 +1,32 @@ +# sh testcase for cmvne $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 21, r3 + +cmvne: + # Zap r7. + movi 0, r7 + + cmvne r1, r2, r7 + bne r2, r7, tr0 + + cmvne r0, r3, r7 + # Make sure r7 is still equal to r2. + bne r2, r7, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fabsd.cgs b/sim/testsuite/sim/sh64/media/fabsd.cgs new file mode 100644 index 00000000000..47060fcc44b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fabsd.cgs @@ -0,0 +1,39 @@ +# sh testcase for fabs.d $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fabs0: + # Ensure fabs(-1) = 1. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fmov.ls r1, fr7 + float.ld fr7, dr2 + fsub.d dr0, dr2, dr4 + fabs.d dr4, dr6 + fcmpeq.d dr6, dr2, r7 + bnei r7, 1, tr0 + +fabs1: + # Ensure fabs(1) = 1. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fmov.ls r1, fr7 + float.ld fr7, dr2 + fabs.d dr2, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fabss.cgs b/sim/testsuite/sim/sh64/media/fabss.cgs new file mode 100644 index 00000000000..dd9aec7e640 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fabss.cgs @@ -0,0 +1,39 @@ +# sh testcase for fabs.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fabs0: + # Ensure fabs(-1) = 1. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.ls r1, fr7 + float.ls fr7, fr1 + fsub.s fr0, fr1, fr2 + fabs.s fr2, fr3 + fcmpeq.s fr3, fr1, r7 + bnei r7, 1, tr0 + +fabs1: + # Ensure fabs(1) = 1. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.ls r1, fr7 + float.ls fr7, fr1 + fabs.s fr1, fr2 + fcmpeq.s fr1, fr2, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/faddd.cgs b/sim/testsuite/sim/sh64/media/faddd.cgs new file mode 100644 index 00000000000..096f8528946 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/faddd.cgs @@ -0,0 +1,33 @@ +# sh testcase for fadd.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 2, r0 + movi 3, r1 + +fadd0: + # Add 2 and 3. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fmov.ls r1, fr7 + float.ld fr7, dr2 + fadd.d dr0, dr2, dr4 + # Check to make sure we got 5. + movi 5, r2 + fmov.ls r2, fr7 + float.ld fr7, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fadds.cgs b/sim/testsuite/sim/sh64/media/fadds.cgs new file mode 100644 index 00000000000..fb93979c737 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fadds.cgs @@ -0,0 +1,34 @@ +# sh testcase for fadd.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fadds +init: + pta wrong, tr0 + movi 2, r0 + movi 3, r1 + +fadd0: + # Add 2 and 3. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.ls r1, fr7 + float.ls fr7, fr1 + fadd.s fr0, fr1, fr2 + # Check to make sure we got 5. + movi 5, r2 + fmov.ls r2, fr7 + float.ls fr7, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpeqd.cgs b/sim/testsuite/sim/sh64/media/fcmpeqd.cgs new file mode 100644 index 00000000000..c19356476f9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpeqd.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpeq.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpeq1: + movi 1, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpeq.d dr2, dr2, r7 + bnei r7, 1, tr0 + +fcmpeq2: + movi 1, r0 + fmov.ls r0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ld fr0, dr4 + float.ld fr1, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpeqs.cgs b/sim/testsuite/sim/sh64/media/fcmpeqs.cgs new file mode 100644 index 00000000000..216894d7d20 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpeqs.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpeq.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpeq1: + movi 1, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpeq2: + movi 1, r0 + fmov.ls r0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpged.cgs b/sim/testsuite/sim/sh64/media/fcmpged.cgs new file mode 100644 index 00000000000..52496cc6b14 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpged.cgs @@ -0,0 +1,46 @@ +# sh testcase for fcmpge.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpge1: # 2 = 2. + movi 2, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpge.d dr2, dr4, r7 + bnei r7, 1, tr0 + +fcmpge2: # 4 > 2. + movi 4, r0 + fmov.ls r0, fr0 + movi 2, r0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpge.d dr2, dr4, r7 + bnei r7, 1, tr0 + +fcmpge3: # 2 < 4. + movi 2, r0 + fmov.ls r0, fr0 + movi 4, r0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpge.d dr2, dr4, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpges.cgs b/sim/testsuite/sim/sh64/media/fcmpges.cgs new file mode 100644 index 00000000000..2dd0a35fd27 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpges.cgs @@ -0,0 +1,46 @@ +# sh testcase for fcmpge.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpge1: # 2 = 2. + movi 2, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpge.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpge2: # 3 > 2. + movi 3, r0 + fmov.ls r0, fr0 + movi 2, r0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpge.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpge3: # 2 < 3. + movi 2, r0 + fmov.ls r0, fr0 + movi 3, r0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpge.s fr2, fr3, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpgtd.cgs b/sim/testsuite/sim/sh64/media/fcmpgtd.cgs new file mode 100644 index 00000000000..aec952097de --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpgtd.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpgt.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpgt1: + movi 2, r0 + fmov.qd r0, dr0 + movi 1, r1 + fmov.qd r1, dr2 + float.qd dr0, dr4 + float.qd dr2, dr6 + fcmpgt.d dr4, dr6, r7 + bnei r7, 1, tr0 + +fcmpgt2: + movi 1, r0 + fmov.qd r0, dr0 + fmov.qd r0, dr2 + float.qd dr0, dr4 + float.qd dr2, dr6 + fcmpgt.d dr4, dr6, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpgts.cgs b/sim/testsuite/sim/sh64/media/fcmpgts.cgs new file mode 100644 index 00000000000..893bbcbf60b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpgts.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpgt.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpgt1: + movi 2, r0 + fmov.ls r0, fr0 + movi 1, r1 + fmov.ls r1, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpgt.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpgt2: + movi 1, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpgt.s fr2, fr3, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpund.cgs b/sim/testsuite/sim/sh64/media/fcmpund.cgs new file mode 100644 index 00000000000..b87fb8d9fb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpund.cgs @@ -0,0 +1,26 @@ +# sh testcase for fcmpun.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcmpund: + movi 0, r0 + movi 1, r1 + fmov.qd r0, dr0 + float.qd dr0, dr0 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fcmpun.d dr0, dr2, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpuns.cgs b/sim/testsuite/sim/sh64/media/fcmpuns.cgs new file mode 100644 index 00000000000..6c2ed96b4a3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpuns.cgs @@ -0,0 +1,26 @@ +# sh testcase for fcmpun.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcmpuns: + movi 0, r0 + movi 1, r1 + fmov.ls r0, fr0 + float.ls fr0, fr0 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fcmpun.s fr0, fr1, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcnvds.cgs b/sim/testsuite/sim/sh64/media/fcnvds.cgs new file mode 100644 index 00000000000..aa6c993fb85 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcnvds.cgs @@ -0,0 +1,27 @@ +# sh testcase for fcnv.ds $drgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcnvds: + movi 9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + fcnv.ds dr0, fr3 + movi 9, r0 + fmov.ls r0, fr4 + float.ls fr4, fr4 + fcmpeq.s fr3, fr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcnvsd.cgs b/sim/testsuite/sim/sh64/media/fcnvsd.cgs new file mode 100644 index 00000000000..6c2396fe815 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcnvsd.cgs @@ -0,0 +1,27 @@ +# sh testcase for fcnv.sd $frgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcnvsd: + movi 9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + fcnv.sd fr0, dr2 + movi 9, r0 + fmov.qd r0, dr4 + float.qd dr4, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fdivd.cgs b/sim/testsuite/sim/sh64/media/fdivd.cgs new file mode 100644 index 00000000000..62401c6b47e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fdivd.cgs @@ -0,0 +1,39 @@ +# sh testcase for fdiv.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fdivd1: + movi 1, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + movi 2, r1 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fdiv.d dr0, dr2, dr4 + +fdvid2: + movi 6, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + movi 2, r1 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fdiv.d dr0, dr2, dr4 + movi 3, r3 + fmov.qd r3, dr6 + float.qd dr6, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fdivs.cgs b/sim/testsuite/sim/sh64/media/fdivs.cgs new file mode 100644 index 00000000000..9b20f686b92 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fdivs.cgs @@ -0,0 +1,39 @@ +# sh testcase for fdiv.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fdivs1: + movi 1, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fdiv.s fr0, fr1, fr2 + +fdvis2: + movi 6, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fdiv.s fr0, fr1, fr2 + movi 3, r3 + fmov.ls r3, fr3 + float.ls fr3, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fgetscr.cgs b/sim/testsuite/sim/sh64/media/fgetscr.cgs new file mode 100644 index 00000000000..6aa227480ce --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fgetscr.cgs @@ -0,0 +1,14 @@ +# sh testcase for fgetscr $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fgetscr +fgetscr: + fgetscr fr0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fiprs.cgs b/sim/testsuite/sim/sh64/media/fiprs.cgs new file mode 100644 index 00000000000..fef62d11c7c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fiprs.cgs @@ -0,0 +1,42 @@ +# sh testcase for fipr.s $fvg, $fvh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + .macro _load val, fpreg + # This macro clobbers r0. + movi \val, r0 + fmov.ls r0, \fpreg + float.ls \fpreg, \fpreg + .endm + + start + + .global fiprs +init: + pta wrong, tr0 + + _load 1, fr0 + _load 2, fr1 + _load 3, fr2 + _load 4, fr3 + _load 1, fr4 + _load 2, fr5 + _load 3, fr6 + _load 4, fr7 + +fiprs: + fipr.s fv0, fv4, fr9 + +check: + _load 30, fr10 + fcmpeq.s fr9, fr10, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fldd.cgs b/sim/testsuite/sim/sh64/media/fldd.cgs new file mode 100644 index 00000000000..ded2a9fe8f5 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldd.cgs @@ -0,0 +1,13 @@ +# sh testcase for fld.d $rm, $disp10x8, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + fld.d r0, 0, dr0 + fld.d r0, 8, dr0 + fld.d r0, -8, dr0 + pass diff --git a/sim/testsuite/sim/sh64/media/fldp.cgs b/sim/testsuite/sim/sh64/media/fldp.cgs new file mode 100644 index 00000000000..8727110378c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldp.cgs @@ -0,0 +1,16 @@ +# sh testcase for fld.p $rm, $disp10x8, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 0x2800, r0 + +fldp: + fld.p r0, 0, fp0 + fld.p r0, 8, fp2 + fld.p r0, -8, fp4 + pass diff --git a/sim/testsuite/sim/sh64/media/flds.cgs b/sim/testsuite/sim/sh64/media/flds.cgs new file mode 100644 index 00000000000..75d5e961e26 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/flds.cgs @@ -0,0 +1,13 @@ +# sh testcase for fld.s $rm, $disp10x4, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + fld.s r0, 0, fr0 + fld.s r0, 4, fr0 + fld.s r0, -4, fr0 + pass diff --git a/sim/testsuite/sim/sh64/media/fldxd.cgs b/sim/testsuite/sim/sh64/media/fldxd.cgs new file mode 100644 index 00000000000..63cb56bb06f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldxd.cgs @@ -0,0 +1,16 @@ +# sh testcase for fldx.d $rm, $rn, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + movi 0, r1 + fldx.d r0, r1, dr0 + movi 8, r1 + fldx.d r0, r1, dr0 + movi -8, r1 + fldx.d r0, r1, dr0 + pass diff --git a/sim/testsuite/sim/sh64/media/fldxp.cgs b/sim/testsuite/sim/sh64/media/fldxp.cgs new file mode 100644 index 00000000000..3d929c6fef8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldxp.cgs @@ -0,0 +1,22 @@ +# sh testcase for fldx.p $rm, $rn, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 0x2800, r0 + +fldxp: + movi 0, r1 + fldx.p r0, r1, fp0 + + movi 8, r1 + fldx.p r0, r1, fp2 + + movi -8, r1 + fldx.p r0, r1, fp4 + + pass diff --git a/sim/testsuite/sim/sh64/media/fldxs.cgs b/sim/testsuite/sim/sh64/media/fldxs.cgs new file mode 100644 index 00000000000..10feb3e54a9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldxs.cgs @@ -0,0 +1,16 @@ +# sh testcase for fldx.s $rm, $rn, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + movi 0, r1 + fldx.s r0, r1, fr0 + movi 4, r1 + fldx.s r0, r1, fr0 + movi -4, r1 + fldx.s r0, r1, fr0 + pass diff --git a/sim/testsuite/sim/sh64/media/floatld.cgs b/sim/testsuite/sim/sh64/media/floatld.cgs new file mode 100644 index 00000000000..31f6111061b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatld.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.ld $frgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.ls r0, fr0 + float.ld fr0, dr0 + pass diff --git a/sim/testsuite/sim/sh64/media/floatls.cgs b/sim/testsuite/sim/sh64/media/floatls.cgs new file mode 100644 index 00000000000..4c8fb992798 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatls.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.ls $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + pass diff --git a/sim/testsuite/sim/sh64/media/floatqd.cgs b/sim/testsuite/sim/sh64/media/floatqd.cgs new file mode 100644 index 00000000000..ea5ddd9e49a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatqd.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.qd $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.qd r0, dr0 + float.qd dr0, dr2 + pass diff --git a/sim/testsuite/sim/sh64/media/floatqs.cgs b/sim/testsuite/sim/sh64/media/floatqs.cgs new file mode 100644 index 00000000000..fcf35e29548 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatqs.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.qs $drgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.qd r0, dr0 + float.qs dr0, fr1 + pass diff --git a/sim/testsuite/sim/sh64/media/fmacs.cgs b/sim/testsuite/sim/sh64/media/fmacs.cgs new file mode 100644 index 00000000000..62219c5fafd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmacs.cgs @@ -0,0 +1,39 @@ +# sh testcase for fmac.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fmacs: + movi 2, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + + movi 3, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + + movi 4, r2 + fmov.ls r2, fr2 + float.ls fr2, fr2 + + fmac.s fr0, fr1, fr2 + + movi 10, r3 + fmov.ls r3, fr3 + float.ls fr3, fr3 + + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovd.cgs b/sim/testsuite/sim/sh64/media/fmovd.cgs new file mode 100644 index 00000000000..03c05ad1776 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovd.cgs @@ -0,0 +1,24 @@ +# sh testcase for fmov.d $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmovd: + movi 4, r0 + fmov.qd r0, dr0 + float.qd dr0, dr2 + fmov.d dr2, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovdq.cgs b/sim/testsuite/sim/sh64/media/fmovdq.cgs new file mode 100644 index 00000000000..ff5c3fe9302 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovdq.cgs @@ -0,0 +1,23 @@ +# sh testcase for fmov.dq $drgh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fmovdq: + movi 4, r0 + fmov.qd r0, dr0 + fmov.dq dr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovls.cgs b/sim/testsuite/sim/sh64/media/fmovls.cgs new file mode 100644 index 00000000000..850ec33d160 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovls.cgs @@ -0,0 +1,26 @@ +# sh testcase for fmov.ls $rm, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +fmovls0: + movi 0, r0 + fmov.ls r0, fr0 + +fmovls1: + movi 1, r1 + fmov.ls r1, fr1 + +upper: + movi 1, r2 + shlli r2, 63, r2 + ori r2, 3, r2 + # Bit 63 should be ignored. + fmov.ls r2, fr2 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fmovqd.cgs b/sim/testsuite/sim/sh64/media/fmovqd.cgs new file mode 100644 index 00000000000..64eac72b3df --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovqd.cgs @@ -0,0 +1,22 @@ +# sh testcase for fmov.qd $rm, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmovdq: + movi 4, r0 + fmov.qd r0, dr0 + fmov.dq dr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovs.cgs b/sim/testsuite/sim/sh64/media/fmovs.cgs new file mode 100644 index 00000000000..f126aa5a41c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovs.cgs @@ -0,0 +1,24 @@ +# sh testcase for fmov.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmovs: + movi 8, r0 + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.s fr0, fr1 + fcmpeq.s fr0, fr1, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovsl.cgs b/sim/testsuite/sim/sh64/media/fmovsl.cgs new file mode 100644 index 00000000000..7dfdab1d145 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovsl.cgs @@ -0,0 +1,21 @@ +# sh testcase for fmov.sl $frgh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +fmovsl: + pta wrong, tr0 + movi 9, r0 + fmov.ls r0, fr0 + fmov.sl fr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmuld.cgs b/sim/testsuite/sim/sh64/media/fmuld.cgs new file mode 100644 index 00000000000..2ad67cdc532 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmuld.cgs @@ -0,0 +1,30 @@ +# sh testcase for fmul.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmuld1: + movi 2, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + movi 3, r1 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fmul.d dr0, dr2, dr4 + movi 6, r2 + fmov.qd r2, dr6 + float.qd dr6, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmuls.cgs b/sim/testsuite/sim/sh64/media/fmuls.cgs new file mode 100644 index 00000000000..4b8875f0c59 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmuls.cgs @@ -0,0 +1,31 @@ +# sh testcase for fmul.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fmuls1: + movi 2, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + movi 3, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fmul.s fr0, fr1, fr2 + movi 6, r2 + fmov.ls r2, fr3 + float.ls fr3, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fnegd.cgs b/sim/testsuite/sim/sh64/media/fnegd.cgs new file mode 100644 index 00000000000..67b381345b6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fnegd.cgs @@ -0,0 +1,35 @@ +# sh testcase for fneg.d $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fnegd0: + # Ensure fnegd(0) = 0. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fneg.d dr0, dr2 + fcmpeq.d dr0, dr2, r7 + bnei r7, 1, tr0 + +fnegd1: + # Ensure fnegd(fnegd(1)) = 1. + fmov.ls r1, fr7 + float.ld fr7, dr0 + fneg.d dr0, dr2 + fneg.d dr2, dr4 + fcmpeq.d dr0, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fnegs.cgs b/sim/testsuite/sim/sh64/media/fnegs.cgs new file mode 100644 index 00000000000..9ad625a1f1f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fnegs.cgs @@ -0,0 +1,35 @@ +# sh testcase for fneg.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fnegs0: + # Ensure fnegs(0) = 0. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fneg.s fr0, fr1 + fcmpeq.s fr0, fr1, r7 + bnei r7, 1, tr0 + +fnegs1: + # Ensure fnegs(fnegs(1)) = 1. + fmov.ls r1, fr7 + float.ls fr7, fr0 + fneg.s fr0, fr1 + fneg.s fr1, fr2 + fcmpeq.s fr0, fr2, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fputscr.cgs b/sim/testsuite/sim/sh64/media/fputscr.cgs new file mode 100644 index 00000000000..28d2e7230ee --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fputscr.cgs @@ -0,0 +1,14 @@ +# sh testcase for fputscr $frgh -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fputscr +fputscr: + fputscr fr0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fsqrtd.cgs b/sim/testsuite/sim/sh64/media/fsqrtd.cgs new file mode 100644 index 00000000000..ae6120002e0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsqrtd.cgs @@ -0,0 +1,27 @@ +# sh testcase for fsqrt.d $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 9, r0 + fmov.ls r0, fr7 + float.ld fr7, dr0 + movi 3, r1 + fmov.ls r1, fr7 + float.ld fr7, dr2 + +fsqrtd: + fsqrt.d dr0, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fsqrts.cgs b/sim/testsuite/sim/sh64/media/fsqrts.cgs new file mode 100644 index 00000000000..f1183933159 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsqrts.cgs @@ -0,0 +1,27 @@ +# sh testcase for fsqrt.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 9, r0 + fmov.ls r0, fr7 + float.ls fr7, fr0 + movi 3, r1 + fmov.ls r1, fr7 + float.ls fr7, fr2 + +fsqrts: + fsqrt.s fr0, fr1 + fcmpeq.s fr1, fr2, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fstd.cgs b/sim/testsuite/sim/sh64/media/fstd.cgs new file mode 100644 index 00000000000..16ab5b6672c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstd.cgs @@ -0,0 +1,34 @@ +# sh testcase for fst.d $rm, $disp10x8, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstd +fstd: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + # Set target address. + movi 0x2800, r1 + fmov.qd r0, dr0 + + fst.d r1, 0, dr0 + fst.d r1, 8, dr0 + fst.d r1, -8, dr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fstp.cgs b/sim/testsuite/sim/sh64/media/fstp.cgs new file mode 100644 index 00000000000..e0c396ac59a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstp.cgs @@ -0,0 +1,14 @@ +# sh testcase for fst.p $rm, $disp10x8, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstp +fstp: + fst.p r0, 0, fp0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fsts.cgs b/sim/testsuite/sim/sh64/media/fsts.cgs new file mode 100644 index 00000000000..fb692cf274c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsts.cgs @@ -0,0 +1,34 @@ +# sh testcase for fst.s $rm, $disp10x4, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fsts +fsts: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + # Set target address. + movi 0x2800, r1 + fmov.ls r0, fr0 + + fst.s r1, 0, fr0 + fst.s r1, 4, fr0 + fst.s r1, -4, fr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fstxd.cgs b/sim/testsuite/sim/sh64/media/fstxd.cgs new file mode 100644 index 00000000000..10f6c1436b5 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstxd.cgs @@ -0,0 +1,31 @@ +# sh testcase for fstx.d $rm, $rn, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstxd +fstxd: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + fmov.qd r0, dr0 + movi 0x2800, r1 + movi -8, r2 + fstx.d r1, r2, dr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fstxp.cgs b/sim/testsuite/sim/sh64/media/fstxp.cgs new file mode 100644 index 00000000000..1829f58eb25 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstxp.cgs @@ -0,0 +1,14 @@ +# sh testcase for fstx.p $rm, $rn, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstxp +fstxp: + fstx.p r0, r0, fp0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fstxs.cgs b/sim/testsuite/sim/sh64/media/fstxs.cgs new file mode 100644 index 00000000000..0b4ff96dba9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstxs.cgs @@ -0,0 +1,30 @@ +# sh testcase for fstx.s $rm, $rn, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + .global fstxs +fstxs: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + fmov.ls r0, fr0 + movi 0x2800, r1 + movi -8, r2 + fstx.s r1, r2, fr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fsubd.cgs b/sim/testsuite/sim/sh64/media/fsubd.cgs new file mode 100644 index 00000000000..93dc421b01f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsubd.cgs @@ -0,0 +1,36 @@ +# sh testcase for fsub.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fsubd +init: + pta wrong, tr0 + +fsubd: + movi 9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + + movi 3, r0 + fmov.qd r0, dr2 + float.qd dr2, dr2 + + fsub.d dr0, dr2, dr4 + + movi 6, r0 + fmov.qd r0, dr6 + float.qd dr6, dr6 + + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fsubs.cgs b/sim/testsuite/sim/sh64/media/fsubs.cgs new file mode 100644 index 00000000000..b009f094054 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsubs.cgs @@ -0,0 +1,36 @@ +# sh testcase for fsub.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fsubs +init: + pta wrong, tr0 + +fsubs: + movi 9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + + movi 3, r0 + fmov.ls r0, fr1 + float.ls fr1, fr1 + + fsub.s fr0, fr1, fr2 + + movi 6, r0 + fmov.ls r0, fr3 + float.ls fr3, fr3 + + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcdl.cgs b/sim/testsuite/sim/sh64/media/ftrcdl.cgs new file mode 100644 index 00000000000..3aafb83dca3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcdl.cgs @@ -0,0 +1,26 @@ +# sh testcase for ftrc.dl $drgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ftrcdl +init: + pta wrong, tr0 + +ftrcdl: + movi -9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + ftrc.dl dr0, fr0 + fmov.sl fr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcdq.cgs b/sim/testsuite/sim/sh64/media/ftrcdq.cgs new file mode 100644 index 00000000000..6cd63fb029e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcdq.cgs @@ -0,0 +1,24 @@ +# sh testcase for ftrc.dq $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +ftrcdq: + movi -9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + ftrc.dq dr0, dr2 + fmov.dq dr2, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcsl.cgs b/sim/testsuite/sim/sh64/media/ftrcsl.cgs new file mode 100644 index 00000000000..9fd7faebd1a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcsl.cgs @@ -0,0 +1,26 @@ +# sh testcase for ftrc.sl $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ftrcsl +init: + pta wrong, tr0 + +ftrcsl: + movi -9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + ftrc.sl fr0, fr1 + fmov.sl fr1, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcsq.cgs b/sim/testsuite/sim/sh64/media/ftrcsq.cgs new file mode 100644 index 00000000000..8f19d595e10 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcsq.cgs @@ -0,0 +1,25 @@ +# sh testcase for ftrc.sq $frgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +ftrcsq: + movi -9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + ftrc.sq fr0, dr2 + fmov.dq dr2, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrvs.cgs b/sim/testsuite/sim/sh64/media/ftrvs.cgs new file mode 100644 index 00000000000..be7a75ad885 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrvs.cgs @@ -0,0 +1,67 @@ +# sh testcase for ftrv.s $mtrxg, $fvh, $fvf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + .macro _load val, fpreg + # This macro clobbers r0. + movi \val, r0 + fmov.ls r0, \fpreg + float.ls \fpreg, \fpreg + .endm + + start + +init: + pta wrong, tr0 + + _load 1, fr0 + _load 2, fr4 + _load 3, fr8 + _load 4, fr12 + _load 5, fr1 + _load 6, fr5 + _load 7, fr9 + _load 8, fr13 + _load 9, fr2 + _load 10, fr6 + _load 11, fr10 + _load 12, fr14 + _load 13, fr3 + _load 14, fr7 + _load 15, fr11 + _load 16, fr15 + + _load 1, fr16 + _load 2, fr17 + _load 3, fr18 + _load 4, fr19 + +ftrvs: + ftrv.s mtrx0, fv16, fv20 + +check: + _load 30, fr0 + _load 70, fr1 + _load 110, fr2 + _load 150, fr3 + + fcmpeq.s fr0, fr20, r0 + bnei r0, 1, tr0 + + fcmpeq.s fr1, fr21, r0 + bnei r0, 1, tr0 + + fcmpeq.s fr2, fr22, r0 + bnei r0, 1, tr0 + + fcmpeq.s fr3, fr23, r0 + bnei r0, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/getcfg.cgs b/sim/testsuite/sim/sh64/media/getcfg.cgs new file mode 100644 index 00000000000..d151739846e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/getcfg.cgs @@ -0,0 +1,10 @@ +# sh testcase for getcfg $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + getcfg r0, 0, r0 + pass diff --git a/sim/testsuite/sim/sh64/media/getcon.cgs b/sim/testsuite/sim/sh64/media/getcon.cgs new file mode 100644 index 00000000000..8eeb43cd5b0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/getcon.cgs @@ -0,0 +1,29 @@ +# sh testcase for getcon $crk, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +getcon1: + movi 22, r0 + putcon r0, cr0 + getcon cr0, r1 + bne r0, r1, tr0 + +getcon2: + movi 12, r0 + shlli r0, 35, r0 + putcon r0, cr20 + getcon cr20, r20 + bne r0, r20, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/gettr.cgs b/sim/testsuite/sim/sh64/media/gettr.cgs new file mode 100644 index 00000000000..8840a361bb0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/gettr.cgs @@ -0,0 +1,48 @@ +# sh testcase for gettr $trb, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + # tr0 is reserved. + # don't use it anywhere else in this test. + pta wrong, tr0 + +gettr1: + # Put garbage in r1, r2. + movi 20, r1 + movi 30, r2 + + pta foo, tr1 + pta foo, tr2 + +check1: + gettr tr1, r1 + gettr tr2, r2 + bne r1, r2, tr0 + +gettr2: + # Put garbage in r3, r4. + movi 21, r3 + movi 42, r4 + +check2: + pta foo, tr1 + gettr tr1, r2 + ptabs r2, tr2 + gettr tr2, r3 + ptabs r3, tr3 + gettr tr3, r4 + bne r2, r4, tr0 + +okay: + pass + +wrong: + fail + +foo: + nop diff --git a/sim/testsuite/sim/sh64/media/icbi.cgs b/sim/testsuite/sim/sh64/media/icbi.cgs new file mode 100644 index 00000000000..9ba18452ef6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/icbi.cgs @@ -0,0 +1,10 @@ +# sh testcase for icbi $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + icbi r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/ldb.cgs b/sim/testsuite/sim/sh64/media/ldb.cgs new file mode 100644 index 00000000000..fad1e6e15ee --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldb.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.b $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldb1: + ld.b r3, 0, r0 +ldb2: + ld.b r3, -1, r0 +ldb3: + ld.b r3, 1, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldhil.cgs b/sim/testsuite/sim/sh64/media/ldhil.cgs new file mode 100644 index 00000000000..4323985ea49 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldhil.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldhi.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldhil +ldhil: + ldhi.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldhiq.cgs b/sim/testsuite/sim/sh64/media/ldhiq.cgs new file mode 100644 index 00000000000..c34a952bba7 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldhiq.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldhi.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldhiq +ldhiq: + ldhi.q r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldl.cgs b/sim/testsuite/sim/sh64/media/ldl.cgs new file mode 100644 index 00000000000..b8b8725dee1 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldl.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.l $rm, $disp10x4, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldl1: + ld.l r3, 0, r0 +ldl2: + ld.l r3, -4, r0 +ldl3: + ld.l r3, 4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldlol.cgs b/sim/testsuite/sim/sh64/media/ldlol.cgs new file mode 100644 index 00000000000..8204f40ebf4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldlol.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldlo.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldlol +ldlol: + ldlo.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldloq.cgs b/sim/testsuite/sim/sh64/media/ldloq.cgs new file mode 100644 index 00000000000..0cf128e2013 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldloq.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldlo.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldloq +ldloq: + ldlo.q r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldq.cgs b/sim/testsuite/sim/sh64/media/ldq.cgs new file mode 100644 index 00000000000..cacc076bb90 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldq.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.q $rm, $disp10x8, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldl1: + ld.q r3, 0, r0 +ldl2: + ld.q r3, -8, r0 +ldl3: + ld.q r3, 8, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldub.cgs b/sim/testsuite/sim/sh64/media/ldub.cgs new file mode 100644 index 00000000000..825ce642e31 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldub.cgs @@ -0,0 +1,22 @@ +# sh testcase for ld.ub $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi 20, r3 + shlli r3, 8, r3 + +ldub1: + ld.ub r3, 0, r0 +ldub2: + ld.ub r3, -1, r0 +ldub3: + ld.ub r3, 1, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/lduw.cgs b/sim/testsuite/sim/sh64/media/lduw.cgs new file mode 100644 index 00000000000..a329802e22b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/lduw.cgs @@ -0,0 +1,22 @@ +# sh testcase for ld.uw $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi 20, r3 + shlli r3, 8, r3 + +lduw1: + ld.uw r3, 0, r0 +lduw2: + ld.uw r3, -2, r0 +lduw3: + ld.uw r3, 2, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldw.cgs b/sim/testsuite/sim/sh64/media/ldw.cgs new file mode 100644 index 00000000000..d39405515a9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldw.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.w $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldw1: + ld.w r3, 0, r0 +ldw2: + ld.w r3, -2, r0 +ldw3: + ld.w r3, 2, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxb.cgs b/sim/testsuite/sim/sh64/media/ldxb.cgs new file mode 100644 index 00000000000..36038df8da4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxb.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxb1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.b r3, r4, r0 + +ldxb2: + movi 20, r3 + shlli r3, 8, r3 + movi 1, r4 + ldx.b r3, r4, r0 + +ldxb3: + movi 20, r3 + shlli r3, 8, r3 + movi -1, r4 + ldx.b r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxl.cgs b/sim/testsuite/sim/sh64/media/ldxl.cgs new file mode 100644 index 00000000000..0596e9f325b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxl.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxl1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.l r3, r4, r0 + +ldxl2: + movi 20, r3 + shlli r3, 8, r3 + movi 4, r4 + ldx.l r3, r4, r0 + +ldxl3: + movi 20, r3 + shlli r3, 8, r3 + movi -4, r4 + ldx.l r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxq.cgs b/sim/testsuite/sim/sh64/media/ldxq.cgs new file mode 100644 index 00000000000..1247f220562 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxq.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxq1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.q r3, r4, r0 + +ldxq2: + movi 20, r3 + shlli r3, 8, r3 + movi 8, r4 + ldx.q r3, r4, r0 + +ldxq3: + movi 20, r3 + shlli r3, 8, r3 + movi -8, r4 + ldx.q r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxub.cgs b/sim/testsuite/sim/sh64/media/ldxub.cgs new file mode 100644 index 00000000000..e863a3bfccf --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxub.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxub1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.ub r3, r4, r0 + +ldxub2: + movi 20, r3 + shlli r3, 8, r3 + movi 1, r4 + ldx.ub r3, r4, r0 + +ldxub3: + movi 20, r3 + shlli r3, 8, r3 + movi -1, r4 + ldx.ub r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxuw.cgs b/sim/testsuite/sim/sh64/media/ldxuw.cgs new file mode 100644 index 00000000000..282812db895 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxuw.cgs @@ -0,0 +1,29 @@ +# sh testcase for ldx.uw $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +ldxuw1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.uw r3, r4, r0 + +ldxuw2: + movi 20, r3 + shlli r3, 8, r3 + movi 2, r4 + ldx.uw r3, r4, r0 + +ldxuw3: + movi 20, r3 + shlli r3, 8, r3 + movi -2, r4 + ldx.uw r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxw.cgs b/sim/testsuite/sim/sh64/media/ldxw.cgs new file mode 100644 index 00000000000..d377fef6177 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxw.cgs @@ -0,0 +1,29 @@ +# sh testcase for ldx.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +ldxw1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.w r3, r4, r0 + +ldxw2: + movi 20, r3 + shlli r3, 8, r3 + movi 2, r4 + ldx.w r3, r4, r0 + +ldxw3: + movi 20, r3 + shlli r3, 8, r3 + movi -2, r4 + ldx.w r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/mabsl.cgs b/sim/testsuite/sim/sh64/media/mabsl.cgs new file mode 100644 index 00000000000..a8af663ea12 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mabsl.cgs @@ -0,0 +1,39 @@ +# sh testcase for mabs.l $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mabsl +init: + pta wrong, tr0 + +mabsl1: + # Pack { 1 3 } into R0. + _packl 1, 3, r0 + + mabs.l r0, r1 + + # Test for { 1 3 } in R0. + _packl 1, 3, r2 + bne r0, r2, tr0 + +mabsl2: + # Pack { -1, -1 } into R0. + _packl 1, 1, r0 + + # Set the left sign bit. + movi 1, r1 + shlli r1, 63, r1 + or r0, r1, r0 + + mabs.l r0, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mabsw.cgs b/sim/testsuite/sim/sh64/media/mabsw.cgs new file mode 100644 index 00000000000..f4e980a19c6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mabsw.cgs @@ -0,0 +1,38 @@ +# sh testcase for mabs.w $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +mabsw1: + # Pack { 1 3 5 7 } into R0. + _packw 1, 3, 5, 7, r0 + + mabs.l r0, r1 + + # Test for { 1 3 5 7 } in R0. + _packw 1, 3, 5, 7, r2 + bne r0, r2, tr0 + +mabsw2: + # Pack { -1, -1, -1, -1 } into R0. + _packw 1, 1, 1, 1, r0 + + # Set the left sign bit + movi 1, r1 + shlli r1, 63, r1 + or r0, r1, r0 + + mabs.w r0, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/maddl.cgs b/sim/testsuite/sim/sh64/media/maddl.cgs new file mode 100644 index 00000000000..4bdf5463866 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddl.cgs @@ -0,0 +1,29 @@ +# sh testcase for madd.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +maddl: + # Load { 1 2 } into r0. + _packl 1, 2, r0 + # Load { 3 4 } into r1. + _packl 3, 4, r1 + + # Add slices to produce { 4 6 }. + madd.l r0, r1, r2 + + _packl 4, 6, r3 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/maddsl.cgs b/sim/testsuite/sim/sh64/media/maddsl.cgs new file mode 100644 index 00000000000..3977275dc89 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddsl.cgs @@ -0,0 +1,14 @@ +# sh testcase for madds.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global maddsl +maddsl: + madds.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/maddsub.cgs b/sim/testsuite/sim/sh64/media/maddsub.cgs new file mode 100644 index 00000000000..a55f927a3e1 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddsub.cgs @@ -0,0 +1,14 @@ +# sh testcase for madds.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global maddsub +maddsub: + madds.ub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/maddsw.cgs b/sim/testsuite/sim/sh64/media/maddsw.cgs new file mode 100644 index 00000000000..45a774ed2fc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddsw.cgs @@ -0,0 +1,14 @@ +# sh testcase for madds.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global maddsw +maddsw: + madds.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/maddw.cgs b/sim/testsuite/sim/sh64/media/maddw.cgs new file mode 100644 index 00000000000..b220ef4aee6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddw.cgs @@ -0,0 +1,29 @@ +# sh testcase for madd.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +maddw: + # Load { 1 2 3 4 } into R0. + _packw 1, 2, 3, 4, r0 + + # Load { 3 4 5 6 } into R1. + _packw 3, 4, 5, 6, r1 + + # Add slices to produce { 4 6 8 10 }. + madd.w r0, r1, r2 + + _packw 4, 6, 8, 10, r3 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mcmpeqb.cgs b/sim/testsuite/sim/sh64/media/mcmpeqb.cgs new file mode 100644 index 00000000000..d7af6fa5f58 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpeqb.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpeq.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpeqb +mcmpeqb: + mcmpeq.b r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpeql.cgs b/sim/testsuite/sim/sh64/media/mcmpeql.cgs new file mode 100644 index 00000000000..2851e80fc5e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpeql.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpeq.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpeql +mcmpeql: + mcmpeq.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpeqw.cgs b/sim/testsuite/sim/sh64/media/mcmpeqw.cgs new file mode 100644 index 00000000000..085df84eeb9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpeqw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpeq.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpeqw +mcmpeqw: + mcmpeq.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtl.cgs b/sim/testsuite/sim/sh64/media/mcmpgtl.cgs new file mode 100644 index 00000000000..2ace0480506 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpgtl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpgt.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpgtl +mcmpgtl: + mcmpgt.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtub.cgs b/sim/testsuite/sim/sh64/media/mcmpgtub.cgs new file mode 100644 index 00000000000..540ce966092 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpgtub.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpgt.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpgtub +mcmpgtub: + mcmpgt.ub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtw.cgs b/sim/testsuite/sim/sh64/media/mcmpgtw.cgs new file mode 100644 index 00000000000..83274512d5e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpgtw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpgt.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpgtw +mcmpgtw: + mcmpgt.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmv.cgs b/sim/testsuite/sim/sh64/media/mcmv.cgs new file mode 100644 index 00000000000..c1f59aa4f88 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmv.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmv $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmv +mcmv: + mcmv r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcnvslw.cgs b/sim/testsuite/sim/sh64/media/mcnvslw.cgs new file mode 100644 index 00000000000..005108b7669 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcnvslw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcnvs.lw $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcnvslw +mcnvslw: + mcnvs.lw r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcnvswb.cgs b/sim/testsuite/sim/sh64/media/mcnvswb.cgs new file mode 100644 index 00000000000..0d25920f310 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcnvswb.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcnvs.wb $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcnvswb +mcnvswb: + mcnvs.wb r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcnvswub.cgs b/sim/testsuite/sim/sh64/media/mcnvswub.cgs new file mode 100644 index 00000000000..2fc74466dd0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcnvswub.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcnvs.wub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcnvswub +mcnvswub: + mcnvs.wub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mextr1.cgs b/sim/testsuite/sim/sh64/media/mextr1.cgs new file mode 100644 index 00000000000..b2cb3c3ff29 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr1.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr1 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr1: + mextr1 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x2535, r3 + shlli r3, 8, r3 + ori r3, 0x45, r3 + shlli r3, 8, r3 + ori r3, 0x55, r3 + shlli r3, 8, r3 + ori r3, 0x65, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr2.cgs b/sim/testsuite/sim/sh64/media/mextr2.cgs new file mode 100644 index 00000000000..cf136be8176 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr2.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr2 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr2: + mextr2 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x3545, r3 + shlli r3, 8, r3 + ori r3, 0x55, r3 + shlli r3, 8, r3 + ori r3, 0x65, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr3.cgs b/sim/testsuite/sim/sh64/media/mextr3.cgs new file mode 100644 index 00000000000..b8d60a447bc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr3.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr3 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr3: + mextr3 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x4555, r3 + shlli r3, 8, r3 + ori r3, 0x65, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr4.cgs b/sim/testsuite/sim/sh64/media/mextr4.cgs new file mode 100644 index 00000000000..e9ebff9be7b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr4.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr4 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr4: + mextr4 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x5565, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr5.cgs b/sim/testsuite/sim/sh64/media/mextr5.cgs new file mode 100644 index 00000000000..c61a0c89f52 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr5.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr5 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr5: + mextr5 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x6575, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + shlli r3, 8, r3 + ori r3, 0x50, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr6.cgs b/sim/testsuite/sim/sh64/media/mextr6.cgs new file mode 100644 index 00000000000..5c6c7f60c79 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr6.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr6 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr6: + mextr6 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x7585, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + shlli r3, 8, r3 + ori r3, 0x50, r3 + shlli r3, 8, r3 + ori r3, 0x60, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr7.cgs b/sim/testsuite/sim/sh64/media/mextr7.cgs new file mode 100644 index 00000000000..e05ec7f9ab3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr7.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr7 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr7: + mextr7 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x8510, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + shlli r3, 8, r3 + ori r3, 0x50, r3 + shlli r3, 8, r3 + ori r3, 0x60, r3 + shlli r3, 8, r3 + ori r3, 0x70, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mmacfxwl.cgs b/sim/testsuite/sim/sh64/media/mmacfxwl.cgs new file mode 100644 index 00000000000..dd2d9a41ae7 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmacfxwl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmacfx.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmacfxwl +mmacfxwl: + mmacfx.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs b/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs new file mode 100644 index 00000000000..ba634d207a3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmacnfx.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmacnfx_wl +mmacnfx_wl: + mmacnfx.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxl.cgs b/sim/testsuite/sim/sh64/media/mmulfxl.cgs new file mode 100644 index 00000000000..7d2d1a63268 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulfxl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulfx.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulfxl +mmulfxl: + mmulfx.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs b/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs new file mode 100644 index 00000000000..13fdcc71d0e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulfxrp.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulfxrpw +mmulfxrpw: + mmulfxrp.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxw.cgs b/sim/testsuite/sim/sh64/media/mmulfxw.cgs new file mode 100644 index 00000000000..e2a66a7c11d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulfxw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulfx.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulfxw +mmulfxw: + mmulfx.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulhiwl.cgs b/sim/testsuite/sim/sh64/media/mmulhiwl.cgs new file mode 100644 index 00000000000..1a41ac59286 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulhiwl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulhi.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulhiwl +mmulhiwl: + mmulhi.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmull.cgs b/sim/testsuite/sim/sh64/media/mmull.cgs new file mode 100644 index 00000000000..b3ed9df3f35 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmull.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmul.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmull +mmull: + mmul.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmullowl.cgs b/sim/testsuite/sim/sh64/media/mmullowl.cgs new file mode 100644 index 00000000000..b50ccfcb5dd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmullowl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmullo.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmullowl +mmullowl: + mmullo.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulsumwq.cgs b/sim/testsuite/sim/sh64/media/mmulsumwq.cgs new file mode 100644 index 00000000000..344710b0e98 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulsumwq.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulsum.wq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulsumwq +mmulsumwq: + mmulsum.wq r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulw.cgs b/sim/testsuite/sim/sh64/media/mmulw.cgs new file mode 100644 index 00000000000..675c620fadc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmul.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulw +mmulw: + mmul.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/movi.cgs b/sim/testsuite/sim/sh64/media/movi.cgs new file mode 100644 index 00000000000..a01bcae84df --- /dev/null +++ b/sim/testsuite/sim/sh64/media/movi.cgs @@ -0,0 +1,29 @@ +# sh testcase for movi $imm16, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +movi0: + movi 0, r0 + bnei r0, 0, tr0 +movi1: + movi 1, r0 + bnei r0, 1, tr0 +movi2: + movi 23, r0 + bnei r0, 23, tr0 +movn: + movi -1, r0 + addi r0, 1, r0 + bnei r0, 0, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mpermw.cgs b/sim/testsuite/sim/sh64/media/mpermw.cgs new file mode 100644 index 00000000000..3b6741e8107 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mpermw.cgs @@ -0,0 +1,51 @@ +# sh testcase for mperm.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 27, r1 + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + +mpermw: + mperm.w r0, r1, r2 + +check: + # Expect 0x7080506030401020. + movi 0x7080, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x10, r0 + shlli r0, 8, r0 + ori r0, 0x20, r0 + + bne r0, r2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/msadubq.cgs b/sim/testsuite/sim/sh64/media/msadubq.cgs new file mode 100644 index 00000000000..4361883b870 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msadubq.cgs @@ -0,0 +1,14 @@ +# sh testcase for msad.ubq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msadubq +msadubq: + msad.ubq r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshaldsl.cgs b/sim/testsuite/sim/sh64/media/mshaldsl.cgs new file mode 100644 index 00000000000..1dd86ec6bb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshaldsl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshalds.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshaldsl +mshaldsl: + mshalds.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshaldsw.cgs b/sim/testsuite/sim/sh64/media/mshaldsw.cgs new file mode 100644 index 00000000000..7ab6797e9a6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshaldsw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshalds.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshaldsw +mshaldsw: + mshalds.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshardl.cgs b/sim/testsuite/sim/sh64/media/mshardl.cgs new file mode 100644 index 00000000000..0dc102e337a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshardl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshard.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshardl +mshardl: + mshard.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshardsq.cgs b/sim/testsuite/sim/sh64/media/mshardsq.cgs new file mode 100644 index 00000000000..5f29afb8b1b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshardsq.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshards.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshardsq +mshardsq: + mshards.q r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshardw.cgs b/sim/testsuite/sim/sh64/media/mshardw.cgs new file mode 100644 index 00000000000..ecc7004febd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshardw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshard.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshardw +mshardw: + mshard.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshfhib.cgs b/sim/testsuite/sim/sh64/media/mshfhib.cgs new file mode 100644 index 00000000000..b7b245e79ae --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshfhib.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshfhi.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshfhib +mshfhib: + mshfhi.b r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshfhil.cgs b/sim/testsuite/sim/sh64/media/mshfhil.cgs new file mode 100644 index 00000000000..2fab7ae1fd9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshfhil.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshfhi.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshfhil +mshfhil: + mshfhi.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshfhiw.cgs b/sim/testsuite/sim/sh64/media/mshfhiw.cgs new file mode 100644 index 00000000000..03111413cf1 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshfhiw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshfhi.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshfhiw +mshfhiw: + mshfhi.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshflob.cgs b/sim/testsuite/sim/sh64/media/mshflob.cgs new file mode 100644 index 00000000000..400e81a0598 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshflob.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshflo.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshflob +mshflob: + mshflo.b r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshflol.cgs b/sim/testsuite/sim/sh64/media/mshflol.cgs new file mode 100644 index 00000000000..2fbdf894e60 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshflol.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshflo.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshflol +mshflol: + mshflo.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshflow.cgs b/sim/testsuite/sim/sh64/media/mshflow.cgs new file mode 100644 index 00000000000..542eb042c52 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshflow.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshflo.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshflow +mshflow: + mshflo.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlldl.cgs b/sim/testsuite/sim/sh64/media/mshlldl.cgs new file mode 100644 index 00000000000..2a17c33002e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlldl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlld.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlldl +mshlldl: + mshlld.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlldw.cgs b/sim/testsuite/sim/sh64/media/mshlldw.cgs new file mode 100644 index 00000000000..e4afe3d732a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlldw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlld.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlldw +mshlldw: + mshlld.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlrdl.cgs b/sim/testsuite/sim/sh64/media/mshlrdl.cgs new file mode 100644 index 00000000000..89e70772b7f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlrdl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlrd.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlrdl +mshlrdl: + mshlrd.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlrdw.cgs b/sim/testsuite/sim/sh64/media/mshlrdw.cgs new file mode 100644 index 00000000000..4cbf2807f9c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlrdw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlrd.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlrdw +mshlrdw: + mshlrd.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubl.cgs b/sim/testsuite/sim/sh64/media/msubl.cgs new file mode 100644 index 00000000000..87151fad728 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubl.cgs @@ -0,0 +1,14 @@ +# sh testcase for msub.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubl +msubl: + msub.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubsl.cgs b/sim/testsuite/sim/sh64/media/msubsl.cgs new file mode 100644 index 00000000000..014422ed8f3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubsl.cgs @@ -0,0 +1,14 @@ +# sh testcase for msubs.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubsl +msubsl: + msubs.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubsub.cgs b/sim/testsuite/sim/sh64/media/msubsub.cgs new file mode 100644 index 00000000000..c92c77ee72e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubsub.cgs @@ -0,0 +1,14 @@ +# sh testcase for msubs.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubsub +msubsub: + msubs.ub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubsw.cgs b/sim/testsuite/sim/sh64/media/msubsw.cgs new file mode 100644 index 00000000000..83b76a1b4b3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubsw.cgs @@ -0,0 +1,14 @@ +# sh testcase for msubs.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubsw +msubsw: + msubs.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubw.cgs b/sim/testsuite/sim/sh64/media/msubw.cgs new file mode 100644 index 00000000000..9d5e639f240 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubw.cgs @@ -0,0 +1,14 @@ +# sh testcase for msub.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubw +msubw: + msub.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mulsl.cgs b/sim/testsuite/sim/sh64/media/mulsl.cgs new file mode 100644 index 00000000000..d65c80cadf2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mulsl.cgs @@ -0,0 +1,54 @@ +# sh testcase for muls.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mulsl +init: + pta wrong, tr0 + +mulsl1: + movi 0, r0 + muls.l r0, r0, r1 + bnei r1, 0, tr0 + +mulsl2: + movi 0, r0 + movi 1, r1 + muls.l r0, r1, r2 + bnei r2, 0, tr0 + +mulsl3: + movi 1, r0 + movi 0, r1 + muls.l r0, r1, r2 + bnei r2, 0, tr0 + +mulsl4: + movi 1, r0 + movi 1, r1 + muls.l r0, r1, r2 + bnei r2, 1, tr0 + +mulsl5: + movi 2, r0 + movi 9, r1 + muls.l r0, r1, r2 + bnei r2, 18, tr0 + +mulsl6: + movi 2, r0 + movi -9, r1 + muls.l r0, r1, r2 + bnei r2, -18, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/mulul.cgs b/sim/testsuite/sim/sh64/media/mulul.cgs new file mode 100644 index 00000000000..b795cf79ec0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mulul.cgs @@ -0,0 +1,54 @@ +# sh testcase for mulu.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mulul +init: + pta wrong, tr0 + +mulul1: + movi 0, r0 + mulu.l r0, r0, r1 + bnei r1, 0, tr0 + +mulul2: + movi 0, r0 + movi 1, r1 + mulu.l r0, r1, r2 + bnei r2, 0, tr0 + +mulul3: + movi 1, r0 + movi 0, r1 + mulu.l r0, r1, r2 + bnei r2, 0, tr0 + +mulul4: + movi 1, r0 + movi 1, r1 + mulu.l r0, r1, r2 + bnei r2, 1, tr0 + +mulul5: + movi 2, r0 + movi 9, r1 + mulu.l r0, r1, r2 + bnei r2, 18, tr0 + +mulul6: + movi 2, r0 + movi -9, r1 + mulu.l r0, r1, r2 + beqi r2, -18, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/nop.cgs b/sim/testsuite/sim/sh64/media/nop.cgs new file mode 100644 index 00000000000..a0e57530542 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/nop.cgs @@ -0,0 +1,10 @@ +# sh testcase for nop -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + nop + pass diff --git a/sim/testsuite/sim/sh64/media/nsb.cgs b/sim/testsuite/sim/sh64/media/nsb.cgs new file mode 100644 index 00000000000..8b3cffef4a8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/nsb.cgs @@ -0,0 +1,66 @@ +# sh testcase for nsb $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +nsb0: + movi 0, r0 + nsb r0, r1 +check0: + movi 63, r4 + bne r1, r4, tr0 + +nsb1: + # set up a loop target reg. + pta again1, tr1 + # r4 holds the loop count. + movi 62, r4 + movi 1, r0 +again1: + nsb r0, r1 + bne r1, r4, tr0 + # okay? go around again. + shlli r0, 1, r0 + addi r4, -1, r4 + bnei r4, 0, tr1 + +nsb2: + # set up a loop target reg. + pta again2, tr1 + # r4 holds the loop count. + movi 63, r4 + movi -1, r0 +again2: + nsb r0, r1 + bne r1, r4, tr0 + # okay? go around again. + shlli r0, 1, r0 + addi r4, -1, r4 + bnei r4, 0, tr1 + +nsb3: + movi 1, r0 + shlli r0, 63, r0 + nsb r0, r1 +check3: + movi 0, r4 + bne r1, r4, tr0 + +nsb4: + movi 7, r0 + shlli r0, 61, r0 + nsb r0, r1 +check4: + movi 2, r4 + bne r1, r4, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ocbi.cgs b/sim/testsuite/sim/sh64/media/ocbi.cgs new file mode 100644 index 00000000000..b210216e3db --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ocbi.cgs @@ -0,0 +1,10 @@ +# sh testcase for ocbi $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + ocbi r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/ocbp.cgs b/sim/testsuite/sim/sh64/media/ocbp.cgs new file mode 100644 index 00000000000..9158c6f4518 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ocbp.cgs @@ -0,0 +1,10 @@ +# sh testcase for ocbp $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + ocbp r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/ocbwb.cgs b/sim/testsuite/sim/sh64/media/ocbwb.cgs new file mode 100644 index 00000000000..6addabcf461 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ocbwb.cgs @@ -0,0 +1,10 @@ +# sh testcase for ocbwb $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + ocbwb r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/or.cgs b/sim/testsuite/sim/sh64/media/or.cgs new file mode 100644 index 00000000000..e06759225ba --- /dev/null +++ b/sim/testsuite/sim/sh64/media/or.cgs @@ -0,0 +1,44 @@ +# sh testcase for or $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +or1: + movi 0, r0 + or r0, r0, r1 + bnei r1, 0, tr0 + +or2: + movi 0, r0 + movi 1, r1 + or r0, r1, r2 + bnei r2, 1, tr0 + +or3: + movi 1, r0 + movi 0, r1 + or r0, r1, r2 + bnei r2, 1, tr0 + +or4: + movi 1, r0 + or r0, r0, r1 + bnei r1, 1, tr0 + +or5: + movi 1, r0 + shlli r0, 63, r0 + movi 1, r1 + or r0, r1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ori.cgs b/sim/testsuite/sim/sh64/media/ori.cgs new file mode 100644 index 00000000000..7b2554227da --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ori.cgs @@ -0,0 +1,41 @@ +# sh testcase for ori $rm, $imm10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +or1: + movi 0, r0 + ori r0, 0, r1 + bnei r1, 0, tr0 + +or2: + movi 0, r0 + ori r0, 1, r2 + bnei r2, 1, tr0 + +or3: + movi 1, r0 + ori r0, 0, r2 + bnei r2, 1, tr0 + +or4: + movi 1, r0 + ori r0, 1, r1 + bnei r1, 1, tr0 + +or5: + movi 1, r0 + shlli r0, 63, r0 + ori r0, 1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/prefi.cgs b/sim/testsuite/sim/sh64/media/prefi.cgs new file mode 100644 index 00000000000..68d7bfe29a4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/prefi.cgs @@ -0,0 +1,10 @@ +# sh testcase for prefi $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + prefi r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/pta.cgs b/sim/testsuite/sim/sh64/media/pta.cgs new file mode 100644 index 00000000000..9f6484a8d4c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/pta.cgs @@ -0,0 +1,26 @@ +# sh testcase for pta$likely $disp16, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +pta0: + pta foo, tr0 +pta1: + pta/l bar, tr1 +pta2: + pta/u baz, tr2 + movi 0, r0 + bnei r0, 1, tr2 + fail + +foo: +bar: +baz: + pass + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/media/ptabs.cgs b/sim/testsuite/sim/sh64/media/ptabs.cgs new file mode 100644 index 00000000000..0c01f838eb8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ptabs.cgs @@ -0,0 +1,25 @@ +# sh testcase for ptabs$likely $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ptabs +ptabs: + movi 16, r0 + shlli r0, 8, r0 + # Add one to stay in SHmedia mode. + addi r0, 29, r0 + ptabs r0, tr0 + + # Now jump. + beqi r63, 0, tr0 + +wrong: + fail + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ptb.cgs b/sim/testsuite/sim/sh64/media/ptb.cgs new file mode 100644 index 00000000000..129d6260439 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ptb.cgs @@ -0,0 +1,29 @@ +# sh testcase for ptb$likely $disp16, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +ptb0: + ptb foo, tr0 +ptb: + ptb/l bar, tr1 +ptb2: + ptb/u baz, tr2 + movi 0, r0 + bnei r0, 1, tr2 + fail + +.mode SHcompact + +foo: +bar: +baz: + trapa #253 + trapa #254 + trapa #254 + trapa #254 + trapa #254 diff --git a/sim/testsuite/sim/sh64/media/ptrel.cgs b/sim/testsuite/sim/sh64/media/ptrel.cgs new file mode 100644 index 00000000000..7e5f19b1b9c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ptrel.cgs @@ -0,0 +1,22 @@ +# sh testcase for ptrel$likely $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # Add one to stay in SHmedia mode. + movi 53, r0 + ptrel r0, tr0 + movi 0, r0 + # Always branch. + bnei r0, 1, tr0 + fail + fail + fail + fail + fail + pass + fail + fail diff --git a/sim/testsuite/sim/sh64/media/putcfg.cgs b/sim/testsuite/sim/sh64/media/putcfg.cgs new file mode 100644 index 00000000000..85385754a48 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/putcfg.cgs @@ -0,0 +1,10 @@ +# sh testcase for putcfg $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + putcfg r0, 0, r0 + pass diff --git a/sim/testsuite/sim/sh64/media/putcon.cgs b/sim/testsuite/sim/sh64/media/putcon.cgs new file mode 100644 index 00000000000..39dfc036280 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/putcon.cgs @@ -0,0 +1,30 @@ +# sh testcase for putcon $rm, $crj -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +putcon1: + movi 22, r0 + putcon r0, cr0 + getcon cr0, r1 + bne r0, r1, tr0 + +putcon2: + movi 12, r0 + shlli r0, 35, r0 + putcon r0, cr20 + getcon cr20, r20 + bne r0, r20, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/rte.cgs b/sim/testsuite/sim/sh64/media/rte.cgs new file mode 100644 index 00000000000..e80f08541cc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/rte.cgs @@ -0,0 +1,11 @@ +# sh testcase for rte -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # Unimplemented. + rte + pass diff --git a/sim/testsuite/sim/sh64/media/shard.cgs b/sim/testsuite/sim/sh64/media/shard.cgs new file mode 100644 index 00000000000..029e52902a2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shard.cgs @@ -0,0 +1,30 @@ +# sh testcase for shard $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shard1: + movi 128, r0 + movi 3, r1 + shard r0, r1, r2 + bnei r2, 16, tr0 + +shard2: + movi -4, r0 + movi 2, r1 + shard r0, r1, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shardl.cgs b/sim/testsuite/sim/sh64/media/shardl.cgs new file mode 100644 index 00000000000..d9acaa54f69 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shardl.cgs @@ -0,0 +1,45 @@ +# sh testcase for shard.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shardl1: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + movi 1, r1 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + movi 20, r1 + shard.l r0, r1, r0 + bnei r0, 5, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shari.cgs b/sim/testsuite/sim/sh64/media/shari.cgs new file mode 100644 index 00000000000..3d3a650fb0c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shari.cgs @@ -0,0 +1,28 @@ +# sh testcase for shari $rm, $imm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shari1: + movi 128, r0 + shari r0, 3, r2 + bnei r2, 16, tr0 + +shari2: + movi -4, r0 + shari r0, 2, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/sharil.cgs b/sim/testsuite/sim/sh64/media/sharil.cgs new file mode 100644 index 00000000000..be946e0c84d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sharil.cgs @@ -0,0 +1,45 @@ +# sh testcase for shari.l $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +sharil1: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + movi 1, r1 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 20, r0 + bnei r0, 5, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/shlld.cgs b/sim/testsuite/sim/sh64/media/shlld.cgs new file mode 100644 index 00000000000..05d2da4cd68 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlld.cgs @@ -0,0 +1,36 @@ +# sh testcase for shlld $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlld1: + movi 1, r0 + movi 5, r1 + shlld r0, r1, r2 + movi 32, r7 + bne r2, r7, tr0 + +shlld2: + movi 2, r1 + shlld r2, r1, r3 + movi 128, r7 + bne r3, r7, tr0 + +shlld3: + movi 32, r1 + shlld r0, r1, r7 + shlld r7, r1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlldl.cgs b/sim/testsuite/sim/sh64/media/shlldl.cgs new file mode 100644 index 00000000000..3d37f53a76b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlldl.cgs @@ -0,0 +1,34 @@ +# sh testcase for shlld.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +shlldl1: + movi 1, r0 + shlli r0, 32, r0 + ori r0, 1, r0 + movi 1, r1 + shlli r1, 7, r1 + ori r1, 3, r1 + + shlld.l r0, r1, r2 + +check1: + bnei r2, 8, tr0 + +shlldl2: + movi 1, r0 + movi 31, r1 + shlld.l r0, r1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlli.cgs b/sim/testsuite/sim/sh64/media/shlli.cgs new file mode 100644 index 00000000000..9ab331c0930 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlli.cgs @@ -0,0 +1,30 @@ +# sh testcase for shlli $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlli: + movi 1, r0 + shlli r0, 3, r0 + bnei r0, 8, tr0 + +shlli2: + shlli r0, 3, r0 + +shlli3: + # Shift all bits out of sight. + shlli r0, 63, r0 + bnei r0, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shllil.cgs b/sim/testsuite/sim/sh64/media/shllil.cgs new file mode 100644 index 00000000000..347acd64084 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shllil.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlli.l $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global shllil +shllil: + shlli.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/shlrd.cgs b/sim/testsuite/sim/sh64/media/shlrd.cgs new file mode 100644 index 00000000000..56f10bf1c0e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlrd.cgs @@ -0,0 +1,30 @@ +# sh testcase for shlrd $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlrd1: + movi 128, r0 + movi 3, r1 + shlrd r0, r1, r2 + bnei r2, 16, tr0 + +shlrd2: + movi -4, r0 + movi 2, r1 + shlrd r0, r1, r2 + addi r2, 1, r2 + beqi r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlrdl.cgs b/sim/testsuite/sim/sh64/media/shlrdl.cgs new file mode 100644 index 00000000000..32b20c0a3cd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlrdl.cgs @@ -0,0 +1,37 @@ +# sh testcase for shlrd.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlrdl1: + movi 1, r0 + shlli r0, 32, r0 + ori r0, 8, r0 + movi 1, r1 + shlli r1, 7, r1 + ori r1, 3, r1 + + shlrd.l r0, r1, r2 + +check1: + bnei r2, 1, tr0 + +shlrdl2: + movi 1, r0 + shlli r0, 31, r0 + movi 31, r1 + shlld.l r0, r1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlri.cgs b/sim/testsuite/sim/sh64/media/shlri.cgs new file mode 100644 index 00000000000..488cac9aec8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlri.cgs @@ -0,0 +1,28 @@ +# sh testcase for shlri $rm, $imm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlri1: + movi 128, r0 + shlri r0, 3, r2 + bnei r2, 16, tr0 + +shlri2: + movi -4, r0 + shlri r0, 2, r2 + addi r2, 1, r2 + beqi r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlril.cgs b/sim/testsuite/sim/sh64/media/shlril.cgs new file mode 100644 index 00000000000..bb1b2a6eaf0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlril.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlri.l $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global shlril +shlril: + shlri.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/shori.cgs b/sim/testsuite/sim/sh64/media/shori.cgs new file mode 100644 index 00000000000..5f02b7d2c5f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shori.cgs @@ -0,0 +1,35 @@ +# sh testcase for shori $imm16, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shori1: + movi 1, r0 + shori 7, r0 + # check it. + andi r0, 15, r7 + bnei r7, 7, tr0 + shlri r0, 16, r0 + bnei r0, 1, tr0 + +shori2: + # Test for zero extension bug reported by + # Alexandre Oliva <aoliva@redhat.com>. + movi 0, r0 + shori 65535, r0 + # check it. + movi 0xffff, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/sleep.cgs b/sim/testsuite/sim/sh64/media/sleep.cgs new file mode 100644 index 00000000000..b4c35ee8f96 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sleep.cgs @@ -0,0 +1,10 @@ +# sh testcase for sleep -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + sleep + pass diff --git a/sim/testsuite/sim/sh64/media/stb.cgs b/sim/testsuite/sim/sh64/media/stb.cgs new file mode 100644 index 00000000000..09de47b14a9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stb.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.b $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stb1: + st.b r0, 0, r7 + +stb2: + st.b r0, 1, r7 + +stb3: + st.b r0, -1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/sthil.cgs b/sim/testsuite/sim/sh64/media/sthil.cgs new file mode 100644 index 00000000000..cfee28444f8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sthil.cgs @@ -0,0 +1,55 @@ +# sh testcase for sthi.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + + movi 40, r0 + shlli r0, 8, r0 + + movi 0x1020, r1 + shlli r1, 8, r1 + addi r1, 0x30, r1 + shlli r1, 8, r1 + addi r1, 0x40, r1 + shlli r1, 8, r1 + addi r1, 0x50, r1 + shlli r1, 8, r1 + addi r1, 0x60, r1 + shlli r1, 8, r1 + addi r1, 0x70, r1 + shlli r1, 8, r1 + addi r1, 0x80, r1 + +sthil1: + sthi.l r0, 0, r1 + +sthil2: + sthi.l r0, 1, r1 + +sthil3: + sthi.l r0, 2, r1 + +sthil4: + sthi.l r0, 3, r1 + +sthil5: + sthi.l r0, -1, r1 + +sthil6: + sthi.l r0, -2, r1 + +sthil7: + sthi.l r0, -3, r1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/sthiq.cgs b/sim/testsuite/sim/sh64/media/sthiq.cgs new file mode 100644 index 00000000000..6310d43e5ad --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sthiq.cgs @@ -0,0 +1,79 @@ +# sh testcase for sthi.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + + movi 40, r0 + shlli r0, 8, r0 + + movi 0x1020, r1 + shlli r1, 8, r1 + addi r1, 0x30, r1 + shlli r1, 8, r1 + addi r1, 0x40, r1 + shlli r1, 8, r1 + addi r1, 0x50, r1 + shlli r1, 8, r1 + addi r1, 0x60, r1 + shlli r1, 8, r1 + addi r1, 0x70, r1 + shlli r1, 8, r1 + addi r1, 0x80, r1 + +sthiq1: + sthi.q r0, 0, r1 + +sthiq2: + sthi.q r0, 1, r1 + +sthiq3: + sthi.q r0, 2, r1 + +sthiq4: + sthi.q r0, 3, r1 + +sthiq5: + sthi.q r0, 4, r1 + +sthiq6: + sthi.q r0, 5, r1 + +sthiq7: + sthi.q r0, 6, r1 + +sthiq8: + sthi.q r0, 7, r1 + +sthiq9: + sthi.q r0, -1, r1 + +sthiq10: + sthi.q r0, -2, r1 + +sthiq11: + sthi.q r0, -3, r1 + +sthiq12: + sthi.q r0, -4, r1 + +sthiq13: + sthi.q r0, -5, r1 + +sthiq14: + sthi.q r0, -6, r1 + +sthiq15: + sthi.q r0, -7, r1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/stl.cgs b/sim/testsuite/sim/sh64/media/stl.cgs new file mode 100644 index 00000000000..8737e354c5b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stl.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.l $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stl1: + st.l r0, 0, r7 + +stl2: + st.l r0, 4, r7 + +stl3: + st.l r0, -4, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stlol.cgs b/sim/testsuite/sim/sh64/media/stlol.cgs new file mode 100644 index 00000000000..f2d90552509 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stlol.cgs @@ -0,0 +1,14 @@ +# sh testcase for stlo.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global stlol +stlol: + stlo.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/stloq.cgs b/sim/testsuite/sim/sh64/media/stloq.cgs new file mode 100644 index 00000000000..35c84c255cc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stloq.cgs @@ -0,0 +1,14 @@ +# sh testcase for stlo.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global stloq +stloq: + stlo.q r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/stq.cgs b/sim/testsuite/sim/sh64/media/stq.cgs new file mode 100644 index 00000000000..e1af7956b84 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stq.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stq1: + st.q r0, 0, r7 + +stq2: + st.q r0, 8, r7 + +stq3: + st.q r0, -8, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stw.cgs b/sim/testsuite/sim/sh64/media/stw.cgs new file mode 100644 index 00000000000..2446aa62795 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stw.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stw1: + st.w r0, 0, r7 + +stw2: + st.w r0, 2, r7 + +stw3: + st.w r0, -2, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxb.cgs b/sim/testsuite/sim/sh64/media/stxb.cgs new file mode 100644 index 00000000000..8ab2ae31d23 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxb.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxb1: + movi 0, r1 + stx.b r0, r1, r7 + +stxb2: + movi 1, r1 + stx.b r0, r1, r7 + +stxb3: + movi -1, r1 + stx.b r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxl.cgs b/sim/testsuite/sim/sh64/media/stxl.cgs new file mode 100644 index 00000000000..8ed2e366ab3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxl.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxl1: + movi 0, r1 + stx.l r0, r1, r7 + +stxl2: + movi 4, r1 + stx.l r0, r1, r7 + +stxl3: + movi -4, r1 + stx.l r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxq.cgs b/sim/testsuite/sim/sh64/media/stxq.cgs new file mode 100644 index 00000000000..10759fd4414 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxq.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxq1: + movi 0, r1 + stx.q r0, r1, r7 + +stxq2: + movi 8, r1 + stx.q r0, r1, r7 + +stxq3: + movi -8, r1 + stx.q r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxw.cgs b/sim/testsuite/sim/sh64/media/stxw.cgs new file mode 100644 index 00000000000..d03981146a2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxw.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxw1: + movi 0, r1 + stx.w r0, r1, r7 + +stxw2: + movi 2, r1 + stx.w r0, r1, r7 + +stxw3: + movi -2, r1 + stx.w r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/sub.cgs b/sim/testsuite/sim/sh64/media/sub.cgs new file mode 100644 index 00000000000..e5e7530100b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sub.cgs @@ -0,0 +1,42 @@ +# sh testcase for sub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +sub1: + # 0 - 0 = 0. + sub r0, r0, r2 + bnei r2, 0, tr0 + +sub2: + # 1 - 0 = 1. + sub r1, r0, r2 + bnei r2, 1, tr0 + +sub3: + # 0 - 1 = -1. + sub r0, r1, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +sub4: + # 5 - 2 = 3. + movi 5, r0 + movi 2, r1 + sub r0, r1, r2 + bnei r2, 3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/subl.cgs b/sim/testsuite/sim/sh64/media/subl.cgs new file mode 100644 index 00000000000..98abe59f666 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/subl.cgs @@ -0,0 +1,38 @@ +# sh testcase for sub.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +subl1: + # Test that the top 32 bits are ignored. + movi 1, r0 + shlli r0, 32, r0 + ori r0, 7, r0 + + movi 1, r1 + shlli r1, 32, r1 + ori r1, 2, r1 + + sub.l r0, r1, r2 + bnei r2, 5, tr0 + +subl2: + # Test that 0 - 1 is sign extended. + movi 0, r0 + movi 1, r1 + sub.l r0, r1, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/swapq.cgs b/sim/testsuite/sim/sh64/media/swapq.cgs new file mode 100644 index 00000000000..6f168b1ff48 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/swapq.cgs @@ -0,0 +1,36 @@ +# sh testcase for swap.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 10, r0 + shlli r0, 8, r0 + ori r0, 20, r0 + shlli r0, 8, r0 + ori r0, 30, r0 + shlli r0, 8, r0 + ori r0, 40, r0 + shlli r0, 8, r0 + ori r0, 50, r0 + shlli r0, 8, r0 + ori r0, 60, r0 + shlli r0, 8, r0 + ori r0, 70, r0 + shlli r0, 8, r0 + ori r0, 80, r0 + + # Set up two address operands. + + movi 40, r1 + shlli r1, 8, r1 + movi 8, r2 + +swapq: + swap.q r1, r2, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/synci.cgs b/sim/testsuite/sim/sh64/media/synci.cgs new file mode 100644 index 00000000000..65e06213a50 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/synci.cgs @@ -0,0 +1,10 @@ +# sh testcase for synci -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + synci + pass diff --git a/sim/testsuite/sim/sh64/media/synco.cgs b/sim/testsuite/sim/sh64/media/synco.cgs new file mode 100644 index 00000000000..2db6df343d4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/synco.cgs @@ -0,0 +1,10 @@ +# sh testcase for synco -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + synco + pass diff --git a/sim/testsuite/sim/sh64/media/testutils.inc b/sim/testsuite/sim/sh64/media/testutils.inc new file mode 100644 index 00000000000..d3b383a1efb --- /dev/null +++ b/sim/testsuite/sim/sh64/media/testutils.inc @@ -0,0 +1,51 @@ +# Support macros for the assembly test cases. + + .macro start + .text + .global start +start: + .endm + + .macro pass + movi 253, r0 + trapa r0 + .endm + + .macro fail + movi 254, r0 + trapa r0 + .endm + + .macro _packb v1 v2 v3 v4 v5 v6 v7 v8 reg + movi \v1, \reg + shlli \reg, 8, \reg + addi \reg, \v2, \reg + shlli \reg, 8, \reg + addi \reg, \v3, \reg + shlli \reg, 8, \reg + addi \reg, \v4, \reg + shlli \reg, 8, \reg + addi \reg, \v5, \reg + shlli \reg, 8, \reg + addi \reg, \v6, \reg + shlli \reg, 8, \reg + addi \reg, \v7, \reg + shlli \reg, 8, \reg + addi \reg, \v8, \reg + .endm + + .macro _packw v1 v2 v3 v4 reg + movi \v1, \reg + shlli \reg, 16, \reg + addi \reg, \v2, \reg + shlli \reg, 16, \reg + addi \reg, \v3, \reg + shlli \reg, 16, \reg + addi \reg, \v4, \reg + .endm + + .macro _packl v1 v2 reg + movi \v1, \reg + shlli \reg, 32, \reg + addi \reg, \v2, \reg + .endm diff --git a/sim/testsuite/sim/sh64/media/trapa.cgs b/sim/testsuite/sim/sh64/media/trapa.cgs new file mode 100644 index 00000000000..c961bac73ba --- /dev/null +++ b/sim/testsuite/sim/sh64/media/trapa.cgs @@ -0,0 +1,11 @@ +# sh testcase for trapa $rm -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # This performs a trap to emit "pass". + movi 253, r0 + trapa r0 diff --git a/sim/testsuite/sim/sh64/media/xor.cgs b/sim/testsuite/sim/sh64/media/xor.cgs new file mode 100644 index 00000000000..80278f0a3e0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/xor.cgs @@ -0,0 +1,54 @@ +# sh testcase for xor $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +xor1: + # 0 xor 0 = 0. + movi 0, r0 + movi 0, r1 + xor r0, r1, r2 + bnei r2, 0, tr0 + +xor2: + # 0 xor 1 = 1. + movi 0, r0 + movi 1, r1 + xor r0, r1, r2 + bnei r2, 1, tr0 + +xor3: + # 1 xor 0 = 1. + movi 1, r0 + movi 0, r1 + xor r0, r1, r2 + bnei r2, 1, tr0 + +xor4: + # 1 xor 1 = 0. + movi 1, r0 + movi 1, r1 + xor r0, r1, r2 + bnei r2, 0, tr0 + +xor5: + movi 1, r0 + shlli r0, 63, r0 + ori r0, 1, r0 + movi 3, r1 + xor r0, r1, r2 + andi r2, 255, r2 + bnei r2, 2, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/xori.cgs b/sim/testsuite/sim/sh64/media/xori.cgs new file mode 100644 index 00000000000..0d4d96a779d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/xori.cgs @@ -0,0 +1,48 @@ +# sh testcase for xori $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +xori1: + # 0 xor 0 = 0. + movi 0, r0 + xori r0, 0, r2 + bnei r2, 0, tr0 + +xori2: + # 0 xor 1 = 1. + movi 0, r0 + xori r0, 1, r2 + bnei r2, 1, tr0 + +xori3: + # 1 xor 0 = 1. + movi 1, r0 + xori r0, 0, r2 + bnei r2, 1, tr0 + +xori4: + # 1 xor 1 = 0. + movi 1, r0 + xori r0, 1, r2 + bnei r2, 0, tr0 + +xori5: + movi 1, r0 + shlli r0, 63, r0 + ori r0, 1, r0 + xori r0, 3, r2 + andi r2, 255, r2 + bnei r2, 2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/misc/fr-dr.s b/sim/testsuite/sim/sh64/misc/fr-dr.s new file mode 100644 index 00000000000..52f0e136638 --- /dev/null +++ b/sim/testsuite/sim/sh64/misc/fr-dr.s @@ -0,0 +1,22 @@ +# sh testcase for floating point register shared state (see below). +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + +# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state). +# Hitachi SH-5 CPU volume 1, p. 15. + + .include "media/testutils.inc" + + start + + movi 42, r0 + fmov.ls r0, fr12 + # save this reg. + fmov.s fr12, fr14 + + movi 42, r0 + fmov.qd r0, dr12 + +okay: + pass |