diff options
author | Jason Molenda <jsm@bugshack.cygnus.com> | 2000-01-06 03:07:20 +0000 |
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committer | Jason Molenda <jsm@bugshack.cygnus.com> | 2000-01-06 03:07:20 +0000 |
commit | 1961aa2638e1c11c166de668e780a4385b724265 (patch) | |
tree | f6ee7ff39bd6a3525560cdf62b30748be2a6f33d /sim/testsuite | |
parent | 3cee212a702cfb7f44caebf7a6389e17771a3072 (diff) | |
download | gdb-1961aa2638e1c11c166de668e780a4385b724265.tar.gz |
import gdb-2000-01-05 snapshot
Diffstat (limited to 'sim/testsuite')
-rw-r--r-- | sim/testsuite/d10v-elf/ChangeLog | 12 | ||||
-rw-r--r-- | sim/testsuite/d10v-elf/Makefile.in | 23 | ||||
-rw-r--r-- | sim/testsuite/d10v-elf/t-macros.i | 73 |
3 files changed, 103 insertions, 5 deletions
diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog index de4a22cc46c..1d73e29f4ad 100644 --- a/sim/testsuite/d10v-elf/ChangeLog +++ b/sim/testsuite/d10v-elf/ChangeLog @@ -1,3 +1,15 @@ +Mon Jan 3 00:17:28 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s , + t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s , + t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s , + t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s , + t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s , + t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests. Check that an address + exception occures when a word/two-word load/store is not word + aligned. + * Makefile.in (TESTS): Update. + Fri Oct 29 18:36:34 1999 Andrew Cagney <cagney@b1.cygnus.com> * t-mvtc.s: Check that the user can not modify the DM bit in the diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in index b170f377d74..079f95d4c54 100644 --- a/sim/testsuite/d10v-elf/Makefile.in +++ b/sim/testsuite/d10v-elf/Makefile.in @@ -60,6 +60,29 @@ TESTS = \ t-sub2w.ok \ t-sub.ok \ t-subi.ok \ + t-ae-ld-d.ok \ + t-ae-ld-i.ok \ + t-ae-ld-id.ok \ + t-ae-ld-im.ok \ + t-ae-ld-ip.ok \ + t-ae-ld2w-d.ok \ + t-ae-ld2w-i.ok \ + t-ae-ld2w-id.ok \ + t-ae-ld2w-im.ok \ + t-ae-ld2w-ip.ok \ + t-ae-st-d.ok \ + t-ae-st-i.ok \ + t-ae-st-id.ok \ + t-ae-st-im.ok \ + t-ae-st-ip.ok \ + t-ae-st-is.ok \ + t-ae-st2w-d.ok \ + t-ae-st2w-i.ok \ + t-ae-st2w-id.ok \ + t-ae-st2w-im.ok \ + t-ae-st2w-ip.ok \ + t-ae-st2w-is.ok \ + t-mod-ld-pre.ok \ # AS_FOR_TARGET = `\ diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i index 2f54d1c0381..f424acfa57b 100644 --- a/sim/testsuite/d10v-elf/t-macros.i +++ b/sim/testsuite/d10v-elf/t-macros.i @@ -21,6 +21,20 @@ _start: .endm + .macro exit1 + ldi r4, 1 + ldi r0, 1 + trap 15 + .endm + + + .macro exit2 + ldi r4, 1 + ldi r0, 2 + trap 15 + .endm + + .macro load reg val ldi \reg, #\val .endm @@ -128,6 +142,53 @@ _start: .endm +;;; Blat our DMAP registers so that they point at on-chip imem + .macro point_dmap_at_imem + .text + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + .endm + +;;; Patch VEC so that it jumps back to code that checks PSW +;;; and then exits with success. + .macro check_interrupt vec psw src +;;; Patch the interrupt vector's AE entry with a jmp to success + .text + ldi r4, #1f + ldi r5, \vec + ;; + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + ;; + bra 9f + nop +;;; Code that gets patched into the interrupt vector + .data +1: ldi r1, 2f@word + jmp r1 +;;; Successfull trap jumps back to here + .text +;;; Verify the PSW +2: mvfc r2, cr0 + cmpeqi r2, #\psw + brf0t 3f + nop + exit1 +;;; Verify the original addr +3: mvfc r2, bpc + cmpeqi r2, #\src@word + brf0t 4f + exit2 +4: exit0 +;;; continue as normal +9: + .endm + + PSW_SM = 0x8000 PSW_01 = 0x4000 PSW_EA = 0x2000 @@ -159,12 +220,14 @@ _start: ;;; - VEC_RI = 0x3fc00 - VEC_BAE = 0x3fc04 - VEC_RIE = 0x3fc08 - VEC_AE = 0x3fc0c - VEC_TRAP = 0x3fc10 + VEC_RI = 0x3ff00 + VEC_BAE = 0x3ff04 + VEC_RIE = 0x3ff08 + VEC_AE = 0x3ff0c + VEC_TRAP = 0x3ff10 VEC_DBT = 0x3ff50 VEC_SDBT = 0x3fff4 VEC_DBI = 0x3ff58 VEC_EI = 0x3ff5c + + |