diff options
| author | Stan Shebs <shebs@apple.com> | 1999-04-16 01:33:56 +0000 |
|---|---|---|
| committer | Stan Shebs <shebs@apple.com> | 1999-04-16 01:33:56 +0000 |
| commit | 838ae13dc4ab603f1efdf1da653e2ca1b7b009e1 (patch) | |
| tree | 8d3c114b0ba9d2a1f0dcadd192ba2aaeeafe7175 /sim/testsuite | |
| download | gdb-838ae13dc4ab603f1efdf1da653e2ca1b7b009e1.tar.gz | |
Initial revision
Diffstat (limited to 'sim/testsuite')
314 files changed, 20754 insertions, 0 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog new file mode 100644 index 00000000000..f8634829394 --- /dev/null +++ b/sim/testsuite/ChangeLog @@ -0,0 +1,321 @@ +Fri Feb 5 12:41:11 1999 Doug Evans <devans@canuck.cygnus.com> + + * lib/sim-defs.exp (sim_run): Print simulator arguments log message. + +1999-01-05 Doug Evans <devans@casey.cygnus.com> + + * lib/sim-defs.exp (run_sim_test): New arg all_machs. + * sim/fr30/allinsn.exp: Update. + * sim/fr30/misc.exp: Update. + * sim/m32r/allinsn.exp: Update. + * sim/m32r/misc.exp: Update. + +Fri Dec 18 17:19:34 1998 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/ldres.cgs: New testcase. + * sim/fr30/copld.cgs: New testcase. + * sim/fr30/copst.cgs: New testcase. + * sim/fr30/copsv.cgs: New testcase. + * sim/fr30/nop.cgs: New testcase. + * sim/fr30/andccr.cgs: New testcase. + * sim/fr30/orccr.cgs: New testcase. + * sim/fr30/addsp.cgs: New testcase. + * sim/fr30/stilm.cgs: New testcase. + * sim/fr30/extsb.cgs: New testcase. + * sim/fr30/extub.cgs: New testcase. + * sim/fr30/extsh.cgs: New testcase. + * sim/fr30/extuh.cgs: New testcase. + * sim/fr30/enter.cgs: New testcase. + * sim/fr30/leave.cgs: New testcase. + * sim/fr30/xchb.cgs: New testcase. + * sim/fr30/dmovb.cgs: New testcase. + * sim/fr30/dmov.cgs: New testcase. + * sim/fr30/dmovh.cgs: New testcase. + +Thu Dec 17 17:18:43 1998 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros. + * sim/fr30/ret.cgs: Add tests fir ret:d. + * sim/fr30/inte.cgs: New testcase. + * sim/fr30/reti.cgs: New testcase. + * sim/fr30/bra.cgs: New testcase. + * sim/fr30/bno.cgs: New testcase. + * sim/fr30/beq.cgs: New testcase. + * sim/fr30/bne.cgs: New testcase. + * sim/fr30/bc.cgs: New testcase. + * sim/fr30/bnc.cgs: New testcase. + * sim/fr30/bn.cgs: New testcase. + * sim/fr30/bp.cgs: New testcase. + * sim/fr30/bv.cgs: New testcase. + * sim/fr30/bnv.cgs: New testcase. + * sim/fr30/blt.cgs: New testcase. + * sim/fr30/bge.cgs: New testcase. + * sim/fr30/ble.cgs: New testcase. + * sim/fr30/bgt.cgs: New testcase. + * sim/fr30/bls.cgs: New testcase. + * sim/fr30/bhi.cgs: New testcase. + +Tue Dec 15 17:47:13 1998 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/div.cgs (int): Add signed division scenario. + * sim/fr30/int.cgs (int): Complete testcase. + * sim/fr30/testutils.inc (_start): Initialize tbr. + (test_s_user,test_s_system,set_i,test_i): New macros. + +1998-12-14 Doug Evans <devans@casey.cygnus.com> + + * lib/sim-defs.exp (run_sim_test): New option xerror, for expected + errors. Translate \n sequences in expected output to newline char. + (slurp_options): Make parentheses optional. + (sim_run): Look for board_info sim,options. + * sim/fr30/hello.ms: Add trailing \n to expected output. + * sim/m32r/hello.ms: Ditto. + * sim/m32r/hw-trap.ms: Ditto. + + * sim/m32r/trap.cgs: Properly align trap2_handler. + + * sim/m32r/uread16.ms: New testcase. + * sim/m32r/uread32.ms: New testcase. + * sim/m32r/uwrite16.ms: New testcase. + * sim/m32r/uwrite32.ms: New testcase. + +1998-12-14 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/call.cgs: Test ret here as well. + * sim/fr30/ld.cgs: Remove bogus comment. + * sim/fr30/testutils.inc (save_rp,restore_rp): New macros. + * sim/fr30/div.ms: New testcase. + * sim/fr30/st.cgs: New testcase. + * sim/fr30/sth.cgs: New testcase. + * sim/fr30/stb.cgs: New testcase. + * sim/fr30/mov.cgs: New testcase. + * sim/fr30/jmp.cgs: New testcase. + * sim/fr30/ret.cgs: New testcase. + * sim/fr30/int.cgs: New testcase. + +Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/div0s.cgs: New testcase. + * sim/fr30/div0u.cgs: New testcase. + * sim/fr30/div1.cgs: New testcase. + * sim/fr30/div2.cgs: New testcase. + * sim/fr30/div3.cgs: New testcase. + * sim/fr30/div4s.cgs: New testcase. + * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros. + +Tue Dec 8 13:16:53 1998 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/testutils.inc (set_s_user): Correct Mask. + (set_s_system): Correct Mask. + * sim/fr30/ld.cgs (ld): Move previously failing test back + into place. + * sim/fr30/ldm0.cgs: New testcase. + * sim/fr30/ldm1.cgs: New testcase. + * sim/fr30/stm0.cgs: New testcase. + * sim/fr30/stm1.cgs: New testcase. + +Thu Dec 3 14:20:03 1998 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/ld.cgs: Implement more loads. + * sim/fr30/call.cgs: New testcase. + * sim/fr30/testutils.inc (testr_h_dr): New macro. + (set_s_user,set_s_system): New macros. + + * sim/fr30: New Directory. + +Wed Nov 18 10:50:19 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * common/bits-gen.c (main): Add BYTE_ORDER so that it matches + recent sim/common/sim-basics.h changes. + * common/Makefile.in: Update. + +Fri Oct 30 00:37:31 1998 Felix Lee <flee@cygnus.com> + + * lib/sim-defs.exp (sim_run): download target program to remote + host, if necessary. for unix-driven win32 testing. + +Tue Sep 15 14:56:22 1998 Doug Evans <devans@canuck.cygnus.com> + + * sim/m32r/testutils.inc (test_h_gr): Use mvaddr_h_gr. + * sim/m32r/rte.cgs: Test bbpc,bbpsw. + * sim/m32r/trap.cgs: Test bbpc,bbpsw. + +Fri Jul 24 09:40:34 1998 Doug Evans <devans@canuck.cygnus.com> + + * Makefile.in (clean,mostlyclean): Change leading spaces to a tab. + +Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com> + + * sim/m32r/hw-trap.ms: New testcase. + +Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com> + + * sim/m32r/addx.cgs: Add another test. + * sim/m32r/jmp.cgs: Add another test. + +Mon Jun 8 16:08:27 1998 Doug Evans <devans@canuck.cygnus.com> + + * sim/m32r/trap.cgs: Test trap 2. + +Mon Jun 1 18:54:22 1998 Frank Ch. Eigler <fche@cygnus.com> + + * lib/sim-defs.exp (sim_run): Add possible environment variable + list to simulator run. + +Thu May 28 14:59:46 1998 Jillian Ye <jillian@cygnus.com> + + * Makefile.in: Take RUNTEST out of FLAG_TO_PASS + so that make check can be invoked recursively. + +Thu May 14 11:48:35 1998 Doug Evans <devans@canuck.cygnus.com> + + * config/default.exp (CC,SIM): Delete. + + * lib/sim-defs.exp (sim_run): Fix handling of output redirection. + New arg prog_opts. All callers updated. + +Fri May 8 18:10:28 1998 Jillian Ye <jillian@cygnus.com> + + * Makefile.in: Made "check" the target of two + dependencies (test1, test2) so that test2 get a chance to + run even when test1 failed if "make -k check" is used. + +Fri May 8 14:41:28 1998 Doug Evans <devans@canuck.cygnus.com> + + * lib/sim-defs.exp (sim_version): Simplify. + (sim_run): Implement. + (run_sim_test): Use sim_run. + (sim_compile): New proc. + +Mon May 4 17:59:11 1998 Frank Ch. Eigler <fche@cygnus.com> + + * config/default.exp: Added C compiler settings. + +Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com> + + * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS. + +Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com> + + * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails, + try all machs. + + * sim/m32r/addx.cgs: Test (-1)+(-1)+1. + +Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com> + + * sim/m32r/mv[ft]achi.cgs: Fix expected result + (sign extension of top 8 bits). + +Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com> + + * Makefile.in (RUNTEST): Fix path to runtest. + + +Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com> + + * sim/m32r/unlock.cgs: Fixed test. + * sim/m32r/mvfc.cgs: Fixed test. + * sim/m32r/remu.cgs: Fixed test. + + * sim/m32r/bnc24.cgs: Test long BNC instruction. + * sim/m32r/bnc8.cgs: Test short BNC instruction. + * sim/m32r/ld-plus.cgs: Test LD instruction. + * sim/m32r/macwhi.cgs: Test MACWHI instruction. + * sim/m32r/macwlo.cgs: Test MACWLO instruction. + * sim/m32r/mulwhi.cgs: Test MULWHI instruction. + * sim/m32r/mulwlo.cgs: Test MULWLO instruction. + * sim/m32r/mvfachi.cgs: Test MVFACHI instruction. + * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction. + * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction. + * sim/m32r/addv.cgs: Test ADDV instruction. + * sim/m32r/addv3.cgs: Test ADDV3 instruction. + * sim/m32r/addx.cgs: Test ADDX instruction. + * sim/m32r/lock.cgs: Test LOCK instruction. + * sim/m32r/neg.cgs: Test NEG instruction. + * sim/m32r/not.cgs: Test NOT instruction. + * sim/m32r/unlock.cgs: Test UNLOCK instruction. +Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com> + + * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an + address into a general register. + + * sim/m32r/or3.cgs: Test OR3 instruction. + * sim/m32r/rach.cgs: Test RACH instruction. + * sim/m32r/rem.cgs: Test REM instruction. + * sim/m32r/sub.cgs: Test SUB instruction. + * sim/m32r/mv.cgs: Test MV instruction. + * sim/m32r/mul.cgs: Test MUL instruction. + * sim/m32r/bl24.cgs: Test long BL instruction. + * sim/m32r/bl8.cgs: Test short BL instruction. + * sim/m32r/blez.cgs: Test BLEZ instruction. + * sim/m32r/bltz.cgs: Test BLTZ instruction. + * sim/m32r/bne.cgs: Test BNE instruction. + * sim/m32r/bnez.cgs: Test BNEZ instruction. + * sim/m32r/bra24.cgs: Test long BRA instruction. + * sim/m32r/bra8.cgs: Test short BRA instruction. + * sim/m32r/jl.cgs: Test JL instruction. + * sim/m32r/or.cgs: Test OR instruction. + * sim/m32r/jmp.cgs: Test JMP instruction. + * sim/m32r/and.cgs: Test AND instruction. + * sim/m32r/and3.cgs: Test AND3 instruction. + * sim/m32r/beq.cgs: Test BEQ instruction. + * sim/m32r/beqz.cgs: Test BEQZ instruction. + * sim/m32r/bgez.cgs: Test BGEZ instruction. + * sim/m32r/bgtz.cgs: Test BGTZ instruction. + * sim/m32r/cmp.cgs: Test CMP instruction. + * sim/m32r/cmpi.cgs: Test CMPI instruction. + * sim/m32r/cmpu.cgs: Test CMPU instruction. + * sim/m32r/cmpui.cgs: Test CMPUI instruction. + * sim/m32r/div.cgs: Test DIV instruction. + * sim/m32r/divu.cgs: Test DIVU instruction. + * sim/m32r/cmpeq.cgs: Test CMPEQ instruction. + * sim/m32r/sll.cgs: Test SLL instruction. + * sim/m32r/sll3.cgs: Test SLL3 instruction. + * sim/m32r/slli.cgs: Test SLLI instruction. + * sim/m32r/sra.cgs: Test SRA instruction. + * sim/m32r/sra3.cgs: Test SRA3 instruction. + * sim/m32r/srai.cgs: Test SRAI instruction. + * sim/m32r/srl.cgs: Test SRL instruction. + * sim/m32r/srl3.cgs: Test SRL3 instruction. + * sim/m32r/srli.cgs: Test SRLI instruction. + * sim/m32r/xor3.cgs: Test XOR3 instruction. + * sim/m32r/xor.cgs: Test XOR instruction. +Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com> + + * config/default.exp: New file. + * lib/sim-defs.exp: New file. + * sim/m32r/*: m32r dejagnu simulator testsuite. + + * Makefile.in (build_alias): Define. + (arch): Define. + (RUNTEST_FOR_TARGET): Delete. + (RUNTEST): Fix. + (check): Depend on site.exp. Run dejagnu. + (site.exp): New target. + * configure.in (arch): Define from target_cpu. + * configure: Regenerate. + +Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * common/bits-gen.c (gen_bit): Pass in the full name of the macro. + (gen_mask): Ditto. + + * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. + (calc): Add support for 8 bit version of macros. + (main): Add tests for 8 bit versions of macros. + (check_sext): Check SEXT of zero clears bits. + + * common/bits-gen.c (main): Generate tests for 8 bit versions of + macros. + +Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * common/Make-common.in: New file, provide generic rules for + running checks. + +Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure.in (configdirs): Test for the target directory instead + of matching on a target. + diff --git a/sim/testsuite/Makefile.in b/sim/testsuite/Makefile.in new file mode 100644 index 00000000000..637a8fe7aa4 --- /dev/null +++ b/sim/testsuite/Makefile.in @@ -0,0 +1,182 @@ +# Makefile for regression testing the GNU debugger. +# Copyright (C) 1997, 1998 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +build_canonical = @build@ +build_alias = @build_alias@ +host_canonical = @host@ +host_alias = @host_alias@ +target_canonical = @target@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ + +arch = @arch@ + +SHELL = /bin/sh +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +EXPECT = `if [ -f $${rootme}/../../expect/expect ] ; then \ + echo $${rootme}/../../expect/expect ; \ + else echo expect ; fi` + +RUNTEST = `if [ -f $${srcdir}/../../dejagnu/runtest ] ; then \ + echo $${srcdir}/../../dejagnu/runtest ; else echo runtest; \ + fi` + +RUNTESTFLAGS = + +#### host, target, and site specific Makefile frags come in here. + +# The use of $$(x_FOR_TARGET) reduces the command line length by not +# duplicating the lengthy definition. + +TARGET_FLAGS_TO_PASS = \ + "prefix=$(prefix)" \ + "exec_prefix=$(exec_prefix)" \ + "against=$(against)" \ + 'CC=$$(CC_FOR_TARGET)' \ + "CC_FOR_TARGET=$(CC_FOR_TARGET)" \ + "CFLAGS=$(TESTSUITE_CFLAGS)" \ + "CHILLFLAGS=$(CHILLFLAGS)" \ + 'CHILL=$$(CHILL_FOR_TARGET)' \ + "CHILL_FOR_TARGET=$(CHILL_FOR_TARGET)" \ + "CHILL_LIB=$(CHILL_LIB)" \ + 'CXX=$$(CXX_FOR_TARGET)' \ + "CXX_FOR_TARGET=$(CXX_FOR_TARGET)" \ + "CXXFLAGS=$(CXXFLAGS)" \ + "MAKEINFO=$(MAKEINFO)" \ + "INSTALL=$(INSTALL)" \ + "INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \ + "INSTALL_DATA=$(INSTALL_DATA)" \ + "RUNTESTFLAGS=$(RUNTESTFLAGS)" + +# "RUNTEST=$(RUNTEST)" \ + +all: + @echo "Nothing to be done for all..." + +.NOEXPORT: +info: +install-info: +dvi: + +install: + +uninstall: force + +installcheck: + +check: check-DEJAGNU check-recursive + +#test1: +check-recursive: + @for i in . ${SUBDIRS}; do \ + if [ $$i = . ] ; then continue ; fi ; \ + if [ -d ./$$i ] ; then \ + if (rootme=`pwd`/ ; export rootme ; \ + rootsrc=`cd $(srcdir); pwd`/ ; export rootsrc ; \ + echo "check recursively into $$i directory..."; \ + cd ./$$i; \ + $(MAKE) $(TARGET_FLAGS_TO_PASS) check) ; then true ; \ + else exit 1 ; fi ; \ + else true ; fi ; \ + done + +#test2: +check-DEJAGNU: site.exp + echo "Dejagnu-checking in `pwd` directory ..." + rootme=`pwd`; export rootme; echo rootme = $$rootme; \ + srcdir=`cd ${srcdir}; pwd`; export srcdir ; echo srcdir = $$srcdir; \ + EXPECT=${EXPECT} ; export EXPECT ; echo EXPECT = $$EXPECT; \ + if [ -f $$rootme/../../expect/expect ]; then \ + TCL_LIBRARY=`cd $$srcdir/../../tcl/library && pwd`; \ + export TCL_LIBRARY; \ + fi; \ + echo TCL_LIBRARY = $$TCL_LIBRARY; \ + runtest=$(RUNTEST); echo runtest = $$runtest; \ + if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ + $$runtest $(RUNTESTFLAGS); \ + else echo "WARNING: could not find \`runtest'" 1>&2; :;\ + fi + + +site.exp: Makefile + @echo 'Making a new site.exp file...' + -@rm -f site.bak + @echo '## these variables are automatically generated by make ##' > $@-t + @echo '# Do not edit here. If you wish to override these values' >> $@-t + @echo '# edit the last section' >> $@-t + @echo 'set tool sim' >> $@-t + @echo 'set srcdir $(srcdir)' >> $@-t + @echo 'set objdir' `pwd` >> $@-t + @echo 'set arch $(arch)' >> $@-t + @echo 'set build_alias $(build_alias)' >> $@-t + @echo 'set build_triplet $(build_canonical)' >> $@-t + @echo 'set host_alias $(host_alias)' >> $@-t + @echo 'set host_triplet $(host_canonical)' >> $@-t + @echo 'set target_alias $(target_alias)' >> $@-t + @echo 'set target_triplet $(target_canonical)' >> $@-t + @echo '## All variables above are generated by configure. Do Not Edit ##' >> $@-t + -@sed '1,/^## All variables above are.*##/ d' site.exp >> $@-t + -@mv site.exp site.bak + @mv $@-t site.exp + +force:; + +clean mostlyclean: + -rm -f *~ core *.o a.out xgdb *.x *.grt + -rm -f *.rum *.c *.dif *.*out + if [ x"${SUBDIRS}" != x ] ; then \ + for dir in ${SUBDIRS}; \ + do \ + echo "$$dir:"; \ + if [ -d $$dir ]; then \ + (cd $$dir; $(MAKE) clean); \ + fi; \ + done ; \ + else true; fi + +distclean maintainer-clean realclean: clean + -rm -f *~ core + -rm -f Makefile config.status *-init.exp + -rm -fr *.log summary detail *.plog *.sum *.psum site.* + if [ x"${SUBDIRS}" != x ] ; then \ + for dir in ${SUBDIRS}; \ + do \ + echo "$$dir:"; \ + if [ -d $$dir ]; then \ + (cd $$dir; $(MAKE) distclean); \ + fi; \ + done ; \ + else true; fi + +Makefile : Makefile.in config.status + $(SHELL) config.status + +config.status: $(srcdir)/configure + $(SHELL) ./config.status --recheck +# FIXME: Requires --enable-maintainer-mode, which one could add, but +# it's provided by automake. Maybe switch to automake someday. +#$(srcdir)/configure: @MAINT@ $(srcdir)/configure.in +# cd $(srcdir) && autoconf diff --git a/sim/testsuite/common/Make-common.in b/sim/testsuite/common/Make-common.in new file mode 100644 index 00000000000..7afef4a99dd --- /dev/null +++ b/sim/testsuite/common/Make-common.in @@ -0,0 +1,90 @@ +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/v850/run ]; then \ + echo ../../../sim/v850/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET=$(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET=$(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET=$(RUN_FOR_TARGET) + +clean: + rm -f $(TESTS) + rm -f *.run *.o + rm -f core *.core + +# Rules for running the tests + +.SUFFIXES: .ok .run .hi .ko .ti +.run.ok: + rm -f tmp-$* $*.hi + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $*.run > tmp-$* + echo 'Hello World!' | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko +.run.ti: + rm -f tmp-$* $*.ti + set +e ; \ + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $(INTFLAGS_FOR_TARGET) $*.run > tmp-$* + test `cat tmp-$* | wc -l` -eq 10 < /dev/null + test `grep Tick tmp-$* | wc -l` -eq 10 < /dev/null + mv tmp-$* $*.ti + + +# Rules for building the test +# Preference is for obtaining the executable (.run) from a prebuilt image + +.SUFFIXES: .uue .s .S .run +.uue.run: + head $* | grep $*.run > /dev/null + uudecode $*.uue +.run.u: + uuencode < $*.run $*.run > $*.u +.o.run: + $(LD_FOR_TARGET) $(LDFLAGS_FOR_TARGET) -o $*.run $*.o +.s.o: + $(AS_FOR_TARGET) $(ASFLAGS_FOR_TARGET) -I$(srcdir) $(srcdir)/$*.s -o $*.o +.S.o: + $(AS_FOR_TARGET) $(ASFLAGS_FOR_TARGET) -I$(srcdir) $(srcdir)/$*.S -o $*.o + + +Makefile: Makefile.in config.status + $(SHELL) ./config.status + +config.status: configure + $(SHELL) ./config.status --recheck diff --git a/sim/testsuite/common/Makefile.in b/sim/testsuite/common/Makefile.in new file mode 100644 index 00000000000..d088501676e --- /dev/null +++ b/sim/testsuite/common/Makefile.in @@ -0,0 +1,53 @@ +CC=gcc +CFLAGS = -Wall -Werror -I../../common -I../../../include -g +default: check + + +# Verify SIM-BITS + +check: bits32m0.ok bits32m31.ok bits64m0.ok bits64m63.ok +all: bits32m0 bits32m31 bits64m0 bits64m63 + +bits32m0.c: bits-gen bits-tst.c + ./bits-gen 32 0 big > tmp-bits32m0.c + cat bits-tst.c >> tmp-bits32m0.c + mv tmp-bits32m0.c bits32m0.c +bits32m31.c: bits-gen bits-tst.c + ./bits-gen 32 31 little > tmp-bits32m31.c + cat bits-tst.c >> tmp-bits32m31.c + mv tmp-bits32m31.c bits32m31.c +bits64m0.c: bits-gen bits-tst.c + ./bits-gen 64 0 big > tmp-bits64m0.c + cat bits-tst.c >> tmp-bits64m0.c + mv tmp-bits64m0.c bits64m0.c +bits64m63.c: bits-gen bits-tst.c + ./bits-gen 64 63 little > tmp-bits64m63.c + cat bits-tst.c >> tmp-bits64m63.c + mv tmp-bits64m63.c bits64m63.c + + + +# Verify SIM-FPU +# +#check: fpu-tst.ok +#all: fpu-tst + + + +# Verify SIM-ALU + +check: alu-tst.ok +all: alu-tst +alu-tst.o: alu-tst.c alu-n-tst.h + +clean: + rm -f *.o + rm -f *.ok + rm -f bits32m0 bits32m31 bits64m0 bits64m63 bits-gen + rm -f tmp-* + rm -f alu-tst + +.SUFIXES: .ok +%.ok: % + ./$< + touch $<.ok diff --git a/sim/testsuite/common/alu-n-tst.h b/sim/testsuite/common/alu-n-tst.h new file mode 100644 index 00000000000..cd218d4339d --- /dev/null +++ b/sim/testsuite/common/alu-n-tst.h @@ -0,0 +1,260 @@ +#ifndef N +#error "N must be #defined" +#endif + +#include "symcat.h" + +/* NOTE: see end of file for #undef of these macros */ +#define unsignedN XCONCAT2(unsigned,N) +#define MAX_INT XCONCAT2(MAX_INT,N) +#define MIN_INT XCONCAT2(MIN_INT,N) +#define alu_N_tests XCONCAT3(alu_,N,_tests) +#define do_alu_N_tests XCONCAT3(do_alu_,N,_tests) +#define OP_BEGIN XCONCAT3(ALU,N,_BEGIN) +#define OP_ADDC XCONCAT3(ALU,N,_ADDC) +#define OP_ADDC_C XCONCAT3(ALU,N,_ADDC_C) +#define OP_SUBC XCONCAT3(ALU,N,_SUBC) +#define OP_SUBB XCONCAT3(ALU,N,_SUBB) +#define OP_SUBB_B XCONCAT3(ALU,N,_SUBB_B) +#define OP_SUBC_X XCONCAT3(ALU,N,_SUBC_X) +#define OP_NEGC XCONCAT3(ALU,N,_NEGC) +#define OP_NEGB XCONCAT3(ALU,N,_NEGB) +#define HAD_CARRY_BORROW (XCONCAT3(ALU,N,_HAD_CARRY_BORROW) != 0) +#define HAD_OVERFLOW (XCONCAT3(ALU,N,_HAD_OVERFLOW) != 0) +#define RESULT XCONCAT3(ALU,N,_RESULT) +#define CARRY_BORROW_RESULT XCONCAT3(ALU,N,_CARRY_BORROW_RESULT) +#define OVERFLOW_RESULT XCONCAT3(ALU,N,_OVERFLOW_RESULT) +#define do_op_N XCONCAT2(do_op_,N) + + +void +do_op_N (const alu_test *tst) +{ + const alu_op *op; + int borrow_p = 0; + OP_BEGIN (tst->begin); + print_hex (tst->begin, N); + for (op = tst->ops; op->op != NULL; op++) + { + printf (" %s ", op->op); + print_hex (op->arg, N); + if (strcmp (op->op, "ADDC") == 0) + OP_ADDC (op->arg); + else if (strcmp (op->op, "ADDC_C0") == 0) + OP_ADDC_C (op->arg, 0); + else if (strcmp (op->op, "ADDC_C1") == 0) + OP_ADDC_C (op->arg, 1); + else if (strcmp (op->op, "SUBC") == 0) + OP_SUBC (op->arg); + else if (strcmp (op->op, "SUBC_X0") == 0) + OP_SUBC_X (op->arg, 0); + else if (strcmp (op->op, "SUBC_X1") == 0) + OP_SUBC_X (op->arg, 1); + else if (strcmp (op->op, "SUBB") == 0) + { + OP_SUBB (op->arg); + borrow_p ++; + } + else if (strcmp (op->op, "SUBB_B0") == 0) + { + OP_SUBB_B (op->arg, 0); + borrow_p ++; + } + else if (strcmp (op->op, "SUBB_B1") == 0) + { + OP_SUBB_B (op->arg, 1); + borrow_p ++; + } + else if (strcmp (op->op, "NEGC") == 0) + OP_NEGC (); + else if (strcmp (op->op, "NEGB") == 0) + { + OP_NEGB (); + borrow_p ++; + } + else + { + printf (" -- operator unknown\n"); + abort (); + } + } + printf (" = "); + print_hex (tst->result, N); + if (borrow_p) + printf (" B:%d", tst->carry_borrow); + else + printf (" C:%d", tst->carry_borrow); + printf (" V:%d", tst->overflow); + if (tst->carry_borrow != HAD_CARRY_BORROW) + { + if (borrow_p) + printf (" -- borrow (%d) wrong", HAD_CARRY_BORROW); + else + printf (" -- carry (%d) wrong", HAD_CARRY_BORROW); + errors ++; + } + if (tst->overflow != HAD_OVERFLOW) + { + printf (" -- overflow (%d) wrong", HAD_OVERFLOW); + errors ++; + } + if ((unsignedN) CARRY_BORROW_RESULT != (unsignedN) tst->result) + { + printf (" -- result for carry/borrow wrong "); + print_hex (CARRY_BORROW_RESULT, N); + errors ++; + } + if ((unsignedN) OVERFLOW_RESULT != (unsignedN) tst->result) + { + printf (" -- result for overflow wrong "); + print_hex (OVERFLOW_RESULT, N); + errors ++; + } + if ((unsignedN) RESULT != (unsignedN) tst->result) + { + printf (" -- result wrong "); + print_hex (RESULT, N); + errors ++; + } + printf ("\n"); +} + + +const alu_test alu_N_tests[] = { + + /* 0 + 0; 0 + 1; 1 + 0; 1 + 1 */ + { 0, { { "ADDC", 0 }, }, 0, 0, 0, }, + { 0, { { "ADDC", 1 }, }, 1, 0, 0, }, + { 1, { { "ADDC", 0 }, }, 1, 0, 0, }, + { 1, { { "ADDC", 1 }, }, 2, 0, 0, }, + + /* 0 + 0 + 0; 0 + 0 + 1; 0 + 1 + 0; 0 + 1 + 1 */ + /* 1 + 0 + 0; 1 + 0 + 1; 1 + 1 + 0; 1 + 1 + 1 */ + { 0, { { "ADDC_C0", 0 }, }, 0, 0, 0, }, + { 0, { { "ADDC_C0", 1 }, }, 1, 0, 0, }, + { 0, { { "ADDC_C1", 0 }, }, 1, 0, 0, }, + { 0, { { "ADDC_C1", 1 }, }, 2, 0, 0, }, + { 1, { { "ADDC_C0", 0 }, }, 1, 0, 0, }, + { 1, { { "ADDC_C0", 1 }, }, 2, 0, 0, }, + { 1, { { "ADDC_C1", 0 }, }, 2, 0, 0, }, + { 1, { { "ADDC_C1", 1 }, }, 3, 0, 0, }, + + /* */ + { MAX_INT, { { "ADDC", 1 }, }, MIN_INT, 0, 1, }, + { MIN_INT, { { "ADDC", -1 }, }, MAX_INT, 1, 1, }, + { MAX_INT, { { "ADDC", MIN_INT }, }, -1, 0, 0, }, + { MIN_INT, { { "ADDC", MAX_INT }, }, -1, 0, 0, }, + { MAX_INT, { { "ADDC", MAX_INT }, }, MAX_INT << 1, 0, 1, }, + { MIN_INT, { { "ADDC", MIN_INT }, }, 0, 1, 1, }, + /* */ + { 0, { { "ADDC_C1", -1 }, }, 0, 1, 0, }, + { 0, { { "ADDC_C1", -2 }, }, -1, 0, 0, }, + { -1, { { "ADDC_C1", 0 }, }, 0, 1, 0, }, + { 0, { { "ADDC_C0", 0 }, }, 0, 0, 0, }, + { -1, { { "ADDC_C1", -1 }, }, -1, 1, 0, }, + { -1, { { "ADDC_C1", 1 }, }, 1, 1, 0, }, + { 0, { { "ADDC_C1", MAX_INT }, }, MIN_INT, 0, 1, }, + { MAX_INT, { { "ADDC_C1", 1 }, }, MIN_INT + 1, 0, 1, }, + { MAX_INT, { { "ADDC_C1", MIN_INT }, }, 0, 1, 0, }, + { MAX_INT, { { "ADDC_C1", MAX_INT }, }, (MAX_INT << 1) + 1, 0, 1, }, + { MAX_INT, { { "ADDC_C0", MAX_INT }, }, MAX_INT << 1, 0, 1, }, + + /* 0 - 0 */ + { 0, { { "SUBC", 0 }, }, 0, 1, 0, }, + { 0, { { "SUBB", 0 }, }, 0, 0, 0, }, + + /* 0 - 1 */ + { 0, { { "SUBC", 1 }, }, -1, 0, 0, }, + { 0, { { "SUBB", 1 }, }, -1, 1, 0, }, + + /* 1 - 0 */ + { 1, { { "SUBC", 0 }, }, 1, 1, 0, }, + { 1, { { "SUBB", 0 }, }, 1, 0, 0, }, + + /* 1 - 1 */ + { 1, { { "SUBC", 1 }, }, 0, 1, 0, }, + { 1, { { "SUBB", 1 }, }, 0, 0, 0, }, + + /* 0 - 0 - 0 */ + { 0, { { "SUBC_X0", 0 }, }, -1, 0, 0, }, + { 0, { { "SUBB_B0", 0 }, }, 0, 0, 0, }, + + /* 0 - 0 - 1 */ + { 0, { { "SUBC_X0", 1 }, }, -2, 0, 0, }, + { 0, { { "SUBB_B0", 1 }, }, -1, 1, 0, }, + + /* 0 - 1 - 0 */ + { 0, { { "SUBC_X1", 0 }, }, 0, 1, 0, }, + { 0, { { "SUBB_B1", 0 }, }, -1, 1, 0, }, + + /* 0 - 1 - 1 */ + { 0, { { "SUBC_X1", 1 }, }, -1, 0, 0, }, + { 0, { { "SUBB_B1", 1 }, }, -2, 1, 0, }, + + /* 1 - 0 - 0 */ + { 1, { { "SUBC_X0", 0 }, }, 0, 1, 0, }, + { 1, { { "SUBB_B0", 0 }, }, 1, 0, 0, }, + + /* 1 - 0 - 1 */ + { 1, { { "SUBC_X0", 1 }, }, -1, 0, 0, }, + { 1, { { "SUBB_B0", 1 }, }, 0, 0, 0, }, + + /* 1 - 1 - 0 */ + { 1, { { "SUBC_X1", 0 }, }, 1, 1, 0, }, + { 1, { { "SUBB_B1", 0 }, }, 0, 0, 0, }, + + /* 1 - 1 - 1 */ + { 1, { { "SUBC_X1", 1 }, }, 0, 1, 0, }, + { 1, { { "SUBB_B1", 1 }, }, -1, 1, 0, }, + + /* */ + { 0, { { "SUBC", MIN_INT }, }, MIN_INT, 0, 1, }, + { MIN_INT, { { "SUBC", 1 }, }, MAX_INT, 1, 1, }, + { MAX_INT, { { "SUBC", MAX_INT }, }, 0, 1, 0, }, + + /* */ + { 0, { { "SUBC_X0", MIN_INT }, }, MAX_INT, 0, 0, }, + { MIN_INT, { { "SUBC_X1", 0 }, }, MIN_INT, 1, 0, }, + { MAX_INT, { { "SUBC_X0", MAX_INT }, }, -1, 0, 0, }, + + /* */ + { MAX_INT, { { "NEGC", 0 }, }, MIN_INT + 1, 0, 0, }, + { MAX_INT, { { "NEGC", 0 }, }, MIN_INT + 1, 0, 0, }, + { MIN_INT, { { "NEGC", 0 }, }, MIN_INT, 0, 1, }, + { 0, { { "NEGC", 0 }, }, 0, 1, 0, }, + { -1, { { "NEGC", 0 }, }, 1, 0, 0, }, + { 1, { { "NEGC", 0 }, }, -1, 0, 0, }, +}; + + +static void +do_alu_N_tests (void) +{ + int i; + for (i = 0; i < sizeof (alu_N_tests) / sizeof (*alu_N_tests); i++) + { + const alu_test *tst = &alu_N_tests[i]; + do_op_N (tst); + } +} + + +#undef OP_BEGIN +#undef OP_ADDC +#undef OP_ADDC_C +#undef OP_SUBB +#undef OP_SUBC +#undef OP_SUBC_X +#undef OP_SUBB_B +#undef HAD_OVERFLOW +#undef HAD_CARRY_BORROW +#undef OVERFLOW_RESULT +#undef CARRY_BORROW_RESULT +#undef RESULT +#undef do_op_N +#undef unsignedN +#undef MAX_INT +#undef MIN_INT +#undef alu_N_tests +#undef do_alu_N_tests + diff --git a/sim/testsuite/common/alu-tst.c b/sim/testsuite/common/alu-tst.c new file mode 100644 index 00000000000..e7fffe502cd --- /dev/null +++ b/sim/testsuite/common/alu-tst.c @@ -0,0 +1,104 @@ +#define WITH_TARGET_WORD_MSB 0 +#define WITH_TARGET_WORD_BITSIZE 64 +#define WITH_HOST_WORD_BITSIZE (sizeof (int) * 8) +#define WITH_TARGET_BYTE_ORDER BIG_ENDIAN /* does not matter */ + +#define ASSERT(EXPRESSION) \ +{ \ + if (!(EXPRESSION)) { \ + fprintf (stderr, "%s:%d: assertion failed - %s\n", \ + __FILE__, __LINE__, #EXPRESSION); \ + abort (); \ + } \ +} + +#define SIM_BITS_INLINE (INCLUDE_MODULE | INCLUDED_BY_MODULE) + +#include <string.h> + +#include "sim-basics.h" + +#include "sim-alu.h" + +#include <stdio.h> + +typedef struct { + char *op; + unsigned64 arg; +} alu_op; + +typedef struct { + unsigned64 begin; + alu_op ops[4]; + unsigned64 result; + int carry_borrow; + int overflow; +} alu_test; + +#define MAX_INT8 UNSIGNED64 (127) +#define MIN_INT8 UNSIGNED64 (128) + +#define MAX_INT16 UNSIGNED64 (32767) +#define MIN_INT16 UNSIGNED64 (32768) + +#define MAX_INT32 UNSIGNED64 (0x7fffffff) +#define MIN_INT32 UNSIGNED64 (0x80000000) + +#define MAX_INT64 UNSIGNED64 (0x7fffffffffffffff) +#define MIN_INT64 UNSIGNED64 (0x8000000000000000) + +static void +print_hex (unsigned64 val, int nr_bits) +{ + switch (nr_bits) + { + case 8: + printf ("0x%02lx", (long) (unsigned8) (val)); + break; + case 16: + printf ("0x%04lx", (long) (unsigned16) (val)); + break; + case 32: + printf ("0x%08lx", (long) (unsigned32) (val)); + break; + case 64: + printf ("0x%08lx%08lx", + (long) (unsigned32) (val >> 32), + (long) (unsigned32) (val)); + break; + default: + abort (); + } +} + + +int errors = 0; + + +#define N 8 +#include "alu-n-tst.h" +#undef N + +#define N 16 +#include "alu-n-tst.h" +#undef N + +#define N 32 +#include "alu-n-tst.h" +#undef N + +#define N 64 +#include "alu-n-tst.h" +#undef N + + + +int +main () +{ + do_alu_8_tests (); + do_alu_16_tests (); + do_alu_32_tests (); + do_alu_64_tests (); + return (errors != 0); +} diff --git a/sim/testsuite/common/bits-gen.c b/sim/testsuite/common/bits-gen.c new file mode 100644 index 00000000000..71ddef303df --- /dev/null +++ b/sim/testsuite/common/bits-gen.c @@ -0,0 +1,319 @@ +/* Miscellaneous simulator utilities. + Copyright (C) 1997 Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include <stdio.h> + + +void +gen_struct (void) +{ + printf ("\n"); + printf ("typedef struct _test_tuples {\n"); + printf (" int line;\n"); + printf (" int row;\n"); + printf (" int col;\n"); + printf (" long long val;\n"); + printf (" long long check;\n"); + printf ("} test_tuples;\n"); + printf ("\n"); + printf ("typedef struct _test_spec {\n"); + printf (" const char *file;\n"); + printf (" const char *macro;\n"); + printf (" int nr_rows;\n"); + printf (" int nr_cols;\n"); + printf (" test_tuples *tuples;\n"); + printf ("} test_spec;\n"); +} + + +void +gen_bit (int bitsize, + int msb, + const char *macro, + int nr_bits) +{ + int i; + + printf ("\n/* Test the %s macro */\n", macro); + printf ("test_tuples %s_tuples[%d] = {\n", macro, nr_bits); + for (i = 0; i < nr_bits; i++) + { + /* compute what we think the value is */ + unsigned long long bit = 1; + if (msb == 0) + bit <<= nr_bits - i - 1; + else + bit <<= i; + if (bitsize == 32) + bit = (unsigned) bit; /* truncate it! */ + /* write it out */ + printf (" { __LINE__, "); + printf ("%d, %2d, ", -1, i); + printf ("%s (%2d), ", macro, i); + printf ("UNSIGNED64 (0x%08lx%08lx), ", + (long) (bit >> 32), (long) bit); + printf ("},\n"); + } + printf ("};\n"); + printf ("\n"); + printf ("test_spec %s_test = { __FILE__, \"%s\", 1, %d, %s_tuples, };\n", + macro, macro, nr_bits, macro); + printf ("\n"); +} + + +void +gen_enum (const char *macro, + int nr_bits) +{ + int i; + + printf ("\n/* Test the %s macro in an enum */\n", macro); + printf ("enum enum_%s {\n", macro); + for (i = 0; i < nr_bits; i++) + { + printf (" elem_%s_%d = %s (%d),\n", macro, i, macro, i); + } + printf ("};\n"); + printf ("\n"); +} + + +void +gen_mask (int bitsize, + const char *msb, + const char *macro, + int nr_bits) +{ + int l; + int h; + printf ("\n/* Test the %s%s macro */\n", msb, macro); + printf ("test_tuples %s_tuples[%d][%d] = {\n", macro, nr_bits, nr_bits); + for (l = 0; l < nr_bits; l++) + { + printf (" {\n"); + for (h = 0; h < nr_bits; h++) + { + printf (" { __LINE__, "); + if ((strcmp (msb, "MS") == 0 && l <= h) + || (strcmp (msb, "MS") != 0 && l >= h) + || (strcmp (macro, "") == 0)) + { + /* compute the mask */ + unsigned long long mask = 0; + int b; + for (b = 0; b < nr_bits; b++) + { + unsigned long long bit = 1; + if (strcmp (msb, "MS") == 0) + { + if ((l <= b && b <= h) + || (h < l && (b <= h || b >= l))) + bit <<= (nr_bits - b - 1); + else + bit = 0; + } + else + { + if ((l >= b && b >= h) + || (h > l && (b >= h || b <= l))) + bit <<= b; + else + bit = 0; + } + mask |= bit; + } + if (bitsize == 32) + mask = (unsigned long) mask; + printf ("%d, %d, ", l, h); + printf ("%s%s (%2d, %2d), ", msb, macro, l, h); + printf ("UNSIGNED64 (0x%08lx%08lx), ", + (long) (mask >> 32), (long) mask); + } + else + printf ("-1, -1, "); + printf ("},\n"); + } + printf (" },\n"); + } + printf ("};\n"); + printf ("\n"); + printf ("test_spec %s_test = { __FILE__, \"%s%s\", %d, %d, &%s_tuples[0][0], };\n", + macro, msb, macro, nr_bits, nr_bits, macro); + printf ("\n"); +} + + +void +usage (int reason) +{ + fprintf (stderr, "Usage:\n"); + fprintf (stderr, " bits-gen <nr-bits> <msb> <byte-order>\n"); + fprintf (stderr, "Generate a test case for the simulator bit manipulation code\n"); + fprintf (stderr, " <nr-bits> = { 32 | 64 }\n"); + fprintf (stderr, " <msb> = { 0 | { 31 | 63 } }\n"); + fprintf (stderr, " <byte-order> = { big | little }\n"); + + switch (reason) + { + case 1: fprintf (stderr, "Wrong number of arguments\n"); + break; + case 2: + fprintf (stderr, "Invalid <nr-bits> argument\n"); + break; + case 3: + fprintf (stderr, "Invalid <msb> argument\n"); + break; + case 4: + fprintf (stderr, "Invalid <byte-order> argument\n"); + break; + default: + } + + exit (1); +} + + + +int +main (argc, argv) + int argc; + char **argv; +{ + int bitsize; + int msb; + char *ms; + int big_endian; + + if (argc != 4) + usage (1); + + if (strcmp (argv [1], "32") == 0) + bitsize = 32; + else if (strcmp (argv [1], "64") == 0) + bitsize = 64; + else + usage (2); + + if (strcmp (argv [2], "0") == 0) + msb = 0; + else if (strcmp (argv [2], "31") == 0 && bitsize == 32) + msb = 31; + else if (strcmp (argv [2], "63") == 0 && bitsize == 64) + msb = 63; + else + usage (3); + if (msb == 0) + ms = "MS"; + else + ms = "LS"; + + if (strcmp (argv [3], "big") == 0) + big_endian = 1; + else if (strcmp (argv [3], "little") == 0) + big_endian = 0; + else + usage (4); + + printf ("#define WITH_TARGET_WORD_BITSIZE %d\n", bitsize); + printf ("#define WITH_TARGET_WORD_MSB %d\n", msb); + printf ("#define WITH_HOST_WORD_BITSIZE %d\n", sizeof (int) * 8); + printf ("#define WITH_TARGET_BYTE_ORDER %s\n", big_endian ? "BIG_ENDIAN" : "LITTLE_ENDIAN"); + printf ("\n"); + printf ("#define SIM_BITS_INLINE (ALL_H_INLINE)\n"); + printf ("\n"); + printf ("#define ASSERT(X) do { if (!(X)) abort(); } while (0)\n"); + printf ("\n"); + printf ("#include \"sim-basics.h\"\n"); + + gen_struct (); + + + + printf ("#define DO_BIT_TESTS\n"); + gen_bit ( 4, msb, "BIT4", 4); + gen_bit ( 5, msb, "BIT5", 5); + gen_bit ( 8, msb, "BIT8", 8); + gen_bit (10, msb, "BIT10", 10); + gen_bit (16, msb, "BIT16", 16); + gen_bit (32, msb, "BIT32", 32); + gen_bit (64, msb, "BIT64", 64); + gen_bit (bitsize, msb, "BIT", 64); + + gen_bit ( 8, 8 - 1, "LSBIT8", 8); + gen_bit (16, 16 - 1, "LSBIT16", 16); + gen_bit (32, 32 - 1, "LSBIT32", 32); + gen_bit (64, 64 - 1, "LSBIT64", 64); + gen_bit (bitsize, bitsize - 1, "LSBIT", 64); + + gen_bit ( 8, 0, "MSBIT8", 8); + gen_bit (16, 0, "MSBIT16", 16); + gen_bit (32, 0, "MSBIT32", 32); + gen_bit (64, 0, "MSBIT64", 64); + gen_bit (bitsize, 0, "MSBIT", 64); + + printf ("test_spec *(bit_tests[]) = {\n"); + printf (" &BIT4_test,\n"); + printf (" &BIT5_test,\n"); + printf (" &BIT8_test,\n"); + printf (" &BIT10_test,\n"); + printf (" &BIT16_test,\n"); + printf (" &BIT32_test,\n"); + printf (" &BIT64_test,\n"); + printf (" &BIT_test,\n"); + printf (" &LSBIT8_test,\n"); + printf (" &LSBIT16_test,\n"); + printf (" &LSBIT32_test,\n"); + printf (" &LSBIT64_test,\n"); + printf (" &LSBIT_test,\n"); + printf (" &MSBIT8_test,\n"); + printf (" &MSBIT16_test,\n"); + printf (" &MSBIT32_test,\n"); + printf (" &MSBIT64_test,\n"); + printf (" &MSBIT_test,\n"); + printf (" 0,\n"); + printf ("};\n\n"); + + gen_enum ("BIT", 64); + gen_enum ("LSBIT", 64); + gen_enum ("MSBIT", 64); + gen_enum ("BIT32", 32); + gen_enum ("LSBIT32", 32); + gen_enum ("MSBIT32", 32); + + printf ("#define DO_MASK_TESTS\n"); + gen_mask ( 8, ms, "MASK8", 8); + gen_mask (16, ms, "MASK16", 16); + gen_mask (32, ms, "MASK32", 32); + gen_mask (64, ms, "MASK64", 64); + gen_mask (bitsize, ms, "MASK", 64); + + printf ("test_spec *(mask_tests[]) = {\n"); + printf (" &MASK8_test,\n"); + printf (" &MASK16_test,\n"); + printf (" &MASK32_test,\n"); + printf (" &MASK64_test,\n"); + printf (" &MASK_test,\n"); + printf (" 0,\n"); + printf ("};\n\n"); + + return 0; +} diff --git a/sim/testsuite/common/bits-tst.c b/sim/testsuite/common/bits-tst.c new file mode 100644 index 00000000000..5a4210a76ab --- /dev/null +++ b/sim/testsuite/common/bits-tst.c @@ -0,0 +1,408 @@ +# 2 "bits-tst.c" + +/* Drive the bit test routines */ + + +long long +calc (const char *call, + long long val, + int row, + int col) +{ + if (strcmp (call, "MASK") == 0) + return MASKED (val, row, col); + if (strcmp (call, "MASK8") == 0) + return MASKED8 (val, row, col); + if (strcmp (call, "MASK16") == 0) + return MASKED16 (val, row, col); + if (strcmp (call, "MASK32") == 0) + return MASKED32 (val, row, col); + if (strcmp (call, "MASK64") == 0) + return MASKED64 (val, row, col); + + if (strcmp (call, "EXTRACT") == 0) + return EXTRACTED (val, row, col); + if (strcmp (call, "EXTRACT8") == 0) + return EXTRACTED8 (val, row, col); + if (strcmp (call, "EXTRACT16") == 0) + return EXTRACTED16 (val, row, col); + if (strcmp (call, "EXTRACT32") == 0) + return EXTRACTED32 (val, row, col); + if (strcmp (call, "EXTRACT64") == 0) + return EXTRACTED64 (val, row, col); + + if (strcmp (call, "LSEXTRACT") == 0) + return LSEXTRACTED (val, row, col); + if (strcmp (call, "LSEXTRACT8") == 0) + return LSEXTRACTED8 (val, row, col); + if (strcmp (call, "LSEXTRACT16") == 0) + return LSEXTRACTED16 (val, row, col); + if (strcmp (call, "LSEXTRACT32") == 0) + return LSEXTRACTED32 (val, row, col); + if (strcmp (call, "LSEXTRACT64") == 0) + return LSEXTRACTED64 (val, row, col); + + if (strcmp (call, "MSEXTRACT") == 0) + return MSEXTRACTED (val, row, col); + if (strcmp (call, "MSEXTRACT8") == 0) + return MSEXTRACTED8 (val, row, col); + if (strcmp (call, "MSEXTRACT16") == 0) + return MSEXTRACTED16 (val, row, col); + if (strcmp (call, "MSEXTRACT32") == 0) + return MSEXTRACTED32 (val, row, col); + if (strcmp (call, "MSEXTRACT64") == 0) + return MSEXTRACTED64 (val, row, col); + + if (strcmp (call, "INSERT") == 0) + return INSERTED (val, row, col); + if (strcmp (call, "INSERT8") == 0) + return INSERTED8 (val, row, col); + if (strcmp (call, "INSERT16") == 0) + return INSERTED16 (val, row, col); + if (strcmp (call, "INSERT32") == 0) + return INSERTED32 (val, row, col); + if (strcmp (call, "INSERT64") == 0) + return INSERTED64 (val, row, col); + + if (strcmp (call, "LSINSERT") == 0) + return LSINSERTED (val, row, col); + if (strcmp (call, "LSINSERT8") == 0) + return LSINSERTED8 (val, row, col); + if (strcmp (call, "LSINSERT16") == 0) + return LSINSERTED16 (val, row, col); + if (strcmp (call, "LSINSERT32") == 0) + return LSINSERTED32 (val, row, col); + if (strcmp (call, "LSINSERT64") == 0) + return LSINSERTED64 (val, row, col); + + if (strcmp (call, "MSINSERT") == 0) + return MSINSERTED (val, row, col); + if (strcmp (call, "MSINSERT8") == 0) + return MSINSERTED8 (val, row, col); + if (strcmp (call, "MSINSERT16") == 0) + return MSINSERTED16 (val, row, col); + if (strcmp (call, "MSINSERT32") == 0) + return MSINSERTED32 (val, row, col); + if (strcmp (call, "MSINSERT64") == 0) + return MSINSERTED64 (val, row, col); + + if (strcmp (call, "MSMASK") == 0) + return MSMASKED (val, row, col); + if (strcmp (call, "MSMASK8") == 0) + return MSMASKED8 (val, row, col); + if (strcmp (call, "MSMASK16") == 0) + return MSMASKED16 (val, row, col); + if (strcmp (call, "MSMASK32") == 0) + return MSMASKED32 (val, row, col); + if (strcmp (call, "MSMASK64") == 0) + return MSMASKED64 (val, row, col); + + if (strcmp (call, "LSMASK") == 0) + return LSMASKED (val, row, col); + if (strcmp (call, "LSMASK8") == 0) + return LSMASKED8 (val, row, col); + if (strcmp (call, "LSMASK16") == 0) + return LSMASKED16 (val, row, col); + if (strcmp (call, "LSMASK32") == 0) + return LSMASKED32 (val, row, col); + if (strcmp (call, "LSMASK64") == 0) + return LSMASKED64 (val, row, col); + + if (strcmp (call, "ROT64") == 0) + return ROT64 (val, col); + if (strcmp (call, "ROT8") == 0) + return ROT8 (val, col); + if (strcmp (call, "ROT16") == 0) + return ROT16 (val, col); + if (strcmp (call, "ROT32") == 0) + return ROT32 (val, col); + + if (strcmp (call, "SEXT") == 0) + return SEXT (val, col); + if (strcmp (call, "SEXT8") == 0) + return SEXT8 (val, col); + if (strcmp (call, "SEXT16") == 0) + return SEXT16 (val, col); + if (strcmp (call, "SEXT32") == 0) + return SEXT32 (val, col); + if (strcmp (call, "SEXT64") == 0) + return SEXT64 (val, col); + + if (strcmp (call, "LSSEXT") == 0) + return LSSEXT (val, col); + if (strcmp (call, "LSSEXT8") == 0) + return LSSEXT8 (val, col); + if (strcmp (call, "LSSEXT16") == 0) + return LSSEXT16 (val, col); + if (strcmp (call, "LSSEXT32") == 0) + return LSSEXT32 (val, col); + if (strcmp (call, "LSSEXT64") == 0) + return LSSEXT64 (val, col); + + if (strcmp (call, "MSSEXT8") == 0) + return MSSEXT8 (val, col); + if (strcmp (call, "MSSEXT16") == 0) + return MSSEXT16 (val, col); + if (strcmp (call, "MSSEXT32") == 0) + return MSSEXT32 (val, col); + if (strcmp (call, "MSSEXT64") == 0) + return MSSEXT64 (val, col); + if (strcmp (call, "MSSEXT") == 0) + return MSSEXT (val, col); + + else + { + fprintf (stderr, + "Unknown call passed to calc (%s, 0x%08lx%08lx, %d, %d)\n", + call, (long)(val >> 32), (long)val, row, col); + abort (); + return val; + } +} + + +int +check_sext (int nr_bits, + int msb_nr, + const char *sexted, + const char *masked, + const char *msmasked) +{ + int errors = 0; + int col; + for (col = 0; col < nr_bits; col ++) + { + long long mask = calc (masked, -1, col, col); + long long msmask = calc (msmasked, -1, + 0, (msb_nr ? nr_bits - col - 1 : col)); + long long sext = calc (sexted, mask, -1, col); + long long mask_1 = mask >> 1; + long long sext_1 = calc (sexted, mask_1, -1, col); + long long mask_0 = (mask << 1) | mask_1; + long long sext_0 = calc (sexted, mask_0, -1, col); + if (sext_0 != mask_1) + { + fprintf (stderr, + "%s:%d: ", __FILE__, __LINE__); + fprintf (stderr, + " %s(0x%08lx%08lx,%d) == 0x%08lx%08lx wrong, != 0x%08lx%08lx\n", + sexted, (long)(mask_0 >> 32), (long)mask_0, col, + (long)(sext_0 >> 32), (long)sext_0, + (long)(mask_1 >> 32), (long)mask_1); + errors ++; + } + if (sext_1 != mask_1) + { + fprintf (stderr, + "%s:%d: ", __FILE__, __LINE__); + fprintf (stderr, + " %s(0x%08lx%08lx,%d) == 0x%08lx%08lx wrong, != 0x%08lx%08lx\n", + sexted, (long)(mask_1 >> 32), (long)mask_1, col, + (long)(sext_1 >> 32), (long)sext_1, + (long)(mask_1 >> 32), (long)mask_1); + errors ++; + } + if (sext != msmask) + { + fprintf (stderr, + "%s:%d: ", __FILE__, __LINE__); + fprintf (stderr, + " %s(0x%08lx%08lx,%d) == 0x%08lx%08lx wrong, != 0x%08lx%08lx (%s(%d,%d))\n", + sexted, (long)(mask >> 32), (long)mask, col, + (long)(sext >> 32), (long)sext, + (long)(msmask >> 32), (long)msmask, + msmasked, 0, (msb_nr ? nr_bits - col - 1 : col)); + errors ++; + } + + } + return errors; +} + + +int +check_rot (int nr_bits, + const char *roted, + const char *masked) +{ + int errors = 0; + int row; + int col; + for (row = 0; row < nr_bits; row++) + for (col = 0; col < nr_bits; col++) + if ((WITH_TARGET_WORD_MSB == 0 && row <= col) + || (WITH_TARGET_WORD_MSB != 0 && row >= col)) + { + long long mask = calc (masked, -1, row, col); + int shift; + for (shift = -nr_bits + 1; shift < nr_bits; shift ++) + { + long long rot = calc (roted, mask, -1, shift); + long long urot = calc (roted, rot, -1, -shift); + if (mask != urot + || (shift == 0 && rot != mask) + || (shift != 0 && rot == mask && abs(row - col) != (nr_bits - 1))) + { + fprintf (stderr, "%s:%d: ", __FILE__, __LINE__); + fprintf (stderr, " %s(%s(0x%08lx%08lx,%d) == 0x%08lx%08lx, %d) failed\n", + roted, roted, + (long)(mask >> 32), (long)mask, shift, + (long)(urot >> 32), (long)urot, -shift); + errors ++; + } + } + } + return errors; +} + + +int +check_extract (int nr_bits, + const char *extracted, + const char *inserted, + const char *masked) +{ + int errors = 0; + int row; + int col; + for (row = 0; row < nr_bits; row++) + for (col = 0; col < nr_bits; col ++) + if ((WITH_TARGET_WORD_MSB == 0 && row <= col) + || (WITH_TARGET_WORD_MSB != 0 && row >= col)) + { + long long mask = calc (masked, -1, row, col); + long long extr = calc (extracted, mask, row, col); + long long inst = calc (inserted, extr, row, col); + if (mask != inst) + { + fprintf (stderr, "%s:%d: ", __FILE__, __LINE__); + fprintf (stderr, " %s(%d,%d)=0x%08lx%08lx -> %s=0x%08lx%08lx -> %s=0x%08lx%08lx failed\n", + masked, row, col, (long)(mask >> 32), (long)mask, + extracted, (long)(extr >> 32), (long)extr, + inserted, (long)(inst >> 32), (long)inst); + errors ++; + } + } + return errors; +} + + +int +check_bits (int call, + test_spec **tests) +{ + int r; + int c; + int errors = 0; + while (*tests != NULL) + { + int nr_rows = (*tests)->nr_rows; + int nr_cols = (*tests)->nr_cols; + test_tuples *tuples = (*tests)->tuples; + for (r = 0; r < nr_rows; r++) + for (c = 0; c < nr_cols; c++) + { + int i = r * nr_rows + c; + test_tuples *tuple = &tuples[i]; + if (tuple->col >= 0) + { + long long val = (!call ? tuple->val : calc ((*tests)->macro, -1, + tuple->row, tuple->col)); + long long check = tuple->check; + if (val != check) + { + fprintf (stderr, "%s:%d:", (*tests)->file, tuple->line); + fprintf (stderr, " %s", (*tests)->macro); + if (tuple->row >= 0) + fprintf (stderr, " (%d, %d)", tuple->row, tuple->col); + else + fprintf (stderr, " (%d)", tuple->col); + fprintf (stderr, " == 0x%08lx%08lx wrong, != 0x%08lx%08lx\n", + (long) (val >> 32), (long) val, + (long) (check >> 32), (long) check); + errors ++; + } + } + } + tests ++; + } + return errors; +} + + +int +main (argc, argv) + int argc; + char **argv; +{ + int errors = 0; + + +#if defined (DO_BIT_TESTS) + printf ("Checking BIT*\n"); + errors += check_bits (0, bit_tests); +#endif + + +#if defined (DO_MASK_TESTS) + printf ("Checking MASK*\n"); + errors += check_bits (0, mask_tests); + + printf ("Checking MASKED*\n"); + errors += check_bits (1, mask_tests); +#endif + + +#if defined (DO_LSMASK_TESTS) + printf ("Checking LSMASK*\n"); + errors += check_bits (0, lsmask_tests); + + printf ("Checking LSMASKED*\n"); + errors += check_bits (1, lsmask_tests); +#endif + + +#if defined (DO_MSMASK_TESTS) + printf ("Checking MSMASK*\n"); + errors += check_bits (0, msmask_tests); + + printf ("Checking MSMASKED*\n"); + errors += check_bits (1, msmask_tests); +#endif + + + printf ("Checking EXTRACTED*\n"); + errors += check_extract ( 8, "EXTRACT8", "INSERT8", "MASK8"); + errors += check_extract (16, "EXTRACT16", "INSERT16", "MASK16"); + errors += check_extract (32, "EXTRACT32", "INSERT32", "MASK32"); + errors += check_extract (64, "EXTRACT64", "INSERT64", "MASK64"); + errors += check_extract (64, "EXTRACT", "INSERT", "MASK"); + + printf ("Checking SEXT*\n"); + errors += check_sext ( 8, WITH_TARGET_WORD_MSB, "SEXT8", "MASK8", "MSMASK8"); + errors += check_sext (16, WITH_TARGET_WORD_MSB, "SEXT16", "MASK16", "MSMASK16"); + errors += check_sext (32, WITH_TARGET_WORD_MSB, "SEXT32", "MASK32", "MSMASK32"); + errors += check_sext (64, WITH_TARGET_WORD_MSB, "SEXT64", "MASK64", "MSMASK64"); + errors += check_sext (64, WITH_TARGET_WORD_MSB, "SEXT", "MASK", "MSMASK"); + + printf ("Checking LSSEXT*\n"); + errors += check_sext ( 8, 8 - 1, "LSSEXT8", "LSMASK8", "MSMASK8"); + errors += check_sext (16, 16 - 1, "LSSEXT16", "LSMASK16", "MSMASK16"); + errors += check_sext (32, 32 - 1, "LSSEXT32", "LSMASK32", "MSMASK32"); + errors += check_sext (64, 64 - 1, "LSSEXT64", "LSMASK64", "MSMASK64"); + errors += check_sext (64, WITH_TARGET_WORD_BITSIZE - 1, "LSSEXT", "LSMASK", "MSMASK"); + + printf ("Checking MSSEXT*\n"); + errors += check_sext (8, 0, "MSSEXT8", "MSMASK8", "MSMASK8"); + errors += check_sext (16, 0, "MSSEXT16", "MSMASK16", "MSMASK16"); + errors += check_sext (32, 0, "MSSEXT32", "MSMASK32", "MSMASK32"); + errors += check_sext (64, 0, "MSSEXT64", "MSMASK64", "MSMASK64"); + errors += check_sext (64, 0, "MSSEXT", "MSMASK", "MSMASK"); + + printf ("Checking ROT*\n"); + errors += check_rot (16, "ROT16", "MASK16"); + errors += check_rot (32, "ROT32", "MASK32"); + errors += check_rot (64, "ROT64", "MASK64"); + + return errors != 0; +} diff --git a/sim/testsuite/common/fpu-tst.c b/sim/testsuite/common/fpu-tst.c new file mode 100644 index 00000000000..d347e12727d --- /dev/null +++ b/sim/testsuite/common/fpu-tst.c @@ -0,0 +1,538 @@ +#define ASSERT(EXPRESSION) \ +do { \ + if (!(EXPRESSION)) { \ + fprintf (stderr, "%s:%d: assertion failed - %s\n", \ + __FILE__, __LINE__, #EXPRESSION); \ + abort (); \ + } \ +} while (0) + +#define SIM_BITS_INLINE (INCLUDE_MODULE | INCLUDED_BY_MODULE) + +#include "milieu.h" +#include "softfloat.h" +#include "systfloat.h" +#include "systmodes.h" + +/* #define SIM_FPU_INLINE (INCLUDE_MODULE | INCLUDED_BY_MODULE) */ + + +#include "sim-bits.h" +#include "sim-fpu.h" +#include "sim-fpu.c" + + + +static int flags; + +int8 +syst_float_flags_clear () +{ + int old_flags = 0; + int i = 1; + while (flags >= i) + { + switch ((sim_fpu_status) (flags & i)) + { + case sim_fpu_status_denorm: + break; + case sim_fpu_status_invalid_snan: + case sim_fpu_status_invalid_qnan: + case sim_fpu_status_invalid_isi: + case sim_fpu_status_invalid_idi: + case sim_fpu_status_invalid_zdz: + case sim_fpu_status_invalid_imz: + case sim_fpu_status_invalid_cvi: + case sim_fpu_status_invalid_cmp: + case sim_fpu_status_invalid_sqrt: + old_flags |= float_flag_invalid; /* v */ + break; + case sim_fpu_status_inexact: + old_flags |= float_flag_inexact; /* x */ + break; + case sim_fpu_status_overflow: + old_flags |= float_flag_overflow; /* o */ + break; + case sim_fpu_status_underflow: + old_flags |= float_flag_underflow; /* u */ + break; + case sim_fpu_status_invalid_div0: + old_flags |= float_flag_divbyzero; /* z */ + break; + case sim_fpu_status_rounded: + break; + } + i <<= 1; + } + flags = 0; + return old_flags; +} + + +sim_fpu_round rounding_mode; + +void +syst_float_set_rounding_mode(int8 mode) +{ + switch (mode) + { + case float_round_nearest_even: + rounding_mode = sim_fpu_round_near; + break; + case float_round_down: + rounding_mode = sim_fpu_round_down; + break; + case float_round_up: + rounding_mode = sim_fpu_round_up; + break; + case float_round_to_zero: + rounding_mode = sim_fpu_round_zero; + break; + } +} + + +float32 +syst_int32_to_float32(int32 a) +{ + float32 z; + sim_fpu s; + flags |= sim_fpu_i32to (&s, a, rounding_mode); + flags |= sim_fpu_round_32 (&s, rounding_mode, 0); + sim_fpu_to32 (&z, &s); + return z; +} + +float64 +syst_int32_to_float64( int32 a ) +{ + float64 z; + sim_fpu s; + flags |= sim_fpu_i32to (&s, a, rounding_mode); + sim_fpu_to64 (&z, &s); + return z; +} + +int32 +syst_float32_to_int32_round_to_zero( float32 a ) +{ + int32 z; + sim_fpu s; + sim_fpu_32to (&s, a); + flags |= sim_fpu_to32i (&z, &s, sim_fpu_round_zero); + return z; +} + +float64 +syst_float32_to_float64 (float32 a) +{ + float64 z; + sim_fpu s; + sim_fpu_32to (&s, a); + flags |= sim_fpu_round_64 (&s, rounding_mode, 0); + sim_fpu_to64 (&z, &s); + return z; +} + +float32 syst_float32_add( float32 a, float32 b ) +{ + float32 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); +#if 0 + fprintf (stdout, "\n "); + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n+ "); + sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n= "); +#endif + flags |= sim_fpu_add (&ans, &A, &B); + flags |= sim_fpu_round_32 (&ans, rounding_mode, 0); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n"); +#endif + sim_fpu_to32 (&z, &ans); + return z; +} + +float32 syst_float32_sub( float32 a, float32 b ) +{ + float32 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " + "); + sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " = "); +#endif + flags |= sim_fpu_sub (&ans, &A, &B); + flags |= sim_fpu_round_32 (&ans, rounding_mode, 0); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n"); +#endif + sim_fpu_to32 (&z, &ans); + return z; +} + +float32 syst_float32_mul( float32 a, float32 b ) +{ + float32 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " + "); + sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " = "); +#endif + flags |= sim_fpu_mul (&ans, &A, &B); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); +#endif + flags |= sim_fpu_round_32 (&ans, rounding_mode, 0); +#if 0 + sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n"); +#endif + sim_fpu_to32 (&z, &ans); + return z; +} + +float32 syst_float32_div( float32 a, float32 b ) +{ + float32 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); + flags |= sim_fpu_div (&ans, &A, &B); + flags |= sim_fpu_round_32 (&ans, rounding_mode, 0); + sim_fpu_to32 (&z, &ans); + return z; +} + +float32 syst_float32_sqrt( float32 a ) +{ + float32 z; + sim_fpu A; + sim_fpu ans; + sim_fpu_32to (&A, a); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " sqrt> "); +#endif + flags |= sim_fpu_sqrt (&ans, &A); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); +#endif + flags |= sim_fpu_round_32 (&ans, rounding_mode, 0); +#if 0 + fprintf (stdout, " (%x)\n", flags); +#endif + sim_fpu_to32 (&z, &ans); + return z; +} + +flag syst_float32_eq( float32 a, float32 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); + flags |= (sim_fpu_eq (&is, &A, &B) & ~sim_fpu_status_invalid_qnan); + return is; +} + +flag syst_float32_eq_signaling( float32 a, float32 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); + flags |= sim_fpu_eq (&is, &A, &B); + return is; +} + +flag syst_float32_le( float32 a, float32 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); + flags |= sim_fpu_le (&is, &A, &B); + return is; +} + +flag syst_float32_le_quiet( float32 a, float32 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); + flags |= (sim_fpu_le (&is, &A, &B) & ~sim_fpu_status_invalid_qnan); + return is; +} + +flag syst_float32_lt( float32 a, float32 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); + flags |= sim_fpu_lt (&is, &A, &B); + return is; +} + +flag syst_float32_lt_quiet( float32 a, float32 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_32to (&A, a); + sim_fpu_32to (&B, b); + flags |= (sim_fpu_lt (&is, &A, &B) & ~sim_fpu_status_invalid_qnan); + return is; +} + +int32 syst_float64_to_int32_round_to_zero( float64 a ) +{ + int32 z; + sim_fpu s; + sim_fpu_64to (&s, a); + flags |= sim_fpu_to32i (&z, &s, sim_fpu_round_zero); + return z; +} + +float32 syst_float64_to_float32( float64 a ) +{ + float32 z; + sim_fpu s; + sim_fpu_64to (&s, a); +#if 0 + sim_fpu_print_fpu (&s, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " -> "); +#endif + flags |= sim_fpu_round_32 (&s, rounding_mode, 0); +#if 0 + sim_fpu_print_fpu (&s, (sim_fpu_print_func*) fprintf, stdout); + sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout); + printf ("\n"); +#endif + sim_fpu_to32 (&z, &s); + return z; +} + +float64 syst_float64_add( float64 a, float64 b ) +{ + float64 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " + "); + sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " = "); +#endif + flags |= sim_fpu_add (&ans, &A, &B); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); +#endif + flags |= sim_fpu_round_64 (&ans, rounding_mode, 0); +#if 0 + fprintf (stdout, " (%x)\n", flags); +#endif + sim_fpu_to64 (&z, &ans); + return z; +} + +float64 syst_float64_sub( float64 a, float64 b ) +{ + float64 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " + "); + sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " = "); +#endif + flags |= sim_fpu_sub (&ans, &A, &B); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); +#endif + flags |= sim_fpu_round_64 (&ans, rounding_mode, 0); +#if 0 + fprintf (stdout, " (%x)\n", flags); +#endif + sim_fpu_to64 (&z, &ans); + return z; +} + +float64 syst_float64_mul( float64 a, float64 b ) +{ + float64 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " * "); + sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " = "); +#endif + flags |= sim_fpu_mul (&ans, &A, &B); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); +#endif + flags |= sim_fpu_round_64 (&ans, rounding_mode, 0); +#if 0 + sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n"); +#endif + sim_fpu_to64 (&z, &ans); + return z; +} + +float64 syst_float64_div( float64 a, float64 b ) +{ + float64 z; + sim_fpu A; + sim_fpu B; + sim_fpu ans; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " + "); + sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, " = "); +#endif + flags |= sim_fpu_div (&ans, &A, &B); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); +#endif + flags |= sim_fpu_round_64 (&ans, rounding_mode, 0); +#if 0 + sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n"); +#endif + sim_fpu_to64 (&z, &ans); + return z; +} + +float64 syst_float64_sqrt( float64 a ) +{ + float64 z; + sim_fpu A; + sim_fpu ans; + sim_fpu_64to (&A, a); +#if 0 + sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout); + printf (" sqrt> "); + printf ("\n"); +#endif + flags |= sim_fpu_sqrt (&ans, &A); +#if 0 + sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout); +#endif + flags |= sim_fpu_round_64 (&ans, rounding_mode, 0); +#if 0 + sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout); + fprintf (stdout, "\n"); +#endif + sim_fpu_to64 (&z, &ans); + return z; +} + +flag syst_float64_eq( float64 a, float64 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); + flags |= (sim_fpu_eq (&is, &A, &B) & ~sim_fpu_status_invalid_qnan); + return is; +} + +flag syst_float64_eq_signaling( float64 a, float64 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); + flags |= sim_fpu_eq (&is, &A, &B); + return is; +} + +flag syst_float64_le( float64 a, float64 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); + flags |= sim_fpu_le (&is, &A, &B); + return is; +} + +flag syst_float64_le_quiet( float64 a, float64 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); + flags |= (sim_fpu_le (&is, &A, &B) & ~sim_fpu_status_invalid_qnan); + return is; +} + +flag syst_float64_lt( float64 a, float64 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); + flags |= sim_fpu_lt (&is, &A, &B); + return is; +} + +flag syst_float64_lt_quiet( float64 a, float64 b ) +{ + sim_fpu A; + sim_fpu B; + int is; + sim_fpu_64to (&A, a); + sim_fpu_64to (&B, b); + flags |= (sim_fpu_lt (&is, &A, &B) & ~sim_fpu_status_invalid_qnan); + return is; +} + diff --git a/sim/testsuite/config/default.exp b/sim/testsuite/config/default.exp new file mode 100644 index 00000000000..56255a33f3a --- /dev/null +++ b/sim/testsuite/config/default.exp @@ -0,0 +1,42 @@ +# Simulator default dejagnu configuration file. + +load_lib sim-defs.exp + +global AS +if ![info exists AS] { + set AS [findfile $base_dir/../../gas/as-new $base_dir/../../gas/as-new \ + [transform as]] +} + +global ASFLAGS +if ![info exists ASFLAGS] { + set ASFLAGS "" +} + +# Compilation is achieved with sim_compile ... so we don't check $CC here. + +global CFLAGS +if ![info exists CFLAGS] { + set CFLAGS "" +} + +global LD +if ![info exists LD] { + set LD [findfile $base_dir/../../ld/ld-new $base_dir/../../ld/ld-new \ + [transform ld]] +} + +global LDFLAGS +if ![info exists LDFLAGS] { + set LDFLAGS "" +} + +# The path to the simulator is obtained with [board_info host sim], +# so we don't check $SIM here. + +global SIMFLAGS +if ![info exists SIMFLAGS] { + set SIMFLAGS "" +} + +sim_init diff --git a/sim/testsuite/configure b/sim/testsuite/configure new file mode 100755 index 00000000000..7c3eef7a344 --- /dev/null +++ b/sim/testsuite/configure @@ -0,0 +1,1022 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.12.2 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; then + eval "$ac_prev=\$ac_option" + ac_prev= + continue + fi + + case "$ac_option" in + -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;; + *) ac_optarg= ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case "$ac_option" in + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir="$ac_optarg" ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build="$ac_optarg" ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file="$ac_optarg" ;; + + -datadir | --datadir | --datadi | --datad | --data | --dat | --da) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \ + | --da=*) + datadir="$ac_optarg" ;; + + -disable-* | --disable-*) + ac_feature=`echo $ac_option|sed -e 's/-*disable-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + eval "enable_${ac_feature}=no" ;; + + -enable-* | --enable-*) + ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "enable_${ac_feature}='$ac_optarg'" ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; 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If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:575: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:596: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:614: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + + +# Directories to use in all configurations. +configdirs="" + +# add test sub-directory for appropriate targets +testdir=`echo ${target} | sed -e 's/-.*-/-/'` +if test -r ${srcdir}/${testdir}/configure ; then + configdirs="${configdirs} $testdir" +fi + +# add any extra subdirectories +case $target in + *) ;; +esac + +# Compute the target architecture. +# FIXME: Will need to canonicalize some values. +# FIXME: Should be in generally accessable place. +case $target in + *) arch=${target_cpu} ;; +esac + + +# configure the subdirectories too +subdirs="$configdirs" + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set) 2>&1 | grep ac_space` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS <<EOF +#! /bin/sh +# Generated automatically by configure. +# Run this file to recreate the current configuration. +# This directory was configured as follows, +# on host `(hostname || uname -n) 2>/dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.12.2" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir + +trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS <<EOF + +# Protect against being on the right side of a sed subst in config.status. +sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g; + s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@CC@%$CC%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g +s%@arch@%$arch%g +s%@subdirs@%$subdirs%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <<EOF + +CONFIG_FILES=\${CONFIG_FILES-"Makefile"} +EOF +cat >> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +EOF +cat >> $CONFIG_STATUS <<EOF + +EOF +cat >> $CONFIG_STATUS <<\EOF + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + +if test "$no_recursion" != yes; then + + # Remove --cache-file and --srcdir arguments so they do not pile up. + ac_sub_configure_args= + ac_prev= + for ac_arg in $ac_configure_args; do + if test -n "$ac_prev"; then + ac_prev= + continue + fi + case "$ac_arg" in + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + ;; + -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) + ac_prev=srcdir ;; + -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) + ;; + *) ac_sub_configure_args="$ac_sub_configure_args $ac_arg" ;; + esac + done + + for ac_config_dir in $configdirs; do + + # Do not complain, so a configure script can configure whichever + # parts of a large source tree are present. + if test ! -d $srcdir/$ac_config_dir; then + continue + fi + + echo configuring in $ac_config_dir + + case "$srcdir" in + .) ;; + *) + if test -d ./$ac_config_dir || mkdir ./$ac_config_dir; then :; + else + { echo "configure: error: can not create `pwd`/$ac_config_dir" 1>&2; exit 1; } + fi + ;; + esac + + ac_popdir=`pwd` + cd $ac_config_dir + + # A "../" for each directory in /$ac_config_dir. + ac_dots=`echo $ac_config_dir|sed -e 's%^\./%%' -e 's%[^/]$%&/%' -e 's%[^/]*/%../%g'` + + case "$srcdir" in + .) # No --srcdir option. We are building in place. + ac_sub_srcdir=$srcdir ;; + /*) # Absolute path. + ac_sub_srcdir=$srcdir/$ac_config_dir ;; + *) # Relative path. + ac_sub_srcdir=$ac_dots$srcdir/$ac_config_dir ;; + esac + + # Check for guested configure; otherwise get Cygnus style configure. + if test -f $ac_sub_srcdir/configure; then + ac_sub_configure=$ac_sub_srcdir/configure + elif test -f $ac_sub_srcdir/configure.in; then + ac_sub_configure=$ac_configure + else + echo "configure: warning: no configuration information is in $ac_config_dir" 1>&2 + ac_sub_configure= + fi + + # The recursion is here. + if test -n "$ac_sub_configure"; then + + # Make the cache file name correct relative to the subdirectory. + case "$cache_file" in + /*) ac_sub_cache_file=$cache_file ;; + *) # Relative path. + ac_sub_cache_file="$ac_dots$cache_file" ;; + esac + + echo "running ${CONFIG_SHELL-/bin/sh} $ac_sub_configure $ac_sub_configure_args --cache-file=$ac_sub_cache_file --srcdir=$ac_sub_srcdir" + # The eval makes quoting arguments work. + if eval ${CONFIG_SHELL-/bin/sh} $ac_sub_configure $ac_sub_configure_args --cache-file=$ac_sub_cache_file --srcdir=$ac_sub_srcdir + then : + else + { echo "configure: error: $ac_sub_configure failed for $ac_config_dir" 1>&2; exit 1; } + fi + fi + + cd $ac_popdir + done +fi + diff --git a/sim/testsuite/configure.in b/sim/testsuite/configure.in new file mode 100644 index 00000000000..0bebb7ae06d --- /dev/null +++ b/sim/testsuite/configure.in @@ -0,0 +1,40 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +AC_INIT(common/bits-tst.c) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../..) +AC_CANONICAL_SYSTEM + +# Directories to use in all configurations. +configdirs="" + +# add test sub-directory for appropriate targets +testdir=`echo ${target} | sed -e 's/-.*-/-/'` +if test -r ${srcdir}/${testdir}/configure ; then + configdirs="${configdirs} $testdir" +fi + +# add any extra subdirectories +case $target in + *) ;; +esac + +# Compute the target architecture. +# FIXME: Will need to canonicalize some values. +# FIXME: Should be in generally accessable place. +case $target in + *) arch=${target_cpu} ;; +esac +AC_SUBST(arch) + +# configure the subdirectories too +AC_CONFIG_SUBDIRS($configdirs) + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog new file mode 100644 index 00000000000..b3b7f8cfac9 --- /dev/null +++ b/sim/testsuite/d10v-elf/ChangeLog @@ -0,0 +1,84 @@ +1999-01-13 Jason Molenda (jsm@bugshack.cygnus.com) + + * t-sadd.s: New file. + * Makefile.in (TESTS): Add t-sadd. + +Mon Feb 16 09:20:57 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i (VEC_*): Define. + (DMAP_REG, DMAP_BASE, DMAP_MASK): Define. + (IMAP[01]_REG): Define. + + * t-rdt.s (test_tdt): New file. + + * t-dbt.s (test_dbt): New file. + + * Makefile.in (TESTS): Add t-rdt and t-dbt. + + +Fri Feb 13 16:21:13 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * t-sp.s: New test. + * Makefile.in (TESTS): Update. + +Wed Feb 11 17:58:50 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i: Update trap calls, func in r4, args in + r0... + (start): Force r0 to zero. + + * t-sub2w.s: Ditto. + +Tue Dec 9 10:41:44 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-rte.s (success): New file. + * Makefile.in: Update. + + * t-rep.s: Check rep repeats correct number of times. + +Fri Dec 5 10:11:18 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S. + + * t-trap.s: New file. + * Makefile.in (TESTS): Update. + +Thu Dec 4 16:56:55 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i: Add definitions for PSW bits. + + * t-mvtc.s: New file. + * Makefile.in (TESTS): Update. + +Wed Dec 3 16:35:24 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-rac.s: New files. + + * t-macros.i: Add macros for checking psw and 2w quantities. + + * Makefile.in (TESTS): Update. + +Tue Dec 2 11:01:36 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New + files. + + * Makefile.in: Update. + +Mon Nov 17 20:14:48 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-subi.s (test_subi): New file. + * Makefile.in: Update. + +Fri Nov 14 14:06:06 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-rep.s: New file. Test case of branch to RPT_E address. + +Mon Nov 10 19:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i (_start): New file. + * t-rachi.s: New file. + + * Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v + directory. + diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in new file mode 100644 index 00000000000..09d59ac7565 --- /dev/null +++ b/sim/testsuite/d10v-elf/Makefile.in @@ -0,0 +1,150 @@ +# Makefile for regression testing the GNU debugger. +# Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +build_canonical = @build@ +host_canonical = @host@ +target_canonical = @target@ +target_cpu = @target_cpu@ + + +SHELL = /bin/sh +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +TESTS = \ + exit47.ko \ + hello.hi \ + t-dbt.ok \ + t-mac.ok \ + t-mvtac.ok \ + t-mvtc.ok \ + t-msbu.ok \ + t-mulxu.ok \ + t-rac.ok \ + t-rachi.ok \ + t-rdt.ok \ + t-rep.ok \ + t-rte.ok \ + t-sadd.ok \ + t-sp.ok \ + t-sub2w.ok \ + t-sub.ok \ + t-subi.ok \ +# + +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/d10v/run ]; then \ + echo ../../../sim/d10v/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET=$(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET=$(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET=$(RUN_FOR_TARGET) + +clean: + rm -f $(TESTS) + rm -f *.run *.o + rm -f core *.core + +# Rules for running the tests + +.SUFFIXES: .ok .run .hi .ko .ti +.run.ok: + rm -f tmp-$* $*.hi + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $*.run > tmp-$* + echo 'Hello World!' | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko +.run.ti: + rm -f tmp-$* $*.ti + set +e ; \ + ulimit -t 5 ; \ + $(RUN_FOR_TARGET) $(RUNFLAGS_FOR_TARGET) $(INTFLAGS_FOR_TARGET) $*.run > tmp-$* + test `cat tmp-$* | wc -l` -eq 10 < /dev/null + test `grep Tick tmp-$* | wc -l` -eq 10 < /dev/null + mv tmp-$* $*.ti + + +# Rules for building the test +# Preference is for obtaining the executable (.run) from a prebuilt image + +.SUFFIXES: .uue .s .S .run +.uue.run: + head $* | grep $*.run > /dev/null + uudecode $*.uue +.run.u: + uuencode < $*.run $*.run > $*.u +.o.run: + $(LD_FOR_TARGET) $(LDFLAGS_FOR_TARGET) -o $*.run $*.o +.s.o: + $(AS_FOR_TARGET) $(ASFLAGS_FOR_TARGET) -I$(srcdir) $(srcdir)/$*.s -o $*.o +.S.o: + $(AS_FOR_TARGET) $(ASFLAGS_FOR_TARGET) -I$(srcdir) $(srcdir)/$*.S -o $*.o + + +Makefile: Makefile.in config.status + $(SHELL) ./config.status + +config.status: configure + $(SHELL) ./config.status --recheck diff --git a/sim/testsuite/d10v-elf/configure b/sim/testsuite/d10v-elf/configure new file mode 100755 index 00000000000..b9348bb1255 --- /dev/null +++ b/sim/testsuite/d10v-elf/configure @@ -0,0 +1,900 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.12 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; 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+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;; + *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*) + ac_configure_args="$ac_configure_args '$ac_arg'" ;; + *) ac_configure_args="$ac_configure_args $ac_arg" ;; + esac +done + +# NLS nuisances. +# Only set these to C if already set. These must not be set unconditionally +# because not all systems understand e.g. LANG=C (notably SCO). +# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'! +# Non-C LC_CTYPE values break the ctype check. +if test "${LANG+set}" = set; then LANG=C; export LANG; fi +if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi +if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi +if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi + +# confdefs.h avoids OS command line length limits that DEFS can exceed. +rm -rf conftest* confdefs.h +# AIX cpp loses on an empty file, so make sure it contains at least a newline. +echo > confdefs.h + +# A filename unique to this package, relative to the directory that +# configure is in, which we can look for to find out if srcdir is correct. +ac_unique_file=Makefile.in + +# Find the source files, if location was not specified. +if test -z "$srcdir"; then + ac_srcdir_defaulted=yes + # Try the directory containing this script, then its parent. + ac_prog=$0 + ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'` + test "x$ac_confdir" = "x$ac_prog" && ac_confdir=. + srcdir=$ac_confdir + if test ! -r $srcdir/$ac_unique_file; then + srcdir=.. + fi +else + ac_srcdir_defaulted=no +fi +if test ! -r $srcdir/$ac_unique_file; then + if test "$ac_srcdir_defaulted" = yes; then + { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; } + else + { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; } + fi +fi +srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'` + +# Prefer explicitly selected file to automatically selected ones. +if test -z "$CONFIG_SITE"; then + if test "x$prefix" != xNONE; then + CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" + else + CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" + fi +fi +for ac_site_file in $CONFIG_SITE; do + if test -r "$ac_site_file"; then + echo "loading site script $ac_site_file" + . "$ac_site_file" + fi +done + +if test -r "$cache_file"; then + echo "loading cache $cache_file" + . $cache_file +else + echo "creating cache $cache_file" + > $cache_file +fi + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then + # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu. + if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then + ac_n= ac_c=' +' ac_t=' ' + else + ac_n=-n ac_c= ac_t= + fi +else + ac_n= ac_c='\c' ac_t= +fi + + + +CC=${CC-cc} + +ac_aux_dir= +for ac_dir in `cd $srcdir;pwd`/../../.. $srcdir/`cd $srcdir;pwd`/../../..; do + if test -f $ac_dir/install-sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f $ac_dir/install.sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + fi +done +if test -z "$ac_aux_dir"; then + { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../../.. $srcdir/`cd $srcdir;pwd`/../../.." 1>&2; exit 1; } +fi +ac_config_guess=$ac_aux_dir/config.guess +ac_config_sub=$ac_aux_dir/config.sub +ac_configure=$ac_aux_dir/configure # This should be Cygnus configure. + + +# Do some error checking and defaulting for the host and target type. +# The inputs are: +# configure --host=HOST --target=TARGET --build=BUILD NONOPT +# +# The rules are: +# 1. You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:572: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`$ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`$ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:593: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`$ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:611: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`$ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS <<EOF +#! /bin/sh +# Generated automatically by configure. +# Run this file to recreate the current configuration. +# This directory was configured as follows, +# on host `(hostname || uname -n) 2>/dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.12" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir + +trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS <<EOF + +# Protect against being on the right side of a sed subst in config.status. +sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g; + s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@CC@%$CC%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <<EOF + +CONFIG_FILES=\${CONFIG_FILES-"Makefile"} +EOF +cat >> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +EOF +cat >> $CONFIG_STATUS <<EOF + +EOF +cat >> $CONFIG_STATUS <<\EOF + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/sim/testsuite/d10v-elf/configure.in b/sim/testsuite/d10v-elf/configure.in new file mode 100644 index 00000000000..e74389e551e --- /dev/null +++ b/sim/testsuite/d10v-elf/configure.in @@ -0,0 +1,19 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +dnl FIXME - think of a truly uniq file to this directory +AC_INIT(Makefile.in) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) +AC_CANONICAL_SYSTEM + +AC_SUBST(target_cpu) + + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/d10v-elf/exit47.s b/sim/testsuite/d10v-elf/exit47.s new file mode 100644 index 00000000000..93e466465e2 --- /dev/null +++ b/sim/testsuite/d10v-elf/exit47.s @@ -0,0 +1,4 @@ +.include "t-macros.i" + + start + exit47 diff --git a/sim/testsuite/d10v-elf/hello.s b/sim/testsuite/d10v-elf/hello.s new file mode 100644 index 00000000000..d060c89adb0 --- /dev/null +++ b/sim/testsuite/d10v-elf/hello.s @@ -0,0 +1,5 @@ + .include "t-macros.i" + + start + hello + exit0 diff --git a/sim/testsuite/d10v-elf/loop.s b/sim/testsuite/d10v-elf/loop.s new file mode 100644 index 00000000000..e1371e4d951 --- /dev/null +++ b/sim/testsuite/d10v-elf/loop.s @@ -0,0 +1,6 @@ + .text + .globl _start + +_start: + bra _start + nop diff --git a/sim/testsuite/d10v-elf/t-dbt.s b/sim/testsuite/d10v-elf/t-dbt.s new file mode 100644 index 00000000000..8c518475be7 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-dbt.s @@ -0,0 +1,33 @@ +.include "t-macros.i" + + start + + PSW_BITS = PSW_DM + +;;; Blat our DMAP registers so that they point at on-chip imem + + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + +;;; Patch the interrupt vector's dbt entry with a jmp to success + + ldi r4, #trap + ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + +test_dbt: + dbt -> nop + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 + + .data +trap: ldi r1, success@word + jmp r1 diff --git a/sim/testsuite/d10v-elf/t-mac.s b/sim/testsuite/d10v-elf/t-mac.s new file mode 100644 index 00000000000..364f61531d1 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-mac.s @@ -0,0 +1,71 @@ +.include "t-macros.i" + + start + + ;; clear FX + loadpsw2 0x8005 + loadacc2 a1 0x7f 0xffff 0xffff + load r8 0xffff + load r9 0x8001 +test_macu1: + MACU a1, r9, r8 + checkacc2 1 a1 0x80 0x8000 0x7FFE + + ;; set FX + loadpsw2 0x8085 + loadacc2 a1 0x7f 0xffff 0xffff + load r8 0xffff + load r9 0x8001 +test_macu2: + MACU a1, r9, r8 + checkacc2 2 a1 0x81 0x0000 0xfffd + + + + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x7FFF +test_macsu1: + MACSU a1, r9, r8 + checkacc2 3 a1 0x80 0x7FFE 0x8000 + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x7FFF +test_macsu2: + MACSU a1, r9, r8 + checkacc2 4 a1 0x80 0xfffd 0x0001 + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_macsu3: + MACSU a1, r9, r8 + checkacc2 5 a1 0x7F 0x8001 0x7FFE + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x8001 +test_macsu4: + MACSU a1, r9, r8 + checkacc2 6 a1 0x7f 0x0002 0xFFFD + + exit0 + diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i new file mode 100644 index 00000000000..2f54d1c0381 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-macros.i @@ -0,0 +1,170 @@ + .macro start + .text + .align 2 + .globl _start +_start: + ldi r0, 0 + .endm + + + .macro exit47 + ldi r4, 1 + ldi r0, 47 + trap 15 + .endm + + + .macro exit0 + ldi r4, 1 + ldi r0, 0 + trap 15 + .endm + + + .macro load reg val + ldi \reg, #\val + .endm + + + .macro load2w reg hi lo + ld2w \reg, @(1f,r0) + .data + .align 2 +1: .short \hi + .short \lo + .text + .endm + + + .macro check exit reg val + cmpeqi \reg, #\val + brf0t 1f +0: ldi r4, 1 + ldi r0, \exit + trap 15 +1: + .endm + + + .macro check2w2 exit reg hi lo + st2w \reg, @(1f,r0) + ld r2, @(1f, r0) + cmpeqi r2, #\hi + brf0f 0f + ld r2, @(1f + 2, r0) + cmpeqi r2, #\lo + brf0f 0f + bra 2f +0: ldi r4, 1 + ldi r0, \exit + trap 15 + .data + .align 2 +1: .long 0 + .text +2: + .endm + + + .macro loadacc2 acc guard hi lo + ldi r2, #\lo + mvtaclo r2, \acc + ldi r2, #\hi + mvtachi r2, \acc + ldi r2, #\guard + mvtacg r2, \acc + .endm + + + .macro checkacc2 exit acc guard hi lo + ldi r2, #\guard + mvfacg r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\hi + mvfachi r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\lo + mvfaclo r3, \acc + cmpeq r2, r3 + brf0f 0f + bra 4f +0: ldi r4, 1 + ldi r0, \exit + trap 15 +4: + .endm + + + .macro loadpsw2 val + ldi r2, #\val + mvtc r2, cr0 + .endm + + + .macro checkpsw2 exit val + mvfc r2, cr0 + cmpeqi r2, #\val + brf0t 1f + ldi r4, 1 + ldi r0, \exit + trap 15 +1: + .endm + + + .macro hello + ;; 4:write (1, string, strlen (string)) + ldi r4, 4 + ldi r0, 1 + ldi r1, 1f + ldi r2, 2f-1f-1 + trap 15 + .section .rodata +1: .string "Hello World!\n" +2: .align 2 + .text + .endm + + + PSW_SM = 0x8000 + PSW_01 = 0x4000 + PSW_EA = 0x2000 + PSW_DB = 0x1000 + PSW_DM = 0x0800 + PSW_IE = 0x0400 + PSW_RP = 0x0200 + PSW_MD = 0x0100 + PSW_FX = 0x0080 + PSW_ST = 0x0040 + PSW_10 = 0x0020 + PSW_11 = 0x0010 + PSW_F0 = 0x0008 + PSW_F1 = 0x0004 + PSW_14 = 0x0002 + PSW_C = 0x0001 + + +;;; + + DMAP_MASK = 0x3fff + DMAP_BASE = 0x8000 + DMAP_REG = 0xff04 + + IMAP0_REG = 0xff00 + IMAP1_REG = 0xff02 + + MAP_INSN = 0x1000 + +;;; + + VEC_RI = 0x3fc00 + VEC_BAE = 0x3fc04 + VEC_RIE = 0x3fc08 + VEC_AE = 0x3fc0c + VEC_TRAP = 0x3fc10 + VEC_DBT = 0x3ff50 + VEC_SDBT = 0x3fff4 + VEC_DBI = 0x3ff58 + VEC_EI = 0x3ff5c diff --git a/sim/testsuite/d10v-elf/t-msbu.s b/sim/testsuite/d10v-elf/t-msbu.s new file mode 100644 index 00000000000..04276cc25d9 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-msbu.s @@ -0,0 +1,28 @@ +.include "t-macros.i" + + start + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu1: + MSBU a1, r9, r8 + checkacc2 1 a1 0X7F 0x7FFF 0x8000 + + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu2: + MSBU a1, r9, r8 + checkacc2 2 a1 0X7E 0xFFFF 0x0001 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-mulxu.s b/sim/testsuite/d10v-elf/t-mulxu.s new file mode 100644 index 00000000000..a8e6ffc8d49 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-mulxu.s @@ -0,0 +1,28 @@ +.include "t-macros.i" + + start + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_mulxu1: + MULXU a1, r9, r8 + checkacc2 1 a1 0x00 0x8000 0x7FFF + + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_mulxu2: + MULXU a1, r9, r8 + checkacc2 2 a1 0x01 0x0000 0xFFFE + + exit0 diff --git a/sim/testsuite/d10v-elf/t-mvtac.s b/sim/testsuite/d10v-elf/t-mvtac.s new file mode 100644 index 00000000000..68452dc827a --- /dev/null +++ b/sim/testsuite/d10v-elf/t-mvtac.s @@ -0,0 +1,19 @@ +.include "t-macros.i" + + start + + ldi r8, 0xbeef + mvtaclo r8, a0 + checkacc2 1 a0 0xff 0xffff 0xbeef + + mvtacg r0, a0 + checkacc2 2 a0 0x00 0xffff 0xbeef + + ldi r8, 0xdead + mvtachi r8, a0 + checkacc2 3 a0 0xff 0xdead 0xbeef + + loadacc2 a1 0xfe 0xbeef 0xdead + checkacc2 4 a1 0xfe 0xbeef 0xdead + + exit0 diff --git a/sim/testsuite/d10v-elf/t-mvtc.s b/sim/testsuite/d10v-elf/t-mvtc.s new file mode 100644 index 00000000000..cbf9308444a --- /dev/null +++ b/sim/testsuite/d10v-elf/t-mvtc.s @@ -0,0 +1,81 @@ +.include "t-macros.i" + + start + +;;; Try out each bit in the PSW + + loadpsw2 PSW_SM + checkpsw2 1 PSW_SM + + loadpsw2 PSW_01 + checkpsw2 2 0 ;; PSW_01 + + loadpsw2 PSW_EA + checkpsw2 3 PSW_EA + + loadpsw2 PSW_DB + checkpsw2 4 PSW_DB + + loadpsw2 PSW_DM + checkpsw2 5 PSW_DM + + loadpsw2 PSW_IE + checkpsw2 6 PSW_IE + + loadpsw2 PSW_RP + checkpsw2 7 PSW_RP + + loadpsw2 PSW_MD + checkpsw2 8 PSW_MD + + loadpsw2 PSW_FX|PSW_ST + checkpsw2 9 PSW_FX|PSW_ST + + ;; loadpsw2 PSW_ST + ;; checkpsw2 10 + + loadpsw2 PSW_10 + checkpsw2 11 0 ;; PSW_10 + + loadpsw2 PSW_11 + checkpsw2 12 0 ;; PSW_11 + + loadpsw2 PSW_F0 + checkpsw2 13 PSW_F0 + + loadpsw2 PSW_F1 + checkpsw2 14 PSW_F1 + + loadpsw2 PSW_14 + checkpsw2 15 0 ;; PSW_14 + + loadpsw2 PSW_C + checkpsw2 16 PSW_C + + +;;; Check that bit 0 (LSB) of the MOD_E & MOD_S registers are stuck at ZERO. + + ldi r6, #0xdead + mvtc r6, cr10 + ldi r6, #0xbeef + mvtc r6, cr11 + + mvfc r7, cr10 + check 17 r7 0xdeac + mvfc r7, cr11 + check 18 r7 0xbeee + +;;; Check that certain bits of the DPSW and BPSW are hardwired to zero + + ldi r6, 0xffff + mvtc r6, bpsw + mvfc r7, bpsw + check 18 r7 0xbfcd + + ldi r6, 0xffff + mvtc r6, dpsw + mvfc r7, dpsw + check 18 r7 0xbfcd + + + exit0 diff --git a/sim/testsuite/d10v-elf/t-rac.s b/sim/testsuite/d10v-elf/t-rac.s new file mode 100644 index 00000000000..f2123116c64 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rac.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + ;; clear FX + loadpsw2 0x8004 + loadacc2 a0 0x80 0x0000 0x0000 + loadacc2 a1 0x00 0x0000 0x5000 + load r10 0x0123 + load r11 0x4567 +test_rac1: + RAC r10, a0, #-2 + checkpsw2 1 0x8008 + check2w2 2 r10 0x8000 0x0000 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-rachi.s b/sim/testsuite/d10v-elf/t-rachi.s new file mode 100644 index 00000000000..ed901959469 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rachi.s @@ -0,0 +1,28 @@ +.include "t-macros.i" + + start + + loadacc2 a0 0x00 0x7FFF 0x8000 +test_rachi_1: + rachi r4, a0, 0 + check 1 r4 0x7FFF + + + loadacc2 a0 0xFF 0x8000 0x1000 +test_rachi_2: + rachi r4, a0, 0 + check 2 r4 0x8000 + + + loadacc2 a0 0x00 0x1000 0xA000 +test_rachi_3: + rachi r4, a0, 0 + check 3 r4 0x1001 + + + loadacc2 a0 0xFF 0xA000 0x7FFF +test_rachi_4: + rachi r4, a0, 0 + check 4 r4 0xa000 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-rdt.s b/sim/testsuite/d10v-elf/t-rdt.s new file mode 100644 index 00000000000..661b583bb13 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rdt.s @@ -0,0 +1,18 @@ +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, dpc + ldi r6, #PSW_BITS + mvtc r6, dpsw + +test_rdt: + RTD + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 diff --git a/sim/testsuite/d10v-elf/t-rep.s b/sim/testsuite/d10v-elf/t-rep.s new file mode 100644 index 00000000000..cea3ea8251d --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rep.s @@ -0,0 +1,45 @@ +.include "t-macros.i" + + start + + + + ;; Check that the instruction @REP_E is executed when it + ;; is reached using a branch instruction + + ldi r2, 1 +test_rep_1: + rep r2, end_rep_1 + nop || nop + nop || nop + nop || nop + nop || nop + ldi r3, 46 + bra end_rep_1 + ldi r3, 42 +end_rep_1: + addi r3, 1 + + check 1 r3 47 + + + ;; Check that the loop is executed the correct number of times + + ldi r2, 10 + ldi r3, 0 + ldi r4, 0 +test_rep_2: + rep r2, end_rep_2 + nop || nop + nop || nop + nop || nop + nop || nop + nop || nop + addi r3, 1 +end_rep_2: + addi r4, 1 + + check 2 r3 10 + check 3 r4 10 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-rte.s b/sim/testsuite/d10v-elf/t-rte.s new file mode 100644 index 00000000000..5ce31ddbf41 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rte.s @@ -0,0 +1,18 @@ +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, bpc + ldi r6, #PSW_BITS + mvtc r6, bpsw + +test_rte: + RTE + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 diff --git a/sim/testsuite/d10v-elf/t-sadd.s b/sim/testsuite/d10v-elf/t-sadd.s new file mode 100644 index 00000000000..f3e4ebe3da4 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-sadd.s @@ -0,0 +1,38 @@ +.include "t-macros.i" + + start + + PSW_BITS = PSW_FX|PSW_ST|PSW_SM + loadpsw2 PSW_BITS + + ;; Test normal sadd + + loadacc2 a0 0x00 0x7fff 0xffff + loadacc2 a1 0xff 0x8000 0x0000 + sadd a1, a0 + checkacc2 1 a0 0x00 0x7fff 0xffff + checkacc2 2 a1 0xff 0x8000 0x7fff + + ;; Test overflow + + loadacc2 a0 0x00 0x0000 0x0000 + loadacc2 a1 0x01 0x8000 0x0000 + sadd a1, a0 + checkacc2 3 a0 0x00 0x0000 0x0000 + checkacc2 4 a1 0x00 0x7fff 0xffff + + loadacc2 a0 0x00 0xffff 0xffff + loadacc2 a1 0x00 0xffff 0xffff + sadd a1, a0 + checkacc2 5 a1 0x00 0x7fff 0xffff + checkacc2 6 a0 0x00 0xffff 0xffff + + ;; Test underflow + + loadacc2 a0 0x00 0x0000 0x0000 + loadacc2 a1 0x80 0x8000 0x0000 + sadd a1, a0 + checkacc2 7 a0 0x00 0x0000 0x0000 + checkacc2 8 a1 0xff 0x8000 0x0000 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-sp.s b/sim/testsuite/d10v-elf/t-sp.s new file mode 100644 index 00000000000..84f9ad48676 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-sp.s @@ -0,0 +1,17 @@ +.include "t-macros.i" + + start + +;;; Read/Write values to SPU/SPI + + loadpsw2 0 + ldi sp, 0xdead + loadpsw2 PSW_SM + ldi sp, 0xbeef + + loadpsw2 0 + check 1 sp 0xdead + loadpsw2 PSW_SM + check 2 sp 0xbeef + + exit0 diff --git a/sim/testsuite/d10v-elf/t-sub.s b/sim/testsuite/d10v-elf/t-sub.s new file mode 100644 index 00000000000..26d0a3a1c9a --- /dev/null +++ b/sim/testsuite/d10v-elf/t-sub.s @@ -0,0 +1,42 @@ +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_sub s x y r c + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + ;; subtract + ldi r10,#\x + ldi r11,#\y + sub r10, r11 + ;; verify result + ldi r12, #\r + cmpeq r10, r12 + brf0t 1f + ldi r6, 1 + ldi r2, #\s + trap 15 +1: + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r6, 1 + ldi r2, #\s + trap 15 +1: + .endm + +check_sub 1 0x0000 0x0000 0x0000 1 +check_sub 2 0x0000 0x0001 0xffff 0 +check_sub 3 0x0001 0x0000 0x0001 1 +check_sub 4 0x0001 0x0001 0x0000 1 +check_sub 5 0x0000 0x8000 0x8000 0 +check_sub 6 0x8000 0x0001 0x7fff 1 +check_sub 7 0x7fff 0x7fff 0x0000 1 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-sub2w.s b/sim/testsuite/d10v-elf/t-sub2w.s new file mode 100644 index 00000000000..9f1bbb7321e --- /dev/null +++ b/sim/testsuite/d10v-elf/t-sub2w.s @@ -0,0 +1,57 @@ +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_sub2w s x y r c v + + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + + ;; load opnds + ld2w r6, @(1f,r0) + ld2w r8, @(2f,r0) + .data +1: .long \x +2: .long \y + .text + + ;; subtract + SUB2W r6, r8 + + ;; verify result + ld2w r10, @(1f,r0) + .data +1: .long \r + .text + cmpeq r6, r10 + brf0f 2f + cmpeq r7, r11 + brf0t 3f +2: ldi r4, 1 + ldi r0, \s + trap 15 +3: + + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r4, 1 + ldi r0, \s + trap 15 +1: + .endm + +check_sub2w 1 0x00000000 0x00000000 0x00000000 1 0 +check_sub2w 2 0x00000000 0x00000001 0xffffffff 0 0 +check_sub2w 3 0x00000001 0x00000000 0x00000001 1 0 +check_sub2w 3 0x00000001 0x00000001 0x00000000 1 0 +check_sub2w 5 0x00000000 0x80000000 0x80000000 0 1 +check_sub2w 6 0x80000000 0x00000001 0x7fffffff 1 1 +check_sub2w 7 0x7fffffff 0x7fffffff 0x00000000 1 0 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-subi.s b/sim/testsuite/d10v-elf/t-subi.s new file mode 100644 index 00000000000..81faad5ec24 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-subi.s @@ -0,0 +1,39 @@ +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_subi s x y r c v + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + ;; subtract + ldi r10,#\x + SUBI r10,#\y + ;; verify result + ldi r11, #\r + cmpeq r10, r11 + brf0t 1f + ldi r6, 1 + ldi r2, \s + trap 15 +1: + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r6, 1 + ldi r2, \s + trap 15 +1: + .endm + + check_subi 1 0000 0x0000 0xfff0 00 ;; 0 - 0x10 + check_subi 2 0x0000 0x0001 0xffff 0 0 + check_subi 3 0x0001 0x0000 0xfff1 0 0 + check_subi 4 0x0001 0x0001 0x0000 1 0 + check_subi 5 0x8000 0x0001 0x7fff 1 1 + + exit0 diff --git a/sim/testsuite/d10v-elf/t-trap.s b/sim/testsuite/d10v-elf/t-trap.s new file mode 100644 index 00000000000..6ac4ae01ef8 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-trap.s @@ -0,0 +1,5 @@ +.include "t-macros.i" + + start + + exit47 diff --git a/sim/testsuite/d30v-elf/ChangeLog b/sim/testsuite/d30v-elf/ChangeLog new file mode 100644 index 00000000000..6d8369f432b --- /dev/null +++ b/sim/testsuite/d30v-elf/ChangeLog @@ -0,0 +1,60 @@ +1999-01-12 Frank Ch. Eigler <fche@cygnus.com> + + * do-flags.S: Added one old, one new regression test. + +1999-01-11 Frank Ch. Eigler <fche@cygnus.com> + + * do-flags.S: New test for parallel PSW update conflicts. + * Makefile.in (TESTS): Run it. + +1999-01-07 Frank Ch. Eigler <fche@cygnus.com> + + * do-2wordops.S: New test for sign-extension by ld2h. + +1998-12-08 Frank Ch. Eigler <fche@cygnus.com> + + * do-2wordops.S: New test for double-word load-like operations. + +1998-12-04 Frank Ch. Eigler <fche@cygnus.com> + + * do-shifts.S: Update an older test case. + +1998-12-03 Frank Ch. Eigler <fche@cygnus.com> + + * do-shifts.S: New test for more SRC shift counts. + +1998-11-22 Frank Ch. Eigler <fche@cygnus.com> + + * do-shifts.S: New test for large SRC shift counts. + +1998-11-12 Frank Ch. Eigler <fche@cygnus.com> + + * br-djsr.S: New test for new R62-update timing. + +1998-11-06 Frank Ch. Eigler <fche@cygnus.com> + + * do-shifts.S: Add test for large mvfacc shifts. + +Tue Oct 13 10:54:51 EDT 1998 Frank Ch. Eigler <fche@cygnus.com> + + * Makefile.in (TESTS): Added do-shifts test case. + * do-shifts.S: New file. + +Wed Apr 29 12:49:00 1998 Frank Ch. Eigler <fche@cygnus.com> + + * ls-modaddr.S: New test for modular addressing. + * Makefile.in: Run it. + +Wed Sep 3 14:33:35 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * Makefile.in (.S.run): Replace .d30v with .run. + +Wed Apr 2 14:10:43 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * Makefile.in (.d30v.ko): Limit the cpu time to 5 seconds. + +Wed Mar 26 11:13:42 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * Makefile.in (.d30v.ko): Disable the shell's exit-on-error which + is enabled by BSD style make. + diff --git a/sim/testsuite/d30v-elf/Makefile.in b/sim/testsuite/d30v-elf/Makefile.in new file mode 100644 index 00000000000..6317fe4fba8 --- /dev/null +++ b/sim/testsuite/d30v-elf/Makefile.in @@ -0,0 +1,217 @@ +# Makefile for regression testing the GNU debugger. +# Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +build_canonical = @build@ +host_canonical = @host@ +target_canonical = @target@ +target_cpu = @target_cpu@ + + +SHELL = /bin/sh +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +EXPECT = `if [ -f $${rootme}/../../expect/expect ] ; then \ + echo $${rootme}/../../expect/expect ; \ + else echo expect ; fi` + +RUNTEST = $(RUNTEST_FOR_TARGET) + +RUNTESTFLAGS = + +RUNTEST_FOR_TARGET = `\ + if [ -f $${srcdir}/../../../dejagnu/runtest ]; then \ + echo $${srcdir}/../../../dejagnu/runtest; \ + else \ + if [ "$(host_canonical)" = "$(target_canonical)" ]; then \ + echo runtest; \ + else \ + t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \ + fi; \ + fi` + + +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/${target_cpu}/run ]; then \ + echo ../../../sim/${target_cpu}/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + +TESTS = \ + em-e0.ok \ + em-e47.ko \ + em-pstr.hi \ + em-pchr.hi \ + \ + ls-ld2h.ko \ + ls-ld2w.ko \ + ls-ld4bh.ko \ + ls-ld4bhu.ko \ + ls-ldb.ko \ + ls-ldbu.ko \ + ls-ldh.ko \ + ls-ldhh.ko \ + ls-ldhu.ko \ + ls-ldw.ko \ + ls-moddec.ko \ + ls-modinc.ko \ + ls-modaddr.ok \ + ls-st2h.hi \ + ls-st2w.hi \ + ls-st4hb.hi \ + ls-stb.hi \ + ls-sth.hi \ + ls-sthh.hi \ + ls-stw.hi \ + \ + br-bra.ok \ + br-bratnz.ok \ + br-bratzr.ok \ + br-bsr.ok \ + br-dbra.ko \ + br-djmp.ko \ + br-djsr.ok \ + \ + os-dbt.ok \ + do-flags.ok \ + do-shifts.ok \ + do-2wordops.ok \ + \ + trap.ok + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET = $(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET = $(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET) + + + +# Rules for running all the tests, put into three types +# exit success, exit fail, print "Hello World" + +.u.log: + uudecode $*.u + $(RUN_FOR_TARGET) $* > $*.log + + +# Rules for running the tests + +.SUFFIXES: .u .ok .run .hi .ko +.run.ok: + rm -f tmp-$* $*.hi + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + echo "Hello World" | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko + + +# Rules for building all the tests and packing them into +# uuencoded files. + +uuencode: em-pstr.u em-e0.u em-e47.u em-pchr.u + +.SUFFIXES: .u .S .run +.S.u: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.S -o $*.o + $(LD_FOR_TARGET) -o $* $*.o + uuencode < $* $* > $*.u + rm -f $*.o $* +.S.run: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.S -o $*.o + $(LD_FOR_TARGET) -o $*.run $*.o + rm -f $*.o $* + + + +# +# Standard +# +clean mostlyclean: + -rm -f *~ core *.o a.out *.x *.grt + rm -f $(TESTS) +# if [ x"${SUBDIRS}" != x ] ; then \ +# for dir in ${SUBDIRS}; \ +# do \ +# echo "$$dir:"; \ +# if [ -d $$dir ]; then \ +# (cd $$dir; $(MAKE) clean); \ +# fi; \ +# done ; \ +# else true; fi + +distclean maintainer-clean realclean: clean + -rm -f *~ core + -rm -f Makefile config.status *-init.exp + -rm -fr *.log summary detail *.plog *.sum *.psum site.* +# if [ x"${SUBDIRS}" != x ] ; then \ +# for dir in ${SUBDIRS}; \ +# do \ +# echo "$$dir:"; \ +# if [ -d $$dir ]; then \ +# (cd $$dir; $(MAKE) distclean); \ +# fi; \ +# done ; \ +# else true; fi + +Makefile : Makefile.in config.status + $(SHELL) config.status + +config.status: configure + $(SHELL) config.status --recheck diff --git a/sim/testsuite/d30v-elf/br-bra.S b/sim/testsuite/d30v-elf/br-bra.S new file mode 100644 index 00000000000..7758b82ba78 --- /dev/null +++ b/sim/testsuite/d30v-elf/br-bra.S @@ -0,0 +1,12 @@ + add r3, r0, dest1 + sub r3, r3, off1 +off1: + bra r3 + + .align 4 +dest1: + bra dest2 + + .align 5 +dest2: + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/br-bratnz.S b/sim/testsuite/d30v-elf/br-bratnz.S new file mode 100644 index 00000000000..cea048a5b4b --- /dev/null +++ b/sim/testsuite/d30v-elf/br-bratnz.S @@ -0,0 +1,12 @@ + add r3, r0, dest1 + sub r3, r3, off1 +off1: + bratnz r3, r3 + + .align 4 +dest1: + bratnz r0, dest2 + .long 0x0e000004, 0x00f00000 + + .align 5 +dest2: diff --git a/sim/testsuite/d30v-elf/br-bratzr.S b/sim/testsuite/d30v-elf/br-bratzr.S new file mode 100644 index 00000000000..783336eae85 --- /dev/null +++ b/sim/testsuite/d30v-elf/br-bratzr.S @@ -0,0 +1,12 @@ + add r3, r0, dest1 + sub r3, r3, off1 +off1: + bratzr r2, r3 + + .align 4 +dest1: + bratzr r3, dest2 + .long 0x0e000004, 0x00f00000 + + .align 5 +dest2: diff --git a/sim/testsuite/d30v-elf/br-bsr.S b/sim/testsuite/d30v-elf/br-bsr.S new file mode 100644 index 00000000000..7629f9765b7 --- /dev/null +++ b/sim/testsuite/d30v-elf/br-bsr.S @@ -0,0 +1,12 @@ + # verify that the return address is set correctly + add r2, r0, 1 + add r3, r0, dest1 + sub r3, r3, off1 +off1: + bsr r3 || nop +ret1: + + .align 5 +dest1: + sub r2, r62, ret1 + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/br-dbra.S b/sim/testsuite/d30v-elf/br-dbra.S new file mode 100644 index 00000000000..887c59fb4ee --- /dev/null +++ b/sim/testsuite/d30v-elf/br-dbra.S @@ -0,0 +1,83 @@ +# perform a delayed branch 47 instructions later + add r3, r0, 47 + srl r3, r3, -3 + dbra r3, dest + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + +.align 4 +dest: + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/br-djmp.S b/sim/testsuite/d30v-elf/br-djmp.S new file mode 100644 index 00000000000..01af9967f6a --- /dev/null +++ b/sim/testsuite/d30v-elf/br-djmp.S @@ -0,0 +1,83 @@ +# perform a delayed jump 47 instructions later + add r3, r0, insn47 + djmp r3, dest + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop +insn47: # actually 45 + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + +.align 4 +dest: + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/br-djsr.S b/sim/testsuite/d30v-elf/br-djsr.S new file mode 100644 index 00000000000..87d47d204b1 --- /dev/null +++ b/sim/testsuite/d30v-elf/br-djsr.S @@ -0,0 +1,79 @@ + # Test macro + + .macro assert reg,value + cmpeq f0,\reg,\value + bra/fx fail + .endm + + + # PR 18230 + + add r62,r0,0xffffffff || nop + add r1,r0,24 || nop + djsr r1,test_end + add r2,r0,r62 +test_end: nop + + assert r2, 0x00000030 + assert r62, 0x00000030 + + +# check return address correctly set by a djsr insn + + add r3, r0, last + sub r3, r3, start +start: + djsr r3, dest + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop +last: + add r2, r2, 1 || nop +nexti: + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + add r2, r2, 1 || nop + +.align 4 +dest: + + assert r62,nexti + + + + # all okay + bra ok + +ok: + add r2, r0, 0 + .long 0x0e000004 + nop + +fail: + add r2, r0, 47 + .long 0x0e000004 + nop diff --git a/sim/testsuite/d30v-elf/configure b/sim/testsuite/d30v-elf/configure new file mode 100755 index 00000000000..94518a0c16b --- /dev/null +++ b/sim/testsuite/d30v-elf/configure @@ -0,0 +1,833 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.10 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; then + eval "$ac_prev=\$ac_option" + ac_prev= + continue + fi + + case "$ac_option" in + -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;; + *) ac_optarg= ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case "$ac_option" in + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir="$ac_optarg" ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build="$ac_optarg" ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file="$ac_optarg" ;; + + -datadir | --datadir | --datadi | --datad | --data | --dat | --da) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \ + | --da=*) + datadir="$ac_optarg" ;; + + -disable-* | --disable-*) + ac_feature=`echo $ac_option|sed -e 's/-*disable-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + eval "enable_${ac_feature}=no" ;; + + -enable-* | --enable-*) + ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "enable_${ac_feature}='$ac_optarg'" ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; + -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ + | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ + | --exec=* | --exe=* | --ex=*) + exec_prefix="$ac_optarg" ;; + + -gas | --gas | --ga | --g) + # Obsolete; use --with-gas. + with_gas=yes ;; + + -help | --help | --hel | --he) + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat << EOF +Usage: configure [options] [host] +Options: [defaults in brackets after descriptions] +Configuration: + --cache-file=FILE cache test results in FILE + --help print this message + --no-create do not create output files + --quiet, --silent do not print \`checking...' messages + --version print the version of autoconf that created configure +Directory and file names: + --prefix=PREFIX install architecture-independent files in PREFIX + [$ac_default_prefix] + --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX + [same as prefix] + --bindir=DIR user executables in DIR [EPREFIX/bin] + --sbindir=DIR system admin executables in DIR [EPREFIX/sbin] + --libexecdir=DIR program executables in DIR [EPREFIX/libexec] + --datadir=DIR read-only architecture-independent data in DIR + [PREFIX/share] + --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data in DIR + [PREFIX/com] + --localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var] + --libdir=DIR object code libraries in DIR [EPREFIX/lib] + --includedir=DIR C header files in DIR [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc in DIR [/usr/include] + --infodir=DIR info documentation in DIR [PREFIX/info] + --mandir=DIR man documentation in DIR [PREFIX/man] + --srcdir=DIR find the sources in DIR [configure dir or ..] + --program-prefix=PREFIX prepend PREFIX to installed program names + --program-suffix=SUFFIX append SUFFIX to installed program names + --program-transform-name=PROGRAM + run sed PROGRAM on installed program names +EOF + cat << EOF +Host type: + --build=BUILD configure for building on BUILD [BUILD=HOST] + --host=HOST configure for HOST [guessed] + --target=TARGET configure for TARGET [TARGET=HOST] +Features and packages: + --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) + --enable-FEATURE[=ARG] include FEATURE [ARG=yes] + --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] + --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) + --x-includes=DIR X include files are in DIR + --x-libraries=DIR X library files are in DIR +EOF + if test -n "$ac_help"; then + echo "--enable and --with options recognized:$ac_help" + fi + exit 0 ;; + + -host | --host | --hos | --ho) + ac_prev=host ;; + -host=* | --host=* | --hos=* | --ho=*) + host="$ac_optarg" ;; + + -includedir | --includedir | --includedi | --included | --include \ + | --includ | --inclu | --incl | --inc) + ac_prev=includedir ;; + -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ + | --includ=* | --inclu=* | --incl=* | --inc=*) + includedir="$ac_optarg" ;; + + -infodir | --infodir | --infodi | --infod | --info | --inf) + ac_prev=infodir ;; + -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) + infodir="$ac_optarg" ;; + + -libdir | --libdir | --libdi | --libd) + ac_prev=libdir ;; + -libdir=* | --libdir=* | --libdi=* | --libd=*) + libdir="$ac_optarg" ;; + + -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ + | --libexe | --libex | --libe) + ac_prev=libexecdir ;; + -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ + | --libexe=* | --libex=* | --libe=*) + libexecdir="$ac_optarg" ;; + + -localstatedir | --localstatedir | --localstatedi | --localstated \ + | --localstate | --localstat | --localsta | --localst \ + | --locals | --local | --loca | --loc | --lo) + ac_prev=localstatedir ;; + -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ + | --localstate=* | --localstat=* | --localsta=* | --localst=* \ + | --locals=* | --local=* | --loca=* | --loc=* | --lo=*) + localstatedir="$ac_optarg" ;; + + -mandir | --mandir | --mandi | --mand | --man | --ma | --m) + ac_prev=mandir ;; + -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) + mandir="$ac_optarg" ;; + + -nfp | --nfp | --nf) + # Obsolete; use --without-fp. + with_fp=no ;; + + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) + no_create=yes ;; + + -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) + no_recursion=yes ;; + + -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ + | --oldinclude | --oldinclud | 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ac_prev=program_suffix ;; + -program-suffix=* | --program-suffix=* | --program-suffi=* \ + | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) + program_suffix="$ac_optarg" ;; + + -program-transform-name | --program-transform-name \ + | --program-transform-nam | --program-transform-na \ + | --program-transform-n | --program-transform- \ + | --program-transform | --program-transfor \ + | --program-transfo | --program-transf \ + | --program-trans | --program-tran \ + | --progr-tra | --program-tr | --program-t) + ac_prev=program_transform_name ;; + -program-transform-name=* | --program-transform-name=* \ + | --program-transform-nam=* | --program-transform-na=* \ + | --program-transform-n=* | --program-transform-=* \ + | --program-transform=* | --program-transfor=* \ + | --program-transfo=* | --program-transf=* \ + | --program-trans=* | --program-tran=* \ + | --progr-tra=* | --program-tr=* | --program-t=*) + program_transform_name="$ac_optarg" ;; + + -q | -quiet | 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You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`$ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`$ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`$ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`$ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\(.*\)-\(.*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + sed -n "s/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=\${\1='\2'}/p" \ + >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS <<EOF +#! /bin/sh +# Generated automatically by configure. +# Run this file to recreate the current configuration. +# This directory was configured as follows, +# on host `(hostname || uname -n) 2>/dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.10" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir + +trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS <<EOF + +# Protect against being on the right side of a sed subst in config.status. +sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g; + s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@CC@%$CC%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g + +CEOF +EOF +cat >> $CONFIG_STATUS <<EOF + +CONFIG_FILES=\${CONFIG_FILES-"Makefile"} +EOF +cat >> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%.*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust relative srcdir, etc. for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" -f conftest.subs $ac_given_srcdir/$ac_file_in > $ac_file +fi; done +rm -f conftest.subs + + + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/sim/testsuite/d30v-elf/configure.in b/sim/testsuite/d30v-elf/configure.in new file mode 100644 index 00000000000..e74389e551e --- /dev/null +++ b/sim/testsuite/d30v-elf/configure.in @@ -0,0 +1,19 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +dnl FIXME - think of a truly uniq file to this directory +AC_INIT(Makefile.in) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) +AC_CANONICAL_SYSTEM + +AC_SUBST(target_cpu) + + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/d30v-elf/do-2wordops.S b/sim/testsuite/d30v-elf/do-2wordops.S new file mode 100644 index 00000000000..2fa92e62872 --- /dev/null +++ b/sim/testsuite/d30v-elf/do-2wordops.S @@ -0,0 +1,80 @@ + # Test macro + + .macro assert reg,value + cmpeq f0,\reg,\value + bra/fx fail + .endm + + .macro nassert reg,value + cmpne f0,\reg,\value + bra/fx fail + .endm + + + # PR 18452 - a.s + + add r1, r0, 0 + add r2,r0,0x11223344 + add r3,r0,0x8899aabb + nop ||mulx2h r0,r2,r3 + + assert r0, 0x0 + assert r1, 0x0 + + # test other double-word loads + + add r2,r0,data + ld2w r0,@(r2,0) + assert r0, 0x0 + assert r1, 0x0 + + add r2,r0,data + ld2h r0,@(r2,0) + assert r0, 0x0 + assert r1, 0x0 + + add r2,r0,data + ld4bh r0,@(r2,0) + assert r0, 0x0 + assert r1, 0x0 + + add r2,r0,data + ld4bhu r0,@(r2,0) + assert r0, 0x0 + assert r1, 0x0 + + + # PR 18679 - a.s + + ld2h r2, @(r0, b) + ld2h r4, @(r0, d) + assert r2, 0x00001111 + assert r3, 0xffff8899 + assert r4, 0x00001111 + assert r5, 0x00002222 + + + # all okay + + bra ok + +ok: + add r2, r0, 0 + .long 0x0e000004 + nop + +fail: + add r2, r0, 47 + .long 0x0e000004 + nop + + # some non-zero data +data: + .long 0x12345678 + .long 0x9abcdef0 + .long 0xdeadbeef + +b: + .word 0x11118899, 0x0 +d: + .word 0x11112222, 0x0 diff --git a/sim/testsuite/d30v-elf/do-flags.S b/sim/testsuite/d30v-elf/do-flags.S new file mode 100644 index 00000000000..25797e50359 --- /dev/null +++ b/sim/testsuite/d30v-elf/do-flags.S @@ -0,0 +1,241 @@ + # Test macro + + .macro assert reg,value + cmpeq f0,\reg,\value + bra/fx fail + .endm + + + # PR 15964 - a.s + + add r8,r0,0x7fff7fff ; + add r9,r0,0x55555555 ; + add r12,r0,0x11111111 ; + add r1,r0,0x80000011 ; for psw + mvtsys psw,r1 ||nop + addhhhh r12,r8,r9 ||addhlll r13,r12,r12 + mvfsys r20,psw ||nop + mvtsys psw,r1 || add r2,r8, r9 + mvfsys r21,psw ||nop + + assert r20, 0x80000000 + assert r21, 0x80000014 + + + # PR 15964 - b.s + + add r40,r0,0x7fffffff + add r41,r0,0x7fffffff + add r1,r0,0x80000000 ; for psw + mvtsys psw,r1,||nop + cmpeq f1,r40,r41,||cmpeq f0,r40,r41,; + mvfsys r42,psw + + assert r42, 0x80005000 + + + # PR 16993 - a.s + + add r8,r0,0x80005555 ; for psw + add r9,r0,0x80000000 ; for psw + add r40,r0,0x11111111 ; + add r41,r0,0x22222222 ; + add r42,r0,0x00000000 ; + mvtsys psw,r8 ||nop + mvtsys psw,r9 ||add r42,r40,r41,; + + mvfsys r10,psw + assert r10, 0x80000000 + + + # PR 16995 - b.s + + add r8,r0,0x80000000 ; for psw + add r9,r0,0x80005555 ; for psw + add r10,r0,0x00000000 ; + add r40,r0,0x11111111 ; + add r41,r0,0x22222222 ; + add r42,r0,0x00000000 ; + mvtsys psw,r8 ||nop + mvtsys psw,r9 ||add r42,r40,r41,; + + mvfsys r10,psw + assert r10, 0x80005544 + + + # PR 17006 - c.s + + add r8,r0,0x80005555 ; for psw + add r9,r0,0x80000000 ; for psw + add r10,r0,0x00000000 ; + add r40,r0,0x00000011 ; + add r41,r0,0x00000011 ; + mvtsys psw,r8 ||nop + mvtsys psw,r9 ||cmpeq f5,r40,r41,; + + mvfsys r10,psw + assert r10, 0x80000010 + + + # PR 17006 - d.s + + add r9,r0,0x80000000 ; for psw + add r40,r0,0x00000011 ; + add r41,r0,0x00000011 ; + nop ||nop + mvtsys psw, r9 || nop + nop ||nop + nop ||cmpeq f5,r40,r41,; + + mvfsys r10,psw + assert r10, 0x80000010 + + + # PR 17106 - a.s + + ; test 000 ; mvtsys(s=0) || sathl(s=0) prallel execution test + add r8,r0,0x80005555 ; for psw + add r9,r0,0x80000000 ; for psw + add r40,r0,0x00000044 ; + add r41,r0,0x00000008 ; + mvtsys psw,r8 ||nop + mvtsys psw,r9 ||sathl r30,r40,r41,; + mvfsys r20, psw ||nop + ;------------------------------- + ; test 001 ; mvtsys(s=0) || sathl(s=1) prallel execution test + _test_001: + add r40,r0,0x00004444 ; + add r41,r0,0x00000008 ; + mvtsys psw,r8 ||nop + mvtsys psw,r9 ||sathl r31,r40,r41,; + mvfsys r21,psw ||nop + ;------------------------------- + ; test 002 ; mvtsys(s=1) || sathl(s=0) prallel execution test + add r8,r0,0x80000000 ; for psw + add r9,r0,0x80005555 ; for psw + add r40,r0,0x00000044 ; + add r41,r0,0x00000008 ; + mvtsys psw,r8 ||nop + mvtsys psw,r9 ||sathl r32,r40,r41,; + mvfsys r22,psw ||nop + ;------------------------------- + ; test 003 ; mvtsys(s=1) || sathl(s=1) prallel execution test + ; init-reg + add r40,r0,0x00004444 ; + add r41,r0,0x00000008 ; + mvtsys psw,r8 ||nop + mvtsys psw,r9 ||sathl r33,r40,r41,; + mvfsys r23,psw ||nop + + assert r20, 0x80000000 + assert r21, 0x80000040 + assert r22, 0x80005555 + assert r23, 0x80005515 + + + # PR 18288 - a.s + + ;------------------------------------------------------------------------ + ; mvtsys (C =1, V= VA = 0) || addc (C= V= VA =0) + ;------------------------------------------------------------------------ + test_000b: + add r1,r0,1 ||nop ; set C bit + mvtsys psw r0 ||nop + mvtsys psw r1 ||addc r20,r0,1 + mvfsys r10,psw ||nop + ; C changed in MU is not used in IU. + ; IU prevail for resulting C. + ;------------------------------------------------------------------------ + ; mvtsys (V =1, C = VA = 0) || add (C= V= VA =0) + ;------------------------------------------------------------------------ + test_001b: + add r1,r0,0x10 ||nop ; set V bit + mvtsys psw r0 ||nop + mvtsys psw r1 ||add r0,r0,r0 + mvfsys r11,psw ||nop + ; IU prevail for resulting V. + ;------------------------------------------------------------------------ + ; mvtsys (V = C= VA = 0) || add (C=0,V= VA =1) + ;------------------------------------------------------------------------ + test_002b: + add r1,r0,0x70000000 + add r2,r0,0x30000000 + mvtsys psw r0 ||nop + mvtsys psw r0 ||add r0,r1,r2 + mvfsys r12,psw ||nop + ; IU prevail for resulting V. + ; VA is set(OR'ed) + ;------------------------------------------------------------------------ + ; mvtsys (C= 0 V = VA = 1) || add (C= V= VA =0) + ;------------------------------------------------------------------------ + test_003b: + add r1,r0,0x14 ||nop ; set V and VA bit + mvtsys psw r0 ||nop + mvtsys psw r1 ||add r0,r0,r0 + mvfsys r13,psw ||nop + ; IU prevail for resulging V + ; VA is set(OR'ed) + ;------------------------------------------------------------------------ + ; mvtsys (f3 =1) || orfg (f3) : GROUP_B + ;------------------------------------------------------------------------ + test_004b: + add r1,r0,0x100 ; set f3 + mvtsys psw r0 ||nop + mvtsys psw,r1 ||orfg f3,f3,0 + mvfsys r14,psw ||nop + ; results of IU prevail. + ;------------------------------------------------------------------------ + ; mvtsys (f4 =1) || sathp + ;------------------------------------------------------------------------ + test_005b: + add r1,r0,0x40 ; set f4 + mvtsys psw r0 ||nop + mvtsys psw r1 ||sathl r2,r1,3 + mvfsys r15,psw ||nop + ; results of MU is used in IU + + assert r20, 0x1 + assert r10, 0x0 + assert r11, 0x0 + assert r12, 0x14 + assert r13, 0x4 + assert r14, 0x0 + assert r15, 0x0 + + + # PR 18288 - b.s + add r7,r0,0x80000000 + mvtsys psw,r7 || nop + + add r8,r0,0x7fff7fff ; + add r9,r0,0x55555555 ; + add r12,r0,0x11111111 ; + add r13,r0,0x00000000 ; + addhhhh r12,r8,r9 ||addhlll r13,r12,r12 + mvfsys r60,psw ||nop + ;------------------------------------------ + add r20,r0,0x66666666 ; + add r21,r0,0x77777777 ; + add r40,r0,0x22222222 ; + add r41,r0,0x55555555 ; + add r22,r20,r21 ||add r42,r40,r41,; + mvfsys r61,psw ||nop + + assert r60, 0x80000000 + assert r61, 0x80000000 + + + + # all okay + + bra ok + +ok: + add r2, r0, 0 + .long 0x0e000004 + nop + +fail: + add r2, r0, 47 + .long 0x0e000004 + nop diff --git a/sim/testsuite/d30v-elf/do-shifts.S b/sim/testsuite/d30v-elf/do-shifts.S new file mode 100644 index 00000000000..1f0129f5211 --- /dev/null +++ b/sim/testsuite/d30v-elf/do-shifts.S @@ -0,0 +1,182 @@ + # Test macro + + .macro assert reg,value + cmpeq f0,\reg,\value + bra/fx fail + .endm + + + # PR 14580 - a.s + + add r8,r0,0x11112222 + add r9,r0,-32 + sra r1,r8,r9 ||nop + sra r2,r8,-32 ||nop + srl r3,r8,r9 ||nop + srl r4,r8,-32 ||nop + + assert r1, 0 + assert r2, 0 + assert r3, 0 + assert r4, 0 + + + # PR 17266 - a.s + + add r20, r0, 0xffffffff + add r21, r0, 0xffffffff + add r22, r0, 0xffffffff + add r23, r0, 0xffffffff + add r1, r0, 0x12345678 + add r2, r0, -33 + srahh r20, r1, r2 + srahl r21, r1, r2 + srlhh r22, r1, r2 + srlhl r23, r1, r2 + sra r24, r1, r2 + srl r25, r1, r2 + rot r26, r1, r2 + + assert r20, 0xacf0ffff + assert r21, 0xffffacf0 + assert r22, 0xacf0ffff + assert r23, 0xffffacf0 + assert r24, 0x2468acf0 + assert r25, 0x2468acf0 + assert r26, 0x2468acf0 + + + # PR 17266 - a2.s + + add r20, r0, 0xffffffff + add r21, r0, 0xffffffff + add r22, r0, 0xffffffff + add r23, r0, 0xffffffff + add r1, r0, 0x12345678 + add r2, r0, -17 + sra2h r20, r1, r2 + srl2h r21, r1, r2 + rot2h r22, r1, r2 + + assert r20, 0x2468acf0 + assert r21, 0x2468acf0 + assert r22, 0x2468acf0 + + + # PR 17685 - a.s + + add r20,r0,r0 + add r21,r0,r0 + add r22,r0,r0 + add r23,r0,r0 + add r24,r0,r0 + add r25,r0,r0 + add r30,r0,r0 + add r31,r0,r0 + + add r8,r0,0x55555555 + add r9,r0,0x1f + sra r20,r8,r9 ||nop + srl r21,r8,r9 ||nop + srahh r22,r8,r9 ||nop + srahl r23,r8,r9 ||nop + srlhh r24,r8,r9 ||nop + srlhl r25,r8,r9 ||nop + + add r8,r0,0x5555aaaa + add r9,r0,0x000ffff1 + sra2h r30,r8,r9 ||nop + srl2h r31,r8,r9 ||nop + + assert r20, 0 + assert r21, 0 + assert r22, 0 + assert r23, 0 + assert r24, 0 + assert r25, 0 + assert r30, 0 + assert r31, 0 + + + # PR 18196 - a.s + + add r1,r0,0xfedcba98 + add r2,r0,0x76543210 + add r3,r0,0x41 + add r4,r0,1 + nop || mvtacc a0 r1,r2 + nop || mvfacc r10,a0 r3 + nop || mvfacc r11,a0 r4 + + assert r10, 0x3b2a1908 + assert r11, 0x3b2a1908 + + + # PR 18329 - a.s + + add r10,r0,0 || add r2,r0,-1 + add r11,r0,0 || add r12,r0,0 + add r13,r0,0 || add r14,r0,0 + add r15,r0,0 || add r16,r0,0 + add r17,r0,0 || add r18,r0,0 + + add r3,r0,0x00000020 ; 32 + src r10,r2,r3 + add r3,r0,0x00000021 ; 33 + src r11,r2,r3 + add r3,r0,0x0000003f ; 63 + src r12,r2,r3 + add r3,r0,0x00000040 ;64 + src r13,r2,r3 + add r3,r0,0x00000041 ;65 + src r14,r2,r3 + + add r3,r0,0xffffffdf ;-33 + src r15,r2,r3 + add r3,r0,0xffffffc1 ;-63 + src r16,r2,r3 + add r3,r0,0xffffffc0 ;-64 + src r17,r2,r3 + add r3,r0,0xffffffbf ;-65 + src r18,r2,r3 + + assert r10, 0x00000000 + assert r11, 0x80000000 + assert r12, 0xfffffffe + assert r13, 0x00000000 + assert r14, 0x80000000 + assert r15, 0x00000001 + assert r16, 0x7fffffff + assert r17, 0xffffffff + assert r18, 0x00000001 + + + # PR 18364 - b.s + + add r1,r0,0x12345678 + add r2,r0,0x9abcdef0 + add r3,r0,0xffffffe0 ; -32 + add r4,r0,0xffffffc0 ; -64 + src r1,r2,r3 ||nop + add r10,r1,r0 ||nop + add r1,r0,0x12345678 + src r1,r2,r4 ||nop + add r11,r1,r0 ||nop + + assert r10, 0x9abcdef0 + assert r11, 0x9abcdef0 + + + # all okay + + bra ok + +ok: + add r2, r0, 0 + .long 0x0e000004 + nop + +fail: + add r2, r0, 47 + .long 0x0e000004 + nop diff --git a/sim/testsuite/d30v-elf/em-e0.S b/sim/testsuite/d30v-elf/em-e0.S new file mode 100644 index 00000000000..d2e9335d5cc --- /dev/null +++ b/sim/testsuite/d30v-elf/em-e0.S @@ -0,0 +1,4 @@ +# Verify that the exit call works + add r2, r0, 0 || nop + .long 0x0e000004 + nop diff --git a/sim/testsuite/d30v-elf/em-e47.S b/sim/testsuite/d30v-elf/em-e47.S new file mode 100644 index 00000000000..9830ffb0cda --- /dev/null +++ b/sim/testsuite/d30v-elf/em-e47.S @@ -0,0 +1,4 @@ +# Verify r2 = 47; exit(r47) works + add r2, r0, 47 + .long 0x0e000004 + nop diff --git a/sim/testsuite/d30v-elf/em-pchr.S b/sim/testsuite/d30v-elf/em-pchr.S new file mode 100644 index 00000000000..6b38b0b7260 --- /dev/null +++ b/sim/testsuite/d30v-elf/em-pchr.S @@ -0,0 +1,28 @@ + + add r2, r0, 'H' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'e' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'l' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'l' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'o' + .long 0x0e000003, 0x00f00000 + add r2, r0, ' ' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'W' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'o' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'r' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'l' + .long 0x0e000003, 0x00f00000 + add r2, r0, 'd' + .long 0x0e000003, 0x00f00000 + add r2, r0, '\n' || nop + .long 0x0e000003, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/em-pstr.S b/sim/testsuite/d30v-elf/em-pstr.S new file mode 100644 index 00000000000..4612c35c8f1 --- /dev/null +++ b/sim/testsuite/d30v-elf/em-pstr.S @@ -0,0 +1,8 @@ + add r2, r0, hello + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + +hello: .ascii "Hello World\n" diff --git a/sim/testsuite/d30v-elf/exit47.s b/sim/testsuite/d30v-elf/exit47.s new file mode 100644 index 00000000000..9830ffb0cda --- /dev/null +++ b/sim/testsuite/d30v-elf/exit47.s @@ -0,0 +1,4 @@ +# Verify r2 = 47; exit(r47) works + add r2, r0, 47 + .long 0x0e000004 + nop diff --git a/sim/testsuite/d30v-elf/hello.s b/sim/testsuite/d30v-elf/hello.s new file mode 100644 index 00000000000..261629e27c3 --- /dev/null +++ b/sim/testsuite/d30v-elf/hello.s @@ -0,0 +1,9 @@ + + add r2, r0, hello + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + +hello: .ascii "Hello World\r\n" diff --git a/sim/testsuite/d30v-elf/loop.s b/sim/testsuite/d30v-elf/loop.s new file mode 100644 index 00000000000..69f2692a26e --- /dev/null +++ b/sim/testsuite/d30v-elf/loop.s @@ -0,0 +1 @@ +loop: bra loop diff --git a/sim/testsuite/d30v-elf/ls-ld2h.S b/sim/testsuite/d30v-elf/ls-ld2h.S new file mode 100644 index 00000000000..fade14ebbe6 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ld2h.S @@ -0,0 +1,11 @@ + # compute 17(mem) + 30(mem+2) = 47 + add r3, r0, 4 || nop + ld2h r2, @(r3,60) + add r2, r2, r3 || nop + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte 0, 17, 0, 30 diff --git a/sim/testsuite/d30v-elf/ls-ld2w.S b/sim/testsuite/d30v-elf/ls-ld2w.S new file mode 100644 index 00000000000..5b564ccc424 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ld2w.S @@ -0,0 +1,12 @@ + # compute 17(mem) + 30(mem+4) = 47 + add r3, r0, 4 || nop + ld2w r2, @(r3,60) + add r2, r2, r3 || nop + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte 0, 0, 0, 17 + .byte 0, 0, 0, 30 diff --git a/sim/testsuite/d30v-elf/ls-ld4bh.S b/sim/testsuite/d30v-elf/ls-ld4bh.S new file mode 100644 index 00000000000..6f22cebb682 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ld4bh.S @@ -0,0 +1,12 @@ + # compute lo : 17(mem+1) + 30(mem+3) = 47 + # compute hi : -1(mem) + 1(mem+2) = 0 + add r3, r0, 4 || nop + ld4bh r2, @(r3,60) + add r2, r2, r3 || nop + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte -1, 17, 1, 30 diff --git a/sim/testsuite/d30v-elf/ls-ld4bhu.S b/sim/testsuite/d30v-elf/ls-ld4bhu.S new file mode 100644 index 00000000000..4d0a9a37eb2 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ld4bhu.S @@ -0,0 +1,11 @@ + # compute lo : 48(mem+1) + 255(mem+3) - 256 = 47 + add r3, r0, 4 || nop + ld4bhu r2, @(r3,60) + add r2, r2, r3 || nop + sub r2, r2, 0x100 + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte 0, 48, 0, 255 diff --git a/sim/testsuite/d30v-elf/ls-ldb.S b/sim/testsuite/d30v-elf/ls-ldb.S new file mode 100644 index 00000000000..c6164ce6183 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ldb.S @@ -0,0 +1,11 @@ + # compute -2(from mem) + 49 = 47 + add r3, r0, 4 || nop + ldb r2, @(r3,60) + add r2, r2, 49 + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte -2, 0xff, 0xff, 0xff diff --git a/sim/testsuite/d30v-elf/ls-ldbu.S b/sim/testsuite/d30v-elf/ls-ldbu.S new file mode 100644 index 00000000000..153d6a4d3de --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ldbu.S @@ -0,0 +1,11 @@ + # compute 254(mem) - 207 = 47 + add r3, r0, 4 || nop + ldbu r2, @(r3,60) + sub r2, r2, 207 + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte -2, 0xff, 0xff, 0xff diff --git a/sim/testsuite/d30v-elf/ls-ldh.S b/sim/testsuite/d30v-elf/ls-ldh.S new file mode 100644 index 00000000000..0650bc05670 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ldh.S @@ -0,0 +1,11 @@ + # load the 47@addr=60 below into r2 + add r3, r0, 4 || nop + ldh r2, @(r3,60) + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte 0, 47, 0xff, 0xff diff --git a/sim/testsuite/d30v-elf/ls-ldhh.S b/sim/testsuite/d30v-elf/ls-ldhh.S new file mode 100644 index 00000000000..146daefa75d --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ldhh.S @@ -0,0 +1,11 @@ + # compute (47 || 0|16) >> 16 + add r3, r0, 4 || nop + ldhh r2, @(r3,60) + srl r2, r2, 16 || nop + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte 0, 47, 0xff, 0xff diff --git a/sim/testsuite/d30v-elf/ls-ldhu.S b/sim/testsuite/d30v-elf/ls-ldhu.S new file mode 100644 index 00000000000..b4f50e2355a --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ldhu.S @@ -0,0 +1,11 @@ + # compute 254(mem) - 207 = 47 + add r3, r0, 4 || nop + ldhu r2, @(r3,60) + sub r2, r2, 207 + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long -1, -1 +# address 64 - remember target is BE + .byte 0xff, -2, 0xff, 0xff diff --git a/sim/testsuite/d30v-elf/ls-ldw.S b/sim/testsuite/d30v-elf/ls-ldw.S new file mode 100644 index 00000000000..78d2ebfdaab --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-ldw.S @@ -0,0 +1,11 @@ + # load the 47@addr=60 below into r2 + add r3, r0, 4 || nop + ldw r2, @(r3,60) + .long 0x0e000004, 0x00f00000 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long 0, 0 + .long 0, 0 +# address 64 - remember target is BE + .byte 0, 0, 0, 47 diff --git a/sim/testsuite/d30v-elf/ls-modaddr.S b/sim/testsuite/d30v-elf/ls-modaddr.S new file mode 100644 index 00000000000..30d28ab00b0 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-modaddr.S @@ -0,0 +1,56 @@ + ; Modular address postincrement/postdecrement test + +start: + ; program PSW for modular address mode + add r1,r0,0x81000000 + nop || nop + mvtsys psw,r1 || nop + nop || nop + +test1: + ; set modular address limits: 0x18 bytes + add r1,r0,0x20000070 ; [start, ... + nop || nop + mvtsys mod_s,r1 || nop + nop || nop + add r1,r0,0x20000088 ; ..., end) + nop || nop + mvtsys mod_e,r1 || nop + + ; modular autoincrement test + add r30,r0,0x20000070 ; base address = mod_s + ld2w r40,@(r30+,r0) || nop ; after: r30 = ...078 + ld2w r40,@(r30+,r0) || nop ; after: r30 = ...080 + ld2w r40,@(r30+,r0) || nop ; after: r30 = ...070 + + add r29,r0,0x20000070 ; expected end address; wrapping around + cmpeq f1,r30,r29 + bra/xf fail + +test2: + ; set modular address limits: 0x18 bytes + add r1,r0,0x20000088 ; [start, ... + nop || nop + mvtsys mod_s,r1 || nop + nop || nop + add r1,r0,0x20000070 ; ..., end) + nop || nop + mvtsys mod_e,r1 || nop + + ; modular autodecrement test + add r30,r0,0x20000088 ; base address = mod_s + ld2w r40,@(r30-,r0) || nop ; after: r30 = ...080 + ld2w r40,@(r30-,r0) || nop ; after: r30 = ...078 + ld2w r40,@(r30-,r0) || nop ; after: r30 = ...088 + + add r29,r0,0x20000088 ; expected end address; wrapping around + cmpeq f1,r30,r29 + bra/xf fail + +ok: + add r2,r0,0 + .long 0x0e000004, 0x00f00000 + +fail: + add r2,r0,47 + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/ls-moddec.S b/sim/testsuite/d30v-elf/ls-moddec.S new file mode 100644 index 00000000000..f1b91439ec4 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-moddec.S @@ -0,0 +1,3 @@ + add r2, r0, 50 + moddec r2, 3 || nop + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/ls-modinc.S b/sim/testsuite/d30v-elf/ls-modinc.S new file mode 100644 index 00000000000..520c3f60de8 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-modinc.S @@ -0,0 +1,3 @@ + add r2, r0, 40 + modinc r2, 7 || nop + .long 0x0e000004, 0x00f00000 diff --git a/sim/testsuite/d30v-elf/ls-st2h.S b/sim/testsuite/d30v-elf/ls-st2h.S new file mode 100644 index 00000000000..d8c4b19adec --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-st2h.S @@ -0,0 +1,13 @@ + add r2, r0, hello + add r4, r0, ('H' << 8) + 'e' + add r5, r0, ('l' << 8) + 'l' + st2h r4, @(r2,0) || nop + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + .align 3 +hello: + .ascii "????o World\n" diff --git a/sim/testsuite/d30v-elf/ls-st2w.S b/sim/testsuite/d30v-elf/ls-st2w.S new file mode 100644 index 00000000000..0cd8b660072 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-st2w.S @@ -0,0 +1,13 @@ + add r2, r0, hello + add r4, r0, ('H' << 24) + ('e' << 16) + ('l' << 8) + ('l' << 0) + add r5, r0, ('o' << 24) + (' ' << 16) + ('W' << 8) + ('o' << 0) + st2w r4, @(r2,0) || nop + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + .align 3 +hello: + .ascii "????....rld\n" diff --git a/sim/testsuite/d30v-elf/ls-st4hb.S b/sim/testsuite/d30v-elf/ls-st4hb.S new file mode 100644 index 00000000000..bf802252ef0 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-st4hb.S @@ -0,0 +1,13 @@ + add r2, r0, hello + add r4, r0, ('H' << 16) + ('e' << 0) + add r5, r0, ('l' << 16) + ('l' << 0) + st4hb r4, @(r2,0) || nop + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + .align 3 +hello: + .ascii "????o World\n" diff --git a/sim/testsuite/d30v-elf/ls-stb.S b/sim/testsuite/d30v-elf/ls-stb.S new file mode 100644 index 00000000000..720a85b2dcc --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-stb.S @@ -0,0 +1,12 @@ + add r2, r0, hello + add r4, r0, 'H' + stb r4, @(r2,0) || nop + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + .align 3 +hello: + .ascii "?ello World\n" diff --git a/sim/testsuite/d30v-elf/ls-sth.S b/sim/testsuite/d30v-elf/ls-sth.S new file mode 100644 index 00000000000..ff236407bce --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-sth.S @@ -0,0 +1,12 @@ + add r2, r0, hello + add r4, r0, ('H' << 8) + ('e' << 0) + sth r4, @(r2,0) || nop + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + .align 3 +hello: + .ascii "??llo World\n" diff --git a/sim/testsuite/d30v-elf/ls-sthh.S b/sim/testsuite/d30v-elf/ls-sthh.S new file mode 100644 index 00000000000..071f30960a6 --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-sthh.S @@ -0,0 +1,12 @@ + add r2, r0, hello + add r4, r0, ('H' << 24) + ('e' << 16) + sthh r4, @(r2,0) || nop + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + .align 3 +hello: + .ascii "??llo World\n" diff --git a/sim/testsuite/d30v-elf/ls-stw.S b/sim/testsuite/d30v-elf/ls-stw.S new file mode 100644 index 00000000000..ac17f2a50ac --- /dev/null +++ b/sim/testsuite/d30v-elf/ls-stw.S @@ -0,0 +1,12 @@ + add r2, r0, hello + add r4, r0, ('H' << 24) + ('e' << 16) + ('l' << 8) + ('l' << 0) + stw r4, @(r2,0) || nop + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + .align 3 +hello: + .ascii "????o World\n" diff --git a/sim/testsuite/d30v-elf/os-dbt.S b/sim/testsuite/d30v-elf/os-dbt.S new file mode 100644 index 00000000000..34688674c9d --- /dev/null +++ b/sim/testsuite/d30v-elf/os-dbt.S @@ -0,0 +1,38 @@ + .globl _start + # + # NOTE: Registers r10-r11 are reserved for the interrupt handler + # while the others can be used by the main loop/start code. + +_start: + # patch the DBT handler + add r1, r0, handler + ldw r2, @(r1, 0) + ldw r3, @(r1, 4) + # DBT vector address + add r1, r0, 0xfffff120 + stw r2, @(r1, 0) + stw r3, @(r1, 4) + + # try out the breakpoint/return + add r2, r0, 47 + #dbt + nop + .long 0x00b00000 + nop + + # exit with what ever the breakpoint hander set r2 to. + nop + .long 0x0e000004 + nop + +handler: + jmp real_handler + + # The Breakpoint handler sets r2 to 0 if PSW was set correctly. +real_handler: + mvfsys r2, cr0 + sub r2, r0, 0x08000000 + #rtd + nop + .long 0x00a00000 + nop diff --git a/sim/testsuite/d30v-elf/tick.s b/sim/testsuite/d30v-elf/tick.s new file mode 100644 index 00000000000..d834ca7af9b --- /dev/null +++ b/sim/testsuite/d30v-elf/tick.s @@ -0,0 +1,51 @@ + .globl _start + # + # NOTE: Registers r10-r11 are reserved for the interrupt handler + # while the others can be used by the main loop/start code. + +_start: + # patch the external interrupt handlers entry + add r1, r0, handler + ldw r2, @(r1, 0) + ldw r3, @(r1, 4) + add r1, r0, 0xfffff138 + stw r2, @(r1, 0) + stw r3, @(r1, 4) + + # enable external interrupts - cr0 == PSW + mvfsys r2, cr0 + or r2, r0, 0x04000000 + mvtsys cr0, r2 + + + # wait for flag to be set +loop: + add r2, r0, flag + ldw r3, @(r2, 0) + bratzr r3, loop + + # clear the flag + stw r0, @(r2, 0) + + add r2, r0, tick + # putstr + .long 0x0e000001, 0x00f00000 + + bra loop + + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + +handler: + jmp real_handler +real_handler: + add r10, r0, 1 + add r11, r0, flag + stb r10, @(r11,0) + reit + + +flag: .long 0 +tick: .ascii "Tick\r\n" diff --git a/sim/testsuite/d30v-elf/trap.S b/sim/testsuite/d30v-elf/trap.S new file mode 100644 index 00000000000..08399f9d21a --- /dev/null +++ b/sim/testsuite/d30v-elf/trap.S @@ -0,0 +1,35 @@ +# verify that trap || cmp works + add r8,r0,0x11223344 ; + add r9,r0,0x11223344 ; + + mvtsys bpsw,r0 || nop + mvtsys bpc,r0 || nop + + add r1,r0,0x97000555 ; for psw + mvtsys psw,r1 || nop + trap 0 || cmpeq f0,r8,r9,; + + .long 0x0e000004, 0x00f00000 + + .section .eit_v, "a" + nop || nop + nop || nop + nop || nop + nop || nop + +# save the old bpsw, psw + mvfsys r4,bpsw || nop + mvfsys r5,psw || nop + +# load up what they should be + add r6,r0,0x97004555 + add r7,r0,0x90000000 + +# verify that they have the right values +# return exit value in r2 -- 0 success, 47 failure + add r2,r0,47 + cmpeq f0,r4,r6 || nop + cmpeq f1,r5,r7 || nop + add/tt r2,r0,r0 || nop + + reit diff --git a/sim/testsuite/fr30-elf/ChangeLog b/sim/testsuite/fr30-elf/ChangeLog new file mode 100644 index 00000000000..7b2d0e4e88b --- /dev/null +++ b/sim/testsuite/fr30-elf/ChangeLog @@ -0,0 +1,8 @@ +Thu Nov 26 11:34:46 1998 Dave Brolley <brolley@cygnus.com> + + * loop.s (_start): Removed direct address hack. + +Mon Nov 23 17:02:47 1998 Dave Brolley <brolley@cygnus.com> + + * Directory created. + diff --git a/sim/testsuite/fr30-elf/Makefile.in b/sim/testsuite/fr30-elf/Makefile.in new file mode 100644 index 00000000000..e93c3efe2ce --- /dev/null +++ b/sim/testsuite/fr30-elf/Makefile.in @@ -0,0 +1,157 @@ +# Makefile for regression testing the fr30 simulator. +# Copyright (C) 1998 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/../../.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +build_canonical = @build@ +host_canonical = @host@ +target_canonical = @target@ +target_cpu = @target_cpu@ + + +SHELL = @SHELL@ +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +EXPECT = `if [ -f ../../../expect/expect ] ; then \ + echo ../../../expect/expect ; \ + else echo expect ; fi` + +RUNTEST = $(RUNTEST_FOR_TARGET) + +RUNTESTFLAGS = + +RUNTEST_FOR_TARGET = `\ + if [ -f $${srcroot}/dejagnu/runtest ]; then \ + echo $${srcroot}/dejagnu/runtest; \ + else \ + if [ "$(host_canonical)" = "$(target_canonical)" ]; then \ + echo runtest; \ + else \ + t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \ + fi; \ + fi` + + +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/${target_cpu}/run ]; then \ + echo ../../../sim/${target_cpu}/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + +TESTS = \ + hello.ok \ + exit47.ko + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET = $(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET = $(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET) + + + +# Rules for running all the tests, put into three types +# exit success, exit fail, print "Hello World" + +.u.log: + uudecode $*.u + $(RUN_FOR_TARGET) $* > $*.log + + +# Rules for running the tests + +.SUFFIXES: .u .ok .run .hi .ko +.run.ok: + rm -f tmp-$* $*.hi + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + echo "Hello World" | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko + + +# Rules for building all the tests and packing them into +# uuencoded files. + +uuencode: em-pstr.u em-e0.u em-e47.u em-pchr.u + +.SUFFIXES: .u .s .run +.s.u: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $* $*.o + uuencode < $* $* > $*.u + rm -f $*.o $* +.s.run: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $*.run $*.o + rm -f $*.o $* + + +clean mostlyclean: + rm -f *~ core *.o a.out + rm -f $(TESTS) + +distclean maintainer-clean realclean: clean + rm -f *~ core + rm -f Makefile config.status *-init.exp + rm -fr *.log summary detail *.plog *.sum *.psum site.* + +Makefile : Makefile.in config.status + $(SHELL) config.status + +config.status: configure + $(SHELL) config.status --recheck diff --git a/sim/testsuite/fr30-elf/configure b/sim/testsuite/fr30-elf/configure new file mode 100755 index 00000000000..fa656cb3e6e --- /dev/null +++ b/sim/testsuite/fr30-elf/configure @@ -0,0 +1,902 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.12.1 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; 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then + eval "$ac_prev=\$ac_option" + ac_prev= + continue + fi + + case "$ac_option" in + -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;; + *) ac_optarg= ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case "$ac_option" in + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir="$ac_optarg" ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build="$ac_optarg" ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file="$ac_optarg" ;; + + -datadir | --datadir | --datadi | --datad | --data | --dat | --da) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \ + | --da=*) + datadir="$ac_optarg" ;; + + -disable-* | --disable-*) + ac_feature=`echo $ac_option|sed -e 's/-*disable-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + eval "enable_${ac_feature}=no" ;; + + -enable-* | --enable-*) + ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "enable_${ac_feature}='$ac_optarg'" ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; + -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ + | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ + | --exec=* | --exe=* | --ex=*) + exec_prefix="$ac_optarg" ;; + + -gas | --gas | --ga | --g) + # Obsolete; use --with-gas. + with_gas=yes ;; + + -help | --help | --hel | --he) + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat << EOF +Usage: configure [options] [host] +Options: [defaults in brackets after descriptions] +Configuration: + --cache-file=FILE cache test results in FILE + --help print this message + --no-create do not create output files + --quiet, --silent do not print \`checking...' messages + --version print the version of autoconf that created configure +Directory and file names: + --prefix=PREFIX install architecture-independent files in PREFIX + [$ac_default_prefix] + --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX + [same as prefix] + --bindir=DIR user executables in DIR [EPREFIX/bin] + --sbindir=DIR system admin executables in DIR [EPREFIX/sbin] + --libexecdir=DIR program executables in DIR [EPREFIX/libexec] + --datadir=DIR read-only architecture-independent data in DIR + [PREFIX/share] + --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data in DIR + [PREFIX/com] + --localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var] + --libdir=DIR object code libraries in DIR [EPREFIX/lib] + --includedir=DIR C header files in DIR [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc in DIR [/usr/include] + --infodir=DIR info documentation in DIR [PREFIX/info] + --mandir=DIR man documentation in DIR [PREFIX/man] + --srcdir=DIR find the sources in DIR [configure dir or ..] + --program-prefix=PREFIX prepend PREFIX to installed program names + --program-suffix=SUFFIX append SUFFIX to installed program names + --program-transform-name=PROGRAM + run sed PROGRAM on installed program names +EOF + cat << EOF +Host type: + --build=BUILD configure for building on BUILD [BUILD=HOST] + --host=HOST configure for HOST [guessed] + --target=TARGET configure for TARGET [TARGET=HOST] +Features and packages: + --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) + --enable-FEATURE[=ARG] include FEATURE [ARG=yes] + --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] + --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) + --x-includes=DIR X include files are in DIR + --x-libraries=DIR X library files are in DIR +EOF + if test -n "$ac_help"; then + echo "--enable and --with options recognized:$ac_help" + fi + exit 0 ;; + + -host | --host | --hos | --ho) + ac_prev=host ;; + -host=* | --host=* | --hos=* | --ho=*) + host="$ac_optarg" ;; + + -includedir | --includedir | --includedi | --included | --include \ + | --includ | --inclu | --incl | --inc) + ac_prev=includedir ;; + -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ + | --includ=* | --inclu=* | --incl=* | --inc=*) + includedir="$ac_optarg" ;; + + -infodir | --infodir | --infodi | --infod | --info | --inf) + ac_prev=infodir ;; + -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) + infodir="$ac_optarg" ;; + + -libdir | --libdir | --libdi | --libd) + ac_prev=libdir ;; + -libdir=* | --libdir=* | --libdi=* | --libd=*) + libdir="$ac_optarg" ;; + + -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ + | --libexe | --libex | --libe) + ac_prev=libexecdir ;; + -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ + | --libexe=* | --libex=* | --libe=*) + libexecdir="$ac_optarg" ;; + + -localstatedir | --localstatedir | --localstatedi | --localstated \ + | --localstate | --localstat | --localsta | --localst \ + | --locals | --local | --loca | --loc | --lo) + ac_prev=localstatedir ;; + -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ + | --localstate=* | --localstat=* | --localsta=* | --localst=* \ + | --locals=* | --local=* | --loca=* | --loc=* | --lo=*) + localstatedir="$ac_optarg" ;; + + -mandir | --mandir | --mandi | --mand | --man | --ma | --m) + ac_prev=mandir ;; + -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) + mandir="$ac_optarg" ;; + + -nfp | --nfp | --nf) + # Obsolete; use --without-fp. + with_fp=no ;; + + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) + no_create=yes ;; + + -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) + no_recursion=yes ;; + + -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ + | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \ + | --oldin | --oldi | --old | --ol | --o) + ac_prev=oldincludedir ;; + -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \ + | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \ + | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*) + oldincludedir="$ac_optarg" ;; + + -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) + ac_prev=prefix ;; + -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) + prefix="$ac_optarg" ;; + + -program-prefix | --program-prefix | --program-prefi | --program-pref \ + | --program-pre | --program-pr | --program-p) + ac_prev=program_prefix ;; + -program-prefix=* | --program-prefix=* | --program-prefi=* \ + | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) + program_prefix="$ac_optarg" ;; + + -program-suffix | --program-suffix | --program-suffi | --program-suff \ + | --program-suf | --program-su | --program-s) + ac_prev=program_suffix ;; + -program-suffix=* | --program-suffix=* | --program-suffi=* \ + | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) + program_suffix="$ac_optarg" ;; + + -program-transform-name | --program-transform-name \ + | --program-transform-nam | --program-transform-na \ + | --program-transform-n | --program-transform- \ + | --program-transform | --program-transfor \ + | --program-transfo | --program-transf \ + | --program-trans | --program-tran \ + | --progr-tra | --program-tr | --program-t) + ac_prev=program_transform_name ;; + -program-transform-name=* | --program-transform-name=* \ + | --program-transform-nam=* | --program-transform-na=* \ + | --program-transform-n=* | --program-transform-=* \ + | --program-transform=* | --program-transfor=* \ + | --program-transfo=* | --program-transf=* \ + | --program-trans=* | --program-tran=* \ + | --progr-tra=* | --program-tr=* | --program-t=*) + program_transform_name="$ac_optarg" ;; + + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil) + silent=yes ;; + + -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) + ac_prev=sbindir ;; + -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ + | --sbi=* | --sb=*) + sbindir="$ac_optarg" ;; + + -sharedstatedir | --sharedstatedir | --sharedstatedi \ + | --sharedstated | --sharedstate | --sharedstat | --sharedsta \ + | --sharedst | --shareds | --shared | --share | --shar \ + | --sha | --sh) + ac_prev=sharedstatedir ;; + -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \ + | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \ + | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \ + | --sha=* | --sh=*) + sharedstatedir="$ac_optarg" ;; + + -site | --site | --sit) + ac_prev=site ;; + -site=* | --site=* | --sit=*) + site="$ac_optarg" ;; + + -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) + ac_prev=srcdir ;; + -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) + srcdir="$ac_optarg" ;; + + -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \ + | --syscon | --sysco | --sysc | --sys | --sy) + ac_prev=sysconfdir ;; + -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ + | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) + sysconfdir="$ac_optarg" ;; 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It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set) 2>&1 | grep ac_space` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS <<EOF +#! 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-s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <<EOF + +CONFIG_FILES=\${CONFIG_FILES-"Makefile"} +EOF +cat >> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +EOF +cat >> $CONFIG_STATUS <<EOF + +EOF +cat >> $CONFIG_STATUS <<\EOF + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/sim/testsuite/fr30-elf/configure.in b/sim/testsuite/fr30-elf/configure.in new file mode 100644 index 00000000000..e74389e551e --- /dev/null +++ b/sim/testsuite/fr30-elf/configure.in @@ -0,0 +1,19 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +dnl FIXME - think of a truly uniq file to this directory +AC_INIT(Makefile.in) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) +AC_CANONICAL_SYSTEM + +AC_SUBST(target_cpu) + + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/fr30-elf/exit47.s b/sim/testsuite/fr30-elf/exit47.s new file mode 100644 index 00000000000..0dc7c99dda6 --- /dev/null +++ b/sim/testsuite/fr30-elf/exit47.s @@ -0,0 +1,7 @@ + ;; Return with exit code 47. + + .global _start +_start: + ldi32 #47,r4 + ldi32 #1,r0 + int #10 diff --git a/sim/testsuite/fr30-elf/hello.s b/sim/testsuite/fr30-elf/hello.s new file mode 100644 index 00000000000..d5259cdb7a5 --- /dev/null +++ b/sim/testsuite/fr30-elf/hello.s @@ -0,0 +1,15 @@ + .global _start +_start: + +; write (hello world) + ldi32 #14,r6 + ldi32 #hello,r5 + ldi32 #1,r4 + ldi32 #5,r0 + int #10 +; exit (0) + ldi32 #0,r4 + ldi32 #1,r0 + int #10 + +hello: .ascii "Hello World!\r\n" diff --git a/sim/testsuite/fr30-elf/loop.s b/sim/testsuite/fr30-elf/loop.s new file mode 100644 index 00000000000..709b78f04eb --- /dev/null +++ b/sim/testsuite/fr30-elf/loop.s @@ -0,0 +1,2 @@ + .global _start +_start: bra _start diff --git a/sim/testsuite/lib/sim-defs.exp b/sim/testsuite/lib/sim-defs.exp new file mode 100644 index 00000000000..16a742fb6da --- /dev/null +++ b/sim/testsuite/lib/sim-defs.exp @@ -0,0 +1,318 @@ +# Simulator dejagnu utilities. + +# Communicate simulator path from sim_init to sim_version. +# For some reason [board_info target sim] doesn't work in sim_version. +# [Presumubly because the target has been "popped" by then. Odd though.] +set sim_path "unknown-run" + +# Initialize the testrun. +# Required by dejagnu. + +proc sim_init { args } { + global sim_path + set sim_path [board_info target sim] + # Need to return an empty string (copied from GAS). + return "" +} + +# Print the version of the simulator being tested. +# Required by dejagnu. + +proc sim_version {} { + global sim_path + set version 0.5 + clone_output "$sim_path $version\n" +} + +# Cover function to target_compile. +# Copied from gdb_compile. + +proc sim_compile { source dest type options } { + set result [target_compile $source $dest $type $options] + regsub "\[\r\n\]*$" "$result" "" result + regsub "^\[\r\n\]*" "$result" "" result + if { $result != "" } { + clone_output "sim compile output: $result" + } + return $result +} + +# Run a program on the simulator. +# Required by dejagnu (at least ${tool}_run used to be). +# +# SIM_OPTS are options for the simulator. +# PROG_OPTS are options passed to the simulated program. +# At present REDIR must be "" or "> foo". +# OPTIONS is a list of options internal to this routine. +# This is modelled after target_compile. We want to be able to add new +# options without having to update all our users. +# Currently: +# env(foo)=val - set environment variable foo to val for this run +# timeout=val - set the timeout to val for this run +# +# The result is a list of two elements. +# The first is one of pass/fail/etc. +# The second is the program's output. +# +# This is different than the sim_load routine provided by +# dejagnu/config/sim.exp. It's not clear how to pass arguments to the +# simulator (not the simulated program, the simulator) with sim_load. + +proc sim_run { prog sim_opts prog_opts redir options } { + global SIMFLAGS + + # Set the default value of the timeout. + # FIXME: The timeout value we actually want is a function of + # host, target, and testcase. + set testcase_timeout [board_info target sim_time_limit] + if { "$testcase_timeout" == "" } { + set testcase_timeout [board_info host testcase_timeout] + } + if { "$testcase_timeout" == "" } { + set testcase_timeout 240 ;# 240 same as in dejagnu/config/sim.exp. + } + + # Initial the environment we pass to the testcase. + set testcase_env "" + + # Process OPTIONS ... + foreach o $options { + if [regexp {^env\((.*)\)=(.*)} $o full var val] { + set testcase_env "$testcase_env $var=$val" + } elseif [regexp {^timeout=(.*)} $o full val] { + set testcase_timeout $val + } + + } + + verbose "testcase timeout is set to $testcase_timeout" 1 + + set sim [board_info target sim] + + if [is_remote host] { + set prog [remote_download host $prog] + if { $prog == "" } { + error "download failed" + return -1; + } + } + + set board [target_info name] + if [board_info $board exists sim,options] { + set always_opts [board_info $board sim,options] + } else { + set always_opts "" + } + + # FIXME: this works for UNIX only + if { "$testcase_env" != "" } { + set sim "env $testcase_env $sim" + } + + send_log "$sim $always_opts $SIMFLAGS $sim_opts $prog $prog_opts\n" + + if { "$redir" == "" } { + remote_spawn host "$sim $always_opts $SIMFLAGS $sim_opts $prog $prog_opts" + } else { + remote_spawn host "$sim $always_opts $SIMFLAGS $sim_opts $prog $prog_opts $redir" writeonly + } + set result [remote_wait host $testcase_timeout] + + set return_code [lindex $result 0] + set output [lindex $result 1] + # Remove the \r part of "\r\n" so we don't break all the patterns + # we want to match. + regsub -all -- "\r" $output "" output + + if [is_remote host] { + # clean up after ourselves. + remote_file host delete $prog + } + + # ??? Not sure the test for pass/fail is right. + # We just care that the simulator ran correctly, not whether the simulated + # program return 0 or non-zero from `main'. + set status fail + if { $return_code == 0 } { + set status pass + } + + return [list $status $output] +} + +# Run testcase NAME. +# NAME is either a fully specified file name, or just the file name in which +# case $srcdir/$subdir will be prepended. +# ALL_MACHS is a list of machs to use if "mach: all" is specified in the file. +# The file can contain options in the form "# option(mach list): value" +# Possibilities: +# mach: [all | machine names] +# as[(mach-list)]: <assembler options> +# ld[(mach-list)]: <linker options> +# sim[(mach-list)]: <simulator options> +# output[(mach-list)]: program output pattern to match with string-match +# xerror[(mach-list)]: program is expected to return with a "failure" exit code +# If `output' is not specified, the program must output "pass" if !xerror or +# "fail" if xerror. +# The parens in "optname()" are optional if the specification is for all machs. + +proc run_sim_test { name all_machs } { + global subdir srcdir + global AS ASFLAGS LD LDFLAGS SIMFLAGS + global opts + + if [string match "*/*" $name] { + set file $name + set name [file tail $name] + } else { + set file "$srcdir/$subdir/$name" + } + + set opt_array [slurp_options "${file}"] + if { $opt_array == -1 } { + unresolved $subdir/$name + return + } + set opts(as) {} + set opts(ld) {} + set opts(sim) {} + set opts(output) {} + set opts(mach) {} + set opts(timeout) {} + set opts(xerror) "no" + + foreach i $opt_array { + set opt_name [lindex $i 0] + set opt_machs [lindex $i 1] + set opt_val [lindex $i 2] + if ![info exists opts($opt_name)] { + perror "unknown option $opt_name in file $file" + unresolved $subdir/$name + return + } + foreach m $opt_machs { + set opts($opt_name,$m) $opt_val + } + if { "$opt_machs" == "" } { + set opts($opt_name) $opt_val + } + } + + set testname $name + set sourcefile $file + if { $opts(output) == "" } { + if { "$opts(xerror)" == "no" } { + set opts(output) "pass\n" + } else { + set opts(output) "fail\n" + } + } + # Change \n sequences to newline chars. + regsub -all "\\\\n" $opts(output) "\n" opts(output) + + foreach mach $opts(mach) { + verbose "Testing $name on $mach." + + if ![info exists opts(as,$mach)] { + set opts(as,$mach) $opts(as) + } + send_log "$AS $ASFLAGS $opts(as,$mach) -I$srcdir/$subdir -o ${name}.o $sourcefile\n" + catch "exec $AS $ASFLAGS $opts(as,$mach) -I$srcdir/$subdir -o ${name}.o $sourcefile" comp_output + + if ![string match "" $comp_output] { + verbose -log "$comp_output" 3 + fail "$mach $testname" + continue + } + + if ![info exists opts(ld,$mach)] { + set opts(ld,$mach) $opts(ld) + } + send_log "$LD $LDFLAGS $opts(ld,$mach) -o ${name}.x ${name}.o\n" + catch "exec $LD $LDFLAGS $opts(ld,$mach) -o ${name}.x ${name}.o" comp_output + + if ![string match "" $comp_output] { + verbose -log "$comp_output" 3 + fail "$mach $testname" + continue + } + + # If no machine specific options, default to the general version. + if ![info exists opts(sim,$mach)] { + set opts(sim,$mach) $opts(sim) + } + + # Build the options argument. + set options "" + if { "$opts(timeout)" != "" } { + set options "$options timeout=$opts(timeout)" + } + + set result [sim_run ${name}.x "$opts(sim,$mach)" "" "" "$options"] + set status [lindex $result 0] + set output [lindex $result 1] + + if { "$status" == "pass" } { + if { "$opts(xerror)" == "no" } { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname" + } + } else { + verbose -log "`pass' return code when expecting failure" 3 + fail "$mach $testname" + } + } elseif { "$status" == "fail" } { + if { "$opts(xerror)" == "no" } { + fail "$mach $testname" + } else { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname" + } + } + } else { + $status "$mach $testname" + } + } +} + +# Subroutine of run_sim_test to process options in FILE. + +proc slurp_options { file } { + if [catch { set f [open $file r] } x] { + #perror "couldn't open `$file': $x" + perror "$x" + return -1 + } + set opt_array {} + # whitespace expression + set ws {[ ]*} + set nws {[^ ]*} + # whitespace is ignored anywhere except within the options list; + # option names are alphabetic only + set pat "^#${ws}(\[a-zA-Z\]*)\\(?(\[^):\]*)\\)?$ws:${ws}(.*)$ws\$" + # Allow comment as first line of file. + set firstline 1 + while { [gets $f line] != -1 } { + set line [string trim $line] + # Whitespace here is space-tab. + if [regexp $pat $line xxx opt_name opt_machs opt_val] { + # match! + lappend opt_array [list $opt_name $opt_machs $opt_val] + } else { + if { ! $firstline } { + break + } + } + set firstline 0 + } + close $f + return $opt_array +} diff --git a/sim/testsuite/m32r-elf/ChangeLog b/sim/testsuite/m32r-elf/ChangeLog new file mode 100644 index 00000000000..371a839bdc1 --- /dev/null +++ b/sim/testsuite/m32r-elf/ChangeLog @@ -0,0 +1,4 @@ +Thu Feb 12 19:09:38 1998 Doug Evans <devans@canuck.cygnus.com> + + * Directory created. + diff --git a/sim/testsuite/m32r-elf/Makefile.in b/sim/testsuite/m32r-elf/Makefile.in new file mode 100644 index 00000000000..bbfb6a55322 --- /dev/null +++ b/sim/testsuite/m32r-elf/Makefile.in @@ -0,0 +1,157 @@ +# Makefile for regression testing the m32r simulator. +# Copyright (C) 1998 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/../../.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +build_canonical = @build@ +host_canonical = @host@ +target_canonical = @target@ +target_cpu = @target_cpu@ + + +SHELL = @SHELL@ +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +EXPECT = `if [ -f ../../../expect/expect ] ; then \ + echo ../../../expect/expect ; \ + else echo expect ; fi` + +RUNTEST = $(RUNTEST_FOR_TARGET) + +RUNTESTFLAGS = + +RUNTEST_FOR_TARGET = `\ + if [ -f $${srcroot}/dejagnu/runtest ]; then \ + echo $${srcroot}/dejagnu/runtest; \ + else \ + if [ "$(host_canonical)" = "$(target_canonical)" ]; then \ + echo runtest; \ + else \ + t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \ + fi; \ + fi` + + +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/${target_cpu}/run ]; then \ + echo ../../../sim/${target_cpu}/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + +TESTS = \ + hello.ok \ + exit47.ko + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET = $(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET = $(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET) + + + +# Rules for running all the tests, put into three types +# exit success, exit fail, print "Hello World" + +.u.log: + uudecode $*.u + $(RUN_FOR_TARGET) $* > $*.log + + +# Rules for running the tests + +.SUFFIXES: .u .ok .run .hi .ko +.run.ok: + rm -f tmp-$* $*.hi + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + echo "Hello World" | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko + + +# Rules for building all the tests and packing them into +# uuencoded files. + +uuencode: em-pstr.u em-e0.u em-e47.u em-pchr.u + +.SUFFIXES: .u .s .run +.s.u: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $* $*.o + uuencode < $* $* > $*.u + rm -f $*.o $* +.s.run: + rm -f $*.o $*.run + $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o + $(LD_FOR_TARGET) -o $*.run $*.o + rm -f $*.o $* + + +clean mostlyclean: + rm -f *~ core *.o a.out + rm -f $(TESTS) + +distclean maintainer-clean realclean: clean + rm -f *~ core + rm -f Makefile config.status *-init.exp + rm -fr *.log summary detail *.plog *.sum *.psum site.* + +Makefile : Makefile.in config.status + $(SHELL) config.status + +config.status: configure + $(SHELL) config.status --recheck diff --git a/sim/testsuite/m32r-elf/configure b/sim/testsuite/m32r-elf/configure new file mode 100755 index 00000000000..fa656cb3e6e --- /dev/null +++ b/sim/testsuite/m32r-elf/configure @@ -0,0 +1,902 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.12.1 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; then + eval "$ac_prev=\$ac_option" + ac_prev= + continue + fi + + case "$ac_option" in + -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;; + *) ac_optarg= ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case "$ac_option" in + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir="$ac_optarg" ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build="$ac_optarg" ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file="$ac_optarg" ;; + + -datadir | --datadir | --datadi | --datad | --data | --dat | --da) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \ + | --da=*) + datadir="$ac_optarg" ;; + + -disable-* | --disable-*) + ac_feature=`echo $ac_option|sed -e 's/-*disable-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + eval "enable_${ac_feature}=no" ;; + + -enable-* | --enable-*) + ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "enable_${ac_feature}='$ac_optarg'" ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; 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If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:573: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:594: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:612: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set) 2>&1 | grep ac_space` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS <<EOF +#! /bin/sh +# Generated automatically by configure. +# Run this file to recreate the current configuration. +# This directory was configured as follows, +# on host `(hostname || uname -n) 2>/dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.12.1" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir + +trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS <<EOF + +# Protect against being on the right side of a sed subst in config.status. +sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g; + s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@CC@%$CC%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <<EOF + +CONFIG_FILES=\${CONFIG_FILES-"Makefile"} +EOF +cat >> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +EOF +cat >> $CONFIG_STATUS <<EOF + +EOF +cat >> $CONFIG_STATUS <<\EOF + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/sim/testsuite/m32r-elf/configure.in b/sim/testsuite/m32r-elf/configure.in new file mode 100644 index 00000000000..e74389e551e --- /dev/null +++ b/sim/testsuite/m32r-elf/configure.in @@ -0,0 +1,19 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +dnl FIXME - think of a truly uniq file to this directory +AC_INIT(Makefile.in) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) +AC_CANONICAL_SYSTEM + +AC_SUBST(target_cpu) + + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/m32r-elf/exit47.s b/sim/testsuite/m32r-elf/exit47.s new file mode 100644 index 00000000000..ab814e3ab9a --- /dev/null +++ b/sim/testsuite/m32r-elf/exit47.s @@ -0,0 +1,7 @@ + ;; Return with exit code 47. + + .globl _start +_start: + ldi8 r1,#47 + ldi8 r0,#1 + trap #0 diff --git a/sim/testsuite/m32r-elf/hello.s b/sim/testsuite/m32r-elf/hello.s new file mode 100644 index 00000000000..a61693462fb --- /dev/null +++ b/sim/testsuite/m32r-elf/hello.s @@ -0,0 +1,17 @@ + + .globl _start +_start: + +; write (hello world) + ldi8 r3,#14 + ld24 r2,#hello + ldi8 r1,#1 + ldi8 r0,#5 + trap #0 +; exit (0) + ldi8 r1,#0 + ldi8 r0,#1 + trap #0 + +length: .long 14 +hello: .ascii "Hello World!\r\n" diff --git a/sim/testsuite/m32r-elf/loop.s b/sim/testsuite/m32r-elf/loop.s new file mode 100644 index 00000000000..b24cfb41fdd --- /dev/null +++ b/sim/testsuite/m32r-elf/loop.s @@ -0,0 +1,2 @@ + .globl _start +_start: bra _start diff --git a/sim/testsuite/mips64el-elf/ChangeLog b/sim/testsuite/mips64el-elf/ChangeLog new file mode 100644 index 00000000000..801ad223a20 --- /dev/null +++ b/sim/testsuite/mips64el-elf/ChangeLog @@ -0,0 +1,5 @@ +Thu Aug 13 22:37:29 EDT 1998 Jim Lemke <jlemke@cygnus.com> + + * Makefile.in, configure, configure.in: + Create a minimal testsuite. + diff --git a/sim/testsuite/mips64el-elf/Makefile.in b/sim/testsuite/mips64el-elf/Makefile.in new file mode 100644 index 00000000000..c8191aea4ae --- /dev/null +++ b/sim/testsuite/mips64el-elf/Makefile.in @@ -0,0 +1,171 @@ +# Makefile for regression testing the GNU debugger. +# Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + +# This file is part of GDB. + +# GDB is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# GDB is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +build_canonical = @build@ +host_canonical = @host@ +target_canonical = @target@ +target_cpu = @target_cpu@ + + +SHELL = /bin/sh +SUBDIRS = @subdirs@ +RPATH_ENVVAR = @RPATH_ENVVAR@ + +EXPECT = `if [ -f $${rootme}/../../expect/expect ] ; then \ + echo $${rootme}/../../expect/expect ; \ + else echo expect ; fi` + +RUNTEST = $(RUNTEST_FOR_TARGET) + +RUNTESTFLAGS = + +RUNTEST_FOR_TARGET = `\ + if [ -f $${srcdir}/../../../dejagnu/runtest ]; then \ + echo $${srcdir}/../../../dejagnu/runtest; \ + else \ + if [ "$(host_canonical)" = "$(target_canonical)" ]; then \ + echo runtest; \ + else \ + t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \ + fi; \ + fi` + + +AS_FOR_TARGET = `\ + if [ -x ../../../gas/as-new ]; then \ + echo ../../../gas/as-new ; \ + else \ + echo $(target_alias)-as ; \ + fi` + +LD_FOR_TARGET = `\ + if [ -x ../../../ld/ld-new ]; then \ + echo ../../../ld/ld-new ; \ + else \ + echo $(target_alias)-ld ; \ + fi` + +RUN_FOR_TARGET = `\ + if [ -x ../../../sim/mips/run ]; then \ + echo ../../../sim/mips/run ; \ + else \ + echo $(target_alias)-run ; \ + fi` + +TESTS = + +check: sanity $(TESTS) +sanity: + @eval echo AS_FOR_TARGET = $(AS_FOR_TARGET) + @eval echo LD_FOR_TARGET = $(LD_FOR_TARGET) + @eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET) + + + +# Rules for running all the tests, put into three types +# exit success, exit fail, print "Hello World" + +.u.log: + uudecode $*.u + $(RUN_FOR_TARGET) $* > $*.log + + +# Rules for running the tests + +.SUFFIXES: .u .uue .ok .ok .run .hi .ko .ko +.run.ok: + rm -f tmp-$* $*.ok + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + mv tmp-$* $*.ok +.run.hi: + rm -f tmp-$* $*.hi diff-$* + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* + echo 'Hello World!' | diff - tmp-$* > diff-$* + cat tmp-$* diff-$* > $*.hi +.run.ko: + rm -f tmp-$* $*.ko + set +e ; \ + ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \ + if [ $$? -eq 47 ] ; then \ + exit 0 ; \ + else \ + exit 1 ; \ + fi + mv tmp-$* $*.ko + + +# Rules for building all the tests and packing them into +# uuencoded files. + +.run.u: + uuencode < $*.run $*.run > $*.u + @echo "Move $*.u $*.uue" +.uue.run: + uudecode $(srcdir)/$*.uue +.o.run: + $(LD_FOR_TARGET) -Ttext 0xa0020000 -o $*.run $*.o +.s.o: + $(AS_FOR_TARGET) -I $(srcdir) $(srcdir)/$*.s -o $*.o + + +# +# Standard +# +clean mostlyclean: + -rm -f *~ core *.o a.out *.x *.grt *.run tmp-* diff-* + rm -f $(TESTS) +# if [ x"${SUBDIRS}" != x ] ; then \ +# for dir in ${SUBDIRS}; \ +# do \ +# echo "$$dir:"; \ +# if [ -d $$dir ]; then \ +# (cd $$dir; $(MAKE) clean); \ +# fi; \ +# done ; \ +# else true; fi + +distclean maintainer-clean realclean: clean + -rm -f *~ core + -rm -f Makefile config.status *-init.exp + -rm -fr *.log summary detail *.plog *.sum *.psum site.* +# if [ x"${SUBDIRS}" != x ] ; then \ +# for dir in ${SUBDIRS}; \ +# do \ +# echo "$$dir:"; \ +# if [ -d $$dir ]; then \ +# (cd $$dir; $(MAKE) distclean); \ +# fi; \ +# done ; \ +# else true; fi + +Makefile : Makefile.in config.status + $(SHELL) config.status + +config.status: configure + $(SHELL) config.status --recheck diff --git a/sim/testsuite/mips64el-elf/configure b/sim/testsuite/mips64el-elf/configure new file mode 100755 index 00000000000..86f083625a0 --- /dev/null +++ b/sim/testsuite/mips64el-elf/configure @@ -0,0 +1,904 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.12.2 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; 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If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:575: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:596: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:614: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set) 2>&1 | grep ac_space` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs + + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS <<EOF +#! /bin/sh +# Generated automatically by configure. +# Run this file to recreate the current configuration. +# This directory was configured as follows, +# on host `(hostname || uname -n) 2>/dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.12.2" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir + +trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS <<EOF + +# Protect against being on the right side of a sed subst in config.status. +sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g; + s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@CC@%$CC%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <<EOF + +CONFIG_FILES=\${CONFIG_FILES-"Makefile"} +EOF +cat >> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +EOF +cat >> $CONFIG_STATUS <<EOF + +EOF +cat >> $CONFIG_STATUS <<\EOF + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/sim/testsuite/mips64el-elf/configure.in b/sim/testsuite/mips64el-elf/configure.in new file mode 100644 index 00000000000..e74389e551e --- /dev/null +++ b/sim/testsuite/mips64el-elf/configure.in @@ -0,0 +1,19 @@ +dnl Process this file file with autoconf to produce a configure script. +dnl This file is a shell script fragment that supplies the information +dnl necessary to tailor a template configure script into the configure +dnl script appropriate for this directory. For more information, check +dnl any existing configure script. + +AC_PREREQ(2.5) +dnl FIXME - think of a truly uniq file to this directory +AC_INIT(Makefile.in) + +CC=${CC-cc} +AC_SUBST(CC) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) +AC_CANONICAL_SYSTEM + +AC_SUBST(target_cpu) + + +AC_OUTPUT(Makefile) diff --git a/sim/testsuite/sim/fr30/add.cgs b/sim/testsuite/sim/fr30/add.cgs new file mode 100644 index 00000000000..1409df1b6fe --- /dev/null +++ b/sim/testsuite/sim/fr30/add.cgs @@ -0,0 +1,55 @@ +# fr30 testcase for add $Rj,$Ri, add $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + ; Test add $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + add r7,r8 + test_cc 0 0 0 0 + test_h_gr 3,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 1,r8 + set_cc 0x05 ; Set mask opposite of expected + add r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + set_cc 0x08 ; Set mask opposite of expected + add r8,r8 + test_cc 0 1 1 1 + test_h_gr 0,r8 + + ; Test add $u4Ri + mvi_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of expected + add 0,r8 + test_cc 0 0 0 0 + test_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of expected + add 1,r8 + test_cc 0 0 0 0 + test_h_gr 5,r8 + set_cc 0x0f ; Set mask opposite of expected + add 15,r8 + test_cc 0 0 0 0 + test_h_gr 20,r8 + mvi_h_gr 0x7fffffff,r8 ; test neg and overflow bits + set_cc 0x05 ; Set mask opposite of expected + add 1,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + set_cc 0x08 ; Set mask opposite of expected + add r8,r8 ; test zero, carry and overflow bits + test_cc 0 1 1 1; + test_h_gr 0,r8 + + pass diff --git a/sim/testsuite/sim/fr30/add.ms b/sim/testsuite/sim/fr30/add.ms new file mode 100644 index 00000000000..9da6868a110 --- /dev/null +++ b/sim/testsuite/sim/fr30/add.ms @@ -0,0 +1,13 @@ +# fr30 testcase for add $Rj,$Ri +# cpu {} + + .include "testutils.inc" + + START + + .text + .global add +add: + add ac,ac + fail + EXIT 0 diff --git a/sim/testsuite/sim/fr30/add2.cgs b/sim/testsuite/sim/fr30/add2.cgs new file mode 100644 index 00000000000..856acde6fe8 --- /dev/null +++ b/sim/testsuite/sim/fr30/add2.cgs @@ -0,0 +1,43 @@ +# fr30 testcase for add2 $m4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + mvi_h_gr 30,r8 + set_cc 0x0e ; Set mask opposite of expected + add2 -16,r8 ; Max value of immediate field + test_cc 0 0 0 1 + test_h_gr 14,r8 + + set_cc 0x0e ; Set mask opposite of expected + add2 -3,r8 ; Mid value of immediate field + test_cc 0 0 0 1 + test_h_gr 11,r8 + + set_cc 0x0e ; Set mask opposite of expected + add2 -1,r8 ; Min value of immediate field + test_cc 0 0 0 1 + test_h_gr 10,r8 + + set_cc 0x0a ; Set mask opposite of expected + add2 -10,r8 ; Test zero and carry bits + test_cc 0 1 0 1 + test_h_gr 0,r8 + + set_cc 0x07 ; Set mask opposite of expected + add2 -16,r8 ; Test negative bit + test_cc 1 0 0 0 + test_h_gr -16,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0c ; Set mask opposite of expected + add2 -1,r8 ; Test overflow bit + test_cc 0 0 1 1 + test_h_gr 0x7fffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addc.cgs b/sim/testsuite/sim/fr30/addc.cgs new file mode 100644 index 00000000000..e13547894b6 --- /dev/null +++ b/sim/testsuite/sim/fr30/addc.cgs @@ -0,0 +1,50 @@ +# fr30 testcase for addc $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0e ; Make sure carry bit is off + addc r7,r8 + test_cc 0 0 0 0 + test_h_gr 3,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 1,r8 + set_cc 0x04 ; Make sure carry bit is off + addc r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + set_cc 0x08 ; Make sure carry bit is off + addc r8,r8 + test_cc 0 1 1 1 + test_h_gr 0,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Make sure carry bit is on + addc r7,r8 + test_cc 0 0 0 0 + test_h_gr 4,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 0,r8 + set_cc 0x05 ; Make sure carry bit is on + addc r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0x7fffffff,r7 + set_cc 0x0b ; Make sure carry bit is on + addc r7,r8 + test_cc 0 1 0 1; + test_h_gr 0,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addn.cgs b/sim/testsuite/sim/fr30/addn.cgs new file mode 100644 index 00000000000..b7638d61995 --- /dev/null +++ b/sim/testsuite/sim/fr30/addn.cgs @@ -0,0 +1,55 @@ +# fr30 testcase for addn $Rj,$Ri, addn $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global addn +addn: + ; Test addn $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn r7,r8 + test_cc 1 1 1 1 + test_h_gr 3,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 1,r8 + set_cc 0x05 ; Set mask opposite of normal result + addn r7,r8 + test_cc 0 1 0 1 + test_h_gr 0x80000000,r8 + + set_cc 0x08 ; Set mask opposite of normal result + addn r8,r8 + test_cc 1 0 0 0 + test_h_gr 0,r8 + + ; Test addn $u4Ri + mvi_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn 0,r8 + test_cc 1 1 1 1 + test_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn 1,r8 + test_cc 1 1 1 1 + test_h_gr 5,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn 15,r8 + test_cc 1 1 1 1 + test_h_gr 20,r8 + mvi_h_gr 0x7fffffff,r8 ; test neg and overflow bits + set_cc 0x05 ; Set mask opposite of normal result + addn 1,r8 + test_cc 0 1 0 1 + test_h_gr 0x80000000,r8 + set_cc 0x08 ; Set mask opposite of normal result + addn r8,r8 ; test zero, carry and overflow bits + test_cc 1 0 0 0; + test_h_gr 0,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addn2.cgs b/sim/testsuite/sim/fr30/addn2.cgs new file mode 100644 index 00000000000..9525baf4502 --- /dev/null +++ b/sim/testsuite/sim/fr30/addn2.cgs @@ -0,0 +1,43 @@ +# fr30 testcase for addn2 $m4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + mvi_h_gr 30,r8 + set_cc 0x0e ; Set mask opposite of normal result + addn2 -16,r8 ; Max value of immediate field + test_cc 1 1 1 0 + test_h_gr 14,r8 + + set_cc 0x0e ; Set mask opposite of normal result + addn2 -3,r8 ; Mid value of immediate field + test_cc 1 1 1 0 + test_h_gr 11,r8 + + set_cc 0x0e ; Set mask opposite of normal result + addn2 -1,r8 ; Min value of immediate field + test_cc 1 1 1 0 + test_h_gr 10,r8 + + set_cc 0x0a ; Set mask opposite of normal result + addn2 -10,r8 ; Test zero and carry bits + test_cc 1 0 1 0 + test_h_gr 0,r8 + + set_cc 0x07 ; Set mask opposite of normal result + addn2 -16,r8 ; Test negative bit + test_cc 0 1 1 1 + test_h_gr -16,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0c ; Set mask opposite of normal result + addn2 -1,r8 ; Test overflow bit + test_cc 1 1 0 0 + test_h_gr 0x7fffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addsp.cgs b/sim/testsuite/sim/fr30/addsp.cgs new file mode 100644 index 00000000000..da5bc36b86a --- /dev/null +++ b/sim/testsuite/sim/fr30/addsp.cgs @@ -0,0 +1,31 @@ +# fr30 testcase for addsp $s10 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global addsp +addsp: + ; Test addsp $s10 + mvr_h_gr sp,r7 ; save stack pointer permanently + mvr_h_gr sp,r8 ; Shadow updated sp + set_cc 0x0f ; Condition codes are irrelevent + addsp 508 + test_cc 1 1 1 1 + inci_h_gr 508,r8 + testr_h_gr r8,sp + + set_cc 0x0e ; Condition codes are irrelevent + addsp 0 + test_cc 1 1 1 0 + testr_h_gr r8,sp + + set_cc 0x0d ; Condition codes are irrelevent + addsp -512 + test_cc 1 1 0 1 + inci_h_gr -512,r8 + testr_h_gr r8,sp + + pass diff --git a/sim/testsuite/sim/fr30/allinsn.exp b/sim/testsuite/sim/fr30/allinsn.exp new file mode 100644 index 00000000000..8c3d5121113 --- /dev/null +++ b/sim/testsuite/sim/fr30/allinsn.exp @@ -0,0 +1,19 @@ +# FR30 simulator testsuite. + +if [istarget fr30*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "fr30" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/fr30/and.cgs b/sim/testsuite/sim/fr30/and.cgs new file mode 100644 index 00000000000..49db6fd2ee1 --- /dev/null +++ b/sim/testsuite/sim/fr30/and.cgs @@ -0,0 +1,51 @@ +# fr30 testcase for and $Rj,$Ri, and $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global and +and: + ; Test and $Rj,$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0x55555555,r8 + set_cc 0x0b ; Set mask opposite of expected + and r7,r8 + test_cc 0 1 1 1 + test_h_gr 0,r8 + + mvi_h_gr 0xffff0000,r8 + set_cc 0x04 ; Set mask opposite of expected + and r7,r8 + test_cc 1 0 0 0 + test_h_gr 0xaaaa0000,r8 + + mvi_h_gr 0xffff,r8 + set_cc 0x0d ; Set mask opposite of expected + and r7,r8 + test_cc 0 0 0 1 + test_h_gr 0xaaaa,r8 + + ; Test and $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + and r7,@sp + test_cc 0 1 1 1 + test_h_mem 0,sp + + mvi_h_mem 0xffff0000,sp + set_cc 0x04 ; Set mask opposite of expected + and r7,@sp + test_cc 1 0 0 0 + test_h_mem 0xaaaa0000,sp + + mvi_h_mem 0xffff,sp + set_cc 0x0d ; Set mask opposite of expected + and r7,@sp + test_cc 0 0 0 1 + test_h_mem 0xaaaa,sp + + pass diff --git a/sim/testsuite/sim/fr30/andb.cgs b/sim/testsuite/sim/fr30/andb.cgs new file mode 100644 index 00000000000..c01d49d276b --- /dev/null +++ b/sim/testsuite/sim/fr30/andb.cgs @@ -0,0 +1,31 @@ +# fr30 testcase for andb $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global andb +andb: + ; Test andb $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + andb r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Set mask opposite of expected + andb r7,@sp + test_cc 1 0 0 0 + test_h_mem 0xaaffffff,sp + + mvi_h_mem 0x0fffffff,sp + set_cc 0x0d ; Set mask opposite of expected + andb r7,@sp + test_cc 0 0 0 1 + test_h_mem 0x0affffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/andccr.cgs b/sim/testsuite/sim/fr30/andccr.cgs new file mode 100644 index 00000000000..7f8f99e25f5 --- /dev/null +++ b/sim/testsuite/sim/fr30/andccr.cgs @@ -0,0 +1,51 @@ +# fr30 testcase for andccr $u8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global andccr +andccr: + set_cc 0x00 + set_i 0 + set_s_system + andccr 0xff + test_cc 0 0 0 0 + test_i 0 + test_s_system + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0xff + test_cc 1 1 1 1 + test_i 1 + test_s_user + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0xaa + test_cc 1 0 1 0 + test_i 0 + test_s_user + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0xc0 + test_cc 0 0 0 0 + test_i 0 + test_s_system + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0x3f ; no effect + test_cc 1 1 1 1 + test_i 1 + test_s_user + + pass diff --git a/sim/testsuite/sim/fr30/andh.cgs b/sim/testsuite/sim/fr30/andh.cgs new file mode 100644 index 00000000000..a172fc764f2 --- /dev/null +++ b/sim/testsuite/sim/fr30/andh.cgs @@ -0,0 +1,31 @@ +# fr30 testcase for andh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global andh +andh: + ; Test andh $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + andh r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00005555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Set mask opposite of expected + andh r7,@sp + test_cc 1 0 0 0 + test_h_mem 0xaaaaffff,sp + + mvi_h_mem 0x00ffffff,sp + set_cc 0x0d ; Set mask opposite of expected + andh r7,@sp + test_cc 0 0 0 1 + test_h_mem 0x00aaffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/asr.cgs b/sim/testsuite/sim/fr30/asr.cgs new file mode 100644 index 00000000000..f783d41ba3d --- /dev/null +++ b/sim/testsuite/sim/fr30/asr.cgs @@ -0,0 +1,65 @@ +# fr30 testcase for asr $Rj,$Ri, asr $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global asr +asr: + ; Test asr $Rj,$Ri + mvi_h_gr 0xdeadbee0,r7 ; Shift by 0 + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + asr r7,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0xdeadbee1,r7 ; Shift by 1 + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr r7,r8 + test_cc 1 0 1 0 + test_h_gr 0xc0000000,r8 + + mvi_h_gr 0xdeadbeff,r7 ; Shift by 31 + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr r7,r8 + test_cc 1 0 1 0 + test_h_gr -1,r8 + + mvi_h_gr 0xdeadbeff,r7 ; clear register + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + asr r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + ; Test asr $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + asr 0,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr 1,r8 + test_cc 1 0 1 0 + test_h_gr 0xc0000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr 15,r8 + test_cc 1 0 1 0 + test_h_gr 0xffff0000,r8 + + mvi_h_gr 0x00004000,r8 + set_cc 0x0a ; Set mask opposite of expected + asr 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/asr2.cgs b/sim/testsuite/sim/fr30/asr2.cgs new file mode 100644 index 00000000000..884e40d5c84 --- /dev/null +++ b/sim/testsuite/sim/fr30/asr2.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for asr2 $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global asr2 +asr2: + ; Test asr2 $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + asr2 0,r8 + test_cc 1 0 0 0 + test_h_gr 0xffff8000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr2 1,r8 + test_cc 1 0 1 0 + test_h_gr 0xffffc000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr2 15,r8 + test_cc 1 0 1 0 + test_h_gr -1,r8 + + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + asr2 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/bandh.cgs b/sim/testsuite/sim/fr30/bandh.cgs new file mode 100644 index 00000000000..45ab5e59f3a --- /dev/null +++ b/sim/testsuite/sim/fr30/bandh.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for bandh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bandh +bandh: + ; Test bandh $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + bandh 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x05555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Condition codes should not change + bandh 0x0a,@sp + test_cc 0 1 0 0 + test_h_mem 0xafffffff,sp + + mvi_h_mem 0xe5ffffff,sp + set_cc 0x0a ; Condition codes should not change + bandh 0x07,@sp + test_cc 1 0 1 0 + test_h_mem 0x65ffffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/bandl.cgs b/sim/testsuite/sim/fr30/bandl.cgs new file mode 100644 index 00000000000..9cd4825965a --- /dev/null +++ b/sim/testsuite/sim/fr30/bandl.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for bandl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bandl +bandl: + ; Test bandl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + bandl 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x50555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Condition codes should not change + bandl 0x0a,@sp + test_cc 0 1 0 0 + test_h_mem 0xfaffffff,sp + + mvi_h_mem 0x5effffff,sp + set_cc 0x0a ; Condition codes should not change + bandl 0x07,@sp + test_cc 1 0 1 0 + test_h_mem 0x56ffffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/bc.cgs b/sim/testsuite/sim/fr30/bc.cgs new file mode 100644 index 00000000000..0502625d32e --- /dev/null +++ b/sim/testsuite/sim/fr30/bc.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bc $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bc +bc: + ; Test bc $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bc + + set_cc 0x0e ; condition codes are irrelevent + no_branch bc + + set_cc 0x0d ; condition codes are irrelevent + take_branch bc + + set_cc 0x0c ; condition codes are irrelevent + no_branch bc + + set_cc 0x0b ; condition codes are irrelevent + take_branch bc + + set_cc 0x0a ; condition codes are irrelevent + no_branch bc + + set_cc 0x09 ; condition codes are irrelevent + take_branch bc + + set_cc 0x08 ; condition codes are irrelevent + no_branch bc + + set_cc 0x07 ; condition codes are irrelevent + take_branch bc + + set_cc 0x06 ; condition codes are irrelevent + no_branch bc + + set_cc 0x05 ; condition codes are irrelevent + take_branch bc + + set_cc 0x04 ; condition codes are irrelevent + no_branch bc + + set_cc 0x03 ; condition codes are irrelevent + take_branch bc + + set_cc 0x02 ; condition codes are irrelevent + no_branch bc + + set_cc 0x01 ; condition codes are irrelevent + take_branch bc + + set_cc 0x00 ; condition codes are irrelevent + no_branch bc + + ; Test bc:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bc:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bc:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bc:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bc:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bc:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bc:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bc:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bc:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bc:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bc:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bc:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bc:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bc:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bc:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bc:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bc:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/beorh.cgs b/sim/testsuite/sim/fr30/beorh.cgs new file mode 100644 index 00000000000..6d07f1af788 --- /dev/null +++ b/sim/testsuite/sim/fr30/beorh.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for beorh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global beorh +beorh: + ; Test beorh $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + beorh 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0xf5555555,sp + + mvi_h_mem 0x0fffffff,sp + set_cc 0x04 ; Condition codes should not change + beorh 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0x0fffffff,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x0a ; Condition codes should not change + beorh 0x0f,@sp + test_cc 1 0 1 0 + test_h_mem 0x0fffffff,sp + + mvi_h_mem 0x9eadbeef,sp + set_cc 0x09 ; Condition codes should not change + beorh 0x04,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/beorl.cgs b/sim/testsuite/sim/fr30/beorl.cgs new file mode 100644 index 00000000000..f7ea05347b3 --- /dev/null +++ b/sim/testsuite/sim/fr30/beorl.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for beorl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global beorl +beorl: + ; Test beorl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + beorl 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x5f555555,sp + + mvi_h_mem 0xf0ffffff,sp + set_cc 0x04 ; Condition codes should not change + beorl 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0xf0ffffff,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x0a ; Condition codes should not change + beorl 0x0f,@sp + test_cc 1 0 1 0 + test_h_mem 0xf0ffffff,sp + + mvi_h_mem 0xddadbeef,sp + set_cc 0x09 ; Condition codes should not change + beorl 0x03,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/beq.cgs b/sim/testsuite/sim/fr30/beq.cgs new file mode 100644 index 00000000000..edd797e4ed2 --- /dev/null +++ b/sim/testsuite/sim/fr30/beq.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for beq $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global beq +beq: + ; Test beq $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch beq + + set_cc 0x0e ; condition codes are irrelevent + take_branch beq + + set_cc 0x0d ; condition codes are irrelevent + take_branch beq + + set_cc 0x0c ; condition codes are irrelevent + take_branch beq + + set_cc 0x0b ; condition codes are irrelevent + no_branch beq + + set_cc 0x0a ; condition codes are irrelevent + no_branch beq + + set_cc 0x09 ; condition codes are irrelevent + no_branch beq + + set_cc 0x08 ; condition codes are irrelevent + no_branch beq + + set_cc 0x07 ; condition codes are irrelevent + take_branch beq + + set_cc 0x06 ; condition codes are irrelevent + take_branch beq + + set_cc 0x05 ; condition codes are irrelevent + take_branch beq + + set_cc 0x04 ; condition codes are irrelevent + take_branch beq + + set_cc 0x03 ; condition codes are irrelevent + no_branch beq + + set_cc 0x02 ; condition codes are irrelevent + no_branch beq + + set_cc 0x01 ; condition codes are irrelevent + no_branch beq + + set_cc 0x00 ; condition codes are irrelevent + no_branch beq + + ; Test beq:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d beq:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d beq:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d beq:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d beq:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d beq:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d beq:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d beq:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d beq:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d beq:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d beq:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d beq:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d beq:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d beq:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d beq:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d beq:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d beq:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bge.cgs b/sim/testsuite/sim/fr30/bge.cgs new file mode 100644 index 00000000000..dd7796ccd94 --- /dev/null +++ b/sim/testsuite/sim/fr30/bge.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bge $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bge +bge: + ; Test bge $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bge + + set_cc 0x0e ; condition codes are irrelevent + take_branch bge + + set_cc 0x0d ; condition codes are irrelevent + no_branch bge + + set_cc 0x0c ; condition codes are irrelevent + no_branch bge + + set_cc 0x0b ; condition codes are irrelevent + take_branch bge + + set_cc 0x0a ; condition codes are irrelevent + take_branch bge + + set_cc 0x09 ; condition codes are irrelevent + no_branch bge + + set_cc 0x08 ; condition codes are irrelevent + no_branch bge + + set_cc 0x07 ; condition codes are irrelevent + no_branch bge + + set_cc 0x06 ; condition codes are irrelevent + no_branch bge + + set_cc 0x05 ; condition codes are irrelevent + take_branch bge + + set_cc 0x04 ; condition codes are irrelevent + take_branch bge + + set_cc 0x03 ; condition codes are irrelevent + no_branch bge + + set_cc 0x02 ; condition codes are irrelevent + no_branch bge + + set_cc 0x01 ; condition codes are irrelevent + take_branch bge + + set_cc 0x00 ; condition codes are irrelevent + take_branch bge + + ; Test bge:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bge:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bge:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bge:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bge:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bge:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bge:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bge:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bge:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bge:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bge:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bge:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bge:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bge:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bge:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bge:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bge:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bgt.cgs b/sim/testsuite/sim/fr30/bgt.cgs new file mode 100644 index 00000000000..525ac2e8f32 --- /dev/null +++ b/sim/testsuite/sim/fr30/bgt.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bgt $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bgt +bgt: + ; Test bgt $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0e ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0d ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0c ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0b ; condition codes are irrelevent + take_branch bgt + + set_cc 0x0a ; condition codes are irrelevent + take_branch bgt + + set_cc 0x09 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x08 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x07 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x06 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x05 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x04 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x03 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x02 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x01 ; condition codes are irrelevent + take_branch bgt + + set_cc 0x00 ; condition codes are irrelevent + take_branch bgt + + ; Test bgt:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bgt:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bgt:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bgt:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bgt:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bgt:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bgt:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bgt:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bgt:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bgt:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bgt:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bgt:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bgt:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bgt:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bgt:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bgt:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bgt:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bhi.cgs b/sim/testsuite/sim/fr30/bhi.cgs new file mode 100644 index 00000000000..f5a15492063 --- /dev/null +++ b/sim/testsuite/sim/fr30/bhi.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bhi $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bhi +bhi: + ; Test bhi $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0e ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0d ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0c ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0b ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0a ; condition codes are irrelevent + take_branch bhi + + set_cc 0x09 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x08 ; condition codes are irrelevent + take_branch bhi + + set_cc 0x07 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x06 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x05 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x04 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x03 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x02 ; condition codes are irrelevent + take_branch bhi + + set_cc 0x01 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x00 ; condition codes are irrelevent + take_branch bhi + + ; Test bhi:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bhi:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bhi:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bhi:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bhi:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bhi:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bhi:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bhi:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bhi:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bhi:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bhi:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bhi:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bhi:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bhi:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bhi:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bhi:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bhi:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/ble.cgs b/sim/testsuite/sim/fr30/ble.cgs new file mode 100644 index 00000000000..1a33f783ce3 --- /dev/null +++ b/sim/testsuite/sim/fr30/ble.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for ble $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ble +ble: + ; Test ble $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch ble + + set_cc 0x0e ; condition codes are irrelevent + take_branch ble + + set_cc 0x0d ; condition codes are irrelevent + take_branch ble + + set_cc 0x0c ; condition codes are irrelevent + take_branch ble + + set_cc 0x0b ; condition codes are irrelevent + no_branch ble + + set_cc 0x0a ; condition codes are irrelevent + no_branch ble + + set_cc 0x09 ; condition codes are irrelevent + take_branch ble + + set_cc 0x08 ; condition codes are irrelevent + take_branch ble + + set_cc 0x07 ; condition codes are irrelevent + take_branch ble + + set_cc 0x06 ; condition codes are irrelevent + take_branch ble + + set_cc 0x05 ; condition codes are irrelevent + take_branch ble + + set_cc 0x04 ; condition codes are irrelevent + take_branch ble + + set_cc 0x03 ; condition codes are irrelevent + take_branch ble + + set_cc 0x02 ; condition codes are irrelevent + take_branch ble + + set_cc 0x01 ; condition codes are irrelevent + no_branch ble + + set_cc 0x00 ; condition codes are irrelevent + no_branch ble + + ; Test ble:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d ble:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d ble:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d ble:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d ble:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d ble:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d ble:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d ble:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d ble:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d ble:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d ble:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d ble:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d ble:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d ble:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d ble:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d ble:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d ble:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bls.cgs b/sim/testsuite/sim/fr30/bls.cgs new file mode 100644 index 00000000000..c0148b7b901 --- /dev/null +++ b/sim/testsuite/sim/fr30/bls.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bls $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bls +bls: + ; Test bls $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bls + + set_cc 0x0e ; condition codes are irrelevent + take_branch bls + + set_cc 0x0d ; condition codes are irrelevent + take_branch bls + + set_cc 0x0c ; condition codes are irrelevent + take_branch bls + + set_cc 0x0b ; condition codes are irrelevent + take_branch bls + + set_cc 0x0a ; condition codes are irrelevent + no_branch bls + + set_cc 0x09 ; condition codes are irrelevent + take_branch bls + + set_cc 0x08 ; condition codes are irrelevent + no_branch bls + + set_cc 0x07 ; condition codes are irrelevent + take_branch bls + + set_cc 0x06 ; condition codes are irrelevent + take_branch bls + + set_cc 0x05 ; condition codes are irrelevent + take_branch bls + + set_cc 0x04 ; condition codes are irrelevent + take_branch bls + + set_cc 0x03 ; condition codes are irrelevent + take_branch bls + + set_cc 0x02 ; condition codes are irrelevent + no_branch bls + + set_cc 0x01 ; condition codes are irrelevent + take_branch bls + + set_cc 0x00 ; condition codes are irrelevent + no_branch bls + + ; Test bls:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bls:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bls:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bls:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bls:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bls:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bls:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bls:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bls:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bls:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bls:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bls:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bls:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bls:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bls:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bls:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bls:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/blt.cgs b/sim/testsuite/sim/fr30/blt.cgs new file mode 100644 index 00000000000..f7b6ff114bf --- /dev/null +++ b/sim/testsuite/sim/fr30/blt.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for blt $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global blt +blt: + ; Test blt $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch blt + + set_cc 0x0e ; condition codes are irrelevent + no_branch blt + + set_cc 0x0d ; condition codes are irrelevent + take_branch blt + + set_cc 0x0c ; condition codes are irrelevent + take_branch blt + + set_cc 0x0b ; condition codes are irrelevent + no_branch blt + + set_cc 0x0a ; condition codes are irrelevent + no_branch blt + + set_cc 0x09 ; condition codes are irrelevent + take_branch blt + + set_cc 0x08 ; condition codes are irrelevent + take_branch blt + + set_cc 0x07 ; condition codes are irrelevent + take_branch blt + + set_cc 0x06 ; condition codes are irrelevent + take_branch blt + + set_cc 0x05 ; condition codes are irrelevent + no_branch blt + + set_cc 0x04 ; condition codes are irrelevent + no_branch blt + + set_cc 0x03 ; condition codes are irrelevent + take_branch blt + + set_cc 0x02 ; condition codes are irrelevent + take_branch blt + + set_cc 0x01 ; condition codes are irrelevent + no_branch blt + + set_cc 0x00 ; condition codes are irrelevent + no_branch blt + + ; Test blt:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d blt:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d blt:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d blt:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d blt:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d blt:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d blt:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d blt:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d blt:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d blt:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d blt:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d blt:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d blt:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d blt:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d blt:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d blt:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d blt:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bn.cgs b/sim/testsuite/sim/fr30/bn.cgs new file mode 100644 index 00000000000..45858fc97ee --- /dev/null +++ b/sim/testsuite/sim/fr30/bn.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bn $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bn +bn: + ; Test bn $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bn + + set_cc 0x0e ; condition codes are irrelevent + take_branch bn + + set_cc 0x0d ; condition codes are irrelevent + take_branch bn + + set_cc 0x0c ; condition codes are irrelevent + take_branch bn + + set_cc 0x0b ; condition codes are irrelevent + take_branch bn + + set_cc 0x0a ; condition codes are irrelevent + take_branch bn + + set_cc 0x09 ; condition codes are irrelevent + take_branch bn + + set_cc 0x08 ; condition codes are irrelevent + take_branch bn + + set_cc 0x07 ; condition codes are irrelevent + no_branch bn + + set_cc 0x06 ; condition codes are irrelevent + no_branch bn + + set_cc 0x05 ; condition codes are irrelevent + no_branch bn + + set_cc 0x04 ; condition codes are irrelevent + no_branch bn + + set_cc 0x03 ; condition codes are irrelevent + no_branch bn + + set_cc 0x02 ; condition codes are irrelevent + no_branch bn + + set_cc 0x01 ; condition codes are irrelevent + no_branch bn + + set_cc 0x00 ; condition codes are irrelevent + no_branch bn + + ; Test bn:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bn:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bn:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bn:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bn:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bn:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bn:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bn:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bn:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bn:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bn:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bn:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bn:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bn:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bn:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bn:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bn:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bnc.cgs b/sim/testsuite/sim/fr30/bnc.cgs new file mode 100644 index 00000000000..9968c43737c --- /dev/null +++ b/sim/testsuite/sim/fr30/bnc.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bnc $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bnc +bc: + ; Test bnc $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bnc + + set_cc 0x0e ; condition codes are irrelevent + take_branch bnc + + set_cc 0x0d ; condition codes are irrelevent + no_branch bnc + + set_cc 0x0c ; condition codes are irrelevent + take_branch bnc + + set_cc 0x0b ; condition codes are irrelevent + no_branch bnc + + set_cc 0x0a ; condition codes are irrelevent + take_branch bnc + + set_cc 0x09 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x08 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x07 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x06 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x05 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x04 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x03 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x02 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x01 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x00 ; condition codes are irrelevent + take_branch bnc + + ; Test bnc:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bnc:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bnc:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bnc:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bnc:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bnc:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bnc:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bnc:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bnc:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bnc:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bnc:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bnc:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bnc:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bnc:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bnc:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bnc:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bnc:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bne.cgs b/sim/testsuite/sim/fr30/bne.cgs new file mode 100644 index 00000000000..58971de1326 --- /dev/null +++ b/sim/testsuite/sim/fr30/bne.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bne $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bne +bne: + ; Test bne $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bne + + set_cc 0x0e ; condition codes are irrelevent + no_branch bne + + set_cc 0x0d ; condition codes are irrelevent + no_branch bne + + set_cc 0x0c ; condition codes are irrelevent + no_branch bne + + set_cc 0x0b ; condition codes are irrelevent + take_branch bne + + set_cc 0x0a ; condition codes are irrelevent + take_branch bne + + set_cc 0x09 ; condition codes are irrelevent + take_branch bne + + set_cc 0x08 ; condition codes are irrelevent + take_branch bne + + set_cc 0x07 ; condition codes are irrelevent + no_branch bne + + set_cc 0x06 ; condition codes are irrelevent + no_branch bne + + set_cc 0x05 ; condition codes are irrelevent + no_branch bne + + set_cc 0x04 ; condition codes are irrelevent + no_branch bne + + set_cc 0x03 ; condition codes are irrelevent + take_branch bne + + set_cc 0x02 ; condition codes are irrelevent + take_branch bne + + set_cc 0x01 ; condition codes are irrelevent + take_branch bne + + set_cc 0x00 ; condition codes are irrelevent + take_branch bne + + ; Test bne:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bne:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bne:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bne:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bne:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bne:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bne:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bne:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bne:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bne:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bne:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bne:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bne:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bne:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bne:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bne:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bne:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bno.cgs b/sim/testsuite/sim/fr30/bno.cgs new file mode 100644 index 00000000000..faef9ba0380 --- /dev/null +++ b/sim/testsuite/sim/fr30/bno.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bno $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bno +bno: + ; Test bno $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bno + + set_cc 0x0e ; condition codes are irrelevent + no_branch bno + + set_cc 0x0d ; condition codes are irrelevent + no_branch bno + + set_cc 0x0c ; condition codes are irrelevent + no_branch bno + + set_cc 0x0b ; condition codes are irrelevent + no_branch bno + + set_cc 0x0a ; condition codes are irrelevent + no_branch bno + + set_cc 0x09 ; condition codes are irrelevent + no_branch bno + + set_cc 0x08 ; condition codes are irrelevent + no_branch bno + + set_cc 0x07 ; condition codes are irrelevent + no_branch bno + + set_cc 0x06 ; condition codes are irrelevent + no_branch bno + + set_cc 0x05 ; condition codes are irrelevent + no_branch bno + + set_cc 0x04 ; condition codes are irrelevent + no_branch bno + + set_cc 0x03 ; condition codes are irrelevent + no_branch bno + + set_cc 0x02 ; condition codes are irrelevent + no_branch bno + + set_cc 0x01 ; condition codes are irrelevent + no_branch bno + + set_cc 0x00 ; condition codes are irrelevent + no_branch bno + + ; Test bno:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bno:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bno:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bno:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bno:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bno:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bno:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bno:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bno:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bno:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bno:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bno:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bno:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bno:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bno:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bno:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bno:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bnv.cgs b/sim/testsuite/sim/fr30/bnv.cgs new file mode 100644 index 00000000000..7615abd6c7d --- /dev/null +++ b/sim/testsuite/sim/fr30/bnv.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bnv $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bnv +bnv: + ; Test bnv $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bnv + + set_cc 0x0e ; condition codes are irrelevent + no_branch bnv + + set_cc 0x0d ; condition codes are irrelevent + take_branch bnv + + set_cc 0x0c ; condition codes are irrelevent + take_branch bnv + + set_cc 0x0b ; condition codes are irrelevent + no_branch bnv + + set_cc 0x0a ; condition codes are irrelevent + no_branch bnv + + set_cc 0x09 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x08 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x07 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x06 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x05 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x04 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x03 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x02 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x01 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x00 ; condition codes are irrelevent + take_branch bnv + + ; Test bnv:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bnv:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bnv:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bnv:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bnv:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bnv:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bnv:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bnv:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bnv:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bnv:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bnv:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bnv:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bnv:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bnv:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bnv:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bnv:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bnv:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/borh.cgs b/sim/testsuite/sim/fr30/borh.cgs new file mode 100644 index 00000000000..039f18a37e2 --- /dev/null +++ b/sim/testsuite/sim/fr30/borh.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for borh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global borh +borh: + ; Test borh $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + borh 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0xf5555555,sp + + mvi_h_mem 0x0fffffff,sp + set_cc 0x04 ; Condition codes should not change + borh 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0x0fffffff,sp + + mvi_h_mem 0xceadbeef,sp + set_cc 0x09 ; Condition codes should not change + borh 0x01,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/borl.cgs b/sim/testsuite/sim/fr30/borl.cgs new file mode 100644 index 00000000000..beb2bbbaa2d --- /dev/null +++ b/sim/testsuite/sim/fr30/borl.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for borl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global borl +borl: + ; Test borl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + borl 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x5f555555,sp + + mvi_h_mem 0xf0ffffff,sp + set_cc 0x04 ; Condition codes should not change + borl 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0xf0ffffff,sp + + mvi_h_mem 0xdcadbeef,sp + set_cc 0x09 ; Condition codes should not change + borl 0x02,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/bp.cgs b/sim/testsuite/sim/fr30/bp.cgs new file mode 100644 index 00000000000..375328305e0 --- /dev/null +++ b/sim/testsuite/sim/fr30/bp.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bp $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bp +bp: + ; Test bp $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bp + + set_cc 0x0e ; condition codes are irrelevent + no_branch bp + + set_cc 0x0d ; condition codes are irrelevent + no_branch bp + + set_cc 0x0c ; condition codes are irrelevent + no_branch bp + + set_cc 0x0b ; condition codes are irrelevent + no_branch bp + + set_cc 0x0a ; condition codes are irrelevent + no_branch bp + + set_cc 0x09 ; condition codes are irrelevent + no_branch bp + + set_cc 0x08 ; condition codes are irrelevent + no_branch bp + + set_cc 0x07 ; condition codes are irrelevent + take_branch bp + + set_cc 0x06 ; condition codes are irrelevent + take_branch bp + + set_cc 0x05 ; condition codes are irrelevent + take_branch bp + + set_cc 0x04 ; condition codes are irrelevent + take_branch bp + + set_cc 0x03 ; condition codes are irrelevent + take_branch bp + + set_cc 0x02 ; condition codes are irrelevent + take_branch bp + + set_cc 0x01 ; condition codes are irrelevent + take_branch bp + + set_cc 0x00 ; condition codes are irrelevent + take_branch bp + + ; Test bp:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bp:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bp:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bp:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bp:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bp:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bp:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bp:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bp:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bp:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bp:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bp:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bp:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bp:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bp:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bp:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bp:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bra.cgs b/sim/testsuite/sim/fr30/bra.cgs new file mode 100644 index 00000000000..3732f74a3ed --- /dev/null +++ b/sim/testsuite/sim/fr30/bra.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bra $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bra +bra: + ; Test bra $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bra + + set_cc 0x0e ; condition codes are irrelevent + take_branch bra + + set_cc 0x0d ; condition codes are irrelevent + take_branch bra + + set_cc 0x0c ; condition codes are irrelevent + take_branch bra + + set_cc 0x0b ; condition codes are irrelevent + take_branch bra + + set_cc 0x0a ; condition codes are irrelevent + take_branch bra + + set_cc 0x09 ; condition codes are irrelevent + take_branch bra + + set_cc 0x08 ; condition codes are irrelevent + take_branch bra + + set_cc 0x07 ; condition codes are irrelevent + take_branch bra + + set_cc 0x06 ; condition codes are irrelevent + take_branch bra + + set_cc 0x05 ; condition codes are irrelevent + take_branch bra + + set_cc 0x04 ; condition codes are irrelevent + take_branch bra + + set_cc 0x03 ; condition codes are irrelevent + take_branch bra + + set_cc 0x02 ; condition codes are irrelevent + take_branch bra + + set_cc 0x01 ; condition codes are irrelevent + take_branch bra + + set_cc 0x00 ; condition codes are irrelevent + take_branch bra + + ; Test bra:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bra:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bra:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bra:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bra:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bra:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bra:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bra:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bra:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bra:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bra:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bra:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bra:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bra:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bra:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bra:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bra:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/btsth.cgs b/sim/testsuite/sim/fr30/btsth.cgs new file mode 100644 index 00000000000..2897c340555 --- /dev/null +++ b/sim/testsuite/sim/fr30/btsth.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for btsth $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global btsth +btsth: + ; Test btsth $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + btsth 0x0a,@sp + test_cc 0 1 1 1 + test_h_mem 0x55555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Set mask opposite of expected + btsth 0x0a,@sp + test_cc 1 0 0 0 + test_h_mem 0xffffffff,sp + + mvi_h_mem 0xe5ffffff,sp + set_cc 0x0e ; Set mask opposite of expected + btsth 0x07,@sp + test_cc 0 0 1 0 + test_h_mem 0xe5ffffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/btstl.cgs b/sim/testsuite/sim/fr30/btstl.cgs new file mode 100644 index 00000000000..cef5a927190 --- /dev/null +++ b/sim/testsuite/sim/fr30/btstl.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for btstl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global btstl +btstl: + ; Test btstl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + btstl 0x0a,@sp + test_cc 0 1 1 1 + test_h_mem 0x55555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x0c ; Set mask opposite of expected + btstl 0x0a,@sp + test_cc 0 0 0 0 + test_h_mem 0xffffffff,sp + + mvi_h_mem 0x5effffff,sp + set_cc 0x0e ; Set mask opposite of expected + btstl 0x07,@sp + test_cc 0 0 1 0 + test_h_mem 0x5effffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/bv.cgs b/sim/testsuite/sim/fr30/bv.cgs new file mode 100644 index 00000000000..68cb9acf165 --- /dev/null +++ b/sim/testsuite/sim/fr30/bv.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bv $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bv +bv: + ; Test bv $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bv + + set_cc 0x0e ; condition codes are irrelevent + take_branch bv + + set_cc 0x0d ; condition codes are irrelevent + no_branch bv + + set_cc 0x0c ; condition codes are irrelevent + no_branch bv + + set_cc 0x0b ; condition codes are irrelevent + take_branch bv + + set_cc 0x0a ; condition codes are irrelevent + take_branch bv + + set_cc 0x09 ; condition codes are irrelevent + no_branch bv + + set_cc 0x08 ; condition codes are irrelevent + no_branch bv + + set_cc 0x07 ; condition codes are irrelevent + take_branch bv + + set_cc 0x06 ; condition codes are irrelevent + take_branch bv + + set_cc 0x05 ; condition codes are irrelevent + no_branch bv + + set_cc 0x04 ; condition codes are irrelevent + no_branch bv + + set_cc 0x03 ; condition codes are irrelevent + take_branch bv + + set_cc 0x02 ; condition codes are irrelevent + take_branch bv + + set_cc 0x01 ; condition codes are irrelevent + no_branch bv + + set_cc 0x00 ; condition codes are irrelevent + no_branch bv + + ; Test bv:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bv:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bv:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bv:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bv:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bv:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bv:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bv:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bv:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bv:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bv:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bv:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bv:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bv:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bv:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bv:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bv:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/call.cgs b/sim/testsuite/sim/fr30/call.cgs new file mode 100644 index 00000000000..413840ed350 --- /dev/null +++ b/sim/testsuite/sim/fr30/call.cgs @@ -0,0 +1,69 @@ +# fr30 testcase for call @$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global call + + ; Test call $Ri + mvi_h_gr 0xdeadbeef,r9 + mvi_h_gr #func1,r0 + set_cc 0x0f ; condition codes shouldn't change +call1: + call @r0 + test_h_gr 0xbeefdead,r9 + pass + +func1: + test_cc 1 1 1 1 + mvi_h_gr #call1,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + mvi_h_gr #func2,r0 + set_cc 0x0f ; condition codes shouldn't change +call2: + call:d @r0 + ldi:8 1,r0 ; Must assume this works + restore_rp + ret +func2: + test_cc 1 1 1 1 + mvi_h_gr #call2,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call3: + call func3 + restore_rp + ret +func3: + test_cc 1 1 1 1 + mvi_h_gr #call3,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call4: + call:d func4 + ldi:8 1,r0 ; Must assume this works + restore_rp + ret +func4: + test_cc 1 1 1 1 + mvi_h_gr #call4,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + mvi_h_gr 0xbeefdead,r9 + ret + + fail diff --git a/sim/testsuite/sim/fr30/cmp.cgs b/sim/testsuite/sim/fr30/cmp.cgs new file mode 100644 index 00000000000..7bfbbf8f1c9 --- /dev/null +++ b/sim/testsuite/sim/fr30/cmp.cgs @@ -0,0 +1,53 @@ +# fr30 testcase for cmp $Rj,$Ri, cmp $u4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global cmp +cmp: + ; Test cmp $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + cmp r7,r8 + test_cc 0 0 0 0 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + cmp r7,r8 + test_cc 0 0 1 0 + + set_cc 0x0b ; Set mask opposite of expected + cmp r8,r8 + test_cc 0 1 0 0 + + mvi_h_gr 0,r8 + set_cc 0x06 ; Set mask opposite of expected + cmp r7,r8 + test_cc 1 0 0 1 + + ; Test cmp $u4,$Ri + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + cmp 1,r8 + test_cc 0 0 0 0 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + cmp 1,r8 + test_cc 0 0 1 0 + + mvi_h_gr 0,r8 + set_cc 0x0b ; Set mask opposite of expected + cmp 0,r8 + test_cc 0 1 0 0 + + set_cc 0x06 ; Set mask opposite of expected + cmp 15,r8 + test_cc 1 0 0 1 + + pass diff --git a/sim/testsuite/sim/fr30/cmp2.cgs b/sim/testsuite/sim/fr30/cmp2.cgs new file mode 100644 index 00000000000..7ba62013cad --- /dev/null +++ b/sim/testsuite/sim/fr30/cmp2.cgs @@ -0,0 +1,27 @@ +# fr30 testcase for cmp2 $u4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global cmp2 +cmp2: + ; Test cmp2 $u4,$Ri + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + cmp2 -1,r8 + test_cc 0 0 0 1 + + mvi_h_gr 0x7ffffffe,r8 + set_cc 0x04 ; Set mask opposite of expected + cmp2 -2,r8 + test_cc 1 0 1 1 + + mvi_h_gr -16,r8 + set_cc 0x0b ; Set mask opposite of expected + cmp2 -16,r8 + test_cc 0 1 0 0 + + pass diff --git a/sim/testsuite/sim/fr30/copld.cgs b/sim/testsuite/sim/fr30/copld.cgs new file mode 100644 index 00000000000..e0ababb0e85 --- /dev/null +++ b/sim/testsuite/sim/fr30/copld.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copld $u4,$cc,$Rj,CRi +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copld +copld: + ; Test copld copld $u4,$cc,$Rj,CRi + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copld 0,0,r0,cr15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copld 15,255,r15,cr0 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/copop.cgs b/sim/testsuite/sim/fr30/copop.cgs new file mode 100644 index 00000000000..b0afd77005b --- /dev/null +++ b/sim/testsuite/sim/fr30/copop.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copop $u4,$cc,$CRj,CRi +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copop +copop: + ; Test copop copop $u4,$cc,$CRj,CRi + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copop 0,0,cr0,cr15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copop 15,255,cr0,cr15 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/copst.cgs b/sim/testsuite/sim/fr30/copst.cgs new file mode 100644 index 00000000000..00120b2096c --- /dev/null +++ b/sim/testsuite/sim/fr30/copst.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copst $u4,$cc,$CRj,Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copst +copst: + ; Test copst copst $u4,$cc,$CRj,Ri + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copst 0,0,cr0,r15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copst 15,255,cr15,r0 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/copsv.cgs b/sim/testsuite/sim/fr30/copsv.cgs new file mode 100644 index 00000000000..e00a4f5315c --- /dev/null +++ b/sim/testsuite/sim/fr30/copsv.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copsv $u4,$cc,$CRj,Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copsv +copsv: + ; Test copsv copsv $u4,$cc,$CRj,Ri + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copsv 0,0,cr0,r15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copsv 15,255,cr15,r0 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/div.ms b/sim/testsuite/sim/fr30/div.ms new file mode 100644 index 00000000000..7e3aaf20ae0 --- /dev/null +++ b/sim/testsuite/sim/fr30/div.ms @@ -0,0 +1,176 @@ +# fr30 testcase for division +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div +div: + ; simple division 12 / 3 + mvi_h_gr 0x00000003,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0x0000000c,mdl + div0s r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div2 r2 + div3 + div4s + test_h_gr 0x00000003,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x00000004,mdl + test_dbits 0x0 + + ; example 1 from div0s the manual + mvi_h_gr 0x01234567,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + div0s r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div2 r2 + div3 + div4s + test_h_gr 0x01234567,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xffffffff,mdl + test_dbits 0x3 + + ; example 2 from div0s the manual + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + mvi_h_gr 0x1234567,r2 + mvi_h_gr 1,r0 + mvi_h_gr 32,r1 + div0s r2 +loop1: sub r0,r1 + bne:d loop1 + div1 r2 + div2 r2 + div3 + div4s + test_h_gr 0x01234567,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xffffffff,mdl + test_dbits 0x3 + + ; example 1 from div0u in the manual + mvi_h_gr 0x01234567,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + div0u r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + test_h_gr 0x01234567,r2 + test_h_dr 0x00000078,mdh + test_h_dr 0x000000e0,mdl + test_dbits 0x0 + + ; example 2 from div0u in the manual + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + mvi_h_gr 0x1234567,r2 + mvi_h_gr 1,r0 + mvi_h_gr 32,r1 + div0u r2 +loop2: sub r0,r1 + bne:d loop2 + div1 r2 + test_h_gr 0x01234567,r2 + test_h_dr 0x00000078,mdh + test_h_dr 0x000000e0,mdl + test_dbits 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/div0s.cgs b/sim/testsuite/sim/fr30/div0s.cgs new file mode 100644 index 00000000000..84d76c4bfb9 --- /dev/null +++ b/sim/testsuite/sim/fr30/div0s.cgs @@ -0,0 +1,64 @@ +# fr30 testcase for div0s $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div0s +div0s: + ; Test div0s $Rj,$Ri + ; example from the manual - negative dividend + mvi_h_gr 0x0fffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0xfffffff0,mdl + set_dbits 0x0 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0x0fffffff,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xfffffff0,mdl + test_dbits 0x3 + + ; negative divisor + mvi_h_gr 0xffffffff,r2 + mvi_h_dr 0xffffffff,mdh + mvi_h_dr 0x7fffffff,mdl + set_dbits 0x1 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0xffffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x7fffffff,mdl + test_dbits 0x2 + + ; Both sign bits 0 + mvi_h_gr 0x0fffffff,r2 + mvi_h_dr 0xffffffff,mdh + mvi_h_dr 0x7ffffff0,mdl + set_dbits 0x3 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0x0fffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x7ffffff0,mdl + test_dbits 0x0 + + ; Both sign bits 1 + mvi_h_gr 0xffffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0xffffffff,mdl + set_dbits 0x2 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0xffffffff,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xffffffff,mdl + test_dbits 0x1 + + pass diff --git a/sim/testsuite/sim/fr30/div0u.cgs b/sim/testsuite/sim/fr30/div0u.cgs new file mode 100644 index 00000000000..8fd84a6c22b --- /dev/null +++ b/sim/testsuite/sim/fr30/div0u.cgs @@ -0,0 +1,25 @@ +# fr30 testcase for div0u $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div0u +div0u: + ; Test div0u $Rj,$Ri + ; operand register has no effect + mvi_h_gr 0xdeadbeef,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0x0ffffff0,mdl + set_dbits 0x3 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0u r2 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0ffffff0,mdl + test_dbits 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/div1.cgs b/sim/testsuite/sim/fr30/div1.cgs new file mode 100644 index 00000000000..dac35fe15c4 --- /dev/null +++ b/sim/testsuite/sim/fr30/div1.cgs @@ -0,0 +1,113 @@ +# fr30 testcase for div1 $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div1 +div1: + ; Test div1 $Ri + ; example from the manual -- all status bits 0 + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00ffffff,mdh + mvi_h_dr 0x00000000,mdl + set_dbits 0x0 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00ffffff,mdh ; misprinted in manual? + test_h_dr 0x00000001,mdl + + ; D0 == 1 + set_dbits 0x1 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x1 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x01fffffe,mdh + test_h_dr 0x00000002,mdl + + ; D1 == 1 + set_dbits 0x2 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x2 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x03fffffc,mdh + test_h_dr 0x00000004,mdl + + ; D0 == 1, D1 == 1 + set_dbits 0x3 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x3 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x08fffff7,mdh + test_h_dr 0x00000009,mdl + + ; C == 1 + mvi_h_gr 0x11ffffef,r2 + set_dbits 0x0 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x0 + test_h_gr 0x11ffffef,r2 + test_h_dr 0x11ffffee,mdh + test_h_dr 0x00000012,mdl + + ; D0 == 1, C == 1 + mvi_h_gr 0x23ffffdd,r2 + set_dbits 0x1 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x1 + test_h_gr 0x23ffffdd,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0x00000025,mdl + + ; D1 == 1, C == 1 + mvi_h_gr 0x00000003,r2 + set_dbits 0x2 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x2 + test_h_gr 0x00000003,r2 + test_h_dr 0x00000001,mdh + test_h_dr 0x0000004b,mdl + + ; D0 == 1, D1 == 1, C == 1 + mvi_h_gr 0xfffffffe,r2 + set_dbits 0x3 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x3 + test_h_gr 0xfffffffe,r2 + test_h_dr 0x00000002,mdh + test_h_dr 0x00000096,mdl + + ; remainder is zero + mvi_h_gr 0x00000004,r2 + set_dbits 0x0 + set_cc 0x00 + div1 r2 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00000004,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000012d,mdl + + pass + + + diff --git a/sim/testsuite/sim/fr30/div2.cgs b/sim/testsuite/sim/fr30/div2.cgs new file mode 100644 index 00000000000..03000a24242 --- /dev/null +++ b/sim/testsuite/sim/fr30/div2.cgs @@ -0,0 +1,120 @@ +# fr30 testcase for div2 $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div2 +div2: + ; Test div2 $Ri + ; example from the manual -- all status bits 0 + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00ffffff,mdh + mvi_h_dr 0x0000000f,mdl + set_dbits 0x0 + set_cc 0x00 + div2 r2 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1 + mvi_h_dr 0x00ffffff,mdh + set_dbits 0x1 + set_cc 0x00 + div2 r2 + test_cc 0 1 0 0 + test_dbits 0x1 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000000f,mdl + + ; D1 == 1 + mvi_h_dr 0x00ffffff,mdh + set_dbits 0x2 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 0 + test_dbits 0x2 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00ffffff,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1, D1 == 1 + set_dbits 0x3 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 0 + test_dbits 0x3 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00ffffff,mdh + test_h_dr 0x0000000f,mdl + + ; C == 1 + mvi_h_dr 0x11ffffee,mdh + mvi_h_gr 0x11ffffef,r2 + set_dbits 0x0 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x0 + test_h_gr 0x11ffffef,r2 + test_h_dr 0x11ffffee,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1, C == 1 + mvi_h_dr 0x23ffffdc,mdh + mvi_h_gr 0x23ffffdd,r2 + set_dbits 0x1 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x1 + test_h_gr 0x23ffffdd,r2 + test_h_dr 0x23ffffdc,mdh + test_h_dr 0x0000000f,mdl + + ; D1 == 1, C == 1 + mvi_h_dr 0xfffffffd,mdh + mvi_h_gr 0x00000004,r2 + set_dbits 0x2 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x2 + test_h_gr 0x00000004,r2 + test_h_dr 0xfffffffd,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1, D1 == 1, C == 1 + mvi_h_dr 0x00000002,mdh + mvi_h_gr 0xffffffff,r2 + set_dbits 0x3 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x3 + test_h_gr 0xffffffff,r2 + test_h_dr 0x00000002,mdh + test_h_dr 0x0000000f,mdl + + ; remainder is zero + mvi_h_dr 0x00000004,mdh + mvi_h_gr 0x00000004,r2 + set_dbits 0x0 + set_cc 0x00 + div2 r2 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00000004,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000000f,mdl + + pass + + + diff --git a/sim/testsuite/sim/fr30/div3.cgs b/sim/testsuite/sim/fr30/div3.cgs new file mode 100644 index 00000000000..ee7da1a8042 --- /dev/null +++ b/sim/testsuite/sim/fr30/div3.cgs @@ -0,0 +1,34 @@ +# fr30 testcase for div3 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div3 +div3: + ; Test div3 + ; example from the manual + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0x0000000f,mdl + set_dbits 0x0 + set_cc 0x04 + div3 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x00000010,mdl + + set_dbits 0x0 + set_cc 0x00 + div3 + test_cc 0 0 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x00000010,mdl + + pass diff --git a/sim/testsuite/sim/fr30/div4s.cgs b/sim/testsuite/sim/fr30/div4s.cgs new file mode 100644 index 00000000000..3b98ecaf1c3 --- /dev/null +++ b/sim/testsuite/sim/fr30/div4s.cgs @@ -0,0 +1,34 @@ +# fr30 testcase for div4s +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div4s +div4s: + ; Test div4s + ; example from the manual + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0x0000000f,mdl + set_dbits 0x3 + set_cc 0x0f + div4s + test_cc 1 1 1 1 + test_dbits 0x3 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0xfffffff1,mdl + + set_dbits 0x0 + set_cc 0x00 + div4s + test_cc 0 0 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0xfffffff1,mdl + + pass diff --git a/sim/testsuite/sim/fr30/dmov.cgs b/sim/testsuite/sim/fr30/dmov.cgs new file mode 100644 index 00000000000..bd2e5cc45ff --- /dev/null +++ b/sim/testsuite/sim/fr30/dmov.cgs @@ -0,0 +1,73 @@ +# fr30 testcase for dmov +# mach(): fr30 + + .include "testutils.inc" + START + + .text + .global dmov +dmov: + ; Test dmov @$dir10,$R13 + mvi_h_gr 0xdeadbeef,r1 + mvi_h_gr 0x200,r2 + mvr_h_mem r1,r2 + set_cc 0x0f ; Condition codes shouldn't change + dmov @0x200,r13 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r13 + + ; Test dmov $R13,@$dir10 + mvi_h_gr 0xbeefdead,r13 + set_cc 0x0e ; Condition codes shouldn't change + dmov r13,@0x200 + test_cc 1 1 1 0 + test_h_mem 0xbeefdead,r2 + + ; Test dmov @$dir10,@R13+ + mvi_h_gr 0x1fc,r13 + set_cc 0x0d ; Condition codes shouldn't change + dmov @0x200,@r13+ + test_cc 1 1 0 1 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefdead,r2 + inci_h_gr 4,r2 + test_h_mem 0xbeefdead,r2 + test_h_gr 0x200,r13 + + ; Test dmov @$R13+,@$dir10 + mvi_h_gr 0x1fc,r13 + mvi_h_mem 0xdeadbeef,r13 + set_cc 0x0c ; Condition codes shouldn't change + dmov @r13+,@0x200 + test_cc 1 1 0 0 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xdeadbeef,r2 + inci_h_gr 4,r2 + test_h_mem 0xdeadbeef,r2 + test_h_gr 0x200,r13 + + ; Test dmov @$dir10,@-R15 + mvi_h_gr 0x200,r15 + mvi_h_mem 0xdeadbeef,r15 + set_cc 0x0b ; Condition codes shouldn't change + dmov @0x200,@-r15 + test_cc 1 0 1 1 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xdeadbeef,r2 + inci_h_gr 4,r2 + test_h_mem 0xdeadbeef,r2 + test_h_gr 0x1fc,r15 + + ; Test dmov @$R15+,@$dir10 + mvi_h_gr 0x1fc,r15 + mvi_h_mem 0xbeefdead,r15 + set_cc 0x0a ; Condition codes shouldn't change + dmov @r15+,@0x200 + test_cc 1 0 1 0 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefdead,r2 + inci_h_gr 4,r2 + test_h_mem 0xbeefdead,r2 + test_h_gr 0x200,r15 + + pass diff --git a/sim/testsuite/sim/fr30/dmovb.cgs b/sim/testsuite/sim/fr30/dmovb.cgs new file mode 100644 index 00000000000..96cfb9d3e08 --- /dev/null +++ b/sim/testsuite/sim/fr30/dmovb.cgs @@ -0,0 +1,46 @@ +# fr30 testcase for dmovb +# mach(): fr30 + + .include "testutils.inc" + START + + .text + .global dmovb +dmovb: + ; Test dmovb @$dir8,$R13 + mvi_h_gr 0xdeadbeef,r1 + mvi_h_gr 0x80,r2 + mvr_h_mem r1,r2 + set_cc 0x0f ; Condition codes shouldn't change + dmovb @0x80,r13 + test_cc 1 1 1 1 + test_h_gr 0xffffffde,r13 + + ; Test dmovb $R13,@$dir8 + mvi_h_gr 0xbeefdead,r13 + set_cc 0x0e ; Condition codes shouldn't change + dmovb r13,@0x80 + test_cc 1 1 1 0 + test_h_mem 0xadadbeef,r2 + + ; Test dmovb @$dir8,@R13+ + mvi_h_gr 0x7c,r13 + mvi_h_mem 0xdeadbeef,r13 + set_cc 0x0d ; Condition codes shouldn't change + dmovb @0x7f,@r13+ + test_cc 1 1 0 1 + mvi_h_gr 0x7c,r2 + test_h_mem 0xefadbeef,r2 + test_h_gr 0x7d,r13 + + ; Test dmovb @$R13+,@$dir8 + mvi_h_gr 0x7c,r13 + mvi_h_mem 0xbeefdead,r13 + set_cc 0x0c ; Condition codes shouldn't change + dmovb @r13+,@0x7f + test_cc 1 1 0 0 + mvi_h_gr 0x7c,r2 + test_h_mem 0xbeefdebe,r2 + test_h_gr 0x7d,r13 + + pass diff --git a/sim/testsuite/sim/fr30/dmovh.cgs b/sim/testsuite/sim/fr30/dmovh.cgs new file mode 100644 index 00000000000..86afb44f411 --- /dev/null +++ b/sim/testsuite/sim/fr30/dmovh.cgs @@ -0,0 +1,46 @@ +# fr30 testcase for dmovh +# mach(): fr30 + + .include "testutils.inc" + START + + .text + .global dmovh +dmovh: + ; Test dmovh @$dir9,$R13 + mvi_h_gr 0xdeadbeef,r1 + mvi_h_gr 0x100,r2 + mvr_h_mem r1,r2 + set_cc 0x0f ; Condition codes shouldn't change + dmovh @0x100,r13 + test_cc 1 1 1 1 + test_h_gr 0xffffdead,r13 + + ; Test dmovh $R13,@$dir9 + mvi_h_gr 0xdeadbeef,r13 + set_cc 0x0e ; Condition codes shouldn't change + dmovh r13,@0x100 + test_cc 1 1 1 0 + test_h_mem 0xbeefbeef,r2 + + ; Test dmovh @$dir9,@R13+ + mvi_h_gr 0x1fc,r13 + mvi_h_mem 0xdeadbeef,r13 + set_cc 0x0d ; Condition codes shouldn't change + dmovh @0x1fe,@r13+ + test_cc 1 1 0 1 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefbeef,r2 + test_h_gr 0x1fe,r13 + + ; Test dmovh @$R13+,@$dir9 + mvi_h_gr 0x1fc,r13 + mvi_h_mem 0xbeefdead,r13 + set_cc 0x0c ; Condition codes shouldn't change + dmovh @r13+,@0x1fe + test_cc 1 1 0 0 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefbeef,r2 + test_h_gr 0x1fe,r13 + + pass diff --git a/sim/testsuite/sim/fr30/enter.cgs b/sim/testsuite/sim/fr30/enter.cgs new file mode 100644 index 00000000000..ae75e16a2e1 --- /dev/null +++ b/sim/testsuite/sim/fr30/enter.cgs @@ -0,0 +1,34 @@ +# fr30 testcase for enter $u10 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global enter +enter: + ; Test enter $u10 + mvr_h_gr sp,r7 ; save stack pointer + mvr_h_gr sp,r8 ; shadow stack pointer + mvr_h_gr sp,r14 ; Initialize + set_cc 0x0f ; Condition codes are irrelevent + enter 0 + test_cc 1 1 1 1 + testr_h_gr r8,sp + inci_h_gr -4,r8 + testr_h_gr r14,r8 + testr_h_mem r7,r14 + + mvr_h_gr sp,r8 ; shadow stack pointer + mvr_h_gr r14,r9 ; save + set_cc 0x0e ; Condition codes are irrelevent + enter 0x3fc + test_cc 1 1 1 0 + inci_h_gr -4,r8 + testr_h_gr r14,r8 + testr_h_mem r9,r14 + inci_h_gr -0x3f8,r8 + testr_h_gr r8,sp + + pass diff --git a/sim/testsuite/sim/fr30/eor.cgs b/sim/testsuite/sim/fr30/eor.cgs new file mode 100644 index 00000000000..a87076151cf --- /dev/null +++ b/sim/testsuite/sim/fr30/eor.cgs @@ -0,0 +1,69 @@ +# fr30 testcase for eor $Rj,$Ri, eor $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global eor +eor: + ; Test eor $Rj,$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0x55555555,r8 + set_cc 0x07 ; Set mask opposite of expected + eor r7,r8 + test_cc 1 0 1 1 + test_h_gr 0xffffffff,r8 + + mvi_h_gr 0x00000000,r7 + mvi_h_gr 0x00000000,r8 + set_cc 0x08 ; Set mask opposite of expected + eor r7,r8 + test_cc 0 1 0 0 + test_h_gr 0x00000000,r8 + + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0xaaaaaaaa,r8 + set_cc 0x0b ; Set mask opposite of expected + eor r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + mvi_h_gr 0xdead0000,r7 + mvi_h_gr 0x0000beef,r8 + set_cc 0x05 ; Set mask opposite of expected + eor r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xdeadbeef,r8 + + ; Test eor $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + eor r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffffffff,sp + + mvi_h_gr 0x00000000,r7 + mvi_h_mem 0x00000000,sp + set_cc 0x08 ; Set mask opposite of expected + eor r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00000000,sp + + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0xaaaaaaaa,sp + set_cc 0x0b ; Set mask opposite of expected + eor r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00000000,sp + + mvi_h_gr 0xdead0000,r7 + mvi_h_mem 0x0000beef,sp + set_cc 0x05 ; Set mask opposite of expected + eor r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/eorb.cgs b/sim/testsuite/sim/fr30/eorb.cgs new file mode 100644 index 00000000000..540f3f7aa1f --- /dev/null +++ b/sim/testsuite/sim/fr30/eorb.cgs @@ -0,0 +1,40 @@ +# fr30 testcase for eorb $Rj,$Ri, eorb $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global eorb +eorb: + ; Test eorb $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + eorb r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xff555555,sp + + mvi_h_gr 0xaaaaaa00,r7 + mvi_h_mem 0x00555555,sp + set_cc 0x08 ; Set mask opposite of expected + eorb r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00555555,sp + + mvi_h_gr 0xaaaaaa55,r7 + mvi_h_mem 0x55aaaaaa,sp + set_cc 0x0b ; Set mask opposite of expected + eorb r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00aaaaaa,sp + + mvi_h_gr 0x000000d0,r7 + mvi_h_mem 0x0eadbeef,sp + set_cc 0x05 ; Set mask opposite of expected + eorb r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/eorh.cgs b/sim/testsuite/sim/fr30/eorh.cgs new file mode 100644 index 00000000000..7cf84735959 --- /dev/null +++ b/sim/testsuite/sim/fr30/eorh.cgs @@ -0,0 +1,40 @@ +# fr30 testcase for eorh $Rj,$Ri, eorh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global eorh +eorh: + ; Test eorh $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + eorh r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffff5555,sp + + mvi_h_gr 0xaaaa0000,r7 + mvi_h_mem 0x00005555,sp + set_cc 0x08 ; Set mask opposite of expected + eorh r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00005555,sp + + mvi_h_gr 0xaaaa5555,r7 + mvi_h_mem 0x5555aaaa,sp + set_cc 0x0b ; Set mask opposite of expected + eorh r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x0000aaaa,sp + + mvi_h_gr 0x0000de00,r7 + mvi_h_mem 0x00adbeef,sp + set_cc 0x05 ; Set mask opposite of expected + eorh r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/extsb.cgs b/sim/testsuite/sim/fr30/extsb.cgs new file mode 100644 index 00000000000..6a18d7e7dae --- /dev/null +++ b/sim/testsuite/sim/fr30/extsb.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for extsb $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extsb +extsb: + ; Test extsb $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 0 1 + test_h_gr 0xffffff80,r7 + + mvi_h_gr 0xffffff7f,r7 + set_cc 0x0c ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 0 0 + test_h_gr 0x7f,r7 + + pass diff --git a/sim/testsuite/sim/fr30/extsh.cgs b/sim/testsuite/sim/fr30/extsh.cgs new file mode 100644 index 00000000000..eb12fd0aae8 --- /dev/null +++ b/sim/testsuite/sim/fr30/extsh.cgs @@ -0,0 +1,48 @@ +# fr30 testcase for extsh $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extsh +extsh: + ; Test extsh $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_gr 0x7fff,r7 + set_cc 0x0c ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 0 0 + test_h_gr 0x7fff,r7 + + mvi_h_gr 0x8000,r7 + set_cc 0x0b ; Condition codes are irrelevent + extsh r7 + test_cc 1 0 1 1 + test_h_gr 0xffff8000,r7 + + mvi_h_gr 0xffff7fff,r7 + set_cc 0x0a ; Condition codes are irrelevent + extsh r7 + test_cc 1 0 1 0 + test_h_gr 0x7fff,r7 + + pass diff --git a/sim/testsuite/sim/fr30/extub.cgs b/sim/testsuite/sim/fr30/extub.cgs new file mode 100644 index 00000000000..ddcc68361cc --- /dev/null +++ b/sim/testsuite/sim/fr30/extub.cgs @@ -0,0 +1,42 @@ +# fr30 testcase for extub $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extub +extub: + ; Test extub $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extub r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extub r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extub r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_gr 0xffffff7f,r7 + set_cc 0x0c ; Condition codes are irrelevent + extub r7 + test_cc 1 1 0 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0xffffff80,r7 + set_cc 0x0b ; Condition codes are irrelevent + extub r7 + test_cc 1 0 1 1 + test_h_gr 0x80,r7 + + pass diff --git a/sim/testsuite/sim/fr30/extuh.cgs b/sim/testsuite/sim/fr30/extuh.cgs new file mode 100644 index 00000000000..fa2579e469f --- /dev/null +++ b/sim/testsuite/sim/fr30/extuh.cgs @@ -0,0 +1,54 @@ +# fr30 testcase for extuh $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extuh +extuh: + ; Test extuh $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_gr 0x7fff,r7 + set_cc 0x0e ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 1 0 + test_h_gr 0x7fff,r7 + + mvi_h_gr 0x8000,r7 + set_cc 0x0d ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 0 1 + test_h_gr 0x8000,r7 + + mvi_h_gr 0xffff7fff,r7 + set_cc 0x0c ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 0 0 + test_h_gr 0x7fff,r7 + + mvi_h_gr 0xffff8000,r7 + set_cc 0x0b ; Condition codes are irrelevent + extuh r7 + test_cc 1 0 1 1 + test_h_gr 0x8000,r7 + + pass diff --git a/sim/testsuite/sim/fr30/hello.ms b/sim/testsuite/sim/fr30/hello.ms new file mode 100644 index 00000000000..0f208dfb927 --- /dev/null +++ b/sim/testsuite/sim/fr30/hello.ms @@ -0,0 +1,19 @@ +# mach: fr30 +# output: Hello world!\n + + .global _start +_start: + +; write (hello world) + ldi32 #14,r6 + ldi32 #hello,r5 + ldi32 #1,r4 + ldi32 #5,r0 + int #10 +; exit (0) + ldi32 #0,r4 + ldi32 #1,r0 + int #10 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/fr30/int.cgs b/sim/testsuite/sim/fr30/int.cgs new file mode 100644 index 00000000000..7cdca7b8c9b --- /dev/null +++ b/sim/testsuite/sim/fr30/int.cgs @@ -0,0 +1,35 @@ +# fr30 testcase for int $u8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global int +int: + ; Test int $u8 - setup and test an interrupt #0xfd (randomly chosen) + mvr_h_gr tbr,r7 + inci_h_gr 8,r7 + mvi_h_mem pass,r7 + mvi_h_gr doint,r9 + inci_h_gr 2,r9 + mvr_h_gr ssp,r10 + set_cc 0x0f ; Condition codes should not change + set_s_user ; Set opposite of expected + set_i 1 ; Set opposite of expected + mvr_h_gr ps,r8 +doint: int 0xfd + fail + +pass: + test_cc 1 1 1 1 + test_s_system + test_i 0 + inci_h_gr -4,r10 + testr_h_mem r8,r10 + inci_h_gr -4,r10 + testr_h_mem r9,r10 + testr_h_dr r10,ssp + + pass diff --git a/sim/testsuite/sim/fr30/inte.cgs b/sim/testsuite/sim/fr30/inte.cgs new file mode 100644 index 00000000000..a15bfd978a2 --- /dev/null +++ b/sim/testsuite/sim/fr30/inte.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for inte +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global inte +inte: + ; Test inte which is essentially int #9 + mvr_h_gr tbr,r7 + inci_h_gr 0x3d8,r7 + mvi_h_mem pass,r7 + mvi_h_gr doint,r9 + inci_h_gr 2,r9 + mvr_h_gr ssp,r10 + set_cc 0x0f ; Condition codes should not change + set_s_user ; Set opposite of expected + set_i 1 ; Should not change + mvr_h_gr ps,r8 +doint: inte + fail + +pass: + test_cc 1 1 1 1 + test_ilm 4 + test_s_system + test_i 1 + inci_h_gr -4,r10 + testr_h_mem r8,r10 + inci_h_gr -4,r10 + testr_h_mem r9,r10 + testr_h_dr r10,ssp + + pass diff --git a/sim/testsuite/sim/fr30/jmp.cgs b/sim/testsuite/sim/fr30/jmp.cgs new file mode 100644 index 00000000000..db4af220d36 --- /dev/null +++ b/sim/testsuite/sim/fr30/jmp.cgs @@ -0,0 +1,29 @@ +# fr30 testcase for jmp @$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global jmp + + ; Test jmp $Ri + mvi_h_gr #func1,r0 + set_cc 0x0f ; condition codes shouldn't change +jmp1: + jmp @r0 + fail +func1: + test_cc 1 1 1 1 + mvi_h_gr #func2,r0 + set_cc 0x0f ; condition codes shouldn't change +jmp2: + jmp:d @r0 + ldi:8 1,r0 ; Must assume this works + fail +func2: + test_cc 1 1 1 1 + testr_h_gr 1,r0 + + pass diff --git a/sim/testsuite/sim/fr30/ld.cgs b/sim/testsuite/sim/fr30/ld.cgs new file mode 100644 index 00000000000..3f2d30bb023 --- /dev/null +++ b/sim/testsuite/sim/fr30/ld.cgs @@ -0,0 +1,219 @@ +# fr30 testcase for +# mach(): fr30 +# ld $Rj,$Ri +# ld @($R13,$Rj),$Ri +# ld @($R14,$disp10),$Ri +# ld @($R15,$udisp6),$Ri +# ld @$R15+,$Ri +# ld @$R15+,$Rs + + .include "testutils.inc" + + START + + .text + .global ld +ld: + ; Test ld $Rj,$Ri + mvi_h_mem #0x00000000,sp + set_cc 0x0f ; condition codes should not change + ld @sp,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x00000001,sp + set_cc 0x07 ; condition codes should not change + ld @sp,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffffff,sp + set_cc 0x0b ; condition codes should not change + ld @sp,r7 + test_cc 1 0 1 1 + test_h_gr 0x7fffffff,r7 + + mvi_h_mem #0x80000000,sp + set_cc 0x0d ; condition codes should not change + ld @sp,r7 + test_cc 1 1 0 1 + test_h_gr 0x80000000,r7 + + mvi_h_mem #0xffffffff,sp + set_cc 0x0e ; condition codes should not change + ld @sp,r7 + test_cc 1 1 1 0 + test_h_gr -1,r7 + + ; Test ld @($R13,$Rj),$Ri + mvr_h_gr sp,r13 + inci_h_gr -8,r13 + mvi_h_gr 8,r8 + + mvi_h_mem #0x00000000,sp + set_cc 0x0f ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x00000001,sp + set_cc 0x07 ; condition codes should not change + ld @(r13,r8),r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffffff,sp + set_cc 0x0b ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 0 1 1 + test_h_gr 0x7fffffff,r7 + + mvi_h_mem #0x80000000,sp + set_cc 0x0d ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 1 0 1 + test_h_gr 0x80000000,r7 + + mvi_h_mem #0xffffffff,sp + set_cc 0x0e ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 1 1 0 + test_h_gr -1,r7 + + ; Test ld @($R14,$disp10),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0x1fc,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + ld @(r14,0x1fc),r7 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0xfc,r14 + set_cc 0x07 ; condition codes should not change + ld @(r14,0x100),r7 + test_cc 0 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x100,r14 + set_cc 0x0b ; condition codes should not change + ld @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x100,r14 + set_cc 0x0d ; condition codes should not change + ld @(r14,-0x100),r7 + test_cc 1 1 0 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x100,r14 + set_cc 0x0e ; condition codes should not change + ld @(r14,-0x200),r7 + test_cc 1 1 1 0 + test_h_gr 0xdeadbeef,r7 + + ; Test ld @($R15,$udisp6),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0x3c,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + ld @(r14,0x3c),r7 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x1c,r14 + set_cc 0x07 ; condition codes should not change + ld @(r14,0x20),r7 + test_cc 0 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x20,r14 + set_cc 0x0b ; condition codes should not change + ld @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xdeadbeef,r7 + + ; Test ld @$R15+,$Ri + mvr_h_gr sp,r8 ; save original stack pointer + mvr_h_gr r8,r9 + inci_h_gr 4,r9 ; original stack pointer + 4 + mvi_h_mem #0xdeadbeef,sp ; prime memory + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,r7 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r7 + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,sp + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,sp ; should not have been incremented + + ; Test ld @$R15+,$Rs + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,tbr + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,tbr + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,rp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,rp + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,mdh + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,mdh + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,mdl + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,mdl + testr_h_gr sp,r9 ; should have been incremented + + set_s_user + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,ssp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,ssp + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,usp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,usp + test_h_gr 0xdeadbeef,sp ; should not have been incremented + + set_s_system + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,usp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,usp + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,ssp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,ssp + test_h_gr 0xdeadbeef,sp ; should not have been incremented + + pass diff --git a/sim/testsuite/sim/fr30/ldi20.cgs b/sim/testsuite/sim/fr30/ldi20.cgs new file mode 100644 index 00000000000..c7a4ef4165f --- /dev/null +++ b/sim/testsuite/sim/fr30/ldi20.cgs @@ -0,0 +1,37 @@ +# fr30 testcase for ldi20 $i20,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldi20 +ldi20: + ; Test ldi20 $i20,$Ri + set_cc 0x0f ; condition codes should not change + ldi20 #0x00000000,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + set_cc 0x07 ; condition codes should not change + ldi:20 1,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + set_cc 0x0b ; condition codes should not change + ldi20 0x7ffff,r7 + test_cc 1 0 1 1 + test_h_gr 0x0007ffff,r7 + + set_cc 0x0d ; condition codes should not change + ldi:20 0x80000,r7 + test_cc 1 1 0 1 + test_h_gr 0x00080000,r7 + + set_cc 0x0e ; condition codes should not change + ldi20 0xfffff,r7 + test_cc 1 1 1 0 + test_h_gr 0x000fffff,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldi32.cgs b/sim/testsuite/sim/fr30/ldi32.cgs new file mode 100644 index 00000000000..3e56db741e3 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldi32.cgs @@ -0,0 +1,37 @@ +# fr30 testcase for ldi32 $i32,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldi32 +ldi32: + ; Test ldi32 $i32,$Ri + set_cc 0x0f ; condition codes should not change + ldi32 #0x00000000,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + set_cc 0x07 ; condition codes should not change + ldi:32 1,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + set_cc 0x0b ; condition codes should not change + ldi32 0x7fffffff,r7 + test_cc 1 0 1 1 + test_h_gr 0x7fffffff,r7 + + set_cc 0x0d ; condition codes should not change + ldi:32 0x80000000,r7 + test_cc 1 1 0 1 + test_h_gr 0x80000000,r7 + + set_cc 0x0e ; condition codes should not change + ldi32 0xffffffff,r7 + test_cc 1 1 1 0 + test_h_gr -1,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldi8.cgs b/sim/testsuite/sim/fr30/ldi8.cgs new file mode 100644 index 00000000000..9b15edead0c --- /dev/null +++ b/sim/testsuite/sim/fr30/ldi8.cgs @@ -0,0 +1,37 @@ +# fr30 testcase for ldi8 $i8,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldi8 +ldi8: + ; Test ldi8 $i8,$Ri + set_cc 0x0f ; condition codes should not change + ldi8 #0x00000000,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + set_cc 0x07 ; condition codes should not change + ldi:20 1,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + set_cc 0x0b ; condition codes should not change + ldi8 0x7f,r7 + test_cc 1 0 1 1 + test_h_gr 0x0000007f,r7 + + set_cc 0x0d ; condition codes should not change + ldi:20 0x80,r7 + test_cc 1 1 0 1 + test_h_gr 0x00000080,r7 + + set_cc 0x0e ; condition codes should not change + ldi8 0xff,r7 + test_cc 1 1 1 0 + test_h_gr 0x000000ff,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldm0.cgs b/sim/testsuite/sim/fr30/ldm0.cgs new file mode 100644 index 00000000000..9deb5642544 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldm0.cgs @@ -0,0 +1,60 @@ +# fr30 testcase for ldm0 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldm0 +ldm0: + ; Test ldm0 ($reglist_low) + mvr_h_gr sp,r9 ; save stack pointer permanently + inci_h_gr -4,sp + mvi_h_mem 3,sp + inci_h_gr -4,sp + mvi_h_mem 2,sp + inci_h_gr -4,sp + mvi_h_mem 1,sp + inci_h_gr -4,sp + mvi_h_mem 0,sp + + set_cc 0x0f ; Condition codes should not change + ldm0 (r0,r2,r4,r6) + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r0 + test_h_gr 1,r2 + test_h_gr 2,r4 + test_h_gr 3,r6 + + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm0 (r1,r3,r5,r7) + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r1 + test_h_gr 1,r3 + test_h_gr 2,r5 + test_h_gr 3,r7 + + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm0 (r1,r5,r7,r3) ; Order speficied should not matter + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r1 + test_h_gr 1,r3 + test_h_gr 2,r5 + test_h_gr 3,r7 + + set_cc 0x0f ; Condition codes should not change + ldm0 () ; Nothing should happen + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r1 + test_h_gr 1,r3 + test_h_gr 2,r5 + test_h_gr 3,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldm1.cgs b/sim/testsuite/sim/fr30/ldm1.cgs new file mode 100644 index 00000000000..33cfcdba770 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldm1.cgs @@ -0,0 +1,59 @@ +# fr30 testcase for ldm1 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldm1 +ldm1: + ; Test ldm1 ($reglist_low) + mvr_h_gr sp,r1 ; save stack pointer permanently + inci_h_gr -4,sp + mvi_h_mem 3,sp + inci_h_gr -4,sp + mvi_h_mem 2,sp + inci_h_gr -4,sp + mvi_h_mem 1,sp + inci_h_gr -4,sp + mvi_h_mem 0,sp + + set_cc 0x0f ; Condition codes should not change + ldm1 (r8,r10,r12,r14) + test_cc 1 1 1 1 + testr_h_gr sp,r1 + test_h_gr 0,r8 + test_h_gr 1,r10 + test_h_gr 2,r12 + test_h_gr 3,r14 + + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm1 (r9,r11,r13,r15) + test_cc 1 1 1 1 + test_h_gr 0,r9 + test_h_gr 1,r11 + test_h_gr 2,r13 + test_h_gr 3,r15 + + mvr_h_gr r1,sp ; restore stack pointer + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm1 (r9,r13,r15,r11); Order speficied should not matter + test_cc 1 1 1 1 + test_h_gr 0,r9 + test_h_gr 1,r11 + test_h_gr 2,r13 + test_h_gr 3,r15 + + mvr_h_gr r1,sp ; restore stack pointer + set_cc 0x0f ; Condition codes should not change + ldm1 () ; Nothing should happen + test_cc 1 1 1 1 + testr_h_gr sp,r1 + test_h_gr 0,r9 + test_h_gr 1,r11 + test_h_gr 2,r13 + + pass diff --git a/sim/testsuite/sim/fr30/ldres.cgs b/sim/testsuite/sim/fr30/ldres.cgs new file mode 100644 index 00000000000..008348992d2 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldres.cgs @@ -0,0 +1,25 @@ +# fr30 testcase for ldres $@Ri+,$u4 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldres +ldres: + ; Test ldres $@Ri+,$u4 + ; The current implementation simply increments Ri + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + ldres @r7+,0 + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + ldres @r7+,0xf + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldub.cgs b/sim/testsuite/sim/fr30/ldub.cgs new file mode 100644 index 00000000000..97e00d9e00a --- /dev/null +++ b/sim/testsuite/sim/fr30/ldub.cgs @@ -0,0 +1,115 @@ +# fr30 testcase for +# mach(): fr30 +# ldub $Rj,$Ri +# ldub @($R13,$Rj),$Ri +# ldub @($R14,$disp8),$Ri + + .include "testutils.inc" + + START + + .text + .global ldub +ldub: + ; Test ldub $Rj,$Ri + mvi_h_mem #0x00adbeef,sp + set_cc 0x0f ; condition codes should not change + ldub @sp,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x01adbeef,sp + set_cc 0x07 ; condition codes should not change + ldub @sp,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fadbeef,sp + set_cc 0x0b ; condition codes should not change + ldub @sp,r7 + test_cc 1 0 1 1 + test_h_gr 0x7f,r7 + + mvi_h_mem #0x80adbeef,sp + set_cc 0x0d ; condition codes should not change + ldub @sp,r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_mem #0xffadbeef,sp + set_cc 0x0e ; condition codes should not change + ldub @sp,r7 + test_cc 1 1 1 0 + test_h_gr 0xff,r7 + + ; Test ldub @($R13,$Rj),$Ri + mvr_h_gr sp,r13 + inci_h_gr -8,r13 + mvi_h_gr 8,r8 + + mvi_h_mem #0x00adbeef,sp + set_cc 0x0f ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x01adbeef,sp + set_cc 0x07 ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fadbeef,sp + set_cc 0x0b ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 0 1 1 + test_h_gr 0x7f,r7 + + mvi_h_mem #0x80adbeef,sp + set_cc 0x0d ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_mem #0xffadbeef,sp + set_cc 0x0e ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 1 1 0 + test_h_gr 0xff,r7 + + ; Test ldub @($R14,$disp8),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0x7f,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + lduh @(r14,0x7f),r7 + test_cc 1 1 1 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x3e,r14 + set_cc 0x07 ; condition codes should not change + lduh @(r14,0x40),r7 + test_cc 0 1 1 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x40,r14 + set_cc 0x0b ; condition codes should not change + lduh @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x40,r14 + set_cc 0x0d ; condition codes should not change + lduh @(r14,-0x40),r7 + test_cc 1 1 0 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x40,r14 + set_cc 0x0e ; condition codes should not change + lduh @(r14,-0x80),r7 + test_cc 1 1 1 0 + test_h_gr 0xde,r7 + + pass diff --git a/sim/testsuite/sim/fr30/lduh.cgs b/sim/testsuite/sim/fr30/lduh.cgs new file mode 100644 index 00000000000..7d36b75cbcc --- /dev/null +++ b/sim/testsuite/sim/fr30/lduh.cgs @@ -0,0 +1,115 @@ +# fr30 testcase for +# mach(): fr30 +# lduh $Rj,$Ri +# lduh @($R13,$Rj),$Ri +# lduh @($R14,$disp9),$Ri + + .include "testutils.inc" + + START + + .text + .global lduh +lduh: + ; Test lduh $Rj,$Ri + mvi_h_mem #0x0000beef,sp + set_cc 0x0f ; condition codes should not change + lduh @sp,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x0001beef,sp + set_cc 0x07 ; condition codes should not change + lduh @sp,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffbeef,sp + set_cc 0x0b ; condition codes should not change + lduh @sp,r7 + test_cc 1 0 1 1 + test_h_gr 0x7fff,r7 + + mvi_h_mem #0x8000beef,sp + set_cc 0x0d ; condition codes should not change + lduh @sp,r7 + test_cc 1 1 0 1 + test_h_gr 0x8000,r7 + + mvi_h_mem #0xffffbeef,sp + set_cc 0x0e ; condition codes should not change + lduh @sp,r7 + test_cc 1 1 1 0 + test_h_gr 0xffff,r7 + + ; Test lduh @($R13,$Rj),$Ri + mvr_h_gr sp,r13 + inci_h_gr -8,r13 + mvi_h_gr 8,r8 + + mvi_h_mem #0x0000beef,sp + set_cc 0x0f ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x0001beef,sp + set_cc 0x07 ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffbeef,sp + set_cc 0x0b ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 0 1 1 + test_h_gr 0x7fff,r7 + + mvi_h_mem #0x8000beef,sp + set_cc 0x0d ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 1 0 1 + test_h_gr 0x8000,r7 + + mvi_h_mem #0xffffbeef,sp + set_cc 0x0e ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 1 1 0 + test_h_gr 0xffff,r7 + + ; Test lduh @($R14,$disp9),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0xfe,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + lduh @(r14,0xfe),r7 + test_cc 1 1 1 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x7e,r14 + set_cc 0x07 ; condition codes should not change + lduh @(r14,0x80),r7 + test_cc 0 1 1 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x80,r14 + set_cc 0x0b ; condition codes should not change + lduh @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x80,r14 + set_cc 0x0d ; condition codes should not change + lduh @(r14,-0x80),r7 + test_cc 1 1 0 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x80,r14 + set_cc 0x0e ; condition codes should not change + lduh @(r14,-0x100),r7 + test_cc 1 1 1 0 + test_h_gr 0xdead,r7 + + pass diff --git a/sim/testsuite/sim/fr30/leave.cgs b/sim/testsuite/sim/fr30/leave.cgs new file mode 100644 index 00000000000..4d3dd70100e --- /dev/null +++ b/sim/testsuite/sim/fr30/leave.cgs @@ -0,0 +1,23 @@ +# fr30 testcase for leave +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global leave +leave: + ; Test leave $u10 + mvr_h_gr sp,r7 ; save Stack pointer + mvr_h_gr sp,r14 + inci_h_gr -4,r14 + mvi_h_mem 0xdeadbeef,r14 + mvi_h_gr 0xbeefdead,r15 + set_cc 0x0f ; Condition codes are irrelevent + leave + test_cc 1 1 1 1 + testr_h_gr sp,r7 + test_h_gr 0xdeadbeef,r14 + + pass diff --git a/sim/testsuite/sim/fr30/lsl.cgs b/sim/testsuite/sim/fr30/lsl.cgs new file mode 100644 index 00000000000..ead749fbbb5 --- /dev/null +++ b/sim/testsuite/sim/fr30/lsl.cgs @@ -0,0 +1,65 @@ +# fr30 testcase for lsl $Rj,$Ri, lsl $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsl +lsl: + ; Test lsl $Rj,$Ri + mvi_h_gr 0xdeadbee0,r7 ; Shift by 0 + mvi_h_gr 2,r8 + set_cc 0x0d ; Set mask opposite of expected + lsl r7,r8 + test_cc 0 0 0 0 + test_h_gr 2,r8 + + mvi_h_gr 0xdeadbee1,r7 ; Shift by 1 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + lsl r7,r8 + test_cc 0 0 1 0 + test_h_gr 4,r8 + + mvi_h_gr 0xdeadbeff,r7 ; Shift by 31 + mvi_h_gr 1,r8 + set_cc 0x07 ; Set mask opposite of expected + lsl r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0xdeadbeff,r7 ; clear register + mvi_h_gr 2,r8 + set_cc 0x0a ; Set mask opposite of expected + lsl r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + ; Test lsl $u4Ri + mvi_h_gr 2,r8 + set_cc 0x0d ; Set mask opposite of expected + lsl 0,r8 + test_cc 0 0 0 0 + test_h_gr 2,r8 + + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + lsl 1,r8 + test_cc 0 0 1 0 + test_h_gr 4,r8 + + mvi_h_gr 1,r8 + set_cc 0x0e ; Set mask opposite of expected + lsl 15,r8 + test_cc 0 0 1 0 + test_h_gr 0x00008000,r8 + + mvi_h_gr 0x00020000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsl 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/lsl2.cgs b/sim/testsuite/sim/fr30/lsl2.cgs new file mode 100644 index 00000000000..58acf84ef2c --- /dev/null +++ b/sim/testsuite/sim/fr30/lsl2.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for lsl2 $Rj,$Ri, lsl2 $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsl2 +lsl2: + ; Test lsl2 $u4Ri + mvi_h_gr 2,r8 + set_cc 0x0d ; Set mask opposite of expected + lsl2 0,r8 + test_cc 0 0 0 0 + test_h_gr 0x20000,r8 + + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + lsl2 1,r8 + test_cc 0 0 1 0 + test_h_gr 0x40000,r8 + + mvi_h_gr 1,r8 + set_cc 0x07 ; Set mask opposite of expected + lsl2 15,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 2,r8 + set_cc 0x0a ; Set mask opposite of expected + lsl2 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/lsr.cgs b/sim/testsuite/sim/fr30/lsr.cgs new file mode 100644 index 00000000000..5b9587fe71f --- /dev/null +++ b/sim/testsuite/sim/fr30/lsr.cgs @@ -0,0 +1,65 @@ +# fr30 testcase for lsr $Rj,$Ri, lsr $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsr +lsr: + ; Test lsr $Rj,$Ri + mvi_h_gr 0xdeadbee0,r7 ; Shift by 0 + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + lsr r7,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0xdeadbee1,r7 ; Shift by 1 + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x40000000,r8 + + mvi_h_gr 0xdeadbeff,r7 ; Shift by 31 + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr r7,r8 + test_cc 0 0 1 0 + test_h_gr 1,r8 + + mvi_h_gr 0xdeadbeff,r7 ; clear register + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsr r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + ; Test lsr $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + lsr 0,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr 1,r8 + test_cc 0 0 1 0 + test_h_gr 0x40000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0e ; Set mask opposite of expected + lsr 15,r8 + test_cc 0 0 1 0 + test_h_gr 0x00010000,r8 + + mvi_h_gr 0x00004000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsr 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/lsr2.cgs b/sim/testsuite/sim/fr30/lsr2.cgs new file mode 100644 index 00000000000..fd6ceaa9ff7 --- /dev/null +++ b/sim/testsuite/sim/fr30/lsr2.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for lsr2 $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsr2 +lsr2: + ; Test lsr2 $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + lsr2 0,r8 + test_cc 0 0 0 0 + test_h_gr 0x00008000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr2 1,r8 + test_cc 0 0 1 0 + test_h_gr 0x00004000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0e ; Set mask opposite of expected + lsr2 15,r8 + test_cc 0 0 1 0 + test_h_gr 1,r8 + + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsr2 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/misc.exp b/sim/testsuite/sim/fr30/misc.exp new file mode 100644 index 00000000000..da1490dd9e4 --- /dev/null +++ b/sim/testsuite/sim/fr30/misc.exp @@ -0,0 +1,20 @@ +# Miscellaneous FR30 simulator testcases + +if [istarget fr30*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "fr30" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/fr30/mov.cgs b/sim/testsuite/sim/fr30/mov.cgs new file mode 100644 index 00000000000..bf99252f061 --- /dev/null +++ b/sim/testsuite/sim/fr30/mov.cgs @@ -0,0 +1,108 @@ +# fr30 testcase for mov $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mov +mov: + ; Test mov $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_dr 0xa,tbr + mvi_h_dr 0xb,rp + mvi_h_dr 0xc,mdh + mvi_h_dr 0xd,mdl + mvr_h_gr sp,ssp + mvr_h_gr sp,usp + + mov r7,r7 + set_cc 0x0f ; Condition codes should not change + test_cc 1 1 1 1 + test_h_gr 1,r7 + + mov r7,r8 + set_cc 0x0e ; Condition codes should not change + test_cc 1 1 1 0 + test_h_gr 1,r7 + test_h_gr 1,r8 + + ; Test mov $Rs,$Ri + set_cc 0x0d ; Condition codes should not change + mov tbr,r7 + test_cc 1 1 0 1 + test_h_gr 0xa,r7 + + set_cc 0x0c ; Condition codes should not change + mov rp,r7 + test_cc 1 1 0 0 + test_h_gr 0xb,r7 + + set_cc 0x0b ; Condition codes should not change + mov mdh,r7 + test_cc 1 0 1 1 + test_h_gr 0xc,r7 + + set_cc 0x0a ; Condition codes should not change + mov mdl,r7 + test_cc 1 0 1 0 + test_h_gr 0xd,r7 + + set_cc 0x09 ; Condition codes should not change + mov usp,r7 + test_cc 1 0 0 1 + testr_h_gr sp,r7 + + set_cc 0x08 ; Condition codes should not change + mov ssp,r7 + test_cc 1 0 0 0 + testr_h_gr sp,r7 + + ; Test mov $Ri,$Rs + set_cc 0x07 ; Condition codes should not change + mov r8,tbr + test_cc 0 1 1 1 + test_h_dr 0x1,tbr + + set_cc 0x06 ; Condition codes should not change + mov r8,rp + test_cc 0 1 1 0 + test_h_dr 0x1,rp + + set_cc 0x05 ; Condition codes should not change + mov r8,mdh + test_cc 0 1 0 1 + test_h_dr 0x1,mdh + + set_cc 0x04 ; Condition codes should not change + mov r8,mdl + test_cc 0 1 0 0 + test_h_dr 0x1,mdl + + set_cc 0x03 ; Condition codes should not change + mov r8,ssp + test_cc 0 0 1 1 + test_h_dr 0x1,ssp + + set_cc 0x02 ; Condition codes should not change + mov r8,usp + test_cc 0 0 1 0 + test_h_dr 0x1,usp + + ; Test mov $PS,$Ri + set_cc 0x01 ; Condition codes affect result + set_dbits 0x3 + mov ps,r7 + test_cc 0 0 0 1 + test_h_gr 0x00000601,r7 + + ; Test mov $Ri,PS + set_cc 0x01 ; Set opposite of expected + set_dbits 0x1 ; Set opposite of expected + mvi_h_gr 0x0000040e,r7 + mov r7,PS + test_cc 1 1 1 0 + test_dbits 0x2 + + pass diff --git a/sim/testsuite/sim/fr30/mul.cgs b/sim/testsuite/sim/fr30/mul.cgs new file mode 100644 index 00000000000..f7cbf58e50e --- /dev/null +++ b/sim/testsuite/sim/fr30/mul.cgs @@ -0,0 +1,240 @@ +# fr30 testcase for mul $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mul +mul: + ; Test mul $Rj,$Ri + ; Positive operands + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr 2,r8 + set_cc 0x0b ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x0a ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 0x3fffffff,r7 ; 31 bit result + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 32 bit result + mvi_h_gr 2,r8 + set_cc 0x04 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 1 0 + test_h_dr 0,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0x40000000,r7 ; 33 bit result + mvi_h_gr 4,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 1,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x7fffffff,r7 ; max positive result + mvi_h_gr 0x7fffffff,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x3fffffff,mdh + test_h_dr 0x00000001,mdl + + ; Mixed operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr -1,mdh + test_h_dr -6,mdl + + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr -1,mdh + test_h_dr -6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x06 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 0 + test_h_dr -1,mdh + test_h_dr -2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr -1,mdh + test_h_dr -2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr -2,r8 + set_cc 0x0b ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr -2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x0a ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 0x20000001,r7 ; 31 bit result + mvi_h_gr -2,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr 0xffffffff,mdh + test_h_dr 0xbffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 32 bit result + mvi_h_gr -2,r8 + set_cc 0x06 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 0 + test_h_dr 0xffffffff,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0x40000001,r7 ; 32 bit result + mvi_h_gr -2,r8 + set_cc 0x0c ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 0 + test_h_dr 0xffffffff,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 33 bit result + mvi_h_gr -4,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0xffffffff,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x7fffffff,r7 ; max negative result + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xc0000000,mdh + test_h_dr 0x80000000,mdl + + ; Negative operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 6,mdl + + mvi_h_gr -1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x0e ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr -1,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 0xc0000001,r7 ; 31 bit result + mvi_h_gr -2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0xc0000000,r7 ; 32 bit result + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 1 0 + test_h_dr 0,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0xc0000000,r7 ; 33 bit result + mvi_h_gr -4,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 1,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x80000001,r7 ; almost max positive result + mvi_h_gr 0x80000001,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x3fffffff,mdh + test_h_dr 0x00000001,mdl + + + mvi_h_gr 0x80000000,r7 ; max positive result + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x40000000,mdh + test_h_dr 0x00000000,mdl + + pass diff --git a/sim/testsuite/sim/fr30/mulh.cgs b/sim/testsuite/sim/fr30/mulh.cgs new file mode 100644 index 00000000000..1421f07b31a --- /dev/null +++ b/sim/testsuite/sim/fr30/mulh.cgs @@ -0,0 +1,211 @@ +# fr30 testcase for mulh $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mulh +mulh: + ; Test mulh $Rj,$Ri + ; Positive operands + mvi_h_gr 0xdead0003,r7 ; multiply small numbers + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr 0xdead0001,r7 ; multiply by 1 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 1 + mvi_h_gr 0xbeef0001,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0000,r7 ; multiply by 0 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 0 + mvi_h_gr 0xbeef0000,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead3fff,r7 ; 15 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x0a ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdead4000,r7 ; 17 bit result + mvi_h_gr 0xbeef0004,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max positive result + mvi_h_gr 0xbeef7fff,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + ; Mixed operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -6,mdl + + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 0 + test_h_dr -2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr -2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead2001,r7 ; 15 bit result + mvi_h_gr -2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr 0xffffbffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 0 + test_h_dr 0xffff8000,mdl + + mvi_h_gr 0xdead4001,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x06 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 0 + test_h_dr 0xffff7ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 17 bit result + mvi_h_gr -4,r8 + set_cc 0x07 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xffff0000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max negative result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x07 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xc0008000,mdl + + ; Negative operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr -1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr -1,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdeadc001,r7 ; 15 bit result + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdeadc000,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x0a ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdeadc000,r7 ; 17 bit result + mvi_h_gr -4,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead8001,r7 ; almost max positive result + mvi_h_gr 0xbeef8001,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + mvi_h_gr 0xdead8000,r7 ; max positive result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x40000000,mdl + + pass diff --git a/sim/testsuite/sim/fr30/mulu.cgs b/sim/testsuite/sim/fr30/mulu.cgs new file mode 100644 index 00000000000..477583b224d --- /dev/null +++ b/sim/testsuite/sim/fr30/mulu.cgs @@ -0,0 +1,101 @@ +# fr30 testcase for mulu $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mulu +mulu: + ; Test mulu $Rj,$Ri + ; Positive operands + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x0f ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr 2,r8 + set_cc 0x0b ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x0a ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 0x3fffffff,r7 ; 31 bit result + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 32 bit result + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0x80000000,r7 ; 33 bit result + mvi_h_gr 2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 1 1 + test_h_dr 1,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x7fffffff,r7 ; max positive result + mvi_h_gr 0x7fffffff,r8 + set_cc 0x0d ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x3fffffff,mdh + test_h_dr 0x00000001,mdl + + mvi_h_gr 0x80000000,r7 ; max positive result + mvi_h_gr 0x80000000,r8 + set_cc 0x09 ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x40000000,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0xffffffff,r7 ; max positive result + mvi_h_gr 0xffffffff,r8 + set_cc 0x05 ; Set mask opposite of expected + mulu r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xfffffffe,mdh + test_h_dr 0x00000001,mdl + + pass diff --git a/sim/testsuite/sim/fr30/muluh.cgs b/sim/testsuite/sim/fr30/muluh.cgs new file mode 100644 index 00000000000..b0c847e1b97 --- /dev/null +++ b/sim/testsuite/sim/fr30/muluh.cgs @@ -0,0 +1,90 @@ +# fr30 testcase for muluh $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global muluh +muluh: + ; Test muluh $Rj,$Ri + ; Positive operands + mvi_h_gr 0xdead0003,r7 ; multiply small numbers + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr 0xdead0001,r7 ; multiply by 1 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x08 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 1 + mvi_h_gr 0xbeef0001,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0000,r7 ; multiply by 0 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 0 + mvi_h_gr 0xbeef0000,r8 + set_cc 0x08 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead3fff,r7 ; 15 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x08 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdead8000,r7 ; 17 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x0b ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max positive result + mvi_h_gr 0xbeef7fff,r8 + set_cc 0x0b ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + mvi_h_gr 0xdead8000,r7 ; max positive result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x0b ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x40000000,mdl + + mvi_h_gr 0xdeadffff,r7 ; max positive result + mvi_h_gr 0xbeefffff,r8 + set_cc 0x07 ; Set mask opposite of expected + muluh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xfffe0001,mdl + + pass diff --git a/sim/testsuite/sim/fr30/nop.cgs b/sim/testsuite/sim/fr30/nop.cgs new file mode 100644 index 00000000000..885c55cfd1a --- /dev/null +++ b/sim/testsuite/sim/fr30/nop.cgs @@ -0,0 +1,16 @@ +# fr30 testcase for nop +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global nop +nop: + ; Test nop + set_cc 0x0f ; Condition codes are irrelevent + nop + test_cc 1 1 1 1 + + pass diff --git a/sim/testsuite/sim/fr30/or.cgs b/sim/testsuite/sim/fr30/or.cgs new file mode 100644 index 00000000000..8acb9702000 --- /dev/null +++ b/sim/testsuite/sim/fr30/or.cgs @@ -0,0 +1,55 @@ +# fr30 testcase for or $Rj,$Ri, or $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global or +or: + ; Test or $Rj,$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0x55555555,r8 + set_cc 0x07 ; Set mask opposite of expected + or r7,r8 + test_cc 1 0 1 1 + test_h_gr 0xffffffff,r8 + + mvi_h_gr 0x00000000,r7 + mvi_h_gr 0x00000000,r8 + set_cc 0x08 ; Set mask opposite of expected + or r7,r8 + test_cc 0 1 0 0 + test_h_gr 0x00000000,r8 + + mvi_h_gr 0xdead0000,r7 + mvi_h_gr 0x0000beef,r8 + set_cc 0x05 ; Set mask opposite of expected + or r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xdeadbeef,r8 + + ; Test or $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + or r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffffffff,sp + + mvi_h_gr 0x00000000,r7 + mvi_h_mem 0x00000000,sp + set_cc 0x08 ; Set mask opposite of expected + or r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00000000,sp + + mvi_h_gr 0xdead0000,r7 + mvi_h_mem 0x0000beef,sp + set_cc 0x05 ; Set mask opposite of expected + or r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/orb.cgs b/sim/testsuite/sim/fr30/orb.cgs new file mode 100644 index 00000000000..a7b36bf5284 --- /dev/null +++ b/sim/testsuite/sim/fr30/orb.cgs @@ -0,0 +1,33 @@ +# fr30 testcase for orb $Rj,$Ri, orb $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global orb +orb: + ; Test orb $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + orb r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xff555555,sp + + mvi_h_gr 0xffffff00,r7 + mvi_h_mem 0x00ffffff,sp + set_cc 0x08 ; Set mask opposite of expected + orb r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00ffffff,sp + + mvi_h_gr 0x000000d0,r7 + mvi_h_mem 0x0eadbeef,sp + set_cc 0x05 ; Set mask opposite of expected + orb r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/orccr.cgs b/sim/testsuite/sim/fr30/orccr.cgs new file mode 100644 index 00000000000..3bc55a84570 --- /dev/null +++ b/sim/testsuite/sim/fr30/orccr.cgs @@ -0,0 +1,38 @@ +# fr30 testcase for orccr $u8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global orccr +orccr: + orccr 0xff + test_cc 1 1 1 1 + test_i 1 + test_s_user + + set_cc 0x0f + orccr 0x00 + test_cc 1 1 1 1 + test_i 1 + test_s_user + + set_cc 0x00 + set_i 0 + set_s_system + orccr 0xaa + test_cc 1 0 1 0 + test_i 0 + test_s_user + + set_cc 0x00 + set_i 0 + set_s_system + orccr 0xc0 + test_cc 0 0 0 0 + test_i 0 + test_s_system + + pass diff --git a/sim/testsuite/sim/fr30/orh.cgs b/sim/testsuite/sim/fr30/orh.cgs new file mode 100644 index 00000000000..b30b4028e85 --- /dev/null +++ b/sim/testsuite/sim/fr30/orh.cgs @@ -0,0 +1,33 @@ +# fr30 testcase for orh $Rj,$Ri, orh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global orh +orh: + ; Test orh $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + orh r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffff5555,sp + + mvi_h_gr 0xffff0000,r7 + mvi_h_mem 0x0000ffff,sp + set_cc 0x08 ; Set mask opposite of expected + orh r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x0000ffff,sp + + mvi_h_gr 0x0000de00,r7 + mvi_h_mem 0x00adbeef,sp + set_cc 0x05 ; Set mask opposite of expected + orh r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/ret.cgs b/sim/testsuite/sim/fr30/ret.cgs new file mode 100644 index 00000000000..7bfa0b230f9 --- /dev/null +++ b/sim/testsuite/sim/fr30/ret.cgs @@ -0,0 +1,75 @@ +# fr30 testcase for ret +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ret + + ; Test ret + mvi_h_gr 0xdeadbeef,r9 + mvi_h_gr #func1,r0 + set_cc 0x0f ; condition codes shouldn't change +call1: + call @r0 + testr_h_gr 2,r0 + test_h_gr 0xbeefdead,r9 + pass + +func1: + test_cc 1 1 1 1 + mvi_h_gr #call1,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + mvi_h_gr #func2,r0 + set_cc 0x0f ; condition codes shouldn't change +call2: + call:d @r0 + ldi:8 1,r0 ; Must assume this works + testr_h_gr 2,r0 + restore_rp + ret +func2: + test_cc 1 1 1 1 + mvi_h_gr #call2,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call3: + call func3 + testr_h_gr 2,r0 + restore_rp + ret +func3: + test_cc 1 1 1 1 + mvi_h_gr #call3,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call4: + call:d func4 + ldi:8 1,r0 ; Must assume this works + testr_h_gr 3,r0 + restore_rp + ret:d + ldi:8 2,r0 ; Must assume this works +func4: + test_cc 1 1 1 1 + mvi_h_gr #call4,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + mvi_h_gr 0xbeefdead,r9 + ret:d + ldi:8 3,r0 ; Must assume this works + + fail diff --git a/sim/testsuite/sim/fr30/reti.cgs b/sim/testsuite/sim/fr30/reti.cgs new file mode 100644 index 00000000000..76a1af0bb82 --- /dev/null +++ b/sim/testsuite/sim/fr30/reti.cgs @@ -0,0 +1,57 @@ +# fr30 testcase for reti +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global reti +reti: + ; Test reti with low reset of ilm allowed + mvr_h_gr sp,r8 ; Save stack pointer + set_s_system + set_i 1 + set_ilm 15 ; attempt reset of low range + set_cc 0x0f ; Condition codes should not change + save_ps + inci_h_gr -4,sp + mvi_h_mem ret1,sp + set_i 0 ; Set opposite of expected + set_ilm 0 ; attempt reset of low range + set_cc 0x00 ; Set opposite of expected + + reti + fail + +ret1: + test_cc 1 1 1 1 + test_s_system + test_i 1 + test_ilm 15 + testr_h_gr r8,sp + + ; Test reti with low reset of ilm not allowed + mvr_h_gr sp,r8 ; Save stack pointer + set_s_system + set_i 0 + set_ilm 15 ; attempt reset of low range + set_cc 0x0f ; Condition codes should not change + save_ps + inci_h_gr -4,sp + mvi_h_mem ret2,sp + set_i 0 ; Set opposite of expected + set_ilm 16 ; disallow reset of low range + set_cc 0x00 ; Set opposite of expected + + reti + fail + +ret2: + test_cc 1 1 1 1 + test_s_system + test_i 0 + test_ilm 31 + testr_h_gr r8,sp + + pass diff --git a/sim/testsuite/sim/fr30/st.cgs b/sim/testsuite/sim/fr30/st.cgs new file mode 100644 index 00000000000..e458d14001b --- /dev/null +++ b/sim/testsuite/sim/fr30/st.cgs @@ -0,0 +1,194 @@ +# fr30 testcase for +# mach(): fr30 +# st $Ri,@$Rj + + .include "testutils.inc" + + START + + .text + .global st +st: + mvr_h_gr sp,r9 ; Save stack pointer + ; Test st $Ri,@Rj + mvi_h_gr 0xdeadbeef,r8 + set_cc 0x0f ; Condition codes should not change + st r8,@sp + test_cc 1 1 1 1 + test_h_mem 0xdeadbeef,sp + test_h_gr 0xdeadbeef,r8 + + ; Test st $Ri,@(R13,Rj) + mvi_h_gr 0xbeefdead,r8 + mvr_h_gr sp,r1 + inci_h_gr -8,sp + mvr_h_gr sp,r2 + inci_h_gr 4,sp + + mvi_h_gr 4,r13 + set_cc 0x0e ; Condition codes should not change + st r8,@(r13,sp) + test_cc 1 1 1 0 + test_h_mem 0xbeefdead,r1 + test_h_gr 0xbeefdead,r8 + + mvi_h_gr 0,r13 + set_cc 0x0d ; Condition codes should not change + st r8,@(r13,sp) + test_cc 1 1 0 1 + test_h_mem 0xbeefdead,sp + test_h_gr 0xbeefdead,r8 + + mvi_h_gr -4,r13 + set_cc 0x0c ; Condition codes should not change + st r8,@(r13,sp) + test_cc 1 1 0 0 + test_h_mem 0xbeefdead,r2 + test_h_gr 0xbeefdead,r8 + + ; Test st $Ri,@(R14,$disp10) + mvi_h_gr 0xdeadbeef,r8 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr sp,r14 + inci_h_gr -508,r14 + mvr_h_gr r14,r2 + inci_h_gr -512,r14 + mvr_h_gr r14,r3 + inci_h_gr 512,r14 + + set_cc 0x0b ; Condition codes should not change + st r8,@(r14,508) + test_cc 1 0 1 1 + test_h_mem 0xdeadbeef,r1 + test_h_gr 0xdeadbeef,r8 + + set_cc 0x0a ; Condition codes should not change + st r8,@(r14,0) + test_cc 1 0 1 0 + test_h_mem 0xdeadbeef,r2 + test_h_gr 0xdeadbeef,r8 + + set_cc 0x09 ; Condition codes should not change + st r8,@(r14,-512) + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,r3 + test_h_gr 0xdeadbeef,r8 + + ; Test st $Ri,@(R15,$udisp6) + mvi_h_gr 0xbeefdead,r8 + mvr_h_gr r9,sp ; Restore stack pointer + inci_h_gr -60,sp + + set_cc 0x08 ; Condition codes should not change + st r8,@(r15,60) + test_cc 1 0 0 0 + test_h_mem 0xbeefdead,r9 + test_h_gr 0xbeefdead,r8 + + set_cc 0x07 ; Condition codes should not change + st r8,@(r15,0) + test_cc 0 1 1 1 + test_h_mem 0xbeefdead,r9 + test_h_gr 0xbeefdead,r8 + + ; Test st $Ri,@-R15 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr r9,r10 + + set_cc 0x06 ; Condition codes should not change + st r15,@-r15 + test_cc 0 1 1 0 + testr_h_mem r9,sp ; original value stored + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + mvi_h_gr 0xdeadbeef,r8 + set_cc 0x05 ; Condition codes should not change + st r8,@-r15 + test_cc 0 1 0 1 + test_h_mem 0xdeadbeef,sp + test_h_gr 0xdeadbeef,r8 + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + ; Test st $Rs,@-R15 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr r9,r10 + mvi_h_dr 0xbeefdead,tbr + mvi_h_dr 0xdeadbeef,rp + mvi_h_dr 0x0000dead,mdh + mvi_h_dr 0xbeef0000,mdl + + set_cc 0x04 ; Condition codes should not change + st tbr,@-r15 + test_cc 0 1 0 0 + test_h_mem 0xbeefdead,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x03 ; Condition codes should not change + st rp,@-r15 + test_cc 0 0 1 1 + test_h_mem 0xdeadbeef,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x02 ; Condition codes should not change + st mdh,@-r15 + test_cc 0 0 1 0 + test_h_mem 0x0000dead,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x01 ; Condition codes should not change + st mdl,@-r15 + test_cc 0 0 0 1 + test_h_mem 0xbeef0000,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + mvr_h_gr sp,usp + set_s_user + set_cc 0x00 ; Condition codes should not change + st ssp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x00 ; Condition codes should not change + st usp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp ; original value stored + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + mvr_h_gr sp,ssp + set_s_system + set_cc 0x00 ; Condition codes should not change + st usp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x00 ; Condition codes should not change + st ssp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp ; original value stored + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + ; Test st $PS,@-R15 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr r9,r10 + + set_cc 0x0f ; Condition codes affect result + set_dbits 3 ; Division bits affect result + st ps,@-r15 + test_cc 1 1 1 1 + test_h_mem 0x0000060f,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + pass diff --git a/sim/testsuite/sim/fr30/stb.cgs b/sim/testsuite/sim/fr30/stb.cgs new file mode 100644 index 00000000000..d9d4fd00aed --- /dev/null +++ b/sim/testsuite/sim/fr30/stb.cgs @@ -0,0 +1,84 @@ +# fr30 testcase for +# mach(): fr30 +# stb $Ri,@$Rj + + .include "testutils.inc" + + START + + .text + .global stb +stb: + mvr_h_gr sp,r9 ; Save stack pointer + ; Test stb $Ri,@Rj + mvi_h_mem 0xdeadbeef,sp + mvi_h_gr 0xaaaaaafe,r8 + set_cc 0x0f ; Condition codes should not change + stb r8,@sp + test_cc 1 1 1 1 + test_h_mem 0xfeadbeef,sp + test_h_gr 0xaaaaaafe,r8 + + ; Test stb $Ri,@(R13,Rj) + mvi_h_mem 0xbeefdead,sp + mvi_h_gr 0xaaaaaade,r8 + mvr_h_gr sp,r1 + inci_h_gr -8,sp + mvr_h_gr sp,r2 + mvi_h_mem 0xbeefdead,sp + inci_h_gr 4,sp + mvi_h_mem 0xbeefdead,sp + + mvi_h_gr 4,r13 + set_cc 0x0e ; Condition codes should not change + stb r8,@(r13,sp) + test_cc 1 1 1 0 + test_h_mem 0xdeefdead,r1 + test_h_gr 0xaaaaaade,r8 + + mvi_h_gr 0,r13 + set_cc 0x0d ; Condition codes should not change + stb r8,@(r13,sp) + test_cc 1 1 0 1 + test_h_mem 0xdeefdead,sp + test_h_gr 0xaaaaaade,r8 + + mvi_h_gr -4,r13 + set_cc 0x0c ; Condition codes should not change + stb r8,@(r13,sp) + test_cc 1 1 0 0 + test_h_mem 0xdeefdead,r2 + test_h_gr 0xaaaaaade,r8 + + ; Test stb $Ri,@(R14,$disp8 + mvr_h_gr r9,sp ; Restore stack pointer + mvi_h_gr 0xaaaaaafe,r8 + mvi_h_mem 0xdeadbeef,sp + mvr_h_gr sp,r14 + inci_h_gr -127,r14 + mvr_h_gr r14,r2 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr -128,r14 + mvr_h_gr r14,r3 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr 128,r14 + + set_cc 0x0b ; Condition codes should not change + stb r8,@(r14,127) + test_cc 1 0 1 1 + test_h_mem 0xfeadbeef,r1 + test_h_gr 0xaaaaaafe,r8 + + set_cc 0x0a ; Condition codes should not change + stb r8,@(r14,0) + test_cc 1 0 1 0 + test_h_mem 0xfeadbeef,r2 + test_h_gr 0xaaaaaafe,r8 + + set_cc 0x09 ; Condition codes should not change + stb r8,@(r14,-128) + test_cc 1 0 0 1 + test_h_mem 0xfeadbeef,r3 + test_h_gr 0xaaaaaafe,r8 + + pass diff --git a/sim/testsuite/sim/fr30/sth.cgs b/sim/testsuite/sim/fr30/sth.cgs new file mode 100644 index 00000000000..64c83e6072f --- /dev/null +++ b/sim/testsuite/sim/fr30/sth.cgs @@ -0,0 +1,84 @@ +# fr30 testcase for +# mach(): fr30 +# sth $Ri,@$Rj + + .include "testutils.inc" + + START + + .text + .global sth +sth: + mvr_h_gr sp,r9 ; Save stack pointer + ; Test sth $Ri,@Rj + mvi_h_mem 0xdeadbeef,sp + mvi_h_gr 0xaaaabeef,r8 + set_cc 0x0f ; Condition codes should not change + sth r8,@sp + test_cc 1 1 1 1 + test_h_mem 0xbeefbeef,sp + test_h_gr 0xaaaabeef,r8 + + ; Test sth $Ri,@(R13,Rj) + mvi_h_mem 0xbeefdead,sp + mvi_h_gr 0xaaaadead,r8 + mvr_h_gr sp,r1 + inci_h_gr -8,sp + mvr_h_gr sp,r2 + mvi_h_mem 0xbeefdead,sp + inci_h_gr 4,sp + mvi_h_mem 0xbeefdead,sp + + mvi_h_gr 4,r13 + set_cc 0x0e ; Condition codes should not change + sth r8,@(r13,sp) + test_cc 1 1 1 0 + test_h_mem 0xdeaddead,r1 + test_h_gr 0xaaaadead,r8 + + mvi_h_gr 0,r13 + set_cc 0x0d ; Condition codes should not change + sth r8,@(r13,sp) + test_cc 1 1 0 1 + test_h_mem 0xdeaddead,sp + test_h_gr 0xaaaadead,r8 + + mvi_h_gr -4,r13 + set_cc 0x0c ; Condition codes should not change + sth r8,@(r13,sp) + test_cc 1 1 0 0 + test_h_mem 0xdeaddead,r2 + test_h_gr 0xaaaadead,r8 + + ; Test sth $Ri,@(R14,$disp9) + mvr_h_gr r9,sp ; Restore stack pointer + mvi_h_gr 0xaaaabeef,r8 + mvi_h_mem 0xdeadbeef,sp + mvr_h_gr sp,r14 + inci_h_gr -254,r14 + mvr_h_gr r14,r2 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr -256,r14 + mvr_h_gr r14,r3 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr 256,r14 + + set_cc 0x0b ; Condition codes should not change + sth r8,@(r14,254) + test_cc 1 0 1 1 + test_h_mem 0xbeefbeef,r1 + test_h_gr 0xaaaabeef,r8 + + set_cc 0x0a ; Condition codes should not change + sth r8,@(r14,0) + test_cc 1 0 1 0 + test_h_mem 0xbeefbeef,r2 + test_h_gr 0xaaaabeef,r8 + + set_cc 0x09 ; Condition codes should not change + sth r8,@(r14,-256) + test_cc 1 0 0 1 + test_h_mem 0xbeefbeef,r3 + test_h_gr 0xaaaabeef,r8 + + pass diff --git a/sim/testsuite/sim/fr30/stilm.cgs b/sim/testsuite/sim/fr30/stilm.cgs new file mode 100644 index 00000000000..197940bbf4f --- /dev/null +++ b/sim/testsuite/sim/fr30/stilm.cgs @@ -0,0 +1,41 @@ +# fr30 testcase for stilm $i8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stilm +stilm: + stilm 0 + test_ilm 0 + + stilm 0xe0 + test_ilm 0 + + stilm 1 + test_ilm 1 + + stilm 15 + test_ilm 15 + + stilm 16 + test_ilm 16 + + stilm 0 + test_ilm 16 + + stilm 1 + test_ilm 17 + + stilm 18 + test_ilm 18 + + stilm 31 + test_ilm 31 + + stilm 0xff + test_ilm 31 + + pass diff --git a/sim/testsuite/sim/fr30/stm0.cgs b/sim/testsuite/sim/fr30/stm0.cgs new file mode 100644 index 00000000000..5cc162c1a31 --- /dev/null +++ b/sim/testsuite/sim/fr30/stm0.cgs @@ -0,0 +1,101 @@ +# fr30 testcase for stm0 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stm0 +stm0: + ; Test stm0 ($reglist_low) + mvr_h_gr sp,r8 ; save stack pointer temporarily + mvr_h_gr sp,r9 ; save stack pointer permanently + mvi_h_gr 0,r0 + mvi_h_gr 1,r1 + mvi_h_gr 2,r2 + mvi_h_gr 3,r3 + mvi_h_gr 4,r4 + mvi_h_gr 5,r5 + mvi_h_gr 6,r6 + mvi_h_gr 7,r7 + set_cc 0x0f ; Condition codes should not change + stm0 (r0,r2,r4,r6) + test_cc 1 1 1 1 + inci_h_gr -4,r8 + test_h_mem 6,r8 + inci_h_gr -4,r8 + test_h_mem 4,r8 + inci_h_gr -4,r8 + test_h_mem 2,r8 + inci_h_gr -4,r8 + test_h_mem 0,r8 + + mvr_h_gr r9,sp ; restore stack pointer + mvr_h_gr r9,r8 ; save stack pointer temporarily + mvi_h_gr 0,r0 + mvi_h_gr 1,r1 + mvi_h_gr 2,r2 + mvi_h_gr 3,r3 + mvi_h_gr 4,r4 + mvi_h_gr 5,r5 + mvi_h_gr 6,r6 + mvi_h_gr 7,r7 + set_cc 0x0f ; Condition codes should not change + stm0 (r1,r3,r5,r7) + test_cc 1 1 1 1 + inci_h_gr -4,r8 + test_h_mem 7,r8 + inci_h_gr -4,r8 + test_h_mem 5,r8 + inci_h_gr -4,r8 + test_h_mem 3,r8 + inci_h_gr -4,r8 + test_h_mem 1,r8 + + mvr_h_gr r9,sp ; restore stack pointer + mvr_h_gr r9,r8 ; save stack pointer temporarily + mvi_h_gr 0,r0 + mvi_h_gr 1,r1 + mvi_h_gr 2,r2 + mvi_h_gr 3,r3 + mvi_h_gr 4,r4 + mvi_h_gr 5,r5 + mvi_h_gr 6,r6 + mvi_h_gr 7,r7 + set_cc 0x0f ; Condition codes should not change + stm0 (r1,r5,r7,r3) ; Order specified should not matter + test_cc 1 1 1 1 + inci_h_gr -4,r8 + test_h_mem 7,r8 + inci_h_gr -4,r8 + test_h_mem 5,r8 + inci_h_gr -4,r8 + test_h_mem 3,r8 + inci_h_gr -4,r8 + test_h_mem 1,r8 + + mvr_h_gr r9,sp ; restore stack pointer + mvr_h_gr r9,r8 ; save stack pointer temporarily + mvi_h_gr 9,r0 + mvi_h_gr 9,r1 + mvi_h_gr 9,r2 + mvi_h_gr 9,r3 + mvi_h_gr 9,r4 + mvi_h_gr 9,r5 + mvi_h_gr 9,r6 + mvi_h_gr 9,r7 + set_cc 0x0f ; Condition codes should not change + stm0 () ; should do nothing + test_cc 1 1 1 1 + testr_h_gr r9,sp + inci_h_gr -4,r8 + test_h_mem 7,r8 + inci_h_gr -4,r8 + test_h_mem 5,r8 + inci_h_gr -4,r8 + test_h_mem 3,r8 + inci_h_gr -4,r8 + test_h_mem 1,r8 + + pass diff --git a/sim/testsuite/sim/fr30/stm1.cgs b/sim/testsuite/sim/fr30/stm1.cgs new file mode 100644 index 00000000000..2ac373d3544 --- /dev/null +++ b/sim/testsuite/sim/fr30/stm1.cgs @@ -0,0 +1,97 @@ +# fr30 testcase for stm1 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stm1 +stm1: + ; Test stm1 ($reglist_low) + mvr_h_gr sp,r1 ; save stack pointer temporarily + mvr_h_gr sp,r2 ; save stack pointer permanently + mvi_h_gr 8,r8 + mvi_h_gr 9,r9 + mvi_h_gr 10,r10 + mvi_h_gr 11,r11 + mvi_h_gr 12,r12 + mvi_h_gr 13,r13 + mvi_h_gr 14,r14 + set_cc 0x0f ; Condition codes should not change + stm1 (r8,r10,r12,r14) + test_cc 1 1 1 1 + inci_h_gr -4,r1 + test_h_mem 14,r1 + inci_h_gr -4,r1 + test_h_mem 12,r1 + inci_h_gr -4,r1 + test_h_mem 10,r1 + inci_h_gr -4,r1 + testr_h_mem 8,r1 + + mvr_h_gr r2,sp ; restore stack pointer + mvr_h_gr r2,r1 ; save stack pointer temporarily + mvi_h_gr 8,r8 + mvi_h_gr 9,r9 + mvi_h_gr 10,r10 + mvi_h_gr 11,r11 + mvi_h_gr 12,r12 + mvi_h_gr 13,r13 + mvi_h_gr 14,r14 + set_cc 0x0f ; Condition codes should not change + stm1 (r9,r11,r13,r15) + test_cc 1 1 1 1 + inci_h_gr -4,r1 + testr_h_mem r2,r1 + inci_h_gr -4,r1 + test_h_mem 13,r1 + inci_h_gr -4,r1 + test_h_mem 11,r1 + inci_h_gr -4,r1 + test_h_mem 9,r1 ; saved r15 is from before stm1 + + mvr_h_gr r2,sp ; restore stack pointer + mvr_h_gr r2,r1 ; save stack pointer temporarily + mvi_h_gr 8,r8 + mvi_h_gr 9,r9 + mvi_h_gr 10,r10 + mvi_h_gr 11,r11 + mvi_h_gr 12,r12 + mvi_h_gr 13,r13 + mvi_h_gr 14,r14 + set_cc 0x0f ; Condition codes should not change + stm1 (r9,r13,r15,r11); Order specified should not matter + test_cc 1 1 1 1 + inci_h_gr -4,r1 + testr_h_mem r2,r1 + inci_h_gr -4,r1 + test_h_mem 13,r1 + inci_h_gr -4,r1 + test_h_mem 11,r1 + inci_h_gr -4,r1 + test_h_mem 9,r1 ; saved r15 is from before stm1 + + mvr_h_gr r2,sp ; restore stack pointer + mvr_h_gr r2,r1 ; save stack pointer temporarily + mvi_h_gr 9,r8 + mvi_h_gr 9,r9 + mvi_h_gr 9,r10 + mvi_h_gr 9,r11 + mvi_h_gr 9,r12 + mvi_h_gr 9,r13 + mvi_h_gr 9,r14 + set_cc 0x0f ; Condition codes should not change + stm1 () ; should do nothing + test_cc 1 1 1 1 + testr_h_gr r2,sp + inci_h_gr -4,r1 + testr_h_mem r2,r1 + inci_h_gr -4,r1 + test_h_mem 13,r1 + inci_h_gr -4,r1 + test_h_mem 11,r1 + inci_h_gr -4,r1 + test_h_mem 9,r1 + + pass diff --git a/sim/testsuite/sim/fr30/stres.cgs b/sim/testsuite/sim/fr30/stres.cgs new file mode 100644 index 00000000000..a85fdf3f9f4 --- /dev/null +++ b/sim/testsuite/sim/fr30/stres.cgs @@ -0,0 +1,25 @@ +# fr30 testcase for stres $@Ri+,$u4 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stres +stres: + ; Test stres $@Ri+,$u4 + ; The current implementation simply increments Ri + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + stres 0,@r7+ + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + stres 0xf,@r7+ + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + pass diff --git a/sim/testsuite/sim/fr30/sub.cgs b/sim/testsuite/sim/fr30/sub.cgs new file mode 100644 index 00000000000..eceaa79c5c6 --- /dev/null +++ b/sim/testsuite/sim/fr30/sub.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for sub $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global sub +sub: + ; Test sub $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + sub r7,r8 + test_cc 0 0 0 0 + test_h_gr 1,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + sub r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x7fffffff,r8 + + set_cc 0x0b ; Set mask opposite of expected + sub r8,r8 + test_cc 0 1 0 0 + test_h_gr 0,r8 + + set_cc 0x06 ; Set mask opposite of expected + sub r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xffffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/subc.cgs b/sim/testsuite/sim/fr30/subc.cgs new file mode 100644 index 00000000000..2978e40c38d --- /dev/null +++ b/sim/testsuite/sim/fr30/subc.cgs @@ -0,0 +1,62 @@ +# fr30 testcase for subc $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global subc +subc: + ; Test subc $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0e ; Make sure carry is off + subc r7,r8 + test_cc 0 0 0 0 + test_h_gr 1,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0c ; Make sure carry is off + subc r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x7fffffff,r8 + + set_cc 0x0a ; Make sure carry is off + subc r8,r8 + test_cc 0 1 0 0 + test_h_gr 0,r8 + + set_cc 0x06 ; Make sure carry is off + subc r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xffffffff,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 3,r8 + set_cc 0x0f ; Make sure carry is on + subc r7,r8 + test_cc 0 0 0 0 + test_h_gr 1,r8 + + mvi_h_gr 0,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Make sure carry is on + subc r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x7fffffff,r8 + + mvi_h_gr 0x7ffffffe,r7 + set_cc 0x0b ; Make sure carry is on + subc r7,r8 + test_cc 0 1 0 0 + test_h_gr 0,r8 + + mvi_h_gr 0,r7 + set_cc 0x07 ; Make sure carry is on + subc r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xffffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/subn.cgs b/sim/testsuite/sim/fr30/subn.cgs new file mode 100644 index 00000000000..c4830468d22 --- /dev/null +++ b/sim/testsuite/sim/fr30/subn.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for subn $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global subn +subn: + ; Test subn $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of usual result + subn r7,r8 + test_cc 1 1 1 1 + test_h_gr 1,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of usual result + subn r7,r8 + test_cc 1 1 0 1 + test_h_gr 0x7fffffff,r8 + + set_cc 0x0b ; Set mask opposite of usual result + subn r8,r8 + test_cc 1 0 1 1 + test_h_gr 0,r8 + + set_cc 0x06 ; Set mask opposite of usual result + subn r7,r8 + test_cc 0 1 1 0 + test_h_gr 0xffffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/testutils.inc b/sim/testsuite/sim/fr30/testutils.inc new file mode 100644 index 00000000000..7523d6f6aa5 --- /dev/null +++ b/sim/testsuite/sim/fr30/testutils.inc @@ -0,0 +1,306 @@ +# r0, r4-r6 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + ldi32 0x7fffc,sp ; TODO -- what's a good value for this? + ldi32 0xffc00,r0 + mov r0,tbr ; defined in manual + mov sp,usp + mov sp,ssp + .endm + +; Exit with return code + .macro exit rc + ldi32 \rc,r4 + ldi32 #1,r0 + int #10 + .endm + +; Pass the test case + .macro pass + ldi32 #5,r6 + ldi32 #passmsg,r5 + ldi32 #1,r4 + ldi32 #5,r0 + int #10 + exit #0 + .endm + +; Fail the testcase + .macro fail + ldi32 #5,r6 + ldi32 #failmsg,r5 + ldi32 #1,r4 + ldi32 #5,r0 + int #10 + exit #1 + .endm + +; Load an immediate value into a general register +; TODO: use minimal sized insn + .macro mvi_h_gr val reg + ldi32 \val,\reg + .endm + +; Load an immediate value into a dedicated register + .macro mvi_h_dr val reg + ldi32 \val,r0 + mov r0,\reg + .endm + +; Load a general register into another general register + .macro mvr_h_gr src targ + mov \src,\targ + .endm + +; Store an immediate into a word in memory + .macro mvi_h_mem val addr + mvi_h_gr \val r4 + mvr_h_mem r4,\addr + .endm + +; Store a register into a word in memory + .macro mvr_h_mem reg addr + st \reg,@\addr + .endm + +; Store the current ps on the stack + .macro save_ps + st ps,@-r15 + .endm + +; Load a word value from memory + .macro ldmem_h_gr addr reg + ld @\addr,\reg + .endm + +; Add 2 general registers + .macro add_h_gr reg1 reg2 + add \reg1,\reg2 + .endm + +; Increment a register by and immediate + .macro inci_h_gr inc reg + mvi_h_gr \inc,r4 + add r4,\reg + .endm + +; Test the value of an immediate against a general register + .macro test_h_gr val reg + .if (\val >= 0) && (\val <= 15) + cmp \val,\reg + .else + .if (\val < 0) && (\val >= -16) + cmp2 \val,\reg + .else + ldi32 \val,r4 + cmp r4,\reg + .endif + .endif + beq test_gr\@ + fail +test_gr\@: + .endm + +; compare two general registers + .macro testr_h_gr reg1 reg2 + cmp \reg1,\reg2 + beq testr_gr\@ + fail +testr_gr\@: + .endm + +; Test the value of an immediate against a dedicated register + .macro test_h_dr val reg + mov \reg,r5 + test_h_gr \val r5 + .endm + +; Test the value of an general register against a dedicated register + .macro testr_h_dr gr dr + mov \dr,r5 + testr_h_gr \gr r5 + .endm + +; Compare an immediate with word in memory + .macro test_h_mem val addr + ldmem_h_gr \addr r5 + test_h_gr \val r5 + .endm + +; Compare a general register with word in memory + .macro testr_h_mem reg addr + ldmem_h_gr \addr r5 + testr_h_gr \reg r5 + .endm + +; Set the condition codes + .macro set_cc mask + andccr 0xf0 + orccr \mask + .endm + +; Set the stack mode + .macro set_s_user + orccr 0x20 + .endm + + .macro set_s_system + andccr 0x1f + .endm + +; Test the stack mode + .macro test_s_user + mvr_h_gr ps,r0 + mvi_h_gr 0x20,r4 + and r4,r0 + test_h_gr 0x20,r0 + .endm + + .macro test_s_system + mvr_h_gr ps,r0 + mvi_h_gr 0x20,r4 + and r4,r0 + test_h_gr 0x0,r0 + .endm + +; Set the interrupt bit + .macro set_i val + .if (\val == 1) + orccr 0x10 + .else + andccr 0x2f + .endif + .endm + +; Test the stack mode + .macro test_i val + mvr_h_gr ps,r0 + mvi_h_gr 0x10,r4 + and r4,r0 + .if (\val == 1) + test_h_gr 0x10,r0 + .else + test_h_gr 0x0,r0 + .endif + .endm + +; Set the ilm + .macro set_ilm val + stilm \val + .endm + +; Test the ilm + .macro test_ilm val + mvr_h_gr ps,r0 + mvi_h_gr 0x1f0000,r4 + and r4,r0 + mvi_h_gr \val,r5 + mvi_h_gr 0x1f,r4 + and r4,r5 + lsl 15,r5 + lsl 1,r5 + testr_h_gr r0,r5 + .endm + +; Test the condition codes + .macro test_cc N Z V C + .if (\N == 1) + bp fail\@ + .else + bn fail\@ + .endif + .if (\Z == 1) + bne fail\@ + .else + beq fail\@ + .endif + .if (\V == 1) + bnv fail\@ + .else + bv fail\@ + .endif + .if (\C == 1) + bnc fail\@ + .else + bc fail\@ + .endif + bra test_cc\@ +fail\@: + fail +test_cc\@: + .endm + +; Set the division bits + .macro set_dbits val + mvr_h_gr ps,r5 + mvi_h_gr 0xfffff8ff,r4 + and r4,r5 + mvi_h_gr \val,r0 + mvi_h_gr 3,r4 + and r4,r0 + lsl 9,r0 + or r0,r5 + mvr_h_gr r5,ps + .endm + +; Test the division bits + .macro test_dbits val + mvr_h_gr ps,r0 + lsr 9,r0 + mvi_h_gr 3,r4 + and r4,r0 + test_h_gr \val,r0 + .endm + +; Save the return pointer + .macro save_rp + st rp,@-R15 + .ENDM + +; restore the return pointer + .macro restore_rp + ld @R15+,rp + .endm + +; Ensure branch taken + .macro take_branch opcode + \opcode take_br\@ + fail +take_br\@: + .endm + + .macro take_branch_d opcode val + \opcode take_brd\@ + ldi:8 \val,r0 + fail +take_brd\@: + test_h_gr \val,r0 + .endm + +; Ensure branch not taken + .macro no_branch opcode + \opcode no_brf\@ + bra no_brs\@ +no_brf\@: + fail +no_brs\@: + .endm + + .macro no_branch_d opcode val + \opcode no_brdf\@ + ldi:8 \val,r0 + bra no_brds\@ +no_brdf\@: + fail +no_brds\@: + test_h_gr \val,r0 + .endm + diff --git a/sim/testsuite/sim/fr30/xchb.cgs b/sim/testsuite/sim/fr30/xchb.cgs new file mode 100644 index 00000000000..3450a2e34cd --- /dev/null +++ b/sim/testsuite/sim/fr30/xchb.cgs @@ -0,0 +1,20 @@ +# fr30 testcase for xchb @$Rj,Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global xchb +xchb: + ; Test xchb @$Rj,Ri + mvi_h_mem 0xdeadbeef,sp + mvi_h_gr 0xbeefdead,r0 + set_cc 0x0f ; Condition codes are irrelevent + xchb @sp,r0 + test_cc 1 1 1 1 + test_h_gr 0xde,r0 + test_h_mem 0xadadbeef,sp + + pass diff --git a/sim/testsuite/sim/m32r/add.cgs b/sim/testsuite/sim/m32r/add.cgs new file mode 100644 index 00000000000..8ed2b3a2ad3 --- /dev/null +++ b/sim/testsuite/sim/m32r/add.cgs @@ -0,0 +1,16 @@ +# m32r testcase for add $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add +add: + + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + add r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/add3.cgs b/sim/testsuite/sim/m32r/add3.cgs new file mode 100644 index 00000000000..d1cc8480ad4 --- /dev/null +++ b/sim/testsuite/sim/m32r/add3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for add3 $dr,$sr,#$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add3 +add3: + + mvi_h_gr r5, 1 + add3 r4, r5, 2 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/addi.cgs b/sim/testsuite/sim/m32r/addi.cgs new file mode 100644 index 00000000000..1448d0d2e2b --- /dev/null +++ b/sim/testsuite/sim/m32r/addi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for addi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addi +addi: + + mvi_h_gr r5, 1 + addi r5, 2 + test_h_gr r5, 3 + + pass + diff --git a/sim/testsuite/sim/m32r/addv.cgs b/sim/testsuite/sim/m32r/addv.cgs new file mode 100644 index 00000000000..704be83c914 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv.cgs @@ -0,0 +1,21 @@ +# m32r testcase for addv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv +addv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 0x80000000 + + addv r4, r5 + + bnc not_ok + test_h_gr r4, 0 + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/addv3.cgs b/sim/testsuite/sim/m32r/addv3.cgs new file mode 100644 index 00000000000..a8c0a108561 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv3.cgs @@ -0,0 +1,28 @@ +# m32r testcase for addv3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv3 +addv3: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 1 + + addv3 r4, r5, #2 + + bc not_ok + + test_h_gr r4, 3 + + mvi_h_gr r5, 0x7fff8001 + + addv3 r4, r5, #0x7fff + + bnc not_ok + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/addx.cgs b/sim/testsuite/sim/m32r/addx.cgs new file mode 100644 index 00000000000..630e3dbe15a --- /dev/null +++ b/sim/testsuite/sim/m32r/addx.cgs @@ -0,0 +1,42 @@ +# m32r testcase for addx $dr,$sr +# mach(): m32r m32rx +# timeout(): 42 + +# timeout is set to test it + + .include "testutils.inc" + + start + + .global addx +addx: + mvi_h_condbit 1 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + addx r4, r5 + bc not_ok + test_h_gr r4, 4 + + mvi_h_gr r4, 0xfffffffe + addx r4, r5 + bnc not_ok + test_h_gr r4, 0 + + mvi_h_gr r4, -1 + mvi_h_gr r5, -1 + mvi_h_condbit 1 + addx r4,r5 + bnc not_ok + test_h_gr r4, -1 + + mvi_h_gr r4,-1 + mvi_h_gr r5,0x7fffffff + mvi_h_condbit 1 + addx r5,r4 + bnc not_ok + test_h_gr r5,0x7fffffff + + pass + +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/allinsn.exp b/sim/testsuite/sim/m32r/allinsn.exp new file mode 100644 index 00000000000..8eed80f91d6 --- /dev/null +++ b/sim/testsuite/sim/m32r/allinsn.exp @@ -0,0 +1,21 @@ +# M32R simulator testsuite. + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/m32r/and.cgs b/sim/testsuite/sim/m32r/and.cgs new file mode 100644 index 00000000000..1c268855411 --- /dev/null +++ b/sim/testsuite/sim/m32r/and.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and +and: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + and r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/and3.cgs b/sim/testsuite/sim/m32r/and3.cgs new file mode 100644 index 00000000000..395de3028e9 --- /dev/null +++ b/sim/testsuite/sim/m32r/and3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and3 +and3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + and3 r4, r5, #3 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/bc24.cgs b/sim/testsuite/sim/m32r/bc24.cgs new file mode 100644 index 00000000000..6bb43334e8f --- /dev/null +++ b/sim/testsuite/sim/m32r/bc24.cgs @@ -0,0 +1,24 @@ +# m32r testcase for bc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bc.l test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.l test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/sim/m32r/bc8.cgs b/sim/testsuite/sim/m32r/bc8.cgs new file mode 100644 index 00000000000..ceb622c1661 --- /dev/null +++ b/sim/testsuite/sim/m32r/bc8.cgs @@ -0,0 +1,23 @@ +# m32r testcase for bc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc8 +bc8: + + mvi_h_condbit 0 + bc.s test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.s test1pass + fail +test1pass: + + pass diff --git a/sim/testsuite/sim/m32r/beq.cgs b/sim/testsuite/sim/m32r/beq.cgs new file mode 100644 index 00000000000..c4d6d8bf0aa --- /dev/null +++ b/sim/testsuite/sim/m32r/beq.cgs @@ -0,0 +1,20 @@ +# m32r testcase for beq $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + mvi_h_gr r4, 12 + mvi_h_gr r5, 12 + beq r4, r5, ok +not_ok: + fail +ok: + mvi_h_gr r5, 11 + beq r4, r5, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/beqz.cgs b/sim/testsuite/sim/m32r/beqz.cgs new file mode 100644 index 00000000000..654737d3d46 --- /dev/null +++ b/sim/testsuite/sim/m32r/beqz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for beqz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beqz +beqz: + mvi_h_gr r4, 0 + beqz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 1 + beqz r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bgez.cgs b/sim/testsuite/sim/m32r/bgez.cgs new file mode 100644 index 00000000000..f7031f0edcb --- /dev/null +++ b/sim/testsuite/sim/m32r/bgez.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgez +bgez: + mvi_h_gr r4, 1 + bgez r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, -1 + bgez r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bgtz.cgs b/sim/testsuite/sim/m32r/bgtz.cgs new file mode 100644 index 00000000000..6ab8989c7e0 --- /dev/null +++ b/sim/testsuite/sim/m32r/bgtz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgtz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgtz +bgtz: + mvi_h_gr r4, 1 + bgtz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 0 + bgtz r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bl24.cgs b/sim/testsuite/sim/m32r/bl24.cgs new file mode 100644 index 00000000000..fd6f0dd69d5 --- /dev/null +++ b/sim/testsuite/sim/m32r/bl24.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl24 +bl24: + bl.l test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bl8.cgs b/sim/testsuite/sim/m32r/bl8.cgs new file mode 100644 index 00000000000..d26369853b7 --- /dev/null +++ b/sim/testsuite/sim/m32r/bl8.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl8 +bl8: + bl.s test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/blez.cgs b/sim/testsuite/sim/m32r/blez.cgs new file mode 100644 index 00000000000..e3d198d93ad --- /dev/null +++ b/sim/testsuite/sim/m32r/blez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for blez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global blez +blez: + mvi_h_gr r4, 0 + blez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 1 + blez r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bltz.cgs b/sim/testsuite/sim/m32r/bltz.cgs new file mode 100644 index 00000000000..c9377fcaab1 --- /dev/null +++ b/sim/testsuite/sim/m32r/bltz.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bltz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bltz +bltz: + mvi_h_gr r4, -1 + bltz r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bltz r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnc24.cgs b/sim/testsuite/sim/m32r/bnc24.cgs new file mode 100644 index 00000000000..692d2d58436 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc24.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc24 +bnc24: + mvi_h_condbit 0 + bnc.l test0pass + +test1fail: + fail +test0pass: + + mvi_h_condbit 1 + bnc.l test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnc8.cgs b/sim/testsuite/sim/m32r/bnc8.cgs new file mode 100644 index 00000000000..dae2613cc9f --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc8.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc8 +bnc8: + mvi_h_condbit 0 + bnc.s test0pass + +test1fail: + fail + +test0pass: + mvi_h_condbit 1 + bnc.s test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bne.cgs b/sim/testsuite/sim/m32r/bne.cgs new file mode 100644 index 00000000000..5e1d7a6ecc5 --- /dev/null +++ b/sim/testsuite/sim/m32r/bne.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bne $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bne +bne: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + bne r4, r5, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 2 + bne r4, r5, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnez.cgs b/sim/testsuite/sim/m32r/bnez.cgs new file mode 100644 index 00000000000..9f102895029 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bnez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnez +bnez: + mvi_h_gr r4, 1 + bnez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bnez r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bra24.cgs b/sim/testsuite/sim/m32r/bra24.cgs new file mode 100644 index 00000000000..d62d2bf0ec3 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra24.cgs @@ -0,0 +1,15 @@ +# m32r testcase for bra $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra24 +bra24: + bra.l ok + + fail + +ok: + pass diff --git a/sim/testsuite/sim/m32r/bra8.cgs b/sim/testsuite/sim/m32r/bra8.cgs new file mode 100644 index 00000000000..f5f50ad2d93 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for bra $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra8 +bra8: + bra.s ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/cmp.cgs b/sim/testsuite/sim/m32r/cmp.cgs new file mode 100644 index 00000000000..6ea67206218 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmp.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmp $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmp +cmp: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + cmp r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmp r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/cmpi.cgs b/sim/testsuite/sim/m32r/cmpi.cgs new file mode 100644 index 00000000000..af11283d68d --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpi.cgs @@ -0,0 +1,24 @@ +# m32r testcase for cmpi $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + cmpi r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmpi r4, #2 + bc not_ok + + + pass diff --git a/sim/testsuite/sim/m32r/cmpu.cgs b/sim/testsuite/sim/m32r/cmpu.cgs new file mode 100644 index 00000000000..e0b4ef10180 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmpu $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpu +cmpu: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, -2 + cmpu r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpu r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/cmpui.cgs b/sim/testsuite/sim/m32r/cmpui.cgs new file mode 100644 index 00000000000..aa30207d933 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpui.cgs @@ -0,0 +1,22 @@ +# m32r testcase for cmpui $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpui +cmpui: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + cmpui r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpui r4, #2 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/div.cgs b/sim/testsuite/sim/m32r/div.cgs new file mode 100644 index 00000000000..733f3629680 --- /dev/null +++ b/sim/testsuite/sim/m32r/div.cgs @@ -0,0 +1,17 @@ +# m32r testcase for div $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global div +div: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + div r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/sim/m32r/divu.cgs b/sim/testsuite/sim/m32r/divu.cgs new file mode 100644 index 00000000000..25342d5dccc --- /dev/null +++ b/sim/testsuite/sim/m32r/divu.cgs @@ -0,0 +1,17 @@ +# m32r testcase for divu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global divu +divu: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + divu r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/sim/m32r/hello.ms b/sim/testsuite/sim/m32r/hello.ms new file mode 100644 index 00000000000..7ae22778001 --- /dev/null +++ b/sim/testsuite/sim/m32r/hello.ms @@ -0,0 +1,19 @@ +# output(): Hello world!\n +# mach(): m32r m32rx + + .globl _start +_start: + +; write (hello world) + ldi8 r3,#14 + ld24 r2,#hello + ldi8 r1,#1 + ldi8 r0,#5 + trap #0 +; exit (0) + ldi8 r1,#0 + ldi8 r0,#1 + trap #0 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/m32r/hw-trap.ms b/sim/testsuite/sim/m32r/hw-trap.ms new file mode 100644 index 00000000000..2aa200b5d70 --- /dev/null +++ b/sim/testsuite/sim/m32r/hw-trap.ms @@ -0,0 +1,31 @@ +# mach(): m32r m32rx +# output(): pass\n + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#bra_insn + ld r0,@r0 + ld24 r1,#trap2_handler + addi r1,#-0x48 ; pc relative address from trap 2 slot to handler + srai r1,#2 + or r0,r1 + ld24 r2,#0x48 ; address of trap 2 slot + st r0,@r2 + +; perform trap + ldi r4,#0 + trap #2 + test_h_gr r4,42 + + pass + +; trap 2 handler +trap2_handler: + ldi r4,#42 + rte + +bra_insn: + bra.l 0 diff --git a/sim/testsuite/sim/m32r/jl.cgs b/sim/testsuite/sim/m32r/jl.cgs new file mode 100644 index 00000000000..a89c26a86bf --- /dev/null +++ b/sim/testsuite/sim/m32r/jl.cgs @@ -0,0 +1,18 @@ +# m32r testcase for jl $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jl +jl: + mvaddr_h_gr r4, ok + jl r4 +not_ok: + fail +ok: + mvaddr_h_gr r4, not_ok + bne r4, r14, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/jmp.cgs b/sim/testsuite/sim/m32r/jmp.cgs new file mode 100644 index 00000000000..ba0864a53f0 --- /dev/null +++ b/sim/testsuite/sim/m32r/jmp.cgs @@ -0,0 +1,19 @@ +# m32r testcase for jmp $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jmp +jmp: + mvaddr_h_gr r4, ok1 + jmp r4 + fail +ok1: + mvaddr_h_gr r4, ok2 + addi r4,#1 + jmp r4 + fail +ok2: + pass diff --git a/sim/testsuite/sim/m32r/ld-d.cgs b/sim/testsuite/sim/m32r/ld-d.cgs new file mode 100644 index 00000000000..151743672b2 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-d.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ld $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_d +ld_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @(#4, r4) + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x11223344 + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ld-plus.cgs b/sim/testsuite/sim/m32r/ld-plus.cgs new file mode 100644 index 00000000000..5feaf62596e --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for ld $dr,@$sr+ +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_plus +ld_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4+ + + test_h_gr r5, 0x12345678 + + mvaddr_h_gr r5, data_loc2 + bne r4, r5, not_ok + + pass +not_ok: + fail + +data_loc: + .word 0x12345678 +data_loc2: + .word 0x11223344 + diff --git a/sim/testsuite/sim/m32r/ld.cgs b/sim/testsuite/sim/m32r/ld.cgs new file mode 100644 index 00000000000..ad0b86ff6d5 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ld $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld +ld: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4 + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ld24.cgs b/sim/testsuite/sim/m32r/ld24.cgs new file mode 100644 index 00000000000..74b155518c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld24.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ld24 $dr,#$uimm24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld24 +ld24: + ld24 r4, #0x123456 + + test_h_gr r4, 0x123456 + + pass diff --git a/sim/testsuite/sim/m32r/ldb-d.cgs b/sim/testsuite/sim/m32r/ldb-d.cgs new file mode 100644 index 00000000000..4a1cebb1fc3 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for ldb $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb_d +ldb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @(#2, r4) + + test_h_gr r5, 0x56 ; big endian processor + + pass + +data_loc: + .word 0x12345678 diff --git a/sim/testsuite/sim/m32r/ldb.cgs b/sim/testsuite/sim/m32r/ldb.cgs new file mode 100644 index 00000000000..9b895450f08 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldb $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb +ldb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @r4 + + test_h_gr r5, 0x12 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ldh-d.cgs b/sim/testsuite/sim/m32r/ldh-d.cgs new file mode 100644 index 00000000000..0be0309b1ef --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh_d +ldh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @(#2, r4) + + test_h_gr r5, 0x5678 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ldh.cgs b/sim/testsuite/sim/m32r/ldh.cgs new file mode 100644 index 00000000000..3d8db953d3d --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ldh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh +ldh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @r4 + + test_h_gr r5, 0x1234 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + + pass diff --git a/sim/testsuite/sim/m32r/ldi16.cgs b/sim/testsuite/sim/m32r/ldi16.cgs new file mode 100644 index 00000000000..478df1c1b32 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi16.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi16 +ldi16: + ldi r4, #0x1234 + + test_h_gr r4, 0x1234 + + pass diff --git a/sim/testsuite/sim/m32r/ldi8.cgs b/sim/testsuite/sim/m32r/ldi8.cgs new file mode 100644 index 00000000000..081e7a86f35 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi8 +ldi8: + ldi r4, #0x78 + + test_h_gr r4, 0x78 + + pass diff --git a/sim/testsuite/sim/m32r/ldub-d.cgs b/sim/testsuite/sim/m32r/ldub-d.cgs new file mode 100644 index 00000000000..7661071b820 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub_d +ldub_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @(#2, r4) + + test_h_gr r5, 0xa0 ; big endian processor + + pass + +data_loc: + .word 0x8090a0b0 + diff --git a/sim/testsuite/sim/m32r/ldub.cgs b/sim/testsuite/sim/m32r/ldub.cgs new file mode 100644 index 00000000000..27913b51f59 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub +ldub: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @r4 + + test_h_gr r5, 0x80 ; big endian processor + + pass + +data_loc: + .word 0x800000f0 + diff --git a/sim/testsuite/sim/m32r/lduh-d.cgs b/sim/testsuite/sim/m32r/lduh-d.cgs new file mode 100644 index 00000000000..96e294f0ec8 --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for lduh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh_d +lduh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @(#2, r4) + + test_h_gr r5, 0xf000 ; big endian processor + + pass + +data_loc: + .word 0x8000f000 diff --git a/sim/testsuite/sim/m32r/lduh.cgs b/sim/testsuite/sim/m32r/lduh.cgs new file mode 100644 index 00000000000..a03bbee240d --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for lduh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh +lduh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @r4 + + test_h_gr r5, 0x8010 ; big endian processor + + pass + +data_loc: + .word 0x8010f020 + + pass diff --git a/sim/testsuite/sim/m32r/lock.cgs b/sim/testsuite/sim/m32r/lock.cgs new file mode 100644 index 00000000000..631525ebbbf --- /dev/null +++ b/sim/testsuite/sim/m32r/lock.cgs @@ -0,0 +1,25 @@ +# m32r testcase for lock $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lock +lock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lock r5, @r4 + + test_h_gr r5, 0x12345678 + + ; There is no way to test the lock bit + + unlock r5, @r4 ; Unlock the processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/machi.cgs b/sim/testsuite/sim/m32r/machi.cgs new file mode 100644 index 00000000000..2e2ef00294c --- /dev/null +++ b/sim/testsuite/sim/m32r/machi.cgs @@ -0,0 +1,17 @@ +# m32r testcase for machi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global machi +machi: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + machi r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/maclo.cgs b/sim/testsuite/sim/m32r/maclo.cgs new file mode 100644 index 00000000000..5d035394dc4 --- /dev/null +++ b/sim/testsuite/sim/m32r/maclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for maclo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global maclo +maclo: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x1230001 + mvi_h_gr r5, 0x4560002 + maclo r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/macwhi.cgs b/sim/testsuite/sim/m32r/macwhi.cgs new file mode 100644 index 00000000000..9ee7a5b0bb9 --- /dev/null +++ b/sim/testsuite/sim/m32r/macwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwhi +macwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + macwhi r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/sim/m32r/macwlo.cgs b/sim/testsuite/sim/m32r/macwlo.cgs new file mode 100644 index 00000000000..a7ce4edac5c --- /dev/null +++ b/sim/testsuite/sim/m32r/macwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwlo +macwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + macwlo r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/sim/m32r/misc.exp b/sim/testsuite/sim/m32r/misc.exp new file mode 100644 index 00000000000..6ed5638ab29 --- /dev/null +++ b/sim/testsuite/sim/m32r/misc.exp @@ -0,0 +1,21 @@ +# Miscellaneous M32R simulator testcases + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/m32r/mul.cgs b/sim/testsuite/sim/m32r/mul.cgs new file mode 100644 index 00000000000..c78f24b8117 --- /dev/null +++ b/sim/testsuite/sim/m32r/mul.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mul $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mul +mul: + mvi_h_gr r4, 3 + mvi_h_gr r5, 7 + + mul r5, r4 + + test_h_gr r5, 21 + + pass diff --git a/sim/testsuite/sim/m32r/mulhi.cgs b/sim/testsuite/sim/m32r/mulhi.cgs new file mode 100644 index 00000000000..77c103d6f36 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulhi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mulhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulhi +mulhi: + + mvi_h_gr r4, 0x40000 + mvi_h_gr r5, 0x50000 + mulhi r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mullo.cgs b/sim/testsuite/sim/m32r/mullo.cgs new file mode 100644 index 00000000000..11aadff3794 --- /dev/null +++ b/sim/testsuite/sim/m32r/mullo.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mullo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mullo +mullo: + + mvi_h_gr r4, 4 + mvi_h_gr r5, 5 + mullo r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mulwhi.cgs b/sim/testsuite/sim/m32r/mulwhi.cgs new file mode 100644 index 00000000000..eb18562d9e7 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwhi +mulwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + mulwhi r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/sim/m32r/mulwlo.cgs b/sim/testsuite/sim/m32r/mulwlo.cgs new file mode 100644 index 00000000000..d22c26827cd --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwlo +mulwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + mulwlo r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/sim/m32r/mv.cgs b/sim/testsuite/sim/m32r/mv.cgs new file mode 100644 index 00000000000..694569535b7 --- /dev/null +++ b/sim/testsuite/sim/m32r/mv.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mv +mv: + mvi_h_gr r4, 1 + mvi_h_gr r5, 0 + + mv r5, r4 + + test_h_gr r5, 1 + + pass diff --git a/sim/testsuite/sim/m32r/mvfachi.cgs b/sim/testsuite/sim/m32r/mvfachi.cgs new file mode 100644 index 00000000000..0222e1b9118 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfachi.cgs @@ -0,0 +1,22 @@ +# m32r testcase for mvfachi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfachi +mvfachi: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0x223344 + + mvi_h_accum0 0x99aabbcc, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0xffaabbcc + + pass diff --git a/sim/testsuite/sim/m32r/mvfaclo.cgs b/sim/testsuite/sim/m32r/mvfaclo.cgs new file mode 100644 index 00000000000..0a88d849aee --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvfaclo $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfaclo +mvfaclo: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfaclo r4 + + test_h_gr r4, 0x55667788 + + pass diff --git a/sim/testsuite/sim/m32r/mvfacmi.cgs b/sim/testsuite/sim/m32r/mvfacmi.cgs new file mode 100644 index 00000000000..580bcae9890 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfacmi.cgs @@ -0,0 +1,15 @@ +# m32r testcase for mvfacmi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfacmi +mvfacmi: + + mvi_h_accum0 0x12345678, 0x87654321 + mvfacmi r4 + test_h_gr r4, 0x56788765 + + pass diff --git a/sim/testsuite/sim/m32r/mvfc.cgs b/sim/testsuite/sim/m32r/mvfc.cgs new file mode 100644 index 00000000000..ca2470e1e2d --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfc.cgs @@ -0,0 +1,23 @@ +# m32r testcase for mvfc $dr,$scr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfc +mvfc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvfc r4, cr1 + + test_h_gr r4, 0 + + mvi_h_condbit 1 + + mvfc r4, cr1 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/sim/m32r/mvtachi.cgs b/sim/testsuite/sim/m32r/mvtachi.cgs new file mode 100644 index 00000000000..6d596169557 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtachi.cgs @@ -0,0 +1,20 @@ +# m32r testcase for mvtachi $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtachi +mvtachi: + mvi_h_accum0 0, 0 + + mvi_h_gr r4, 0x11223344 + mvtachi r4 + test_h_accum0 0x223344, 0x0 + + mvi_h_gr r4, 0x99aabbcc + mvtachi r4 + test_h_accum0 0xffaabbcc, 0x0 + + pass diff --git a/sim/testsuite/sim/m32r/mvtaclo.cgs b/sim/testsuite/sim/m32r/mvtaclo.cgs new file mode 100644 index 00000000000..baafd839acb --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvtaclo $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtaclo +mvtaclo: + mvi_h_accum0 0, 0 + mvi_h_gr r4, 0x11223344 + + mvtaclo r4 + + test_h_accum0 0, 0x11223344 + + pass diff --git a/sim/testsuite/sim/m32r/mvtc.cgs b/sim/testsuite/sim/m32r/mvtc.cgs new file mode 100644 index 00000000000..94780dfa11a --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtc.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mvtc $sr,$dcr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtc +mvtc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvtc r4, cr1 + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/neg.cgs b/sim/testsuite/sim/m32r/neg.cgs new file mode 100644 index 00000000000..6051efaf256 --- /dev/null +++ b/sim/testsuite/sim/m32r/neg.cgs @@ -0,0 +1,17 @@ +# m32r testcase for neg $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global neg +neg: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + neg r4, r5 + + test_h_gr r4, -2 + + pass diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs new file mode 100644 index 00000000000..05b44bc552d --- /dev/null +++ b/sim/testsuite/sim/m32r/nop.cgs @@ -0,0 +1,10 @@ +# m32r testcase for nop +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global nop +nop: + pass diff --git a/sim/testsuite/sim/m32r/not.cgs b/sim/testsuite/sim/m32r/not.cgs new file mode 100644 index 00000000000..e6ceb643ebf --- /dev/null +++ b/sim/testsuite/sim/m32r/not.cgs @@ -0,0 +1,17 @@ +# m32r testcase for not $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global not +not: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + not r4, r5 + + test_h_gr r4, 0xfffffffd + + pass diff --git a/sim/testsuite/sim/m32r/or.cgs b/sim/testsuite/sim/m32r/or.cgs new file mode 100644 index 00000000000..1b08bd0c2a7 --- /dev/null +++ b/sim/testsuite/sim/m32r/or.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or +or: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + or r4, r5 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/sim/m32r/or3.cgs b/sim/testsuite/sim/m32r/or3.cgs new file mode 100644 index 00000000000..dc76ada9333 --- /dev/null +++ b/sim/testsuite/sim/m32r/or3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or3 $dr,$sr,#$ulo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or3 +or3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + or3 r4, r5, #3 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/sim/m32r/rac.cgs b/sim/testsuite/sim/m32r/rac.cgs new file mode 100644 index 00000000000..35b9ae3cd91 --- /dev/null +++ b/sim/testsuite/sim/m32r/rac.cgs @@ -0,0 +1,23 @@ +# m32r testcase for rac +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac +rac: + + mvi_h_accum0 1, 0x4001 + rac + test_h_accum0 2, 0x10000 + + mvi_h_accum0 0x3fff, 0xffff4000 + rac + test_h_accum0 0x7fff, 0xffff0000 + + mvi_h_accum0 0xffff8000, 0 + rac + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rach.cgs b/sim/testsuite/sim/m32r/rach.cgs new file mode 100644 index 00000000000..c22469834f7 --- /dev/null +++ b/sim/testsuite/sim/m32r/rach.cgs @@ -0,0 +1,22 @@ +# m32r testcase for rach +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach +rach: + mvi_h_accum0 1, 0x40004001 + rach + test_h_accum0 3, 0 + + mvi_h_accum0 0x3fff, 0xc0000000 + rach + test_h_accum0 0x7fff, 0 + + mvi_h_accum0 0xffff8000, 0 + rach + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rem.cgs b/sim/testsuite/sim/m32r/rem.cgs new file mode 100644 index 00000000000..78c11cbcf90 --- /dev/null +++ b/sim/testsuite/sim/m32r/rem.cgs @@ -0,0 +1,17 @@ +# m32r testcase for rem $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rem +rem: + mvi_h_gr r4, 12345678 + mvi_h_gr r5, 7 + + rem r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/remu.cgs b/sim/testsuite/sim/m32r/remu.cgs new file mode 100644 index 00000000000..36336306b27 --- /dev/null +++ b/sim/testsuite/sim/m32r/remu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for remu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global remu +remu: + mvi_h_gr r4, 17 + mvi_h_gr r5, 7 + + remu r4, r5 + + test_h_gr r4, 3 + + mvi_h_gr r4, -17 + + remu r4, r5 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/sim/m32r/rte.cgs b/sim/testsuite/sim/m32r/rte.cgs new file mode 100644 index 00000000000..b389fe15431 --- /dev/null +++ b/sim/testsuite/sim/m32r/rte.cgs @@ -0,0 +1,87 @@ +# m32r testcase for rte +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rte +rte: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = ret1 + mvaddr_h_gr r4, ret1 + mvtc r4, bpc + + rte + fail + +ret1: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvfc r4, cr0 + test_h_gr r4, 0xc1 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = 0 + mvfc r4, bpc + test_h_gr r4, 0 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = ret2 + 2 + mvaddr_h_gr r4, ret2 + 2 + mvtc r4, bpc + + rte + fail + +ret2: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc100 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = 42 + mvfc r4, bpc + test_h_gr r4, 42 + + pass diff --git a/sim/testsuite/sim/m32r/seth.cgs b/sim/testsuite/sim/m32r/seth.cgs new file mode 100644 index 00000000000..aec3230a548 --- /dev/null +++ b/sim/testsuite/sim/m32r/seth.cgs @@ -0,0 +1,20 @@ +# m32r testcase for seth $dr,#$hi16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global seth +seth: + seth r4, #0x1234 + + ; do not use test_h_gr macro since this uses seth + + srli r4, #16 + ld24 r5, #0x1234 + beq r4, r5, ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/sll.cgs b/sim/testsuite/sim/m32r/sll.cgs new file mode 100644 index 00000000000..fa3cfed8861 --- /dev/null +++ b/sim/testsuite/sim/m32r/sll.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll +sll: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + sll r4, r5 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/sll3.cgs b/sim/testsuite/sim/m32r/sll3.cgs new file mode 100644 index 00000000000..ddd360cd111 --- /dev/null +++ b/sim/testsuite/sim/m32r/sll3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll3 +sll3: + mvi_h_gr r4, 1 + mvi_h_gr r5, 6 + sll3 r4, r5, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/slli.cgs b/sim/testsuite/sim/m32r/slli.cgs new file mode 100644 index 00000000000..eab77daa695 --- /dev/null +++ b/sim/testsuite/sim/m32r/slli.cgs @@ -0,0 +1,14 @@ +# m32r testcase for slli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global slli +slli: + mvi_h_gr r4, 6 + slli r4, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/sra.cgs b/sim/testsuite/sim/m32r/sra.cgs new file mode 100644 index 00000000000..11671ed8658 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra +sra: + + mvi_h_gr r4, 0xf0f0f0ff + mvi_h_gr r5, 4 + sra r4, r5 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/sra3.cgs b/sim/testsuite/sim/m32r/sra3.cgs new file mode 100644 index 00000000000..0dd387adf46 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra3 +sra3: + + mvi_h_gr r4, 0 + mvi_h_gr r5, 0xf0f0f0ff + sra3 r4, r5, #4 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/srai.cgs b/sim/testsuite/sim/m32r/srai.cgs new file mode 100644 index 00000000000..2a1569422a5 --- /dev/null +++ b/sim/testsuite/sim/m32r/srai.cgs @@ -0,0 +1,14 @@ +# m32r testcase for srai $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srai +srai: + mvi_h_gr r5, 0xf0f0f0ff + srai r5, #4 + test_h_gr r5, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/srl.cgs b/sim/testsuite/sim/m32r/srl.cgs new file mode 100644 index 00000000000..8838c2fbd48 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl +srl: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + srl r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/srl3.cgs b/sim/testsuite/sim/m32r/srl3.cgs new file mode 100644 index 00000000000..a1dc4840f63 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl3 +srl3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + srl3 r4, r5, #1 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/srli.cgs b/sim/testsuite/sim/m32r/srli.cgs new file mode 100644 index 00000000000..f358a768a7f --- /dev/null +++ b/sim/testsuite/sim/m32r/srli.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srli +srli: + mvi_h_gr r5, 6 + srli r5, #1 + test_h_gr r5, 3 + + + pass diff --git a/sim/testsuite/sim/m32r/st-d.cgs b/sim/testsuite/sim/m32r/st-d.cgs new file mode 100644 index 00000000000..e2668a05c04 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-d.cgs @@ -0,0 +1,26 @@ +# m32r testcase for st $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_d +st_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/sim/m32r/st-minus.cgs b/sim/testsuite/sim/m32r/st-minus.cgs new file mode 100644 index 00000000000..fc90351c389 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-minus.cgs @@ -0,0 +1,29 @@ +# m32r testcase for st $src1,@-$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_minus +st_minus: + mvaddr_h_gr r4, data_loc2 + mvi_h_gr r5, 1 + + st r5, @-r4 + + mvaddr_h_gr r5, data_loc + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/sim/m32r/st-plus.cgs b/sim/testsuite/sim/m32r/st-plus.cgs new file mode 100644 index 00000000000..7bb4dd16fe7 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for st $src1,@+$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_plus +st_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @+r4 + + mvaddr_h_gr r5, data_loc2 + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/st.cgs b/sim/testsuite/sim/m32r/st.cgs new file mode 100644 index 00000000000..9588b8c40c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/st.cgs @@ -0,0 +1,21 @@ +# m32r testcase for st $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st +st: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @r4 + + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/stb-d.cgs b/sim/testsuite/sim/m32r/stb-d.cgs new file mode 100644 index 00000000000..37c2d733d72 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for stb $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb_d +stb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/stb.cgs b/sim/testsuite/sim/m32r/stb.cgs new file mode 100644 index 00000000000..01283169023 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for stb $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb +stb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/sth-d.cgs b/sim/testsuite/sim/m32r/sth-d.cgs new file mode 100644 index 00000000000..11aaa6d76c1 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for sth $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth_d +sth_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/sth.cgs b/sim/testsuite/sim/m32r/sth.cgs new file mode 100644 index 00000000000..1a10fde1ce3 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth.cgs @@ -0,0 +1,21 @@ +# m32r testcase for sth $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth +sth: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/sub.cgs b/sim/testsuite/sim/m32r/sub.cgs new file mode 100644 index 00000000000..4d676e58083 --- /dev/null +++ b/sim/testsuite/sim/m32r/sub.cgs @@ -0,0 +1,18 @@ +# m32r testcase for sub $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sub +sub: + + mvi_h_gr r4, 7 + mvi_h_gr r5, 3 + + sub r4, r5 + + test_h_gr r4, 4 + + pass diff --git a/sim/testsuite/sim/m32r/subv.cgs b/sim/testsuite/sim/m32r/subv.cgs new file mode 100644 index 00000000000..9474766e55b --- /dev/null +++ b/sim/testsuite/sim/m32r/subv.cgs @@ -0,0 +1,20 @@ +# m32r testcase for subv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subv +subv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 3 + + subv r4, r5 + + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/subx.cgs b/sim/testsuite/sim/m32r/subx.cgs new file mode 100644 index 00000000000..e890fcfabd7 --- /dev/null +++ b/sim/testsuite/sim/m32r/subx.cgs @@ -0,0 +1,26 @@ +# m32r testcase for subx $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subx +subx: + mvi_h_condbit 1 + mvi_h_gr r4, 6 + mvi_h_gr r5, 4 + subx r4, r5 + bc not_ok + test_h_gr r4, 1 + + mvi_h_condbit 1 + mvi_h_gr r4, 4 + mvi_h_gr r5, 4 + subx r4, r5 + bnc not_ok + test_h_gr r4, 0xffffffff + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/testutils.inc b/sim/testsuite/sim/m32r/testutils.inc new file mode 100644 index 00000000000..1d8822ae098 --- /dev/null +++ b/sim/testsuite/sim/m32r/testutils.inc @@ -0,0 +1,95 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + .endm + + .macro exit rc + ldi8 r1, \rc + ldi8 r0, #1 + trap #0 + .endm + + .macro pass + ldi8 r3, 5 + ld24 r2, passmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 0 + .endm + + .macro fail + ldi8 r3, 5 + ld24 r2, failmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 1 + .endm + + .macro mvi_h_gr reg, val + .if (\val >= -128) && (\val <= 127) + ldi8 \reg, \val + .else + seth \reg, high(\val) + or3 \reg, \reg, low(\val) + .endif + .endm + + .macro mvaddr_h_gr reg, addr + seth \reg, high(\addr) + or3 \reg, \reg, low(\addr) + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + beq \reg, r0, test_gr\@ + fail +test_gr\@: + .endm + + .macro mvi_h_condbit val + ldi8 r0, 0 + ldi8 r1, 1 + .if \val + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_condbit val + .if \val + bc test_c1\@ + fail +test_c1\@: + .else + bnc test_c0\@ + fail +test_c0\@: + .endif + .endm + + .macro mvi_h_accum0 hi, lo + mvi_h_gr r0, \hi + mvtachi r0 + mvi_h_gr r0, \lo + mvtaclo r0 + .endm + + .macro test_h_accum0 hi, lo + mvfachi r1 + test_h_gr r1, \hi + mvfaclo r1 + test_h_gr r1, \lo + .endm + diff --git a/sim/testsuite/sim/m32r/trap.cgs b/sim/testsuite/sim/m32r/trap.cgs new file mode 100644 index 00000000000..59e136a0173 --- /dev/null +++ b/sim/testsuite/sim/m32r/trap.cgs @@ -0,0 +1,109 @@ +# m32r testcase for trap #$uimm4 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global trap +trap: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bpc + + ; Copy trap2_handler to trap area of memory. + ld24 r0,#0x48 ; address of trap 2 handler + ld24 r1,#trap2_handler + ld r2,@r1 + st r2,@r0 + ; Set up return address. + ld24 r5,#trap2_ret1 + +trap_insn1: + trap #2 + fail + +trap2_ret1: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn1 + 4 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bpc + + ; Set up return address. + ld24 r5,#trap2_ret2 + +trap_insn2: + trap #2 + fail + +trap2_ret2: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc180 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn2 + 4 + + pass + + .data + +; Don't use rte as it will undo the effects of trap we're testing. + + .p2align 2 +trap2_handler: + jmp r5 + nop diff --git a/sim/testsuite/sim/m32r/unlock.cgs b/sim/testsuite/sim/m32r/unlock.cgs new file mode 100644 index 00000000000..1a51b7ae4cf --- /dev/null +++ b/sim/testsuite/sim/m32r/unlock.cgs @@ -0,0 +1,30 @@ +# m32r testcase for unlock $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global unlock +unlock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + lock r5, @r4 + + mvi_h_gr r5, 2 + unlock r5, @r4 + + ld r6, @r4 + test_h_gr r6, 2 + + mvi_h_gr r5, 0 + unlock r5, @r4 ; This should be a nop since the processor should be unlocked. + + ld r6, @r4 + test_h_gr r6, 2 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/uread16.ms b/sim/testsuite/sim/m32r/uread16.ms new file mode 100644 index 00000000000..550e99a2dfc --- /dev/null +++ b/sim/testsuite/sim/m32r/uread16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ldh r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/sim/m32r/uread32.ms b/sim/testsuite/sim/m32r/uread32.ms new file mode 100644 index 00000000000..935c71624e4 --- /dev/null +++ b/sim/testsuite/sim/m32r/uread32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ld r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/sim/m32r/uwrite16.ms b/sim/testsuite/sim/m32r/uwrite16.ms new file mode 100644 index 00000000000..11bfd6ee2a9 --- /dev/null +++ b/sim/testsuite/sim/m32r/uwrite16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + sth r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/sim/m32r/uwrite32.ms b/sim/testsuite/sim/m32r/uwrite32.ms new file mode 100644 index 00000000000..495a123b60e --- /dev/null +++ b/sim/testsuite/sim/m32r/uwrite32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + st r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/sim/m32r/xor.cgs b/sim/testsuite/sim/m32r/xor.cgs new file mode 100644 index 00000000000..254da798167 --- /dev/null +++ b/sim/testsuite/sim/m32r/xor.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor +xor: + + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + xor r4, r5 + test_h_gr r4, 5 + + pass diff --git a/sim/testsuite/sim/m32r/xor3.cgs b/sim/testsuite/sim/m32r/xor3.cgs new file mode 100644 index 00000000000..eee7269f934 --- /dev/null +++ b/sim/testsuite/sim/m32r/xor3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor3 +xor3: + + mvi_h_gr r5, 0 + mvi_h_gr r4, 3 + xor3 r5, r4, #6 + test_h_gr r5, 5 + + pass |