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| author | M R Swami Reddy <MR.Swami.Reddy@nsc.com> | 2008-05-05 10:25:20 +0000 |
|---|---|---|
| committer | M R Swami Reddy <MR.Swami.Reddy@nsc.com> | 2008-05-05 10:25:20 +0000 |
| commit | f17c372c0002aea6ed33212b5eb1192ab9388b41 (patch) | |
| tree | 2adfd3d1d5e9ebbcfad6ecd1e226d49bb93b365c /sim | |
| parent | f9981127db2e8a657248b1d74cb22f3871e5a7b1 (diff) | |
| download | gdb-f17c372c0002aea6ed33212b5eb1192ab9388b41.tar.gz | |
Added 3 miscellaneous testcases like read32.ms uread16.ms hw-trap.ms.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/testsuite/sim/cr16/hw-trap.ms | 10 | ||||
| -rw-r--r-- | sim/testsuite/sim/cr16/uread16.ms | 17 | ||||
| -rw-r--r-- | sim/testsuite/sim/cr16/uread32.ms | 17 |
3 files changed, 44 insertions, 0 deletions
diff --git a/sim/testsuite/sim/cr16/hw-trap.ms b/sim/testsuite/sim/cr16/hw-trap.ms new file mode 100644 index 00000000000..8c8c185829c --- /dev/null +++ b/sim/testsuite/sim/cr16/hw-trap.ms @@ -0,0 +1,10 @@ +# mach(): cr16 + + .include "testutils.inc" + + start + +# perform trap + movw $0,r2 + movw $0x410,r0 + pass # the pass macro use the trap 8 diff --git a/sim/testsuite/sim/cr16/uread16.ms b/sim/testsuite/sim/cr16/uread16.ms new file mode 100644 index 00000000000..54253b462e9 --- /dev/null +++ b/sim/testsuite/sim/cr16/uread16.ms @@ -0,0 +1,17 @@ +# mach: cr16 + + .include "testutils.inc" + + start + + .global read16 +read16: + loadw foo,r1 + cmpw $42, r1 + beq ok + fail +ok: + pass + +foo: + .word 42 diff --git a/sim/testsuite/sim/cr16/uread32.ms b/sim/testsuite/sim/cr16/uread32.ms new file mode 100644 index 00000000000..c2181e5c2ae --- /dev/null +++ b/sim/testsuite/sim/cr16/uread32.ms @@ -0,0 +1,17 @@ +# mach: cr16 + + .include "testutils.inc" + + start + + .global read32 +read32: + loadd foo, (r1,r0) + cmpd $0x12345678, (r1,r0) + beq ok + fail +ok: + pass + +foo: + .long 0x12345678 |