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authorAlexandre Oliva <aoliva@redhat.com>2000-06-22 20:03:32 +0000
committerAlexandre Oliva <aoliva@redhat.com>2000-06-22 20:03:32 +0000
commit34f777747ffe6c77f031cac6e6c26010e2778b97 (patch)
tree85eda7901459f54c28542a32155a46044cb7b626 /sim
parent4e16ec15dcae4cc9d54bc4b578c0317f5239d649 (diff)
downloadgdb-34f777747ffe6c77f031cac6e6c26010e2778b97.tar.gz
* armemu.c (MultiplyAdd64): Fix computation of flag N.
Diffstat (limited to 'sim')
-rw-r--r--sim/arm/ChangeLog4
-rw-r--r--sim/arm/armemu.c7
2 files changed, 7 insertions, 4 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index a2329be7593..4780f0a2a6e 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,7 @@
+2000-06-22 Alexandre Oliva <aoliva@cygnus.com>
+
+ * armemu.c (MultiplyAdd64): Fix computation of flag N.
+
2000-06-20 Alexandre Oliva <aoliva@cygnus.com>
* armemu.h (NEGBRANCH): Do not overwrite the two most significant
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index acbcb752959..426617d6bb3 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -3871,10 +3871,9 @@ MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
if (scc)
{
- if ((RdHi == 0) && (RdLo == 0))
- ARMul_NegZero (state, RdHi); /* zero value */
- else
- ARMul_NegZero (state, scc); /* non-zero value */
+ /* Ensure that both RdHi and RdLo are used to compute Z, but
+ don't let RdLo's sign bit make it to N. */
+ ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
}
return scount + 1; /* extra cycle for addition */