diff options
author | Alexandre Oliva <aoliva@redhat.com> | 2000-05-18 22:56:28 +0000 |
---|---|---|
committer | Alexandre Oliva <aoliva@redhat.com> | 2000-05-18 22:56:28 +0000 |
commit | 976eb2cafa455203d507e5bbda8d6874236e12ec (patch) | |
tree | d8994018e1bd57521acb8d37712f2a5f09ddc491 /sim | |
parent | 88a2d75f0fecddfce065483e186baea1d217f4c7 (diff) | |
download | gdb-976eb2cafa455203d507e5bbda8d6874236e12ec.tar.gz |
* mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,
genericXor, genericBtst): Use `unsigned32'.
* op_utils.c: Likewise.
* mn10300.igen, am33.igen: Use `unsigned32', `signed32',
`unsigned64' or `signed64' where type width is relevant.
Diffstat (limited to 'sim')
-rw-r--r-- | sim/mn10300/ChangeLog | 8 | ||||
-rw-r--r-- | sim/mn10300/am33.igen | 208 | ||||
-rw-r--r-- | sim/mn10300/mn10300.igen | 94 | ||||
-rw-r--r-- | sim/mn10300/mn10300_sim.h | 12 | ||||
-rw-r--r-- | sim/mn10300/op_utils.c | 20 |
5 files changed, 175 insertions, 167 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index f18c31fbfed..550c550d3ad 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,11 @@ +2000-05-18 Alexandre Oliva <aoliva@cygnus.com> + + * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr, + genericXor, genericBtst): Use `unsigned32'. + * op_utils.c: Likewise. + * mn10300.igen, am33.igen: Use `unsigned32', `signed32', + `unsigned64' or `signed64' where type width is relevant. + 2000-04-25 Alexandre Oliva <aoliva@cygnus.com> * am33.igen (inc4 Rn): Use genericAdd so as to modify flags. diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen index 8465c10f1d0..86ec8159c0e 100644 --- a/sim/mn10300/am33.igen +++ b/sim/mn10300/am33.igen @@ -111,7 +111,7 @@ "syscall" *am33 { - unsigned int sp, next_pc; + unsigned32 sp, next_pc; PC = cia; sp = State.regs[REG_SP]; @@ -192,8 +192,8 @@ "movm" *am33 { - unsigned long usp = State.regs[REG_USP]; - unsigned long mask; + unsigned32 usp = State.regs[REG_USP]; + unsigned32 mask; PC = cia; mask = REGS; @@ -283,8 +283,8 @@ "movm" *am33 { - unsigned long usp = State.regs[REG_USP]; - unsigned long mask; + unsigned32 usp = State.regs[REG_USP]; + unsigned32 mask; if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) { @@ -499,7 +499,7 @@ { int srcreg, dstreg; int z, c, n, v; - unsigned long reg1, reg2, sum; + unsigned32 reg1, reg2, sum; PC = cia; srcreg = translate_rreg (SD_, RM2); @@ -541,7 +541,7 @@ { int srcreg, dstreg; int z, c, n, v; - unsigned long reg1, reg2, difference; + unsigned32 reg1, reg2, difference; PC = cia; srcreg = translate_rreg (SD_, RM2); @@ -710,7 +710,7 @@ *am33 { int srcreg, dstreg; - long temp; + signed32 temp; int c, z, n; PC = cia; @@ -792,7 +792,7 @@ { int dstreg; int c, n, z; - unsigned long value; + unsigned32 value; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -816,7 +816,7 @@ { int dstreg; int c, n, z; - unsigned long value; + unsigned32 value; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -839,7 +839,7 @@ *am33 { int srcreg, dstreg; - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -862,7 +862,7 @@ *am33 { int srcreg, dstreg; - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -885,7 +885,7 @@ *am33 { int srcreg, dstreg; - long long temp; + signed64 temp; int n, z; PC = cia; @@ -910,7 +910,7 @@ *am33 { int srcreg, dstreg; - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -1143,7 +1143,7 @@ *am33 { int srcreg1, srcreg2; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -1171,7 +1171,7 @@ *am33 { int srcreg1, srcreg2; - unsigned long long temp, sum; + unsigned64 temp, sum; int c, v; PC = cia; @@ -1199,7 +1199,7 @@ *am33 { int srcreg1, srcreg2; - long temp, sum; + signed32 temp, sum; int v; PC = cia; @@ -1222,7 +1222,7 @@ *am33 { int srcreg1, srcreg2; - long long temp, sum; + signed64 temp, sum; int v; PC = cia; @@ -1245,7 +1245,7 @@ *am33 { int srcreg1, srcreg2; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -1273,7 +1273,7 @@ *am33 { int srcreg1, srcreg2; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -1301,7 +1301,7 @@ *am33 { int srcreg1, srcreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; int v; PC = cia; @@ -1326,7 +1326,7 @@ *am33 { int srcreg1, srcreg2; - unsigned long temp, temp2, sum; + unsigned32 temp, temp2, sum; int v; PC = cia; @@ -1351,7 +1351,7 @@ *am33 { int srcreg, dstreg; - long temp; + signed32 temp; PC = cia; srcreg = translate_rreg (SD_, RM2); @@ -1371,7 +1371,7 @@ *am33 { int srcreg, dstreg; - unsigned long temp; + unsigned32 temp; PC = cia; srcreg = translate_rreg (SD_, RM2); @@ -1429,7 +1429,7 @@ /* 32bit saturation. */ if (State.regs[srcreg] == 0x20) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -1445,7 +1445,7 @@ /* 16bit saturation */ else if (State.regs[srcreg] == 0x10) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -1461,7 +1461,7 @@ /* 8 bit saturation */ else if (State.regs[srcreg] == 0x8) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -1477,7 +1477,7 @@ /* 9 bit saturation */ else if (State.regs[srcreg] == 0x9) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -1493,7 +1493,7 @@ /* 9 bit saturation */ else if (State.regs[srcreg] == 0x30) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -1639,7 +1639,7 @@ { int dstreg, imm; int z, c, n, v; - unsigned long reg1, reg2, sum; + unsigned32 reg1, reg2, sum; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -1680,7 +1680,7 @@ { int imm, dstreg; int z, c, n, v; - unsigned long reg1, reg2, difference; + unsigned32 reg1, reg2, difference; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -1786,7 +1786,7 @@ *am33 { int dstreg; - long temp; + signed32 temp; int c, z, n; PC = cia; @@ -1845,7 +1845,7 @@ *am33 { int dstreg; - unsigned long long temp; + unsigned64 temp; int z, n; PC = cia; @@ -1867,7 +1867,7 @@ *am33 { int dstreg; - unsigned long long temp; + unsigned64 temp; int z, n; PC = cia; @@ -2109,7 +2109,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -2136,7 +2136,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -2163,7 +2163,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -2190,7 +2190,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -2217,7 +2217,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -2244,7 +2244,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -2281,7 +2281,7 @@ /* 32bit saturation. */ if (IMM8 == 0x20) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -2297,7 +2297,7 @@ /* 16bit saturation */ else if (IMM8 == 0x10) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -2313,7 +2313,7 @@ /* 8 bit saturation */ else if (IMM8 == 0x8) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -2329,7 +2329,7 @@ /* 9 bit saturation */ else if (IMM8 == 0x9) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -2345,7 +2345,7 @@ /* 9 bit saturation */ else if (IMM8 == 0x30) { - long long tmp; + signed64 tmp; tmp = State.regs[REG_MCRH]; tmp <<= 32; @@ -2367,7 +2367,7 @@ *am33 { int z, c, n, v; - unsigned long sum, source1, source2; + unsigned32 sum, source1, source2; int srcreg1, srcreg2, dstreg; PC = cia; @@ -2397,7 +2397,7 @@ *am33 { int z, c, n, v; - unsigned long sum, source1, source2; + unsigned32 sum, source1, source2; int srcreg1, srcreg2, dstreg; PC = cia; @@ -2427,7 +2427,7 @@ *am33 { int z, c, n, v; - unsigned long difference, source1, source2; + unsigned32 difference, source1, source2; int srcreg1, srcreg2, dstreg; PC = cia; @@ -2457,7 +2457,7 @@ *am33 { int z, c, n, v; - unsigned long difference, source1, source2; + unsigned32 difference, source1, source2; int srcreg1, srcreg2, dstreg; PC = cia; @@ -2553,7 +2553,7 @@ *am33 { int z, c, n; - long temp; + signed32 temp; int srcreg1, srcreg2, dstreg; PC = cia; @@ -2624,7 +2624,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - signed long long temp; + signed64 temp; int n, z; PC = cia; @@ -2651,7 +2651,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - signed long long temp; + signed64 temp; int n, z; PC = cia; @@ -2834,8 +2834,8 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - signed long long temp; - unsigned long sum; + signed64 temp; + unsigned32 sum; int c, v; PC = cia; @@ -2870,8 +2870,8 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - signed long long temp; - unsigned long sum; + signed64 temp; + unsigned32 sum; int c, v; PC = cia; @@ -2906,7 +2906,7 @@ *am33 { int srcreg1, srcreg2, dstreg; - long temp, sum; + signed32 temp, sum; int v; PC = cia; @@ -2934,7 +2934,7 @@ *am33 { int srcreg1, srcreg2, dstreg; - long temp, sum; + signed32 temp, sum; int v; PC = cia; @@ -2962,7 +2962,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long long temp, sum; + signed64 temp, sum; int v; PC = cia; @@ -2992,7 +2992,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long long temp, sum; + signed64 temp, sum; int v; PC = cia; @@ -3022,7 +3022,7 @@ *am33 { int srcreg1, srcreg2, dstreg; - long temp, temp2, sum; + signed32 temp, temp2, sum; int v; PC = cia; @@ -3052,7 +3052,7 @@ *am33 { int srcreg1, srcreg2, dstreg; - long temp, temp2, sum; + signed32 temp, temp2, sum; int v; PC = cia; @@ -3082,7 +3082,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - signed long long temp; + signed64 temp; PC = cia; srcreg1 = translate_rreg (SD_, RM2); @@ -3104,7 +3104,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - signed long long temp; + signed64 temp; PC = cia; srcreg1 = translate_rreg (SD_, RM2); @@ -3227,7 +3227,7 @@ *am33 { int dstreg, z, n, c, v; - unsigned long sum, imm, reg2; + unsigned32 sum, imm, reg2; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -3266,7 +3266,7 @@ *am33 { int dstreg, z, n, c, v; - unsigned long difference, imm, reg2; + unsigned32 difference, imm, reg2; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -3372,7 +3372,7 @@ *am33 { int dstreg; - long temp; + signed32 temp; int c, z, n; PC = cia; @@ -3432,7 +3432,7 @@ *am33 { int dstreg; - unsigned long long temp; + unsigned64 temp; int z, n; PC = cia; @@ -3454,7 +3454,7 @@ *am33 { int dstreg; - unsigned long long temp; + unsigned64 temp; int z, n; PC = cia; @@ -3711,7 +3711,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -3738,7 +3738,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -3765,7 +3765,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -3792,7 +3792,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -3819,7 +3819,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -3846,7 +3846,7 @@ *am33 { int srcreg; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -3984,7 +3984,7 @@ *am33 { int dstreg; - unsigned int imm, reg2, sum; + unsigned32 imm, reg2, sum; int z, n, c, v; PC = cia; @@ -4024,7 +4024,7 @@ *am33 { int dstreg; - unsigned int imm, reg2, difference; + unsigned32 imm, reg2, difference; int z, n, c, v; PC = cia; @@ -4131,7 +4131,7 @@ *am33 { int dstreg; - long temp; + signed32 temp; int c, z, n; PC = cia; @@ -4190,7 +4190,7 @@ *am33 { int dstreg; - unsigned long long temp; + unsigned64 temp; int z, n; PC = cia; @@ -4212,7 +4212,7 @@ *am33 { int dstreg; - unsigned long long temp; + unsigned64 temp; int z, n; PC = cia; @@ -4467,7 +4467,7 @@ *am33 { int srcreg, imm; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -4495,7 +4495,7 @@ *am33 { int srcreg, imm; - long long temp, sum; + signed64 temp, sum; int c, v; PC = cia; @@ -4523,7 +4523,7 @@ *am33 { int srcreg, imm; - long temp, sum; + signed32 temp, sum; int v; PC = cia; @@ -4546,7 +4546,7 @@ *am33 { int srcreg, imm; - long temp, sum; + signed32 temp, sum; int v; PC = cia; @@ -4569,7 +4569,7 @@ *am33 { int srcreg, imm; - long temp, sum; + signed32 temp, sum; int v; PC = cia; @@ -4592,7 +4592,7 @@ *am33 { int srcreg, imm; - long temp, sum; + signed32 temp, sum; int v; PC = cia; @@ -4615,7 +4615,7 @@ *am33 { int srcreg, imm; - long temp, temp2, sum; + signed32 temp, temp2, sum; int v; PC = cia; @@ -4640,7 +4640,7 @@ *am33 { int srcreg, imm; - long temp, temp2, sum; + signed32 temp, temp2, sum; int v; PC = cia; @@ -4665,7 +4665,7 @@ *am33 { int imm, dstreg; - long temp; + signed32 temp; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -4685,7 +4685,7 @@ *am33 { int imm, dstreg; - long temp; + signed32 temp; PC = cia; dstreg = translate_rreg (SD_, RN0); @@ -6988,7 +6988,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7012,7 +7012,7 @@ *am33 { int srcreg1, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7035,7 +7035,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7059,7 +7059,7 @@ *am33 { int srcreg1, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7082,7 +7082,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7106,7 +7106,7 @@ *am33 { int srcreg1, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7129,7 +7129,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7153,7 +7153,7 @@ *am33 { int srcreg1, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7176,7 +7176,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7202,7 +7202,7 @@ *am33 { int srcreg1, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7227,7 +7227,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7251,7 +7251,7 @@ *am33 { int srcreg1, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7275,7 +7275,7 @@ *am33 { int srcreg1, srcreg2, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); @@ -7299,7 +7299,7 @@ *am33 { int srcreg1, dstreg1, dstreg2; - long temp, temp2, sum; + signed32 temp, temp2, sum; PC = cia; srcreg1 = translate_rreg (SD_, RM1); diff --git a/sim/mn10300/mn10300.igen b/sim/mn10300/mn10300.igen index 2ffa9805ec5..60df8a65083 100644 --- a/sim/mn10300/mn10300.igen +++ b/sim/mn10300/mn10300.igen @@ -720,7 +720,7 @@ { /* OP_2C0000 (); */ - unsigned long value; + unsigned32 value; PC = cia; value = EXTEND16 (FETCH16(IMM16A, IMM16B)); @@ -737,7 +737,7 @@ { /* OP_FCCC0000 (); */ - unsigned long value; + unsigned32 value; PC = cia; value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); @@ -754,7 +754,7 @@ { /* OP_240000 (); */ - unsigned long value; + unsigned32 value; PC = cia; value = FETCH16(IMM16A, IMM16B); @@ -1618,7 +1618,7 @@ { /* OP_F8FE00 (); */ - unsigned long imm; + unsigned32 imm; /* Note: no PSW changes. */ PC = cia; @@ -1636,7 +1636,7 @@ { /* OP_FAFE0000 (); */ - unsigned long imm; + unsigned32 imm; /* Note: no PSW changes. */ PC = cia; @@ -1654,7 +1654,7 @@ { /* OP_FCFE0000 (); */ - unsigned long imm; + unsigned32 imm; /* Note: no PSW changes. */ PC = cia; @@ -1673,7 +1673,7 @@ { /* OP_F140 (); */ int z, c, n, v; - unsigned long reg1, reg2, sum; + unsigned32 reg1, reg2, sum; PC = cia; reg1 = State.regs[REG_D0 + DM1]; @@ -1786,7 +1786,7 @@ { /* OP_F180 (); */ int z, c, n, v; - unsigned long reg1, reg2, difference; + unsigned32 reg1, reg2, difference; PC = cia; reg1 = State.regs[REG_D0 + DM1]; @@ -1815,7 +1815,7 @@ { /* OP_F240 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -1839,7 +1839,7 @@ { /* OP_F250 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -1936,7 +1936,7 @@ { /* OP_40 (); */ - unsigned int imm; + unsigned32 imm; PC = cia; imm = 1; @@ -2428,7 +2428,7 @@ { /* OP_F080 (); */ - unsigned long temp; + unsigned32 temp; int z; PC = cia; @@ -2451,7 +2451,7 @@ { /* OP_FE000000 (); */ - unsigned long temp; + unsigned32 temp; int z; PC = cia; @@ -2474,7 +2474,7 @@ { /* OP_FAF00000 (); */ - unsigned long temp; + unsigned32 temp; int z; PC = cia; @@ -2496,7 +2496,7 @@ { /* OP_F090 (); */ - unsigned long temp; + unsigned32 temp; int z; PC = cia; @@ -2519,7 +2519,7 @@ { /* OP_FE010000 (); */ - unsigned long temp; + unsigned32 temp; int z; PC = cia; @@ -2542,7 +2542,7 @@ { /* OP_FAF40000 (); */ - unsigned long temp; + unsigned32 temp; int z; PC = cia; @@ -2564,7 +2564,7 @@ { /* OP_F2B0 (); */ - long temp; + signed32 temp; int z, n, c; PC = cia; @@ -2588,7 +2588,7 @@ { /* OP_F8C800 (); */ - long temp; + signed32 temp; int z, n, c; PC = cia; @@ -2716,7 +2716,7 @@ { /* OP_F284 (); */ - unsigned long value; + unsigned32 value; int c,n,z; PC = cia; @@ -2742,7 +2742,7 @@ { /* OP_F280 (); */ - unsigned long value; + unsigned32 value; int c,n,z; PC = cia; @@ -3291,7 +3291,7 @@ { /* OP_F0F0 (); */ - unsigned int next_pc, sp; + unsigned32 next_pc, sp; PC = cia; sp = State.regs[REG_SP]; @@ -3312,7 +3312,7 @@ { /* OP_FAFF0000 (); */ - unsigned int next_pc, sp; + unsigned32 next_pc, sp; PC = cia; sp = State.regs[REG_SP]; @@ -3333,7 +3333,7 @@ { /* OP_FCFF0000 (); */ - unsigned int next_pc, sp; + unsigned32 next_pc, sp; PC = cia; sp = State.regs[REG_SP]; @@ -3354,7 +3354,7 @@ { /* OP_F0FC (); */ - unsigned int sp; + unsigned32 sp; sp = State.regs[REG_SP]; State.regs[REG_PC] = load_word(sp); @@ -3371,7 +3371,7 @@ { /* OP_F0FD (); */ - unsigned int sp; + unsigned32 sp; sp = State.regs[REG_SP]; PSW = load_half(sp); @@ -3390,7 +3390,7 @@ { /* OP_F0FE (); */ - unsigned int sp, next_pc; + unsigned32 sp, next_pc; PC = cia; sp = State.regs[REG_SP]; @@ -3468,7 +3468,7 @@ { /* OP_F600 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3492,7 +3492,7 @@ { /* OP_F90000 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3516,7 +3516,7 @@ { /* OP_FB000000 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3540,7 +3540,7 @@ { /* OP_FD000000 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3564,7 +3564,7 @@ { /* OP_F610 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3588,7 +3588,7 @@ { /* OP_F91400 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3612,7 +3612,7 @@ { /* OP_FB140000 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3636,7 +3636,7 @@ { /* OP_FD140000 (); */ - unsigned long long temp; + unsigned64 temp; int n, z; PC = cia; @@ -3745,8 +3745,8 @@ { /* OP_CE00 (); */ - unsigned long sp = State.regs[REG_SP]; - unsigned long mask; + unsigned32 sp = State.regs[REG_SP]; + unsigned32 mask; PC = cia; mask = REGS; @@ -3841,8 +3841,8 @@ { /* OP_CF00 (); */ - unsigned long sp = State.regs[REG_SP]; - unsigned long mask; + unsigned32 sp = State.regs[REG_SP]; + unsigned32 mask; PC = cia; mask = REGS; @@ -3937,8 +3937,8 @@ { /* OP_CD000000 (); */ - unsigned int next_pc, sp; - unsigned long mask; + unsigned32 next_pc, sp; + unsigned32 mask; PC = cia; sp = State.regs[REG_SP]; @@ -4043,8 +4043,8 @@ { /* OP_DD000000 (); */ - unsigned int next_pc, sp; - unsigned long mask; + unsigned32 next_pc, sp; + unsigned32 mask; PC = cia; sp = State.regs[REG_SP]; @@ -4149,8 +4149,8 @@ { /* OP_DF0000 (); */ - unsigned int sp, offset; - unsigned long mask; + unsigned32 sp, offset; + unsigned32 mask; PC = cia; State.regs[REG_SP] += IMM8; @@ -4251,8 +4251,8 @@ { /* OP_DE0000 (); */ - unsigned int sp, offset; - unsigned long mask; + unsigned32 sp, offset; + unsigned32 mask; PC = cia; State.regs[REG_SP] += IMM8; diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h index 0e419432ce8..da6c25915be 100644 --- a/sim/mn10300/mn10300_sim.h +++ b/sim/mn10300/mn10300_sim.h @@ -366,12 +366,12 @@ void put_byte PARAMS ((uint8 *, uint8)); extern uint8 *map PARAMS ((SIM_ADDR addr)); -INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned long source, unsigned long destReg)); -INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned long source, unsigned long destReg)); -INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd)); -INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned long source, unsigned long destReg)); -INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned long source, unsigned long destReg)); -INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd)); +INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd)); +INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd)); INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb, struct cb_syscall *sc, unsigned long taddr, diff --git a/sim/mn10300/op_utils.c b/sim/mn10300/op_utils.c index 0a966ed7355..b46210f6b40 100644 --- a/sim/mn10300/op_utils.c +++ b/sim/mn10300/op_utils.c @@ -36,10 +36,10 @@ INLINE_SIM_MAIN (void) -genericAdd(unsigned long source, unsigned long destReg) +genericAdd(unsigned32 source, unsigned32 destReg) { int z, c, n, v; - unsigned long dest, sum; + unsigned32 dest, sum; dest = State.regs[destReg]; sum = source + dest; @@ -60,10 +60,10 @@ genericAdd(unsigned long source, unsigned long destReg) INLINE_SIM_MAIN (void) -genericSub(unsigned long source, unsigned long destReg) +genericSub(unsigned32 source, unsigned32 destReg) { int z, c, n, v; - unsigned long dest, difference; + unsigned32 dest, difference; dest = State.regs[destReg]; difference = dest - source; @@ -81,10 +81,10 @@ genericSub(unsigned long source, unsigned long destReg) } INLINE_SIM_MAIN (void) -genericCmp(unsigned long leftOpnd, unsigned long rightOpnd) +genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd) { int z, c, n, v; - unsigned long value; + unsigned32 value; value = rightOpnd - leftOpnd; @@ -101,7 +101,7 @@ genericCmp(unsigned long leftOpnd, unsigned long rightOpnd) INLINE_SIM_MAIN (void) -genericOr(unsigned long source, unsigned long destReg) +genericOr(unsigned32 source, unsigned32 destReg) { int n, z; @@ -114,7 +114,7 @@ genericOr(unsigned long source, unsigned long destReg) INLINE_SIM_MAIN (void) -genericXor(unsigned long source, unsigned long destReg) +genericXor(unsigned32 source, unsigned32 destReg) { int n, z; @@ -127,9 +127,9 @@ genericXor(unsigned long source, unsigned long destReg) INLINE_SIM_MAIN (void) -genericBtst(unsigned long leftOpnd, unsigned long rightOpnd) +genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd) { - unsigned long temp; + unsigned32 temp; int z, n; temp = rightOpnd; |