import gdb-1999-12-06 snapshot

21 files changed, 1108 insertions, 85 deletions

diff --git a/sim/ChangeLog b/sim/ChangeLog
index eb1261fdffa..2dd4f3ab39a 100644
--- a/sim/ChangeLog
+++ b/sim/ChangeLog
@@ -1,3 +1,9 @@
+1999-11-18  Ben Elliston  <bje@cygnus.com>
+
+	* configure.in: Require autoconf 2.13 and remove obsolete
+	invocation of AC_C_CROSS.
+	* configure: Regenerate.
+
 1999-09-29  Doug Evans  <devans@casey.cygnus.com>
 
 	* configure.in: Configure the testsuite directory for thumb.
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index eb432557bd5..bdaf8af8c30 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,10 @@
+1999-11-22  Nick Clifton  <nickc@cygnus.com>
+
+	* armos.c (SWIread): Generate an error message if a huge read is
+	performed.
+	(SWIwrite): Generate an error message if a huge write is
+	performed.
+
 1999-10-27  Nick Clifton  <nickc@cygnus.com>
 
 	* thumbemu.c (ARMul_ThumbDecode): Accept 0xbebe as a thumb
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index fa994e06c2e..b9b669df076 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -878,7 +878,6 @@ mainswitch:
              break ;
 
           case 0x10 : /* TST reg and MRS CPSR and SWP word */
-	 
 #ifdef MODET
              if (BITS(4,11) == 0xB) {
                /* STRH register offset, no write-back, down, pre indexed */
@@ -2410,13 +2409,13 @@ mainswitch:
 *                        Co-Processor Data Transfers                        *
 \***************************************************************************/
 
-          case 0xc0 :
-          case 0xc4 : /* Store , No WriteBack , Post Dec */
+          case 0xc4 :
+          case 0xc0 : /* Store , No WriteBack , Post Dec */
              ARMul_STC(state,instr,LHS) ;
              break ;
 
-          case 0xc1 :
-          case 0xc5 : /* Load , No WriteBack , Post Dec */
+          case 0xc5 :
+          case 0xc1 : /* Load , No WriteBack , Post Dec */
              ARMul_LDC(state,instr,LHS) ;
              break ;
 
@@ -2511,7 +2510,8 @@ mainswitch:
 *            Co-Processor Register Transfers (MCR) and Data Ops             *
 \***************************************************************************/
 
-          case 0xe0 : case 0xe2 : case 0xe4 : case 0xe6 :
+       case 0xe2 :
+          case 0xe0 : case 0xe4 : case 0xe6 :
           case 0xe8 : case 0xea : case 0xec : case 0xee :
              if (BIT(4)) { /* MCR */
                 if (DESTReg == 15) {
diff --git a/sim/arm/armos.c b/sim/arm/armos.c
index 9f0f1fee49b..be4cbaf1c1d 100644
--- a/sim/arm/armos.c
+++ b/sim/arm/armos.c
@@ -308,6 +308,12 @@ SWIread (ARMul_State *state, ARMword f, ARMword ptr, ARMword len)
   int i;
   char *local = malloc (len);
 
+  if (local == NULL)
+    {
+      fprintf (stderr, "sim: Unable to read 0x%x bytes - out of memory\n", len);
+      return;
+    }
+  
   res = read (f, local, len);
   if (res > 0)
     for (i = 0; i < res; i++) 
@@ -325,10 +331,15 @@ SWIwrite (ARMul_State *state, ARMword f, ARMword ptr, ARMword len)
   int i;
   char *local = malloc (len);
 
-  for (i = 0; i < len; i++) 
+  if (local == NULL)
     {
-      local[i] = ARMul_ReadByte (state, ptr + i);
+      fprintf (stderr, "sim: Unable to write 0x%x bytes - out of memory\n", len);
+      return;
     }
+  
+  for (i = 0; i < len; i++) 
+    local[i] = ARMul_ReadByte (state, ptr + i);
+
   res = write (f, local, len);
   state->Reg[0] = res == -1 ? -1 : len - res;
   free (local);
diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog
index c2d1c8c3c9b..1aa9ecc42c4 100644
--- a/sim/common/ChangeLog
+++ b/sim/common/ChangeLog
@@ -1,3 +1,34 @@
+1999-12-01  Dave Brolley  <brolley@cygnus.com>
+
+	* cgen-accfp.c (subsf): Check status code.
+	(mulsf): Ditto.
+	(negsf): Ditto.
+	(abssf): Ditto.
+	(sqrtsf): Ditto.
+	(invsf): Ditto.
+	(minsf): Ditto.
+	(maxsf): Ditto.
+	(subdf): Ditto.
+	(muldf): Ditto.
+	(divdf): Ditto.
+	(negdf): Ditto.
+	(absdf): Ditto.
+	(sqrtdf): Ditto.
+	(invdf): Ditto.
+	(mindf): Ditto.
+	(maxdf): Ditto.
+
+1999-11-26  Dave Brolley  <brolley@cygnus.com>
+
+	* cgen-par.h (fn_df_write): Mode of data is DF.
+	(sim_queue_fn_df_write): Mode of data is DF.
+	* cgen-par.c (sim_queue_fn_df_write): Mode of data is DF.
+
+1999-11-22  Dave Brolley  <brolley@cygnus.com>
+
+	* cgen-trace.c (SIZE_TRACE_BUF): Inxrease size of trace buffer.
+	* cgen-par.h (CGEN_WRITE_QUEUE_SIZE): Increase size of queue.
+
 1999-11-04  Dave Brolley  <brolley@cygnus.com>
 
 	* cgen-par.h (cgen_write_queue_kind): Add CGEN_FN_XI_WRITE and
diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
index 0ef61fd4185..e9175225a87 100644
--- a/sim/common/cgen-accfp.c
+++ b/sim/common/cgen-accfp.c
@@ -42,10 +42,13 @@ subsf (CGEN_FPU* fpu, SF x, SF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
   sim_fpu_32to (&op2, y);
-  sim_fpu_sub (&ans, &op1, &op2);
+  status = sim_fpu_sub (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -58,10 +61,13 @@ mulsf (CGEN_FPU* fpu, SF x, SF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
   sim_fpu_32to (&op2, y);
-  sim_fpu_mul (&ans, &op1, &op2);
+  status = sim_fpu_mul (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -92,9 +98,12 @@ negsf (CGEN_FPU* fpu, SF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
-  sim_fpu_neg (&ans, &op1);
+  status = sim_fpu_neg (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -106,9 +115,12 @@ abssf (CGEN_FPU* fpu, SF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
-  sim_fpu_abs (&ans, &op1);
+  status = sim_fpu_abs (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -120,9 +132,12 @@ sqrtsf (CGEN_FPU* fpu, SF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
-  sim_fpu_sqrt (&ans, &op1);
+  status = sim_fpu_sqrt (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -134,9 +149,12 @@ invsf (CGEN_FPU* fpu, SF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
-  sim_fpu_inv (&ans, &op1);
+  status = sim_fpu_inv (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -149,10 +167,13 @@ minsf (CGEN_FPU* fpu, SF x, SF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
   sim_fpu_32to (&op2, y);
-  sim_fpu_min (&ans, &op1, &op2);
+  status = sim_fpu_min (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -165,10 +186,13 @@ maxsf (CGEN_FPU* fpu, SF x, SF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned32 res;
+  sim_fpu_status status;
 
   sim_fpu_32to (&op1, x);
   sim_fpu_32to (&op2, y);
-  sim_fpu_max (&ans, &op1, &op2);
+  status = sim_fpu_max (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to32 (&res, &ans);
 
   return res;
@@ -354,10 +378,13 @@ subdf (CGEN_FPU* fpu, DF x, DF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
   sim_fpu_64to (&op2, y);
-  sim_fpu_sub (&ans, &op1, &op2);
+  status = sim_fpu_sub (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -370,10 +397,13 @@ muldf (CGEN_FPU* fpu, DF x, DF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
   sim_fpu_64to (&op2, y);
-  sim_fpu_mul (&ans, &op1, &op2);
+  status = sim_fpu_mul (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -386,10 +416,13 @@ divdf (CGEN_FPU* fpu, DF x, DF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
   sim_fpu_64to (&op2, y);
-  sim_fpu_div (&ans, &op1, &op2);
+  status = sim_fpu_div (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -401,9 +434,12 @@ negdf (CGEN_FPU* fpu, DF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
-  sim_fpu_neg (&ans, &op1);
+  status = sim_fpu_neg (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -415,9 +451,12 @@ absdf (CGEN_FPU* fpu, DF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
-  sim_fpu_abs (&ans, &op1);
+  status = sim_fpu_abs (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -429,9 +468,12 @@ sqrtdf (CGEN_FPU* fpu, DF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
-  sim_fpu_sqrt (&ans, &op1);
+  status = sim_fpu_sqrt (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -443,9 +485,12 @@ invdf (CGEN_FPU* fpu, DF x)
   sim_fpu op1;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
-  sim_fpu_inv (&ans, &op1);
+  status = sim_fpu_inv (&ans, &op1);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -458,10 +503,13 @@ mindf (CGEN_FPU* fpu, DF x, DF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
   sim_fpu_64to (&op2, y);
-  sim_fpu_min (&ans, &op1, &op2);
+  status = sim_fpu_min (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
@@ -474,10 +522,13 @@ maxdf (CGEN_FPU* fpu, DF x, DF y)
   sim_fpu op2;
   sim_fpu ans;
   unsigned64 res;
+  sim_fpu_status status;
 
   sim_fpu_64to (&op1, x);
   sim_fpu_64to (&op2, y);
-  sim_fpu_max (&ans, &op1, &op2);
+  status = sim_fpu_max (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
   sim_fpu_to64 (&res, &ans);
 
   return res;
diff --git a/sim/common/cgen-par.c b/sim/common/cgen-par.c
index fece2c9f11f..44cc50f005a 100644
--- a/sim/common/cgen-par.c
+++ b/sim/common/cgen-par.c
@@ -142,7 +142,7 @@ void sim_queue_fn_xi_write (
 
 void sim_queue_fn_df_write (
   SIM_CPU *cpu,
-  void (*write_function)(SIM_CPU *cpu, UINT, DI),
+  void (*write_function)(SIM_CPU *cpu, UINT, DF),
   UINT regno,
   DF value
 )
diff --git a/sim/common/cgen-par.h b/sim/common/cgen-par.h
index 6771e40635b..3748d947ffd 100644
--- a/sim/common/cgen-par.h
+++ b/sim/common/cgen-par.h
@@ -73,8 +73,8 @@ typedef struct {
     } fn_di_write;
     struct {
       UINT regno;
-      DI   value;
-      void (*function)(SIM_CPU *, UINT, DI);
+      DF   value;
+      void (*function)(SIM_CPU *, UINT, DF);
     } fn_df_write;
     struct {
       UINT regno;
@@ -121,7 +121,7 @@ extern void cgen_write_queue_element_execute (
 
 /* Instance of the queue for parallel write-after support.  */
 /* FIXME: Should be dynamic?  */
-#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now.  */
+#define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now.  */
 
 typedef struct {
   int index;
@@ -151,7 +151,7 @@ extern void sim_queue_pc_write (SIM_CPU *, USI);
 extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
 extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
 extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
-extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);
+extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF);
 extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *);
 extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI);
 
diff --git a/sim/common/cgen-trace.c b/sim/common/cgen-trace.c
index db852d5306c..4e382d4930a 100644
--- a/sim/common/cgen-trace.c
+++ b/sim/common/cgen-trace.c
@@ -51,7 +51,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #endif
 
 #ifndef SIZE_TRACE_BUF
-#define SIZE_TRACE_BUF 256
+#define SIZE_TRACE_BUF 1024
 #endif
 
 static void
diff --git a/sim/configure b/sim/configure
index 3b8c1f6aacf..38aab98c5c5 100755
--- a/sim/configure
+++ b/sim/configure
@@ -30,7 +30,6 @@ program_suffix=NONE
 program_transform_name=s,x,x,
 silent=
 site=
-sitefile=
 srcdir=
 target=NONE
 verbose=
@@ -145,7 +144,6 @@ Configuration:
   --help                  print this message
   --no-create             do not create output files
   --quiet, --silent       do not print \`checking...' messages
-  --site-file=FILE        use FILE as the site file
   --version               print the version of autoconf that created configure
 Directory and file names:
   --prefix=PREFIX         install architecture-independent files in PREFIX
@@ -316,11 +314,6 @@ EOF
   -site=* | --site=* | --sit=*)
     site="$ac_optarg" ;;
 
-  -site-file | --site-file | --site-fil | --site-fi | --site-f)
-    ac_prev=sitefile ;;
-  -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*)
-    sitefile="$ac_optarg" ;;
-
   -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
     ac_prev=srcdir ;;
   -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
@@ -486,16 +479,12 @@ fi
 srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
 
 # Prefer explicitly selected file to automatically selected ones.
-if test -z "$sitefile"; then
-  if test -z "$CONFIG_SITE"; then
-    if test "x$prefix" != xNONE; then
-      CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
-    else
-      CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
-    fi
+if test -z "$CONFIG_SITE"; then
+  if test "x$prefix" != xNONE; then
+    CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+  else
+    CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
   fi
-else
-  CONFIG_SITE="$sitefile"
 fi
 for ac_site_file in $CONFIG_SITE; do
   if test -r "$ac_site_file"; then
@@ -538,7 +527,7 @@ fi
 # Extract the first word of "gcc", so it can be a program name with args.
 set dummy gcc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:542: checking for $ac_word" >&5
+echo "configure:531: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -568,7 +557,7 @@ if test -z "$CC"; then
   # Extract the first word of "cc", so it can be a program name with args.
 set dummy cc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:572: checking for $ac_word" >&5
+echo "configure:561: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -619,7 +608,7 @@ fi
       # Extract the first word of "cl", so it can be a program name with args.
 set dummy cl; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:623: checking for $ac_word" >&5
+echo "configure:612: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -651,7 +640,7 @@ fi
 fi
 
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:655: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:644: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
 
 ac_ext=c
 # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -662,12 +651,12 @@ cross_compiling=$ac_cv_prog_cc_cross
 
 cat > conftest.$ac_ext << EOF
 
-#line 666 "configure"
+#line 655 "configure"
 #include "confdefs.h"
 
 main(){return(0);}
 EOF
-if { (eval echo configure:671: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:660: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   ac_cv_prog_cc_works=yes
   # If we can't run a trivial program, we are probably using a cross compiler.
   if (./conftest; exit) 2>/dev/null; then
@@ -693,12 +682,12 @@ if test $ac_cv_prog_cc_works = no; then
   { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
 fi
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:697: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:686: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
 cross_compiling=$ac_cv_prog_cc_cross
 
 echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:702: checking whether we are using GNU C" >&5
+echo "configure:691: checking whether we are using GNU C" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -707,7 +696,7 @@ else
   yes;
 #endif
 EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:711: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:700: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
   ac_cv_prog_gcc=yes
 else
   ac_cv_prog_gcc=no
@@ -726,7 +715,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
 ac_save_CFLAGS="$CFLAGS"
 CFLAGS=
 echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:730: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:719: checking whether ${CC-cc} accepts -g" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -788,7 +777,7 @@ ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
 # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
 # ./install, which can be erroneously created by make from ./install.sh.
 echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:792: checking for a BSD compatible install" >&5
+echo "configure:781: checking for a BSD compatible install" >&5
 if test -z "$INSTALL"; then
 if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -847,7 +836,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
 fi
 
 echo $ac_n "checking host system type""... $ac_c" 1>&6
-echo "configure:851: checking host system type" >&5
+echo "configure:840: checking host system type" >&5
 
 host_alias=$host
 case "$host_alias" in
@@ -868,7 +857,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
 echo "$ac_t""$host" 1>&6
 
 echo $ac_n "checking build system type""... $ac_c" 1>&6
-echo "configure:872: checking build system type" >&5
+echo "configure:861: checking build system type" >&5
 
 build_alias=$build
 case "$build_alias" in
@@ -894,7 +883,7 @@ fi
 # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ar; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:898: checking for $ac_word" >&5
+echo "configure:887: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -926,7 +915,7 @@ fi
 # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:930: checking for $ac_word" >&5
+echo "configure:919: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -958,7 +947,7 @@ if test -n "$ac_tool_prefix"; then
   # Extract the first word of "ranlib", so it can be a program name with args.
 set dummy ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:962: checking for $ac_word" >&5
+echo "configure:951: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1038,7 +1027,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
 fi
 
 echo $ac_n "checking host system type""... $ac_c" 1>&6
-echo "configure:1042: checking host system type" >&5
+echo "configure:1031: checking host system type" >&5
 
 host_alias=$host
 case "$host_alias" in
@@ -1059,7 +1048,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
 echo "$ac_t""$host" 1>&6
 
 echo $ac_n "checking target system type""... $ac_c" 1>&6
-echo "configure:1063: checking target system type" >&5
+echo "configure:1052: checking target system type" >&5
 
 target_alias=$target
 case "$target_alias" in
@@ -1077,7 +1066,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
 echo "$ac_t""$target" 1>&6
 
 echo $ac_n "checking build system type""... $ac_c" 1>&6
-echo "configure:1081: checking build system type" >&5
+echo "configure:1070: checking build system type" >&5
 
 build_alias=$build
 case "$build_alias" in
@@ -1121,7 +1110,7 @@ test "$program_transform_name" = "" && program_transform_name="s,x,x,"
 # Extract the first word of "gcc", so it can be a program name with args.
 set dummy gcc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1125: checking for $ac_word" >&5
+echo "configure:1114: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1151,7 +1140,7 @@ if test -z "$CC"; then
   # Extract the first word of "cc", so it can be a program name with args.
 set dummy cc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1155: checking for $ac_word" >&5
+echo "configure:1144: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1202,7 +1191,7 @@ fi
       # Extract the first word of "cl", so it can be a program name with args.
 set dummy cl; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1206: checking for $ac_word" >&5
+echo "configure:1195: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1234,7 +1223,7 @@ fi
 fi
 
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:1238: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:1227: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
 
 ac_ext=c
 # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -1245,12 +1234,12 @@ cross_compiling=$ac_cv_prog_cc_cross
 
 cat > conftest.$ac_ext << EOF
 
-#line 1249 "configure"
+#line 1238 "configure"
 #include "confdefs.h"
 
 main(){return(0);}
 EOF
-if { (eval echo configure:1254: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1243: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   ac_cv_prog_cc_works=yes
   # If we can't run a trivial program, we are probably using a cross compiler.
   if (./conftest; exit) 2>/dev/null; then
@@ -1276,12 +1265,12 @@ if test $ac_cv_prog_cc_works = no; then
   { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
 fi
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:1280: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:1269: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
 cross_compiling=$ac_cv_prog_cc_cross
 
 echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:1285: checking whether we are using GNU C" >&5
+echo "configure:1274: checking whether we are using GNU C" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1290,7 +1279,7 @@ else
   yes;
 #endif
 EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1294: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1283: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
   ac_cv_prog_gcc=yes
 else
   ac_cv_prog_gcc=no
@@ -1309,7 +1298,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
 ac_save_CFLAGS="$CFLAGS"
 CFLAGS=
 echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:1313: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:1302: checking whether ${CC-cc} accepts -g" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1347,7 +1336,7 @@ AR=${AR-ar}
 # Extract the first word of "ranlib", so it can be a program name with args.
 set dummy ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1351: checking for $ac_word" >&5
+echo "configure:1340: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1376,7 +1365,6 @@ fi
 
 
 # Put a plausible default for CC_FOR_BUILD in Makefile.
-
 if test "x$cross_compiling" = "xno"; then
   CC_FOR_BUILD='$(CC)'
 else
diff --git a/sim/configure.in b/sim/configure.in
index ce47feda2f4..8bee260306c 100644
--- a/sim/configure.in
+++ b/sim/configure.in
@@ -1,5 +1,5 @@
 dnl Process this file with autoconf to produce a configure script.
-AC_PREREQ(2.12.1)dnl
+AC_PREREQ(2.13)dnl
 AC_INIT(Makefile.in)
 
 AC_PROG_CC
@@ -18,7 +18,6 @@ AC_SUBST(AR)
 AC_PROG_RANLIB
 
 # Put a plausible default for CC_FOR_BUILD in Makefile.
-AC_C_CROSS
 if test "x$cross_compiling" = "xno"; then
   CC_FOR_BUILD='$(CC)'
 else
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 449e256085f..f39999d6c1b 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,8 @@
+1999-11-25  Nick Clifton  <nickc@cygnus.com>
+
+	* simops.c (OP_4E0F): New function: Simulate new bit pattern for
+	cpfg instruction.
+
 Fri Oct 29 18:34:28 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* simops.c (move_to_cr): Don't allow user to set PSW.DM in either
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index d80c9238894..9c1f3f65a1b 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -1087,6 +1087,28 @@ OP_4E09 ()
   trace_output_flag ();
 }
 
+/* cpfg */
+void
+OP_4E0F ()
+{
+  uint8 val;
+  
+  trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
+  
+  if (OP[1] == 0)
+    val = PSW_F0;
+  else if (OP[1] == 1)
+    val = PSW_F1;
+  else
+    val = PSW_C;
+  if (OP[0] == 0)
+    SET_PSW_F0 (val);
+  else
+    SET_PSW_F1 (val);
+
+  trace_output_flag ();
+}
+
 /* dbt */
 void
 OP_5F20 ()
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 6c8bc4a0dbb..8c3860bf2bf 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,11 @@
+1999-11-29  Mark Salter  <msalter@cygnus.com>
+
+	* dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
+	to clear status bits in sdisr register. This is how the hardware works.
+
+	* interp.c (sim_open): Added more memory aliases for jmr3904 hardware
+	being used by cygmon.
+
 1999-11-11  Andrew Haley  <aph@cygnus.com>
 
 	* interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
diff --git a/sim/mips/dv-tx3904sio.c b/sim/mips/dv-tx3904sio.c
index a1e3ddbefd2..5ba8e37a82e 100644
--- a/sim/mips/dv-tx3904sio.c
+++ b/sim/mips/dv-tx3904sio.c
@@ -1,6 +1,6 @@
 /*  This file is part of the program GDB, the GNU debugger.
     
-    Copyright (C) 1998 Free Software Foundation, Inc.
+    Copyright (C) 1998, 1999 Free Software Foundation, Inc.
     Contributed by Cygnus Solutions.
     
     This program is free software; you can redistribute it and/or modify
@@ -167,6 +167,7 @@ struct tx3904sio
   unsigned_4 sdisr;
 #define SDISR_WR_MASK       0x00070000U
 #define SDISR_SET_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
+#define SDISR_CLEAR_FLAG_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) & ((b)<< (o)*8)))
 #define SDISR_GET_TDIS(c)   ((c)->sdisr & 0x00020000)
 #define SDISR_SET_TDIS(c)   ((c)->sdisr |= 0x00020000)
 #define SDISR_GET_RDIS(c)   ((c)->sdisr & 0x00010000)
@@ -419,7 +420,7 @@ tx3904sio_io_write_buffer (struct hw *me,
 	    last_int = controller->sdisr & controller->sdicr;
 	    /* HW_TRACE ((me, "sdisr - sdisr %08x sdicr %08x", 
 	       controller->sdisr, controller->sdicr)); */
-	    SDISR_SET_BYTE(controller, reg_offset, write_byte);
+	    SDISR_CLEAR_FLAG_BYTE(controller, reg_offset, write_byte);
 	    /* HW_TRACE ((me, "sdisr + sdisr %08x sdicr %08x", 
 	       controller->sdisr, controller->sdicr)); */
 	    next_int = controller->sdisr & controller->sdicr;
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index ef70ca63c4a..6fba8df7820 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -13,8 +13,8 @@
    THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
-   $Revision: 1.187 $
-   $Date: 1999/11/11 18:13:32 $             
+   $Revision: 1.188 $
+   $Date: 1999/11/29 14:48:10 $             
 
 NOTEs:
 
@@ -462,8 +462,9 @@ sim_open (kind, cb, abfd, argv)
       sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
       sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
       sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x804); /* DRAMC */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
       sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
+      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
+      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
       sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
       sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
 
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index be554f525d4..78998b09ba4 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -3235,6 +3235,7 @@
 
 
 // MOVF
+// MOVT
 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
 "mov%s<TF> r<RD>, r<RS>, <CC>"
 *mipsIV:
@@ -3246,6 +3247,7 @@
 
 
 // MOVF.fmt
+// MOVT.fmt
 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
 *mipsIV:
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index cc37c7b2392..23f3ca6a472 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -59,6 +59,15 @@ Tue Feb 16 23:57:17 1999  Jeffrey A Law  (law@cygnus.com)
 	generation. (mn103int_finish): Install it as ioctl handler.
 	* dv-mn103tim.c: Support timer 6 specially.  Endianness fixes.
 	
+Wed Oct 14 12:11:05 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen: Allow autoincrement stores using the same register
+	for source and destination operands.
+
+Mon Aug 31 10:19:55 1998  Jeffrey A Law  (law@cygnus.com)
+
+        * am33.igen: Reverse HI/LO outputs of 4 operand "mul" and "mulu".
+
 Fri Aug 28 14:40:49 1998  Joyce Janczyn  <janczyn@cygnus.com>
 
 	* interp.c (sim_open): Check for invalid --board option, fix
@@ -73,6 +82,21 @@ Mon Aug 24 11:50:09 1998  Joyce Janczyn  <janczyn@cygnus.com>
 
 	* sim-main.h (SIM_HANDLES_LMA): Define SIM_HANDLES_LMA.
 
+Wed Aug 12 12:36:07 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen: Handle case where first DSP operation modifies a 
+	register used in the second DSP operation correctly.
+
+Tue Jul 28 10:10:25 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen: Detect cases where two operands must not match for
+	DSP instructions too.
+
+Mon Jul 27 12:04:17 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen: Detect cases where two operands must not match in
+	non-DSP instructions.
+
 Fri Jul 24 18:15:21 1998  Joyce Janczyn  <janczyn@cygnus.com>
 
 	* op_utils.c (do_syscall): Rewrite to use common/syscall.c.
@@ -83,21 +107,71 @@ Fri Jul 24 18:15:21 1998  Joyce Janczyn  <janczyn@cygnus.com>
 	* mn10300.igen: Change C++ style comments to C style comments.
 	Check for divide by zero in div and divu ops.
 
+Fri Jul 24 12:49:28 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen (translate_xreg): New function.  Use it as needed.
+
+Thu Jul 23 10:05:28 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen: Add some missing instructions.
+
+	* am33.igen: Autoincrement loads/store fixes.
+
+Tue Jul 21 09:48:14 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen: Add mov_lCC DSP instructions.
+
+	* am33.igen: Add most am33 DSP instructions.
+
 Thu Jul  9 10:06:55 1998  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300.igen: Fix Z bit for addc and subc instructions.
 	Minor fixes in multiply/divide patterns.
 
+	* am33.igen: Add missing mul[u] imm32,Rn.  Fix condition code
+	handling for many instructions.  Fix sign extension for some
+	24bit immediates.
+
+	* am33.igen: Fix Z bit for remaining addc/subc instructions.
+	Do not sign extend immediate for mov imm,XRn.
+	More random mul, mac & div fixes.
+	Remove some unused variables.
+	Sign extend 24bit displacement in memory addresses.
+
+	* am33.igen: Fix Z bit for addc Rm,Rn and subc Rm,Rn.  Various
+	fixes to 2 register multiply, divide and mac instructions.  Set
+	Z,N correctly for sat16.  Sign extend 24 bit immediate for add,
+	and sub instructions.
+
+	* am33.igen: Add remaining non-DSP instructions.
+
+Wed Jul  8 16:29:12 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* am33.igen (translate_rreg): New function.  Use it as appropriate.
+
+	* am33.igen: More am33 instructions.  Fix "div".
+
+Mon Jul  6 15:39:22 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.igen: Add am33 support.
+
+	* Makefile.in: Use multi-sim to support both a mn10300 and am33
+	simulator.
+
+	* am33.igen: Add many more am33 instructions.
 
 Wed Jul  1 17:07:09 1998  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300_sim.h (FETCH24): Define.
 
+	* mn10300_sim.h: Add defines for some registers found on the AM33.
+	* am33.igen: New file with some am33 support.
 
 Tue Jun 30 11:23:20 1998  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300_sim.h: Include bfd.h
 	(struct state): Add more room for processor specific registers.
+	(REG_E0): Define.
 
 Thu Jun 25 10:12:03 1998  Joyce Janczyn  <janczyn@cygnus.com>
 
diff --git a/sim/mn10300/Makefile.in b/sim/mn10300/Makefile.in
index 612576cce3b..4d02e5bc70d 100644
--- a/sim/mn10300/Makefile.in
+++ b/sim/mn10300/Makefile.in
@@ -113,6 +113,8 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
 	../igen/igen \
 		$(IGEN_TRACE) \
 		-G gen-direct-access \
+                -M mn10300,am33 -G gen-multi-sim=am33 \
+		-I $(srcdir) \
 		-i $(IGEN_INSN) \
 		-o $(IGEN_DC) \
 		-x \
diff --git a/sim/mn10300/mn10300.igen b/sim/mn10300/mn10300.igen
index 1b42db401e8..2ffa9805ec5 100644
--- a/sim/mn10300/mn10300.igen
+++ b/sim/mn10300/mn10300.igen
@@ -3,6 +3,7 @@
 :option:::insn-specifying-widths:true
 :option:::hi-bit-nr:7
 :model:::mn10300:mn10300:
+:model:::am33:am33:
 
 // What do we do with an illegal instruction?
 :internal::::illegal:
@@ -15,6 +16,7 @@
 4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
 "mov"
 *mn10300
+*am33
 {
   /*  OP_8000 (); */
   signed32 immed = EXTEND8 (IMM8);
@@ -26,6 +28,7 @@
 4.0x8,2.DM1,2.DN0!DM1:S0:::mov
 "mov"
 *mn10300
+*am33
 {
   PC = cia;
   /* OP_80 (); */
@@ -37,6 +40,7 @@
 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F1E0 (); */
   PC = cia;
@@ -48,6 +52,7 @@
 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F1D0 (); */
   PC = cia;
@@ -59,6 +64,7 @@
 4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
 "mov"
 *mn10300
+*am33
 {
    PC = cia;
    /* OP_9000 (); */
@@ -70,6 +76,7 @@
 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
 "mov"
 *mn10300
+*am33
 {
    PC = cia;
    /* OP_90 (); */
@@ -81,6 +88,7 @@
 4.0x3,11,2.AN0:S0b:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_3C (); */
   PC = cia;
@@ -92,6 +100,7 @@
 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F2F0 (); */
   PC = cia;
@@ -103,6 +112,7 @@
 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F2E4 (); */
   PC = cia;
@@ -114,6 +124,7 @@
 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F2F3 (); */
   PC = cia;
@@ -125,6 +136,7 @@
 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F2E0 (); */
   PC = cia;
@@ -136,6 +148,7 @@
 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F2F2 (); */
   PC = cia;
@@ -147,6 +160,7 @@
 4.0x7,2.DN1,2.AM0:S0c:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_70 (); */
   PC = cia;
@@ -158,6 +172,7 @@
 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F80000 (); */
   PC = cia;
@@ -170,6 +185,7 @@
 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FA000000 (); */
   PC = cia;
@@ -182,6 +198,7 @@
 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FC000000 (); */
   PC = cia;
@@ -195,6 +212,7 @@
 4.0x5,10,2.DN0+8.D8:S1:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_5800 (); */
   PC = cia;
@@ -206,6 +224,7 @@
 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FAB40000 (); */
   PC = cia;
@@ -218,6 +237,7 @@
 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FCB40000 (); */
   PC = cia;
@@ -230,6 +250,7 @@
 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F300 (); */
   PC = cia;
@@ -242,6 +263,7 @@
 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_300000 (); */
   PC = cia;
@@ -252,6 +274,7 @@
 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FCA40000 (); */
   PC = cia;
@@ -263,6 +286,7 @@
 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F000 (); */
   PC = cia;
@@ -274,6 +298,7 @@
 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F82000 (); */
   PC = cia;
@@ -286,6 +311,7 @@
 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FA200000 (); */
   PC = cia;
@@ -299,6 +325,7 @@
 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FC200000 (); */
   PC = cia;
@@ -312,6 +339,7 @@
 4.0x5,11,2.AN0+8.D8:S1a:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_5C00 (); */
   PC = cia;
@@ -324,6 +352,7 @@
 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FAB00000 (); */
   PC = cia;
@@ -336,6 +365,7 @@
 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FCB00000 (); */
   PC = cia;
@@ -349,6 +379,7 @@
 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F380 (); */
   PC = cia;
@@ -362,6 +393,7 @@
 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FAA00000 (); */
   PC = cia;
@@ -373,6 +405,7 @@
 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FCA00000 (); */
   PC = cia;
@@ -385,6 +418,7 @@
 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F8F000 (); */
   PC = cia;
@@ -397,6 +431,7 @@
 4.0x6,2.DM1,2.AN0:S0d:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_60 (); */
   PC = cia;
@@ -408,6 +443,7 @@
 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F81000 (); */
   PC = cia;
@@ -420,6 +456,7 @@
 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FA100000 (); */
   PC = cia;
@@ -432,6 +469,7 @@
 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FC100000 (); */
   PC = cia;
@@ -445,6 +483,7 @@
 4.0x4,2.DM1,10+8.D8:S1b:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_4200 (); */
   PC = cia;
@@ -456,6 +495,7 @@
 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FA910000 (); */
   PC = cia;
@@ -468,6 +508,7 @@
 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FC910000 (); */
   PC = cia;
@@ -480,6 +521,7 @@
 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F340 (); */
   PC = cia;
@@ -492,6 +534,7 @@
 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_10000 (); */
   PC = cia;
@@ -503,6 +546,7 @@
 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FC810000 (); */
   PC = cia;
@@ -515,6 +559,7 @@
 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F010 (); */
   PC = cia;
@@ -526,6 +571,7 @@
 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_F83000 (); */
   PC = cia;
@@ -538,6 +584,7 @@
 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FA300000 (); */
   PC = cia;
@@ -550,6 +597,7 @@
 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
 "mov"
 *mn10300
+*am33
 {
   /* OP_FC300000 (); */
   PC = cia;
@@ -563,6 +611,9 @@
 4.0x4,2.AM1,11+8.D8:S1c:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_4300 (); */
   PC = cia;
@@ -574,6 +625,9 @@
 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_FA900000 (); */
   PC = cia;
@@ -586,6 +640,9 @@
 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_FC900000 (); */
   PC = cia;
@@ -598,6 +655,9 @@
 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_F3C0 (); */
   PC = cia;
@@ -610,6 +670,9 @@
 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_FA800000 (); */
   PC = cia;
@@ -622,6 +685,9 @@
 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_FC800000 (); */
   PC = cia;
@@ -634,6 +700,9 @@
 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_F8F400 (); */
   PC = cia;
@@ -646,6 +715,9 @@
 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_2C0000 (); */
   unsigned long value;
@@ -660,6 +732,9 @@
 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_FCCC0000 (); */
   unsigned long value;
@@ -674,6 +749,9 @@
 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
   /* OP_240000 (); */
   unsigned long value;
@@ -688,6 +766,9 @@
 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
 "mov"
 *mn10300
+
+*am33
+
 {
     /* OP_FCDC0000 (); */
     PC = cia;
@@ -699,6 +780,9 @@
 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F040 (); */
   PC = cia;
@@ -711,6 +795,9 @@
 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F84000 (); */
   PC = cia;
@@ -723,6 +810,9 @@
 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FA400000 (); */
   PC = cia;
@@ -736,6 +826,9 @@
 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC400000 (); */
   PC = cia;
@@ -749,6 +842,9 @@
 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F8B800 (); */
   PC = cia;
@@ -761,6 +857,9 @@
 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FAB80000 (); */
   PC = cia;
@@ -774,6 +873,9 @@
 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FCB80000 (); */
   PC = cia;
@@ -787,6 +889,9 @@
 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F400 (); */
   PC = cia;
@@ -800,6 +905,9 @@
 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_340000 (); */
   PC = cia;
@@ -811,6 +919,9 @@
 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FCA80000 (); */
   PC = cia;
@@ -823,6 +934,9 @@
 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F050 (); */
   PC = cia;
@@ -834,6 +948,9 @@
 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F85000 (); */
   PC = cia;
@@ -846,6 +963,9 @@
 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FA500000 (); */
   PC = cia;
@@ -858,6 +978,9 @@
 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC500000 (); */
   PC = cia;
@@ -871,6 +994,9 @@
 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F89200 (); */
   PC = cia;
@@ -882,6 +1008,9 @@
 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FA920000 (); */
   PC = cia;
@@ -894,6 +1023,9 @@
 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC920000 (); */
   PC = cia;
@@ -906,6 +1038,9 @@
 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_F440 (); */
   PC = cia;
@@ -918,6 +1053,9 @@
 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_20000 (); */
   PC = cia;
@@ -930,6 +1068,9 @@
 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
 "movbu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC820000 (); */
   PC = cia;
@@ -942,6 +1083,9 @@
 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F060 (); */
   PC = cia;
@@ -954,6 +1098,9 @@
 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F86000 (); */
   PC = cia;
@@ -966,6 +1113,9 @@
 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FA600000 (); */
   PC = cia;
@@ -979,6 +1129,9 @@
 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC600000 (); */
   PC = cia;
@@ -992,6 +1145,9 @@
 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F8BC00 (); */
   PC = cia;
@@ -1004,6 +1160,9 @@
 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FABC0000 (); */
   PC = cia;
@@ -1016,6 +1175,9 @@
 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FCBC0000 (); */
   PC = cia;
@@ -1028,6 +1190,9 @@
 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F480 (); */
   PC = cia;
@@ -1040,6 +1205,9 @@
 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_380000 (); */
   PC = cia;
@@ -1051,6 +1219,9 @@
 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FCAC0000 (); */
   PC = cia;
@@ -1063,6 +1234,9 @@
 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F070 (); */
   PC = cia;
@@ -1075,6 +1249,9 @@
 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F87000 (); */
   PC = cia;
@@ -1087,6 +1264,9 @@
 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FA700000 (); */
   PC = cia;
@@ -1099,6 +1279,9 @@
 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC700000 (); */
   PC = cia;
@@ -1112,6 +1295,9 @@
 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F89300 (); */
   PC = cia;
@@ -1124,6 +1310,9 @@
 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FA930000 (); */
   PC = cia;
@@ -1136,6 +1325,9 @@
 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC930000 (); */
   PC = cia;
@@ -1148,6 +1340,9 @@
 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_F4C0 (); */
   PC = cia;
@@ -1160,6 +1355,9 @@
 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_30000 (); */
   PC = cia;
@@ -1171,6 +1369,9 @@
 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
 "movhu"
 *mn10300
+
+*am33
+
 {
   /* OP_FC830000 (); */
   PC = cia;
@@ -1183,6 +1384,9 @@
 8.0xf2+4.0xd,00,2.DN0:D0:::ext
 "ext"
 *mn10300
+
+*am33
+
 {
   /* OP_F2D0 (); */
   PC = cia;
@@ -1197,6 +1401,9 @@
 4.0x1,00,2.DN0:S0:::extb
 "extb"
 *mn10300
+
+*am33
+
 {
   /* OP_10 (); */
   PC = cia;
@@ -1208,6 +1415,9 @@
 4.0x1,01,2.DN0:S0:::extbu
 "extbu"
 *mn10300
+
+*am33
+
 {
   /* OP_14 (); */
   PC = cia;
@@ -1219,6 +1429,9 @@
 4.0x1,10,2.DN0:S0:::exth
 "exth"
 *mn10300
+
+*am33
+
 {
   /* OP_18 (); */
   PC = cia;
@@ -1230,6 +1443,9 @@
 4.0x1,11,2.DN0:S0:::exthu
 "exthu"
 *mn10300
+
+*am33
+
 {
   /* OP_1C (); */
   PC = cia;
@@ -1241,6 +1457,9 @@
 4.0x0,2.DN1,00:S0:::clr
 "clr"
 *mn10300
+
+*am33
+
 {
   /* OP_0 (); */
   PC = cia;
@@ -1255,6 +1474,9 @@
 4.0xe,2.DM1,2.DN0:S0:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_E0 (); */
   PC = cia;
@@ -1265,6 +1487,9 @@
 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_F160 (); */
   PC = cia;
@@ -1276,6 +1501,9 @@
 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_F150 (); */
   PC = cia;
@@ -1287,6 +1515,9 @@
 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_F170 (); */
   PC = cia;
@@ -1298,6 +1529,9 @@
 4.0x2,10,2.DN0+8.IMM8:S1:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_2800 (); */
   PC = cia;
@@ -1309,6 +1543,9 @@
 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_FAC00000 (); */
   PC = cia;
@@ -1320,6 +1557,9 @@
 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_FCC00000 (); */
   PC = cia;
@@ -1331,6 +1571,9 @@
 4.0x2,00,2.AN0+8.IMM8:S1a:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_2000 (); */
   PC = cia;
@@ -1342,6 +1585,9 @@
 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_FAD00000 (); */
   PC = cia;
@@ -1353,6 +1599,9 @@
 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_FCD00000 (); */
   PC = cia;
@@ -1364,6 +1613,9 @@
 8.0xf8+8.0xfe+8.IMM8:D1:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_F8FE00 (); */
   unsigned long imm;
@@ -1379,6 +1631,9 @@
 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_FAFE0000 (); */
   unsigned long imm;
@@ -1394,6 +1649,9 @@
 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
 "add"
 *mn10300
+
+*am33
+
 {
   /* OP_FCFE0000 (); */
   unsigned long imm;
@@ -1409,6 +1667,9 @@
 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
 "addc"
 *mn10300
+
+*am33
+
 {
   /* OP_F140 (); */
   int z, c, n, v;
@@ -1436,6 +1697,9 @@
 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
 "sub"
 *mn10300
+
+*am33
+
 {
   /* OP_F100 (); */
   PC = cia;
@@ -1446,6 +1710,9 @@
 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
 "sub"
 *mn10300
+
+*am33
+
 {
   /* OP_F120 (); */
   PC = cia;
@@ -1457,6 +1724,9 @@
 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
 "sub"
 *mn10300
+
+*am33
+
 {
   /* OP_F110 (); */
   PC = cia;
@@ -1468,6 +1738,9 @@
 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
 "sub"
 *mn10300
+
+*am33
+
 {
   /* OP_F130 (); */
   PC = cia;
@@ -1479,6 +1752,9 @@
 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
 "sub"
 *mn10300
+
+*am33
+
 {
   /* OP_FCC40000 (); */
   PC = cia;
@@ -1490,6 +1766,9 @@
 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
 "sub"
 *mn10300
+
+*am33
+
 {
   /* OP_FCD40000 (); */
   PC = cia;
@@ -1501,6 +1780,9 @@
 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
 "subc"
 *mn10300
+
+*am33
+
 {
   /* OP_F180 (); */
   int z, c, n, v;
@@ -1528,6 +1810,9 @@
 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
 "mul"
 *mn10300
+
+*am33
+
 {
   /* OP_F240 (); */
   unsigned long long temp;
@@ -1549,6 +1834,9 @@
 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
 "mulu"
 *mn10300
+
+*am33
+
 {
   /* OP_F250 (); */
   unsigned long long temp;
@@ -1570,6 +1858,9 @@
 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
 "div"
 *mn10300
+
+*am33
+
 {
   /* OP_F260 (); */
   signed64 temp;
@@ -1604,6 +1895,9 @@
 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
 "divu"
 *mn10300
+
+*am33
+
 {
   /* OP_F270 (); */
   unsigned64 temp;
@@ -1637,6 +1931,9 @@
 4.0x4,2.DN1,00:S0:::inc
 "inc"
 *mn10300
+
+*am33
+
 {
   /* OP_40 (); */
   unsigned int imm;
@@ -1651,6 +1948,9 @@
 4.0x4,2.AN1,01:S0a:::inc
 "inc"
 *mn10300
+
+*am33
+
 {
   /* OP_41 (); */
   PC = cia;
@@ -1662,6 +1962,9 @@
 4.0x5,00,2.AN0:S0:::inc4
 "inc4"
 *mn10300
+
+*am33
+
 {
   /* OP_50 (); */
   PC = cia;
@@ -1673,6 +1976,9 @@
 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   PC = cia;
   /* OP_A000 (); */
@@ -1684,6 +1990,9 @@
 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   PC = cia;
   /* OP_A0 (); */
@@ -1695,6 +2004,9 @@
 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   /* OP_F1A0 (); */
   PC = cia;
@@ -1706,6 +2018,9 @@
 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   /* OP_F190 (); */
   PC = cia;
@@ -1717,6 +2032,9 @@
 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   PC = cia;
   /* OP_B000 (); */
@@ -1729,6 +2047,9 @@
 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   PC = cia;
   /* OP_B0 (); */
@@ -1740,6 +2061,9 @@
 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   /* OP_FAC80000 (); */
   PC = cia;
@@ -1752,6 +2076,9 @@
 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   /* OP_FCC80000 (); */
   PC = cia;
@@ -1764,6 +2091,9 @@
 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   /* OP_FAD80000 (); */
   PC = cia;
@@ -1776,6 +2106,9 @@
 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
 "cmp"
 *mn10300
+
+*am33
+
 {
   /* OP_FCD80000 (); */
   PC = cia;
@@ -1788,6 +2121,9 @@
 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
 "and"
 *mn10300
+
+*am33
+
 {
   /* OP_F200 (); */
   int n, z;
@@ -1805,6 +2141,9 @@
 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
 "and"
 *mn10300
+
+*am33
+
 {
   /* OP_F8E000 (); */
   int n, z;
@@ -1822,6 +2161,9 @@
 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
 "and"
 *mn10300
+
+*am33
+
 {
   /* OP_FAE00000 (); */
   int n, z;
@@ -1839,6 +2181,9 @@
 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
 "and"
 *mn10300
+
+*am33
+
 {
   /* OP_FCE00000 (); */
   int n, z;
@@ -1857,6 +2202,9 @@
 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
 "and"
 *mn10300
+
+*am33
+
 {
   /* OP_FAFC0000 (); */
   PC = cia;
@@ -1869,6 +2217,9 @@
 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
 "or"
 *mn10300
+
+*am33
+
 {
   /* OP_F210 (); */
   PC = cia;
@@ -1880,6 +2231,9 @@
 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
 "or"
 *mn10300
+
+*am33
+
 {
   /* OP_F8E400 (); */
   PC = cia;
@@ -1891,6 +2245,9 @@
 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
 "or"
 *mn10300
+
+*am33
+
 {
   /* OP_FAE40000 (); */
   PC = cia;
@@ -1902,6 +2259,9 @@
 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
 "or"
 *mn10300
+
+*am33
+
 {
   /* OP_FCE40000 (); */
   PC = cia;
@@ -1913,6 +2273,9 @@
 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
 "or"
 *mn10300
+
+*am33
+
 {
   /* OP_FAFD0000 (); */
   PC = cia;
@@ -1924,6 +2287,9 @@
 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
 "xor"
 *mn10300
+
+*am33
+
 {
   /* OP_F220 (); */
   PC = cia;
@@ -1935,6 +2301,9 @@
 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
 "xor"
 *mn10300
+
+*am33
+
 {
   /* OP_FAE80000 (); */
   PC = cia;
@@ -1946,6 +2315,9 @@
 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
 "xor"
 *mn10300
+
+*am33
+
 {
   /* OP_FCE80000 (); */
   PC = cia;
@@ -1957,6 +2329,9 @@
 8.0xf2+4.0x3,00,2.DN0:D0:::not
 "not"
 *mn10300
+
+*am33
+
 {
   /* OP_F230 (); */
   int n, z;
@@ -1974,6 +2349,9 @@
 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
 "btst"
 *mn10300
+
+*am33
+
 {
   /* OP_F8EC00 (); */
   PC = cia;
@@ -1985,6 +2363,9 @@
 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
 "btst"
 *mn10300
+
+*am33
+
 {
   /* OP_FAEC0000 (); */
   PC = cia;
@@ -1996,6 +2377,9 @@
 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
 "btst"
 *mn10300
+
+*am33
+
 {
   /* OP_FCEC0000 (); */
   PC = cia;
@@ -2008,6 +2392,9 @@
 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
 "btst"
 *mn10300
+
+*am33
+
 {
   /* OP_FE020000 (); */
   PC = cia;
@@ -2021,6 +2408,9 @@
 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
 "btst"
 *mn10300
+
+*am33
+
 {
   /* OP_FAF80000 (); */
   PC = cia;
@@ -2033,6 +2423,9 @@
 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
 "bset"
 *mn10300
+
+*am33
+
 {
   /* OP_F080 (); */
   unsigned long temp;
@@ -2053,6 +2446,9 @@
 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
 "bset"
 *mn10300
+
+*am33
+
 {
   /* OP_FE000000 (); */
   unsigned long temp;
@@ -2073,6 +2469,9 @@
 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
 "bset"
 *mn10300
+
+*am33
+
 {
   /* OP_FAF00000 (); */
   unsigned long temp;
@@ -2092,6 +2491,9 @@
 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
 "bclr"
 *mn10300
+
+*am33
+
 {
   /* OP_F090 (); */
   unsigned long temp;
@@ -2112,6 +2514,9 @@
 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
 "bclr"
 *mn10300
+
+*am33
+
 {
   /* OP_FE010000 (); */
   unsigned long temp;
@@ -2132,6 +2537,9 @@
 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
 "bclr"
 *mn10300
+
+*am33
+
 {
   /* OP_FAF40000 (); */
   unsigned long temp;
@@ -2151,6 +2559,9 @@
 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
 "asr"
 *mn10300
+
+*am33
+
 {
   /* OP_F2B0 (); */
   long temp;
@@ -2172,6 +2583,9 @@
 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
 "asr"
 *mn10300
+
+*am33
+
 {
   /* OP_F8C800 (); */
   long temp;
@@ -2193,6 +2607,9 @@
 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
 "lsr"
 *mn10300
+
+*am33
+
 {
   /* OP_F2A0 (); */
   int z, n, c;
@@ -2212,6 +2629,9 @@
 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
 "lsr"
 *mn10300
+
+*am33
+
 {
   /* OP_F8C400 (); */
   int z, n, c;
@@ -2230,6 +2650,9 @@
 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
 "asl"
 *mn10300
+
+*am33
+
 {
   /* OP_F290 (); */
   int n, z;
@@ -2248,6 +2671,9 @@
 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
 "asl"
 *mn10300
+
+*am33
+
 {
   /* OP_F8C000 (); */
   int n, z;
@@ -2265,6 +2691,9 @@
 4.0x5,01,2.DN0:S0:::asl2
 "asl2"
 *mn10300
+
+*am33
+
 {
   /* OP_54 (); */
   int n, z;
@@ -2282,6 +2711,9 @@
 8.0xf2+4.0x8,01,2.DN0:D0:::ror
 "ror"
 *mn10300
+
+*am33
+
 {
   /* OP_F284 (); */
   unsigned long value;
@@ -2305,6 +2737,9 @@
 8.0xf2+4.0x8,00,2.DN0:D0:::rol
 "rol"
 *mn10300
+
+*am33
+
 {
   /* OP_F280 (); */
   unsigned long value;
@@ -2328,6 +2763,9 @@
 8.0xc8+8.D8:S1:::beq
 "beq"
 *mn10300
+
+*am33
+
 {
   /* OP_C800 (); */
   PC = cia;
@@ -2343,6 +2781,9 @@
 8.0xc9+8.D8:S1:::bne
 "bne"
 *mn10300
+
+*am33
+
 {
   /* OP_C900 (); */
   PC = cia;
@@ -2358,6 +2799,9 @@
 8.0xc1+8.D8:S1:::bgt
 "bgt"
 *mn10300
+
+*am33
+
 {
   /* OP_C100 (); */
   PC = cia;
@@ -2374,6 +2818,9 @@
 8.0xc2+8.D8:S1:::bge
 "bge"
 *mn10300
+
+*am33
+
 {
   /* OP_C200 (); */
   PC = cia;
@@ -2389,6 +2836,9 @@
 8.0xc3+8.D8:S1:::ble
 "ble"
 *mn10300
+
+*am33
+
 {
   /* OP_C300 (); */
   PC = cia;
@@ -2405,6 +2855,9 @@
 8.0xc0+8.D8:S1:::blt
 "blt"
 *mn10300
+
+*am33
+
 {
   /* OP_C000 (); */
   PC = cia;
@@ -2420,6 +2873,9 @@
 8.0xc5+8.D8:S1:::bhi
 "bhi"
 *mn10300
+
+*am33
+
 {
   /* OP_C500 (); */
   PC = cia;
@@ -2435,6 +2891,9 @@
 8.0xc6+8.D8:S1:::bcc
 "bcc"
 *mn10300
+
+*am33
+
 {
   /* OP_C600 (); */
   PC = cia;
@@ -2450,6 +2909,9 @@
 8.0xc7+8.D8:S1:::bls
 "bls"
 *mn10300
+
+*am33
+
 {
   /* OP_C700 (); */
   PC = cia;
@@ -2465,6 +2927,9 @@
 8.0xc4+8.D8:S1:::bcs
 "bcs"
 *mn10300
+
+*am33
+
 {
   /* OP_C400 (); */
   PC = cia;
@@ -2480,6 +2945,9 @@
 8.0xf8+8.0xe8+8.D8:D1:::bvc
 "bvc"
 *mn10300
+
+*am33
+
 {
   /* OP_F8E800 (); */
   PC = cia;
@@ -2495,6 +2963,9 @@
 8.0xf8+8.0xe9+8.D8:D1:::bvs
 "bvs"
 *mn10300
+
+*am33
+
 {
   /* OP_F8E900 (); */
   PC = cia;
@@ -2510,6 +2981,9 @@
 8.0xf8+8.0xea+8.D8:D1:::bnc
 "bnc"
 *mn10300
+
+*am33
+
 {
   /* OP_F8EA00 (); */
   PC = cia;
@@ -2525,6 +2999,9 @@
 8.0xf8+8.0xeb+8.D8:D1:::bns
 "bns"
 *mn10300
+
+*am33
+
 {
   /* OP_F8EB00 (); */
   PC = cia;
@@ -2540,6 +3017,9 @@
 8.0xca+8.D8:S1:::bra
 "bra"
 *mn10300
+
+*am33
+
 {
   /* OP_CA00 (); */
   PC = cia;
@@ -2552,6 +3032,9 @@
 8.0xd8:S0:::leq
 "leq"
 *mn10300
+
+*am33
+
 {
   /* OP_D8 (); */
   PC = cia;
@@ -2567,6 +3050,9 @@
 8.0xd9:S0:::lne
 "lne"
 *mn10300
+
+*am33
+
 {
   /* OP_D9 (); */
   PC = cia;
@@ -2582,6 +3068,9 @@
 8.0xd1:S0:::lgt
 "lgt"
 *mn10300
+
+*am33
+
 {
   /* OP_D1 (); */
   PC = cia;
@@ -2598,6 +3087,9 @@
 8.0xd2:S0:::lge
 "lge"
 *mn10300
+
+*am33
+
 {
   /* OP_D2 (); */
   PC = cia;
@@ -2613,6 +3105,9 @@
 8.0xd3:S0:::lle
 "lle"
 *mn10300
+
+*am33
+
 {
   /* OP_D3 (); */
   PC = cia;
@@ -2629,6 +3124,9 @@
 8.0xd0:S0:::llt
 "llt"
 *mn10300
+
+*am33
+
 {
   /* OP_D0 (); */
   PC = cia;
@@ -2644,6 +3142,9 @@
 8.0xd5:S0:::lhi
 "lhi"
 *mn10300
+
+*am33
+
 {
   /* OP_D5 (); */
   PC = cia;
@@ -2659,6 +3160,9 @@
 8.0xd6:S0:::lcc
 "lcc"
 *mn10300
+
+*am33
+
 {
   /* OP_D6 (); */
   PC = cia;
@@ -2674,6 +3178,9 @@
 8.0xd7:S0:::lls
 "lls"
 *mn10300
+
+*am33
+
 {
   /* OP_D7 (); */
   PC = cia;
@@ -2689,6 +3196,9 @@
 8.0xd4:S0:::lcs
 "lcs"
 *mn10300
+
+*am33
+
 {
   /* OP_D4 (); */
   PC = cia;
@@ -2704,6 +3214,9 @@
 8.0xda:S0:::lra
 "lra"
 *mn10300
+
+*am33
+
 {
   /* OP_DA (); */
   PC = cia;
@@ -2716,6 +3229,9 @@
 8.0xdb:S0:::setlb
 "setlb"
 *mn10300
+
+*am33
+
 {
   /* OP_DB (); */
   PC = cia;
@@ -2728,6 +3244,9 @@
 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
 "jmp"
 *mn10300
+
+*am33
+
 {
   /* OP_F0F4 (); */
   PC = State.regs[REG_A0 + AN0];
@@ -2739,6 +3258,9 @@
 8.0xcc+8.D16A+8.D16B:S2:::jmp
 "jmp"
 *mn10300
+
+*am33
+
 {
   /* OP_CC0000 (); */
   PC = cia + EXTEND16(FETCH16(D16A, D16B));
@@ -2750,6 +3272,9 @@
 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
 "jmp"
 *mn10300
+
+*am33
+
 {
   /* OP_DC000000 (); */
   PC = cia + FETCH32(D32A, D32B, D32C, D32D);
@@ -2761,6 +3286,9 @@
 8.0xf0+4.0xf,00,2.AN0:D0:::calls
 "calls"
 *mn10300
+
+*am33
+
 {
   /* OP_F0F0 (); */
   unsigned int next_pc, sp;
@@ -2779,6 +3307,9 @@
 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
 "calls"
 *mn10300
+
+*am33
+
 {
   /* OP_FAFF0000 (); */
   unsigned int next_pc, sp;
@@ -2797,6 +3328,9 @@
 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
 "calls"
 *mn10300
+
+*am33
+
 {
   /* OP_FCFF0000 (); */
   unsigned int next_pc, sp;
@@ -2815,6 +3349,9 @@
 8.0xf0+8.0xfc:D0:::rets
 "rets"
 *mn10300
+
+*am33
+
 {
   /* OP_F0FC (); */
   unsigned int sp;
@@ -2829,6 +3366,9 @@
 8.0xf0+8.0xfd:D0:::rti
 "rti"
 *mn10300
+
+*am33
+
 {
   /* OP_F0FD (); */
   unsigned int sp;
@@ -2845,6 +3385,9 @@
 8.0xf0+8.0xfe:D0:::trap
 "trap"
 *mn10300
+
+*am33
+
 {
   /* OP_F0FE (); */
   unsigned int sp, next_pc;
@@ -2861,6 +3404,9 @@
 8.0xf0+8.0xff:D0:::rtm
 "rtm"
 *mn10300
+
+*am33
+
 {
   /* OP_F0FF (); */
   PC = cia;
@@ -2872,6 +3418,9 @@
 8.0xcb:S0:::nop
 "nop"
 *mn10300
+
+*am33
+
 {
   /* OP_CB (); */
   PC = cia;
@@ -2893,6 +3442,9 @@
 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
 "getx"
 *mn10300
+
+*am33
+
 {
   /* OP_F6F0 (); */
   int z, n;
@@ -2911,6 +3463,9 @@
 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
 "mulq"
 *mn10300
+
+*am33
+
 {
   /* OP_F600 (); */
   unsigned long long temp;
@@ -2932,6 +3487,9 @@
 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
 "mulq"
 *mn10300
+
+*am33
+
 {
   /* OP_F90000 (); */
   unsigned long long temp;
@@ -2953,6 +3511,9 @@
 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
 "mulq"
 *mn10300
+
+*am33
+
 {
   /* OP_FB000000 (); */
   unsigned long long temp;
@@ -2974,6 +3535,9 @@
 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
 "mulq"
 *mn10300
+
+*am33
+
 {
   /* OP_FD000000 (); */
   unsigned long long temp;
@@ -2995,6 +3559,9 @@
 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
 "mulqu"
 *mn10300
+
+*am33
+
 {
   /* OP_F610 (); */
   unsigned long long temp;
@@ -3016,6 +3583,9 @@
 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
 "mulqu"
 *mn10300
+
+*am33
+
 {
   /* OP_F91400 (); */
   unsigned long long temp;
@@ -3037,6 +3607,9 @@
 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
 "mulqu"
 *mn10300
+
+*am33
+
 {
   /* OP_FB140000 (); */
   unsigned long long temp;
@@ -3058,6 +3631,9 @@
 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
 "mulqu"
 *mn10300
+
+*am33
+
 {
   /* OP_FD140000 (); */
   unsigned long long temp;
@@ -3079,6 +3655,9 @@
 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
 "sat16"
 *mn10300
+
+*am33
+
 {
   /* OP_F640 (); */
   int temp;
@@ -3095,6 +3674,9 @@
 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
 "sat24"
 *mn10300
+
+*am33
+
 {
   /* OP_F650 (); */
   int temp;
@@ -3111,6 +3693,9 @@
 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
 "bsch"
 *mn10300
+
+*am33
+
 {
   /* OP_F670 (); */
   int temp, c;
@@ -3128,6 +3713,9 @@
 8.0xf0+8.0xc0:D0:::syscall
 "syscall"
 *mn10300
+
+*am33
+
 {
   /* OP_F0C0 (); */
   PC = cia;
@@ -3139,6 +3727,9 @@
 8.0xff:S0:::break
 "break"
 *mn10300
+
+*am33
+
 {
   /* OP_FF (); */
   PC = cia;
@@ -3149,6 +3740,9 @@
 8.0xce+8.REGS:S1:::movm
 "movm"
 *mn10300
+
+*am33
+
 {
   /* OP_CE00 (); */
   unsigned long sp = State.regs[REG_SP];
@@ -3200,6 +3794,38 @@
       sp += 4;
     }
 
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+    {
+      if (mask & 0x1)
+	{
+	  /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+	  sp += 16;
+	  State.regs[REG_E0 + 1] = load_word (sp);
+	  sp += 4;
+	  State.regs[REG_E0 + 0] = load_word (sp);
+	  sp += 4;
+	}
+
+      if (mask & 0x2)
+        {
+	  State.regs[REG_E0 + 7] = load_word (sp);
+	  sp += 4;
+	  State.regs[REG_E0 + 6] = load_word (sp);
+	  sp += 4;
+	  State.regs[REG_E0 + 5] = load_word (sp);
+	  sp += 4;
+	  State.regs[REG_E0 + 4] = load_word (sp);
+	  sp += 4;
+	}
+
+      if (mask & 0x4)
+	{
+	  State.regs[REG_E0 + 3] = load_word (sp);
+	  sp += 4;
+	  State.regs[REG_E0 + 2] = load_word (sp);
+	  sp += 4;
+	}
+    }
 
   /* And make sure to update the stack pointer.  */
   State.regs[REG_SP] = sp;
@@ -3210,6 +3836,9 @@
 8.0xcf+8.REGS:S1a:::movm
 "movm"
 *mn10300
+
+*am33
+
 {
   /* OP_CF00 (); */
   unsigned long sp = State.regs[REG_SP];
@@ -3218,6 +3847,38 @@
   PC = cia;
   mask = REGS;
 
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+    {
+      if (mask & 0x4)
+	{
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 2]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 3]);
+	}
+
+      if (mask & 0x2)
+        {
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 4]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 5]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 6]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 7]);
+	}
+
+      if (mask & 0x1)
+	{
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 0]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 1]);
+	  sp -= 16;
+	  /* Need to save MDQR, MCRH, MCRL, and MCVF */
+	}
+    }
 
   if (mask & 0x80)
     {
@@ -3271,6 +3932,9 @@
 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
 "call"
 *mn10300
+
+*am33
+
 {
   /* OP_CD000000 (); */
   unsigned int next_pc, sp;
@@ -3283,6 +3947,38 @@
 
   mask = REGS;
 
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+    {
+      if (mask & 0x4)
+	{
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 2]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 3]);
+	}
+
+      if (mask & 0x2)
+        {
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 4]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 5]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 6]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 7]);
+	}
+
+      if (mask & 0x1)
+	{
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 0]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 1]);
+	  sp -= 16;
+	  /* Need to save MDQR, MCRH, MCRL, and MCVF */
+	}
+    }
 
   if (mask & 0x80)
     {
@@ -3342,6 +4038,9 @@
 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
 "call"
 *mn10300
+
+*am33
+
 {
   /* OP_DD000000 (); */
   unsigned int next_pc, sp;
@@ -3355,6 +4054,38 @@
 
   mask = REGS;
 
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+    {
+      if (mask & 0x4)
+	{
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 2]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 3]);
+	}
+
+      if (mask & 0x2)
+        {
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 4]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 5]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 6]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 7]);
+	}
+
+      if (mask & 0x1)
+	{
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 0]);
+	  sp -= 4;
+	  store_word (sp, State.regs[REG_E0 + 1]);
+	  sp -= 16;
+	  /* Need to save MDQR, MCRH, MCRL, and MCVF */
+	}
+    }
 
   if (mask & 0x80)
     {
@@ -3413,6 +4144,9 @@
 8.0xdf+8.REGS+8.IMM8:S2:::ret
 "ret"
 *mn10300
+
+*am33
+
 {
   /* OP_DF0000 (); */
   unsigned int sp, offset;
@@ -3425,6 +4159,40 @@
   offset = -4;
   mask = REGS;
 
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+    {
+
+      if (mask & 0x4)
+	{
+	  State.regs[REG_E0 + 2] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 3] = load_word (sp + offset);
+	  offset -= 4;
+	}
+
+      if (mask & 0x2)
+        {
+	  State.regs[REG_E0 + 4] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 5] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 6] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 7] = load_word (sp + offset);
+	  offset -= 4;
+	}
+
+      if (mask & 0x1)
+	{
+	  /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+	  offset -= 16;
+	  State.regs[REG_E0 + 0] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 1] = load_word (sp + offset);
+	  offset -= 4;
+	}
+
+    }
 
   if (mask & 0x80)
     {
@@ -3478,6 +4246,9 @@
 8.0xde+8.REGS+8.IMM8:S2:::retf
 "retf"
 *mn10300
+
+*am33
+
 {
   /* OP_DE0000 (); */
   unsigned int sp, offset;
@@ -3491,6 +4262,40 @@
   offset = -4;
   mask = REGS;
 
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+    {
+
+      if (mask & 0x4)
+	{
+	  State.regs[REG_E0 + 2] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 3] = load_word (sp + offset);
+	  offset -= 4;
+	}
+
+      if (mask & 0x2)
+        {
+	  State.regs[REG_E0 + 4] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 5] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 6] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 7] = load_word (sp + offset);
+	  offset -= 4;
+	}
+
+      if (mask & 0x1)
+	{
+	  /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+	  offset -= 16;
+	  State.regs[REG_E0 + 0] = load_word (sp + offset);
+	  offset -= 4;
+	  State.regs[REG_E0 + 1] = load_word (sp + offset);
+	  offset -= 4;
+	}
+
+    }
 
   if (mask & 0x80)
     {
@@ -3536,3 +4341,6 @@
   nia = PC;
 }
 
+
+:include::am33:am33.igen
+
diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
index b794fd05419..0e419432ce8 100644
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300_sim.h
@@ -115,6 +115,13 @@ extern struct simops Simops[];
 #define REG_LIR 12
 #define REG_LAR 13
 #define REG_MDRQ 14
+#define REG_E0 15
+#define REG_SSP 23
+#define REG_MSP 24
+#define REG_USP 25
+#define REG_MCRH 26
+#define REG_MCRL 27
+#define REG_MCVF 28
 
 #if WITH_COMMON
 /* These definitions conflict with similar macros in common.  */