New simulator for Fujitsu frv contributed by Red Hat.

39 files changed, 145235 insertions, 0 deletions

diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,2358 @@
+2003-08-20  Micheal Snyder  <msnyder@redhat.com>
+
+	* All generated files: Regenerate.
+
+2001-10-11  Dave Brolley  <brolley@redhat.com>
+
+	* cpu.h,decode.c,decode.h,sem.c: Regenerate.
+
+2001-10-09  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_rett): Halt if PSR.S and PSR.ET are both set or both
+	not set.
+	* reset.c (frv_hardware_reset): Invalidate both caches.
+	* registers.c: Update init, reset and read-only masks for all registers
+	on all machines.
+	* profile.h (cur_gr_complex): New field of FRV_PROFILE_STATE
+	(prev_gr_complex): New field of FRV_PROFILE_STATE
+	(set_use_is_gr_complex): New function.
+	(set_use_not_gr_complex): New function.
+	(use_is_gr_complex): New function.
+	(decrease_GR_busy): New function.
+	* profile.c (reset_gr_flags): New function.
+	(reset_cc_flags): New function.
+	(set_use_is_gr_complex): New function.
+	(set_use_not_gr_complex): New function.
+	(use_is_gr_complex): New function.
+	(update_latencies): Reset gr and cc flags when latency reaches 0.
+	(decrease_GR_busy): New function.
+	* profile-fr400.h (fr500_reset_acc_flags): Removed.
+	(fr500_reset_cc_flags): New function.
+	* profile-fr500.c (frvbf_model_fr400_u_*): Reflect latencies from fr500
+	LSI version 1.41.
+	* profile-fr400.h (fr400_reset_gr_flags): New function.
+	(fr400_reset_fr_flags): New function.
+	(fr400_reset_acc_flags): New function.
+	* profile-fr400.c (set_use_not_media_p4): New function.
+	(set_use_not_media_p6): New function.
+	(set_acc_use_not_media_p2): New function.
+	(set_acc_use_not_media_p4): New function.
+	(fr400_reset_gr_flags): New function.
+	(fr400_reset_fr_flags): New function.
+	(fr400_reset_acc_flags): New function.
+	(frvbf_model_fr400_u_*): Reflect latencies from fr400 LSI version 1.1.
+	(frvbf_model_fr400_u_media_hilo): New function.
+	* pipeline.c (frv_vliw_setup_insn): Don't clear MSR0.MTT.
+	* memory.c (fr400_check_data_read_address): Check address range only
+	for double word loads. Don't check alignment here.
+	(fr400_check_readwrite_address): New function.
+	(fr500_check_readwrite_address): New function.
+	(check_readwrite_address): New function.
+	(fr500_check_insn_read_address): Correct address ranges.
+	(frvbf_read_mem_*): Check address range here.
+	(frv_address_forbidden): Removed.
+	(fr400_check_write_address): New function.
+	(check_write_address): New function.
+	(frvbf_write_mem_*): Don't check address range here.
+	(frvbf_mem_set_*): Check address range here.
+	* interrupts.c (frv_queue_data_access_error_interrupt): Now takes an
+	address as second argument.
+	(frv_queue_data_access_exception_interrupt): New function.
+	(frv_queue_illegal_instruction_interrupt): Generate fp_exception for
+	media insns on fr400.
+	(frv_queue_non_implemented_instruction_interrupt): Generate mp_exception
+	for media insns on fr400.
+	(frv_detect_insn_access_interrupts): Don't check for illegal addresses
+	of insns here.  Check for MTRAP insn if PSR.EM is not set.
+	(frv_set_mp_exception_registers): Only set MSR0.MTT if it is not already
+	set.
+	(set_exception_status_registers): Do not always set EPCR. Set EAR for
+	data_acess_error only if not fr400.
+	* frv.c (do_media_average): New function.
+	(frvbf_media_average): New function.
+	(frvbf_insn_cache_invalidate): Check for illegal invocation.
+	(frvbf_data_cache_invalidate): Ditto.
+	(frvbf_data_cache_flush): Ditto.
+	* frv-sim.h (GET_FSR_QNE): New macro.
+	(frv_msr_mtt): Remove MTT_SEQUENCE_ERROR.
+	(GET_MSR_SRDAV): New macro.
+	(GET_MSR_RDAV): New macro.
+	(GET_MSR_RD): New macro.
+	(frv_queue_data_access_error_interrupt): Now takes an address as second
+	argument.
+	(frv_address_forbidden): Removed.
+	* cache.c (non_cache_access): Correct address ranges. Now takes cache
+	as first argument.
+	* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2001-08-20  Dave Brolley  <brolley@redhat.com>
+
+	* sim-main.h (_sim_cpu): New field 'elf_flags'.
+	* sim-if.c (sim_open): Extract the elf_flags from the input file and
+	save them with each cpu.
+	* mloop.in (main loop): Pass elf flags to frv_vliw_reset.  Set
+	last_insn_p before executing the insn.
+	* cache.c (frv_cache_invalidate): Flush scache if this is the cpu's
+	insn cache.
+	(frv_cache_invalidate_all): Ditto.
+
+2001-08-20  Richard Sandiford  <rsandifo@redhat.com>
+
+	* traps.c (syscall_read_mem): Flush the data cache before reading.
+	(syscall_write_mem): Flush the data cache before writing.
+	Invalidate both caches.
+
+2001-07-05  Ben Elliston  <bje@redhat.com>
+
+	* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
+	(stamp-cpu): Likewise.
+
+2001-05-23  Dave Brolley  <brolley@redhat.com>
+
+	* profile-fr400.c (acc_use_is_media_p2): New function.
+	(frvbf_model_fr400_u_media_2): Account for latency of output
+	accumulators.
+	(frvbf_model_fr400_u_media_2_quad): Ditto.
+	(frvbf_model_fr400_u_media_2_acc): New function.
+	(frvbf_model_fr400_u_media_2_acc_dual): New function.
+	(frvbf_model_fr400_u_media_2_add_sub): New function.
+	(frvbf_model_fr400_u_media_2_add_sub_dual): New function.
+	(frvbf_model_fr400_u_media_3_dual): New function.
+	(frvbf_model_fr400_u_media_4_acc_dual): New function.
+	* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2001-05-15  Dave Brolley  <brolley@redhat.com>
+
+	* registers.c (fr400_spr): Enable write access to HSR0.CBM.
+	* profile.h (FRV_PROFILE_STATE): New field 'all_cache_entries'.
+	* profile.c (CACHE_QUEUE_ELEMENT): New 'all' field.
+	(request_cache_flush): Save 'all' argument.
+	(request_cache_invalidate): Save all_cache_entries from profile state
+	to 'all' field of the request.
+	(submit_cache_request): Pass the 'all' field of the request to
+	frv_cache_request_invalidate.
+	* frv.c (frv_insn_cache_invalidate): Add new 'all' parameter. Perform
+	operation even if HSR0.ICE is not set.
+	(frv_data_cache_invalidate): Add new 'all' parameter. Perform
+	operation even if HSR0.DCE is not set.
+	(frv_data_cache_flush): Ditto.
+	* frv-sim.h (frv_insn_cache_invalidate): Add new 'all' parameter.
+	(frv_data_cache_invalidate): Add new 'all' parameter.
+	(frv_data_cache_flush): Add new 'all' parameter.
+	* cache.h (FRV_CACHE_INVALIDATE_REQUEST): Add new 'all' field.
+	(frv_cache_request_invalidate): Add new 'all' parameter.
+	* cache.c (frv_cache_request_invalidate): Add new 'all' parameter. Save
+	its value in the invalidate request.
+	(address_interference): Accept the value '-1' for the address argument
+	to mean 'any address'.
+	(handle_req_invalidate): Handle request to invalidate all cache lines.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2001-05-14  Dave Brolley  <brolley@redhat.com>
+
+	* profile.h (past_first_p): New field of profiling state.
+	(branch_penalty): Ditto.
+	(branch_hint): Ditto.
+	(update_branch_penalty): New function.
+	* profile.c (frvbf_model_insn_after): Reset past_first_p and
+	branch_address fields of the profiling state.
+	(frvbf_model_branch): New function.
+	(update_branch_penalty): New function.
+	* profile-fr500.c (frvbf_model_fr500_u_branch): Remove ICCi_3 and
+	FCCi_3 inputs.
+	(frvbf_model_fr500_u_trap): New function.
+	(frvbf_model_fr500_u_check): New function.
+	(frvbf_model_fr500_u_media_dual_htob): post-processing latency is 3
+	cycles.
+	* profile-fr400.c (frvbf_model_fr400_u_branch): Set branch penalties
+	as documented in the fr400 LSI. Remove ICCi_3 and FCCi_3 inputs.
+	(frvbf_model_fr400_u_media_dual_expand): Check resource usage as
+	documented in teh fr400 LSI.
+	(frvbf_model_fr400_u_media_dual_htob): Ditto.
+	(frvbf_model_fr400_u_media_dual_unpack): Removed.
+	(frvbf_model_fr500_u_trap): New function.
+	(frvbf_model_fr500_u_check): New function.
+	* mloop.in (simulate_dual_insn_prefetch): New function.
+	(@cpu@_simulate_insn_prefetch): Call simulate_dual_insn_prefetch with
+	arguments for each machine type.
+	* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2001-05-09  Dave Brolley  <brolley@redhat.com>
+
+	* Makefile.in (profile.o): Add profile-fr400.h as a dependency.
+	(profile-fr400.o): New target.
+	* profile.c: New file.
+	* profile.h: New file.
+	* profile-fr400.c: New file.
+	* profile-fr400.h: New file.
+	* profile-fr500.c: New file.
+	* profile-fr500.h: New file.
+	* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2001-05-02  Dave Brolley  <brolley@redhat.com>
+
+	* sim-main.h (profile.h): #include it.
+	(CPU_PROFILE_STATE): New macro.
+	(profile_state): New frv specific cpu field.
+	* reset.c (frv_initialize): insn_fetch_address and branch_address now
+	part of global profiling state.
+	* Makefile.in (SIM_OBJS): Add profile.o and profile-fr500.o.
+	(SIM_EXTRA_DEPS): Add profile.h.
+	(registers.o): Correct name of source file.
+	(profile.o): New target.
+	(profile-fr500.o): New target.
+	* frv-sim.h: Move profile related data structures to profile.h.
+	* frv.c: Move fr500 specific functions to profile-fr500.c.
+	* cpu.h: Regenerated.
+
+2001-04-27  Dave Brolley  <brolley@redhat.com>
+
+	* sim-main.h (CPU_PIPELINE): Renamed to CPU_VLIW.
+	* interrupts.c: Rename FRV_PIPELINE to FRV_VLIW.
+	Rename pipeline to vliw. Rename CPU_PIPELINE to CPU_VLIW.
+	Rename PIPE_* to UNIT_*.
+	(frv_queue_illegal_instruction_interrupt): Use
+	frv_is_float_insn and frv_is_media_insn.
+	(frv_queue_non_implemented_instruction_interrupt): Ditto.
+	(frv_detect_insn_access_interrupts): Ditto.
+	* frv.c: Rename FRV_PIPELINE to FRV_VLIW. Rename pipeline to vliw.
+	Rename CPU_PIPELINE to CPU_VLIW. Rename PIPE_* to UNIT_*.
+	* memory.c: Ditto.
+	* pipeline.c: Ditto.
+	* mloop.in: Ditto.
+	* frv-sim.h (frv_pipeline_setup_insn): Renamed to frv_vliw_setup_insn.
+	* cache.c: Rename PIPE_* to UNIT_*.
+
+2001-04-24  Dave Brolley  <brolley@redhat.com>
+
+	* frv.c (frvbf_load_quad_GR): Delete have_data and hsr0.
+	(frvbf_load_quad_FRint): Ditto.
+	(frvbf_load_quad_CPR): Ditto.
+	* cache.c (frv_cache_init): Initialize cache for fr400 vs other
+	machines.
+	(bfd.h): #include it.
+	(non_cache_access): Update for revised fr500 and for fr400.
+	* registers.c (frv_spr): Don't reset PSR.PS.
+	(fr500_spr): Ditto.
+	(frv_reset_spr): Set PSR.PS to the former value of PSR.S.
+
+2001-04-23  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_core_signal): On fr400, generate data_access_error.
+	(frvbf_media_cr_not_aligned): On fr400, generate illegal_instruction.
+	(frvbf_media_acc_not_aligned): Ditto.
+	(frvbf_media_register_not_aligned): Ditto.
+	(frvbf_division_exception): Use GET_ISR_EDE.
+	* registers.c (frv_check_spr_read_access): New function.
+	(frv_check_spr_write_access): New function.
+	(frv_check_spr_access): Deleted.
+	(frv_check_register_access): On fr400, generate illegal_instruction.
+	* memory.c (fr400_check_data_read_address): New function.
+	(fr500_check_data_read_address): Ditto.
+	(check_data_read_address): Ditto.
+	(fr400_check_insn_read_address): Ditto.
+	(fr500_check_insn_read_address): Ditto.
+	(check_insn_read_address): Ditto.
+	(frvbf_read_mem_QI): Call check_data_read_access.
+	(frvbf_read_mem_UQI): Ditto.
+	(frvbf_read_mem_HI): Ditto.
+	(frvbf_read_mem_UHI): Ditto.
+	(frvbf_read_mem_SI): Ditto.
+	(frvbf_read_mem_DI): Ditto.
+	(frvbf_read_mem_DF): Ditto.
+	(frvbf_read_imem_USI): Call check_insn_read_access.
+	(frv_address_forbidden): Now takes cpu as first argument. Check based
+	on machine type.
+	(fr400_mem_address_unaligned): New function.
+	(fr500_mem_address_unaligned): Ditto.
+	(check_write_address): Ditto.
+	(frvbf_mem_set_QI): Call check_write_address.
+	(frvbf_mem_set_HI): Ditto.
+	(frvbf_mem_set_SI): Ditto.
+	(frvbf_mem_set_DI): Ditto.
+	(frvbf_mem_set_DF): Ditto.
+	(frvbf_mem_set_XI): Ditto.
+	* interrupts.c (bfd.h): #include it.
+	(frv_queue_data_access_error_interrupt): New function.
+	(frv_queue_instruction_access_error_interrupt): New function.
+	(frv_queue_instruction_access_exception_interrupt): New function.
+	(frv_queue_illegal_instruction_interrupt): No fp_exception on fr400.
+	(frv_queue_non_implemented_instruction_interrupt): Ditto.
+	(frv_detect_insn_access_interrupts): Reorder tests to match priority
+	from the LSI manual.
+	(set_isr_exception_fields): Accumulate dtt bits.
+	* frv.c (check_register_alignment): New function.
+	(check_fr_register_alignment): New function.
+	(check_memory_alignment): New function.
+	(frvbf_h_gr_double_get_handler): Call check_register_alignment.
+	(frvbf_h_gr_double_set_handler): Ditto.
+	(frvbf_h_cpr_double_get_handler): Ditto.
+	(frvbf_h_cpr_double_set_handler): Ditto.
+	(frvbf_h_gr_quad_set_handler): Ditto.
+	(frvbf_h_cpr_quad_set_handler): Ditto.
+	(frvbf_h_fr_double_get_handler): Call check_fr_register_alignment.
+	(frvbf_h_fr_double_set_handler): Ditto.
+	(frvbf_h_fr_quad_set_handler): Ditto.
+	(frvbf_h_spr_get_handler): Call frv_check_spr_read_access.
+	(frvbf_h_spr_set_handler): Call frv_check_spr_write_access.
+	(frvbf_load_quad_GR): Call check_memory_aligment.
+	(frvbf_load_quad_FRint): Ditto.
+	(frvbf_load_quad_CPR): Ditto.
+	(frvbf_store_quad_GR): Call check_memory_aligment and
+	check_register_alignment.
+	(frvbf_store_quad_FRint): Ditto.
+	(frvbf_store_quad_CPR): Ditto.
+	(frvbf_signed_integer_divide: Use GET_ISR_EDEM.
+	* frv-sim.h (H_SPR_ACC0): New macro.
+	(H_SPR_ACC63): New macro.
+	(H_SPR_ACCG0): New macro.
+	(H_SPR_ACCG63): New macro.
+	(frv_dtt): New enumerator.
+	(GET_ISR_EDE): Renamed from GET_ISR_EDEM.
+	(GET_ISR_DTT): New macro.
+	(frv_queue_data_access_error_interrupt): New function.
+	(frv_queue_instruction_access_error_interrupt): New function.
+	(frv_queue_instruction_access_exception_interrupt): New function.
+	(frv_address_forbidden): Now takes cpu as first argument.
+	* cpu.h: Regenerate.
+
+2001-04-10  Dave Brolley  <brolley@redhat.com>
+
+	* registers.c (fr500_spr): Add new fields to fr500 PSR register.
+	(fr500_spr): Add STBAR and MMCR unimplemented registers for fr500.
+	(fr400_spr): Implement SPR registers for fr400.
+	(frv_register_control_init): Handle bfd_mach_fr400 properly.
+	* frv.c (spr_bpsr_get_handler): Mask field before shifting.
+	(spr_psr_get_handler): Ditto.
+	(spr_ccr_get_handler): Ditto.
+	(spr_cccr_get_handler): Ditto.
+	(frvbf_clear_accumulators): Only 4 accumulators on fr400.
+	* frv-sim.h: Update comment about MCCR_* macros.
+	* cpu.c,cpu.h: Regenerate.
+
+2001-04-05  Dave Brolley  <brolley@redhat.com>
+
+	* cpu.h,decode.c,model.c,sem.c:	Regenerate.
+
+2001-04-05  Dave Brolley  <brolley@redhat.com>
+
+	* reset.c: Update copyright.
+	* registers.c (frv_register_control_init): Handle bfd_mach_fr400.
+	* frv.c (frvbf_model_fr400_u_exec): New function.
+	* Makefile.in (stamp-cpu): Add fr400 to list of machines.
+	* arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
+	Regenerate.
+
+2000-11-22  Dave Brolley  <brolley@redhat.com>
+
+	* arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
+	Regenerate.
+
+2000-11-10  Dave Brolley  <brolley@redhat.com>
+
+	* decode.c: Regenerate.
+
+2000-09-12  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_sim_engine_halt_hook): New function.
+	(frv_itrap): Caches now invalidated in sim_engine_halt via
+	SIM_ENGINE_HALT_HOOK.
+	(frv_break): Ditto.
+	* sim-main.h (frv_sim_engine_halt_hook): New function.
+	(SIM_ENGINE_HALT_HOOK): New macro.
+	(SIM_ENGINE_RESTART_HOOK): New macro.
+	* interrupts.c: Call to frv_term now done within sim_engine_halt via
+	SIM_ENGINE_HALT_HOOK.
+
+2000-09-08  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_itrap): Invalidate and flush the data and insn caches
+	respectively when stopping for a breakpoint.
+	(frv_break): Ditto.
+	* cache.h (frv_cache_invalidate_all): New function.
+	* cache.c (frv_cache_invalidate_all): New function.
+
+2000-09-05  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_break): If SIM_HAVE_BREAKPOINTS, call
+	sim_handle_breakpoint. Otherwise if environment != operating call
+	sim_engine_halt. Otherwise handle normally.
+	* interrupts.c (frv_queue_break_interrupt): Don't handle debugger
+	breakpoints here. Moved to frv_break in traps.c.
+
+	* sem.c: Regenerate.
+
+2000-09-01  Dave Brolley  <brolley@redhat.com>
+
+        * interrupts.c (frv_queue_break_interrupt): Call sim_handle_breakpoint
+	before queuing an interrupt in order to allow 'break' to be used as
+	the breakpoint insn.
+
+2000-08-29  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_itrap): Invalidate the insn cache at a breakpoint.
+
+2000-07-27  Dave Brolley  <brolley@redhat.com>
+
+	* cpu.h,decode.c: Rebuild.
+
+2000-07-26  Dave Brolley  <brolley@redhat.com>
+
+	* frv.c (spr_cccr_get_handler): Change CRx to CCx.
+	(spr_cccr_set_handler): Change CRx to CCx.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+2000-07-24  Dave Brolley  <brolley@redhat.com>
+
+	* sem.c: Regenerate.
+	* frv.c (frvbf_unsigned_integer_divide): Queue a write for the result.
+	Don't write it directly.
+
+Thu Jul  6 13:51:12 2000  Dave Brolley  <brolley@topaz>
+
+	* configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2000-07-05  Ben Elliston  <bje@redhat.com>
+
+	* configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2000-06-28  Dave Brolley  <brolley@redhat.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+2000-06-21  Dave Brolley  <brolley@redhat.com>
+
+	* pipeline.c: All code except frv_pipeline_setup_insn moved to
+	frv.opc.
+	* mloop.in (main loop): frv_pipeline_add_insn broken up into
+	frv_pipeline_add_insn and frv_pipeline_setup_insn.
+	* frv-sim.h: Move pipeline status code to frv.opc.
+	* model.c: Regenerate.
+
+2000-06-12  Dave Brolley  <brolley@redhat.com>
+
+	* options.c (frv_option_handler): --profile-parallel implies
+	--profile-model.
+	* mloop.in (fetch_buffer): Removed.
+	(@cpu@_simulate_insn_prefetch): Monitoring of fetch buffer moved to
+	run_caches.  Use cache directly if not counting cycles.  Don't use
+	cache at all if not counting cycles and cache not enabled.
+	* frv.c (frv_insn_fetch_buffer): New global variable. 
+	(run_caches): Monitor the status of insn prefetch requests.
+	* frv-sim.h (FRV_INSN_FETCH_BUFFER): New struct type.
+	(frv_insn_fetch_buffer): New global variable.
+
+2000-06-12  Dave Brolley  <brolley@redhat.com>
+
+	* mloop.in (fetch_buffer): New static struct.
+	(@cpu@_simulate_insn_prefetch): Rewritten.
+	* cache.c (frv_cache_request_invalidate): Don't invalidate return
+	buffer.
+	(address_interference): Defer to any WAR request in either pipeline.
+
+2000-06-09  Dave Brolley  <brolley@redhat.com>
+
+	* pipeline.c (insns_in_slot): New Array.
+	(frv_pipeline_add_insn): Call COUNT_INSNS_IN_SLOT.
+	* options.c (frv_options): Remove 'NONBLOCK' argument from data-cache
+	option.
+	(parse_cache_option): New function.
+	(frv_option_handler): Call parse_cache_option.
+	* frv.c (vliw_branch_taken): New variable.
+	(vliw_load_stall): New variable.
+	(handle_resource_wait): Update vliw_load_stall.
+	(frvbf_model_insn_before): Initialize vliw_branch_taken and
+	vliw_load_stall.
+	(frvbf_model_insn_after): Increment PROFILE_MODEL_LOAD_STALL_CYCLES.
+	(load_wait_for_FR): Update vliw_load_stall.
+	(load_wait_for_GR): Update vliw_load_stall.
+	(load_wait_for_FRdouble): Update vliw_load_stall.
+	(load_wait_for_GRdouble): Update vliw_load_stall.
+	(frvbf_model_fr500_u_branch): Count branches taken and not taken.
+	(slot_names): New static array.
+	(print_parallel): Now takes second argument 'verbose'. Print cycles per
+	VLIW insn and instructions per cycle. Also tabulate the number of insns
+	in each type of VLIW slot.
+	(frv_profile_info): Call print_parallel with new second argument.
+	* frv-sim.h (insn_in_slot): New array.
+	(COUNT_INSNS_IN_SLOT): New macro.
+	(INSNS_IN_SLOT): New macro.
+	* cache.c: Remove references to non_blocking_count. Remove references to
+	last_was_hit. Remove references to req_none.
+	(handle_req_store): Adjust statistics before requeuing the store
+	request.
+	(handle_req_WAR): Don't let the WAR request affect the cache statistics.
+	* cache.h: Remove references to non_blocking_count. Remove references to
+	last_was_hit. Remove references to req_none.
+	* model.c: Regenerate.
+
+2000-06-08  Dave Brolley  <brolley@redhat.com>
+
+	* frv.c (request_complete): Copy load data from the correct return
+	buffer.
+
+2000-06-07  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_core_signal): Call frv_term before exiting.
+	(frv_itrap): Call frv_term before exiting.
+	(next_available_nesr): Make sure NECR is implemented before reading it.
+	(next_valid_nesr): Ditto.
+	(frvbf_check_non_excepting_load): Ditto.
+	(frvbf_clear_ne_flags): Ditto.
+	(frvbf_commit): Ditto.
+	(frvbf_check_recovering_store): Delay cache operation if 'model_insn'.
+	* sim-main.h (_sim_cpu): Add load_address, load_length, load_flag and
+	store_flag members.
+	(CPU_LOAD_ADDRESS): New macro.
+	(CPU_LOAD_LENGTH): New macro.
+	(CPU_LOAD_SIGNED): New macro.
+	(CPU_LOAD_LOCK): New macro.
+	* reset.c (frv_term): New function.
+	(frv_power_on_reset): Use SETMEMSI if the cache is not enabled.
+	(frv_hardware_reset): Use SETMEMSI if the cache is not enabled.
+	(frv_software_reset): Use SETMEMSI if the cache is not enabled.
+	* mloop.in (execute): Call FRV_COUNT_CYCLES to decide whether to model
+	the insn. Model the insn in two passes. One before and one after
+	execution.
+	(cache_reqno): new static variable.
+	(@cpu@_simulate_insn_prefetch): Model fetch latency by waiting for the
+	cache rather than assuming a fixed latency.
+	(xinit): Turn on PROFILE_MODEL_P before each vliw insn if the timer is
+	enabled so that modeling data is collected by cgen during execution.
+	(full-exec): Restore PROFILE_MODEL_P after each vliw insn.
+	* memory.c (data_non_cache_access): Removed.
+	(insn_non_cache_access): Removed.
+	(frvbf_read_mem_QI): Delay read operation if 'model_insn'.
+	(frvbf_read_mem_UQI): Delay read operation if 'model_insn'.
+	(frvbf_read_mem_HI): Delay read operation if 'model_insn'.
+	(frvbf_read_mem_UHI): Delay read operation if 'model_insn'.
+	(frvbf_read_mem_SI): Delay read operation if 'model_insn'.
+	(frvbf_read_mem_DI): Delay read operation if 'model_insn'.
+	(frvbf_read_mem_DF): Delay read operation if 'model_insn'.
+	(frvbf_read_imem_USI): Read the cache or ememory passively.
+	(frvbf_write_mem_QI): Don't check for non-cache access here.
+	(frvbf_write_mem_UQI): Call frvbf_write_mem_QI.
+	(frvbf_write_mem_HI): Don't check for non-cache access here.
+	(frvbf_write_mem_UHI): Call frvbf_write_mem_QI.
+	(frvbf_write_mem_SI): Don't check for non-cache access here.
+	(frvbf_write_mem_DI): Don't check for non-cache access here.
+	(frvbf_write_mem_DF): Don't check for non-cache access here.
+	(frvbf_mem_set_QI): Use cycle-accurate cache write if 'model_insn'.
+	(frvbf_mem_set_HI): Use cycle-accurate cache write if 'model_insn'.
+	(frvbf_mem_set_SI): Use cycle-accurate cache write if 'model_insn'.
+	(frvbf_mem_set_DI): Use cycle-accurate cache write if 'model_insn'.
+	(frvbf_mem_set_DF): Use cycle-accurate cache write if 'model_insn'.
+	(frvbf_mem_set_XI): Use cycle-accurate cache write if 'model_insn'.
+	* interrupts.c (check_reset): Read the cache and memory passively.
+	(frv_program_or_software_interrupt): Call frv_term before calling
+	sim_engine_halt.
+	* frv.c (all modeling functions): Break into two passes. One before
+	execuetion and one after. call load_wait_for_* for all GR and FR
+	registers.
+	(frvbf_load_quad_GR): Delay performing the load if 'model_insn'.
+	(frvbf_load_quad_FRint): Delay performing the load if 'model_insn'.
+	(frvbf_load_quad_CPR): Delay performing the load if 'model_insn'.
+	(frvbf_insn_cache_preload): Delay cache operation if 'model_insn'.
+	(frvbf_data_cache_preload): Delay cache operation if 'model_insn'.
+	(frvbf_insn_cache_unlock): Delay cache operation if 'model_insn'.
+	(frvbf_data_cache_unlock): Delay cache operation if 'model_insn'.
+	(frvbf_insn_cache_invalidate): Delay cache operation if 'model_insn'.
+	(frvbf_data_cache_invalidate): Delay cache operation if 'model_insn'.
+	(frvbf_data_cache_flush): Delay cache operation if 'model_insn'.
+	(model_insn): New global variable.
+	(fr_ptime): New array.
+	(cache_request): New enumeration.
+	(CACHE_QUEUE_ELEMENT): New struct type.
+	(CACHE_QUEUE_SIZE): New macro.
+	(cache_queue): New static struct.
+	(request_cache_load): New function.
+	(request_cache_flush): New function.
+	(request_cache_invalidate): New function.
+	(request_cache_preload): New function.
+	(request_cache_unlock): New function.
+	(submit_cache_request): New function.
+	(activate_cache_requests): New function.
+	(load_pending_for_register): New function.
+	(flush_pending_for_address): New function.
+	(remove_cache_queue_element): New function.
+	(copy_load_data): New function.
+	(request_complete): New function.
+	(run_caches): New function.
+	(frv_model_trace_wait_cycles): New function.
+	(wait_for_flush): New function.
+	(frvbf_model_insn_before): Insn prefect wait now modeled in
+	frvbf_simulate_insn_prefetch. Incremement vliw_insns here. Call
+	wait_for_flush.
+	(frvbf_model_insn_after): Call activate_cache_requests. Don't increment
+	vliw_insns here anymore.
+	(update_FR_latency_for_load): New function.
+	(update_FRdouble_latency_for_load): New function.
+	(update_FR_ptime): New function.
+	(update_FRdouble_ptime): New function.
+	(update_GR_latency_for_swap): New function.
+	(load_wait_for_GR): New function.
+	(load_wait_for_FR): New function.
+	(load_wait_for_GRdouble): New function.
+	(load_wait_for_FRdouble): New function.
+	(frvbf_model_fr500_u_ici): New function.
+	(frvbf_model_fr500_u_dci): New function.
+	(frvbf_model_fr500_u_dcf): New function.
+	(frvbf_model_fr500_u_icpl): New function.
+	(frvbf_model_fr500_u_dcpl): New function.
+	(frvbf_model_fr500_u_icul): New function.
+	(frvbf_model_fr500_u_dcul): New function.
+	* frv-sim.h (frv_term): New function.
+	(insn_non_cache_access): Removed.
+	(FRV_COUNT_CYCLES): New macro.
+	(frv_save_peofile_model_p): New global variable.
+	(model_insn): New enumerated global variable.
+	(frv_model_advance_cycles): New function.
+	(frv_model_trace_wait_cycles): New function.
+	* cache.h (FRV_CACHE_REQUEST_KIND): New enumeration.
+	(FRV_CACHE_WAR_REQUEST): New struct type.
+	(FRV_CACHE_STORE_REQUEST): New struct type.
+	(FRV_CACHE_INVALIDATE_REQUEST): New struct type.
+	(FRV_CACHE_PRELOAD_REQUEST): New struct type.
+	(FRV_CACHE_REQUEST): New struct type.
+	(FRV_CACHE_RETURN_BUFFER): New struct type.
+	(FRV_CACHE_FLUSH_STATUS): New struct type.
+	(FRV_CACHE_STATUS): New struct type.
+	(FRV_CACHE_STAGE): New struct type.
+	(FRV_CACHE_STAGES): New enumeration.
+	(FRV_CACHE_WAR): New struct type.
+	(FRV_CACHE_PIPELINE): New struct type.
+	(FRV_CACHE_ARS): New struct type.
+	(FRV_CACHE_STATISTICS): New struct type.
+	(FRV_CACHE): Add pipeline, statistics, BARS and NARS.
+	(CACHE_RETURN_DATA): 'return_buffer' is now within 'status'.
+	(CACHE_RETURN_DATA_ADDRESS): New macro.
+	(frv_cache_read): Now takes pipe index as second argument.
+	(frv_cache_enabled): New function.
+	(frv_cache_request_load): New function.
+	(frv_cache_request_store): New function.
+	(frv_cache_request_invalidate): New function.
+	(frv_cache_request_preload): New function.
+	(frv_cache_request_unlock): New function.
+	(frv_cache_run): New function.
+	(frv_cache_read_passive_SI): New function.
+	(frv_cache_data_in_buffer): New function.
+	(frv_cache_data_flushed): New function.
+	* cache.c (frv_cache_init): Initialize pipelines and xARS registers.
+	(frv_cache_enabled): New function.
+	(non_cache_access): New function.
+	(write_data_to_memory): Count write accesses for each mode. Write to
+	memory using sim_core_write_unaligned_1;
+	(read_data_from_memory): New function.
+	(fill_line_from_memory): Use read_data_from_memory.
+	(copy_line_to_return_buffer): New function.
+	(copy_memory_to_return_buffer): New function.
+	(set_return_buffer_reqno): New function.
+	(frv_cache_read): Now takes pipe index as second argument. Check for
+	non-cache access.
+	(frv_cache_preload): Check for non-cache access.
+	(frv_cache_unlock): Check for non-cache access.
+	(invalidate_return_buffer): New function.
+	(frv_cache_invalidate): Check for non-cache access.
+	(convert_slot_to_index): New function.
+	(FREE_CHAIN_SIZE): New macro.
+	(frv_cache_request_free_chain): New static variable.
+	(frv_store_request_free_chain): New static variable.
+	(allocate_new_cache_requests): New function.
+	(new_cache_request): New function.
+	(free_cache_request): New function.
+	(new_store_request): New function.
+	(pipeline_remove_request): New function.
+	(pipeline_add_request): New function.
+	(pipeline_requeue_request): New function.
+	(next_priority): New function.
+	(add_WAR_request): New function.
+	(pipeline_next_request): New function.
+	(pipeline_stage_request): New function.
+	(advance_pipelines): New function.
+	(frv_cache_request_load): New function.
+	(frv_cache_request_store): New function.
+	(frv_cache_request_invalidate): New function.
+	(frv_cache_request_preload): New function.
+	(frv_cache_request_unlock): New function.
+	(address_interference): New function.
+	(wait_for_WAR): New function.
+	(wait_in_WAR): New function.
+	(handle_req_load): New function.
+	(handle_req_preload): New function.
+	(handle_req_store): New function.
+	(handle_req_invalidate): New function.
+	(handle_req_unlock): New function.
+	(handle_req_WAR): New function.
+	(arbitrate_requests): New function.
+	(move_ARS_to_WAR): New function.
+	(decrease_latencies): New function.
+	(frv_cache_run): New function.
+	(frv_cache_read_passive_SI): New function.
+	(frv_cache_data_in_buffer): New function.
+	(frv_cache_data_flushed): New function.
+	* arch.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+Wed May 24 14:40:34 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2000-05-19  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_rett): Check for exceptions in the order specified in the
+	architecture spec. Allow privileged_instruction interrrupt to be handled
+	normally.
+	* registers.c (frv_register_control_init): Handle bfd_mach_frvtomcat.
+	* frv.c (frvbf_signed_integer_divide): Use updated dtt to decide whether
+	to clear the NE flag.
+	(frvbf_model_tomcat_u_exec): New function.
+	* frv-sim.h (frvbf_division_exception): Now returns updated dtt.
+	* Makefile.in (stamp-cpu): Add 'tomcat' to 'mach' value.
+	* arch.c,arch.h,cpu.h,cpuall.h,model.h,decode.c,sem.c: Regenerate.
+
+2000-05-18  Dave Brolley  <brolley@redhat.com>
+
+	* sim-if.c (elf-bfd.h): #include it.
+	(sim_open): Set machine amd architecture based on elf flags.
+
+2000-04-04  Dave Brolley  <brolley@redhat.com>
+
+	* frv-sim.h (frv_h_psr_esr_set_handler): Removed.
+	Delete '#if 0' blocks.
+	* frv.c: Delete '#if 0' blocks.
+	(spr_psr_set_handler): Remove special handling for circular referencing of handlers for
+	PSR.S and PSR.ESR.
+	(frv_h_psr_esr_set_handler): Removed.
+	* interrupts.c: Delete '#if 0' blocks.
+	* memory.c: Delete '#if 0' blocks.
+	* cpu.c,cpu.h: Regenerate.
+
+2000-04-03  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frvbf_check_recovering_store): Invalidate data cache line
+	containing the target address.
+	(clear_nesr_neear): No longer takes hi_available and lo_available.
+	Remove bogus check for available GR registers.
+	(frvbf_clear_ne_flags): Update call to clear_nesr_neear.
+	(frvbf_commit): Update call to clear_nesr_neear.
+	* interrupts.c (next_available_esr): Removed.
+	(next_available_edr): Removed.
+	(next_available_fq): Removed.
+	* frv.c (frvbf_fetch_register): Remove "FIXME" comment.
+	(frvbf_store_register): Remove "FIXME" comment.
+	* frv-sim.h (UART_INCHAR_ADDR): Removed.
+	(UART_OUTCHAR_ADDR):  Removed.
+	(UART_STATUS_ADDR):  Removed.
+	(UART_INPUT_READY):  Removed.
+	(UART_OUTPUT_READY):  Removed.
+	(FRV_DEVICE_ADDR):  Removed.
+	(FRV_DEVICE_LEN):  Removed.
+	(SET_NESR): Call frvbf_force_update.
+	(SET_NEEAR): Call frvbf_force_update.
+	(SET_NE_FLAGS): Call frvbf_force_update.
+
+2000-03-30  Dave Brolley  <brolley@redhat.com>
+
+	* configure: Regenerated.
+
+2000-03-30  Dave Brolley  <brolley@redhat.com>
+
+	* registers.c (fr500_spr): Define ESR14-15 and EPCSR14-15 for fr500.
+	* memory.c (frvbf_write_mem_*): Save slot containing the insn
+	performing the write.
+	(frvbf_mem_set_*): Overwrite the slot information of the interrupt
+	queue element with the information in the interrupt state.
+	* interrupts.c (frv_queue_interrupt): Call frv_set_interrupt_queue_slot.
+	(frv_queue_fp_exception_interrupt): Initialize 'new_element'.
+	(frv_set_interrupt_queue_slot): New function.
+	(esr_for_data_access_exception): New function.
+	(set_edr_register): edr_index is now passed in.
+	(fq_for_exception): New function.
+	(set_fp_exception_registers): Call fq_for_exception. Interrupt queue
+	element now passed in.
+	(set_exception_status_registers): Obtain slot from interrupt queue
+	element. Call esr_for_data_access_exception. Use ESR14
+	for data_store_error. Use ESR15 for data_access_error. Use EDR0.
+	(frv_save_data_written_for_interrupts): Save slot containing the insn
+	performing the write.
+	* frv-sim.h (struct frv_fp_exception_info): Use frv_fsr_traps and
+	frv_fsr_ftt.
+	(struct frv_interrupt_state): Add 'slot' field.
+	(frv_set_interrupt_queue_slot): New function.
+	(frv_set_write_queue_slot): New function.
+
+2000-03-24  Dave Brolley  <brolley@redhat.com>
+
+	* mloop.in (_parallel_write_init): Initialize
+	frv_interrupt_state.imprecise_interrupt.
+	(_parallel_write_queued): After an imprecise interrupt, only perform
+	forced writes and floating point writes (for certain exceptions).
+	* interrupts.c (handle_interrupt): Set
+	frv_interrupt_state.imprecise_interrupt for writeback after an imprecise
+	interrupt.
+	(frv_process_interrupts): No need to clear f_ne_flags.
+	* frv.c (frvbf_signed_integer_divide): Queue writes to GR registers and
+	force them to happen even if there is an overflow exception.
+	(frvbf_force_update): New function.
+	* frv-sim.h (frvbf_force_update): New function.
+	(struct frv_interrupt_state): Add imprecise_interrupt.
+	(FRV_WRITE_QUEUE_FORCE_WRITE): New macro.
+	* sem.c: Regenerate.
+
+2000-03-23  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_rett): Queue FRV_ILLEGAL_INSTRUCTION directly.
+	* registers.c (frv_spr): MCIRL -> MCILR.
+	* interrupts.c (frv_queue_non_implemented_instruction_interrupt):
+	New function.
+	(frv_detect_insn_access_interrupts):
+	Call frv_queue_non_implemented_instruction_interrupt.
+	(frv_process_interrupts): Clear accumulated NE flags.
+	* frv.c (frvbf_media_cop): New function.
+	(frvbf_set_ne_index): Now takes (SIM_CPU *) as first argument.  Clear
+	the NE flag of the given target register.
+	(frvbf_model_fr500_u_float_arith): Account for FRdouble registers.
+	(frvbf_model_fr500_u_float_dual_arith): Account for FRdouble registers.
+	(frvbf_model_fr500_u_float_dual_sqrt): New function.
+	(frvbf_model_fr500_u_float_convert): Account for FRdouble registers.
+	(frvbf_model_fr500_u_float_dual_convert): New function.
+	* frv-sim.h (frvbf_media_cop): New function.
+	(GET_FQ): Use H_SPR_FQST0.
+	(SET_FQ): Use H_SPR_FQST0.
+	(SET_FQ_OPC): Use J_SPR_FQOP0.
+	(GET_MSR_EMCI): New macro.
+	(frv_queue_non_implemented_instruction_interrupt): New function.
+	* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2000-03-08  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_rett): Align new_pc.
+	* memory.c (frvbf_read_mem_HI): Align address.
+	(frvbf_read_mem_UHI): Align address.
+	(frvbf_read_mem_SI): Align address.
+	(frvbf_read_mem_DI): Align address.
+	(frvbf_read_mem_DF): Align address.
+	(frvbf_read_imem_USI): Align address.
+	(frvbf_mem_set_HI): Align address.
+	(frvbf_mem_set_SI): Align address.
+	(frvbf_mem_set_DI): Align address.
+	(frvbf_mem_set_DF): Align address.
+	(frvbf_mem_set_XI): Align address.
+	* registers.c (frv_spr): Initialize FSR0.NS to 1.
+	(fr500_spr): Initialize FSR0.NS to 1.
+	* interrupts.c (frv_queue_mem_address_not_aligned_interrupt): Check
+	whether the exception is masked.
+	* frv.c (frvbf_load_quad_GR): Align address.
+	(frvbf_store_quad_GR): Align address.
+	(frvbf_load_quad_FRint): Align address.
+	(frvbf_store_quad_FRint): Align address.
+	(frvbf_load_quad_CPR): Align address.
+	(frvbf_store_quad_CPR): Align address.
+	* frv-sim.h (GET_ISR_EMAM): New macro.
+
+2000-03-08  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frvbf_division_exception): Check for masked overflow and
+	set NE flags, if necessary.
+	(frvbf_check_recovering_store): Queue writes to the hardware.
+	(check_registers_available): Removed.
+	(which_registers_available): Call frv_{fr,gr}_registers_available.
+	(frvbf_clear_ne_flags): Call check_register_access.
+	(frvbf_commit): Call check_register_access.
+	* registers.h (frv_fr_registers_available): New function.
+	(frv_gr_registers_available): New function.
+	(frv_check_register_access): New function.
+	(frv_check_gr_access): New function.
+	(frv_check_fr_access): New function.
+	* registers.c (frv_spr): Correct initial value of ISR.
+	(fr500_spr): Correct initial value of ISR.
+	(frv_fr_registers_available): New function.
+	(frv_gr_registers_available): New function.
+	(frv_check_register_access): New function.
+	(frv_check_gr_access): New function.
+	(frv_check_fr_access): New function.
+	* interrupts.c (frv_queue_division_exception_interrupt): New function.
+	(set_isr_exception_fields): New function.
+	(set_exception_status_registers): Set ISR fields for division exception.
+	(frv_save_data_written_for_interrupts): Handle CGEN_FN_SF_WRITE.
+	* frv.c (frvbf_h_gr_get_handler): New function.
+	(frvbf_h_gr_set_handler): New function.
+	(frvbf_h_fr_get_handler): New function.
+	(frvbf_h_fr_set_handler): New function.
+	(frvbf_h_spr_get_handler): Remove special handling for ISR.
+	(frvbf_h_spr_set_handler): Remove special handling for ISR.
+	(spr_isr_get_handler): Removed.
+	(spr_isr_set_handler): Removed.
+	(frvbf_signed_integer_divide): New funciton.
+	(frvbf_unsigned_integer_divide): New funciton.
+	* frv-sim.h (frvbf_h_gr_get_handler): New function.
+	(frvbf_h_gr_set_handler): New function.
+	(frvbf_h_fr_get_handler): New function.
+	(frvbf_h_fr_set_handler): New function.
+	(frvbf_signed_integer_divide): New funciton.
+	(frvbf_unsigned_integer_divide): New funciton.
+	(frv_dtt): New enumeration.
+	(struct frv_interrupt_queue_element): Add dtt member.
+	(GET_ISR): New macro.
+	(SET_ISR): New macro.
+	(GET_ISR_EDEM): New macro.
+	(SET_ISR_DTT): New macro.
+	(SET_ISR_AEXC): New macro.
+	(frvbf_division_exception): Add 2 'int' arguments.
+	(frvbf_check_non_excepting_divide): Removed.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2000-02-29  Dave Brolley  <brolley@redhat.com>
+
+	* traps.c (frv_itrap): Use GET_H_GR, SET_H_GR, GET_H_FR.
+	(frv_rett): Use hardware access macros. Write PSR as a whole.
+	(next_available_nesr): Check that NECR is valid.
+	(next_valid_nesr): Check that NECR is valid.
+	(frvbf_check_non_excepting_load): User new NECR access macros. Don't
+	call hardware access functions. Use cover macros.
+	(check_registers_available): New function.
+	(clear_nesr_near): Check register availability.
+	(clear_ne_flags): Check register availability.
+	(frvbf_clear_ne_flags): Check register availability.
+	(frvbf_commit): Check register availability.
+	(which_registers_available): New function.
+	* sim-main.h (registers.h): #include it.
+	(register_control): New cpu field.
+	(CPU_REGISTER_CONTROL): New macro.
+	* reset.c (frv_initialize): Set HSR0 fields for cache here.
+	(frv_power_on_reset): Initialize SPR registers and RSTR.
+	(frv_hardware_reset): Initialize SPR registers and RSTR.
+	(frv_software_reset): Reset SPR registers and RSTR.
+	* options.c (frv_option_handler): Don't set HSR0 fields for cache here.
+	Call frv_cache_init.
+	* mloop.in (main loop): Check for insn access interrupts before
+	executing the insn.
+	* interrupts.c (frv_queue_external_interrupt): Use GET_H_PSR_ET.
+	(frv_detect_insn_access_interrupts): Don't call hardware access
+	functions directly. Use cover macros.
+	(check_reset): Don't reset RSTR here.
+	(next_available_esr): ESFR -> ESFR_FLAG.
+	(next_available_edr): ESFR -> ESFR_FLAG.
+	(clear_exception_status_registers): Use GET_ESFR and SET_ESFR.
+	ESFR -> ESFR_FLAG.
+	(frv_break_interrupt): Don't call hardware access functions directly.
+	Use cover macros.
+	(frv_program_or_software_interrupt): Ditto.
+	(frv_external_interrupt): Ditto.
+	* frv.c (frvbf_fetch_register): Don't call 'get' functions directly.
+	(frvbf_store_register): Don't call 'set' functions directly.
+	(frvbf_h_gr_double_get_handler): Use GET_H_GR.
+	(frvbf_h_gr_double_set_handler): Use SET_H_GR.
+	(frvbf_h_fr_double_get_handler): Use GET_H_FR.
+	(frvbf_h_fr_double_set_handler): Use SET_H_FR.
+	(frvbf_h_fr_int_get_handler): Use GET_H_FR.
+	(frvbf_h_fr_int_set_handler): Use SET_H_FR.
+	(frvbf_h_cpr_double_get_handler): Use GET_H_CPR.
+	(frvbf_h_cpr_double_set_handler): Use SET_H_CPR.
+	(frvbf_h_gr_quad_set_handler): Use SET_H_GR.
+	(frvbf_h_fr_quad_set_handler): Use SET_H_FR.
+	(frvbf_h_spr_get_handler): Check SPR access. Call renamed functions.
+	Support shadow registers.
+	(frvbf_h_spr_set_handler): Check SPR access. Call renamed functions.
+	Support shadow registers.
+	(spr_psr_get_handler): Renamed from frvbf_h_psr_get_handler.
+	(spr_psr_set_handler): Renamed from frvbf_h_psr_set_handler.
+	(spr_tbr_get_handler): Renamed from frvbf_h_tbr_get_handler.
+	(spr_tbr_set_handler): Renamed from frvbf_h_tbr_set_handler.
+	(spr_bpsr_get_handler): Renamed from frvbf_h_bpsr_get_handler.
+	(spr_bpsr_set_handler): Renamed from frvbf_h_bpsr_set_handler.
+	(spr_ccr_get_handler): Renamed from frvbf_h_ccr_get_handler.
+	(spr_ccr_set_handler): Renamed from frvbf_h_ccr_set_handler.
+	(spr_lr_get_handler): Renamed from frvbf_h_lr_get_handler.
+	(spr_lr_set_handler): Renamed from frvbf_h_lr_set_handler.
+	(spr_cccr_get_handler): Renamed from frvbf_h_cccr_get_handler.
+	(spr_cccr_set_handler): Renamed from frvbf_h_cccr_set_handler.
+	(spr_isr_get_handler): Renamed from frvbf_h_isr_get_handler.
+	(spr_isr_set_handler): Renamed from frvbf_h_isr_set_handler.
+	(spr_sr_get_handler): Renamed from frvbf_h_sr_get_handler.
+	(spr_sr_set_handler): Renamed from frvbf_h_sr_set_handler.
+	(frvbf_h_psr_esr_set_handler): Update to conform to FRV architecture
+	version 1.3a.
+	(spr_ccr_get_handler): Don't reference the hardware directly.
+	(spr_ccr_set_handler): Don't reference the hardware directly.
+	(spr_cccr_get_handler): Don't reference the hardware directly.
+	(spr_cccr_set_handler): Don't reference the hardware directly.
+	(spr_sr_get_handler): New function.
+	(spr_sr_set_handler): New function.
+	(frvbf_switch_supervisor_user_context): Temporarily switch to
+	supervisor mode.
+	(frvbf_store_quad_GR): Don't call handler directly.
+	(frvbf_store_quad_FRint): Don't call handler directly.
+	(frvbf_store_quad_CPR): Don't call handler directly.
+	(frvbf_clear_all_accumulators): Removed.
+	(frvbf_clear_accumulators): New function.
+	(frvbf_model_fr500_u_media): Expand busy_adjustment to 8 members.
+	Account for in_ACCGi and out_ACCGk.
+	* frv-sim.h (RSTR_HARDWARE_RESET): New macro.
+	(RSTR_SOFTWARE_RESET): New macro.
+	(spr_psr_get_handler): Renamed from frvbf_h_psr_get_handler.
+	(spr_psr_set_handler): Renamed from frvbf_h_psr_set_handler.
+	(spr_tbr_get_handler): Renamed from frvbf_h_tbr_get_handler.
+	(spr_tbr_set_handler): Renamed from frvbf_h_tbr_set_handler.
+	(spr_bpsr_get_handler): Renamed from frvbf_h_bpsr_get_handler.
+	(spr_bpsr_set_handler): Renamed from frvbf_h_bpsr_set_handler.
+	(spr_ccr_get_handler): Renamed from frvbf_h_ccr_get_handler.
+	(spr_ccr_set_handler): Renamed from frvbf_h_ccr_set_handler.
+	(spr_lr_get_handler): Renamed from frvbf_h_lr_get_handler.
+	(spr_lr_set_handler): Renamed from frvbf_h_lr_set_handler.
+	(spr_cccr_get_handler): Renamed from frvbf_h_cccr_get_handler.
+	(spr_cccr_set_handler): Renamed from frvbf_h_cccr_set_handler.
+	(spr_isr_get_handler): Renamed from frvbf_h_isr_get_handler.
+	(spr_isr_set_handler): Renamed from frvbf_h_isr_set_handler.
+	(spr_sr_get_handler): Renamed from frvbf_h_sr_get_handler.
+	(spr_sr_set_handler): Renamed from frvbf_h_sr_set_handler.
+	(frvbf_clear_all_accumulators): Removed.
+	(frvbf_clear_accumulators): New function.
+	(GET_HSR0): Use GET_H_SPR.
+	(SET_HSR0): Use SET_H_SPR.
+	(CLEAR_HSR0_ICE): New macro.
+	(CLEAR_HSR0_DCE): New macro.
+	(GET_IHSR8): Use GET_H_SPR.
+	(GET_PSR): New macro.
+	(SET_PSR_ET): New macro.
+	(GET_PSR_PS): New macro.
+	(SET_PSR_S): New macro.
+	(GET_ESFR): Changed to reference entire register.
+	(SET_ESFR): Changed to reference entire register.
+	(GET_ESFR_FLAG): New macro.
+	(SET_ESFR_FLAG): New macro.
+	(NECR_ELOS): Removed.
+	(NECR_NEN): Removed.
+	(NECR_VALID): Removed.
+	(GET_NECR): New macro.
+	(GET_NECR_ELOS): New macro.
+	(GET_NECR_NEN): New macro.
+	(GET_NECR_VALID): New macro.
+	(NESR_RANGE): Removed.
+	(GET_NESR): Use GET_H_SPR.
+	(GET_NE_FLAGS): Use GET_H_SPR.
+	* cache.h (CACHE_INITIALIZED): New macro.
+	* Makefile.in (SIM_OBJS): Add registers.o.
+	(SIM_EXTRA_DEPS): Add registers.h.
+	(registers.o): New target.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+2000-02-17  Dave Brolley  <brolley@redhat.com>
+
+	* interrupts.c (frv_interrupt_table): Update priority order and handler
+	offsets to conform to the architecture version 1.3a.
+	* frv-sim.h (frv_interrupt_kind): Update priority order to conform
+	to the architecture version 1.3a.
+
+2000-02-17  Dave Brolley  <brolley@redhat.com>
+
+	* interrupts.c (frv_interrupt_table): Update priority order and handler
+	offsets to conform to the latest specifications.
+	(frv_queue_interrupt): Correct comment. Identical interrupts can be
+	queued. New variable 'iclass' used to test for external interrupts.
+	* frv-sim.h (frv_interrupt_kind): Update priority order to conform
+	to the latest specifications.
+
+2000-01-20  Dave Brolley  <brolley@redhat.com>
+
+	* sim-if.c (sim_open): Move frv-specific initialization to
+	frv_initialize in reset.c.
+	* interrupts.c (check_reset): Use RSTR_ADDRESS. Check and reset RSTR
+	status bits for hardware vs software reset.
+	* reset.c: New file.
+	* frv-sim.h (frv_initialize): New function.
+	(frv_power_on_reset): New function.
+	(frv_hardware_reset): New function.
+	(frv_software_reset): New function.
+	(RSTR_ADDRESS): New macro.
+	(RSTR_INITIAL_VALUE): New macro.
+	(GET_RSTR_HR): New macro.
+	(GET_RSTR_SR): New macro.
+	(SET_RSTR_H): New macro.
+	(SET_RSTR_S): New macro.
+	(CLEAR_RSTR_P): New macro.
+	(CLEAR_RSTR_H): New macro.
+	(CLEAR_RSTR_S): New macro.
+	(CLEAR_RSTR_HR): New macro.
+	(CLEAR_RSTR_SR): New macro.
+
+2000-01-03  Dave Brolley  <brolley@cygnus.com>
+
+	* mloop.in (execute): Only call modeling function if the pointer is not
+	NULL.
+	* frv.c (frvbf_model_insn_after): Only access FR500_MODEL_DATA for
+	fr500.
+
+2000-01-03  Dave Brolley  <brolley@cygnus.com>
+
+	* options.c (OPTION_FRV_MEMORY_LATENCY): New enumerator.
+	(frv_options): Add --memory-latency.
+	(frv_option_handler): Handle FRV_OPTION_MEMORY_LATENCY.
+	* mloop.in (@cpu@_simulate_insn_prefetch): Use cache memory_latency.
+	* frv.c (SET_ACC_USE_IS_MEDIA_P1): operate on d->curr_acc_p1
+	(SET_ACC_USE_NOT_MEDIA_P1): operate on d->curr_acc_p1
+	(SET_ACC_USE_IS_MEDIA_P2): operate on d->curr_acc_p1
+	(SET_ACC_USE_NOT_MEDIA_P2): operate on d->curr_acc_p1
+	(update_latencies): Only clear usage flags if the register has no
+	target latency.
+	(frvbf_model_insn_before): Update cur_acc_p1 and cur_acc_p2. Use | (or)
+	not |= (or assgnment).
+	(frvbf_model_insn_after): Print post processing wait for all insns.
+	Update prev_acc_p1 and prev_acc_p2.
+	(frvbf_model_fr500_u_gr_load_store): Use cache memory_latency.
+	(frvbf_model_fr500_u_fr_load_store): Use cache memory_latency.
+	(frvbf_model_fr500_u_swap): Use cache memory_latency.
+	(frvbf_model_fr500_u_media): Use busy_adjustment[4] for out_ACC40Sk.
+	(frvbf_model_fr500_u_media): Use busy_adjustment[5] for out_ACC40Uk.
+	(frvbf_model_fr500_u_media_quad_arith): New function.
+	(frvbf_model_fr500_u_media_dual_mul): New function.
+	(frvbf_model_fr500_u_media_quad_mul): New function.
+	(frvbf_model_fr500_u_media_quad_complex): New function.
+	(frvbf_model_fr500_u_media_dual_expand): New function.
+	(frvbf_model_fr500_u_media_dual_unpack): New function.
+	(frvbf_model_fr500_u_media_dual_btoh): New function.
+	(frvbf_model_fr500_u_media_dual_htob): New function.
+	(frvbf_model_fr500_u_media_dual_btohe): New function.
+	(frv_ref_SI): New function.
+	* cache.h (FRV_CACHE): Add memory_latency field.
+	* cache.c (frv_cache_init): Initialize memory_latency.
+	* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-12-17  Dave Brolley  <brolley@cygnus.com>
+
+	* sim-if.c (sim_open): Initialize insn prefetch and reset register.
+	* options.c (OPTIONS_FRV_PROFILE_CACHE): New enumeration.
+	(OPTIONS_FRV_PROFILE_PARALLEL): New enumeration.
+	(OPTIONS_FRV_TIMER): New enumeration.
+	(frv_options): Add --profile-cache, --profile-parallel, --timer.
+	(frv_option_handler): Override common implementation of -p. Handle
+	--profile-cache, --profile-parallel, --timer.
+	* mloop.in (execute): Call profiling functions if the timer interrupt
+	is enabled.
+	(@cpu@_simulate_insn_prefetch): New function.
+	(main loop): Call @cpu@_simulate_insn_prefetch.
+	* interrupts.c (frv_queue_interrupt): Don't queue two external
+	interrupts of the same priority.
+	(frv_queue_external_interrupt): New function.
+	(frv_external_interrupt): New function.
+	(handle_interrupt): Handle external interrupts.
+	(check_reset): New function.
+	(frv_process_interrupts): Call check_reset.
+	* frv.c: Include "bfd.h"
+	(frvbf_h_psr_get_handler): Set the PIL field.
+	(frvbf_h_psr_set_handler): Get the PIL field.
+	(DUAL_REG): New macro.
+	(DUAL_DOUBLE): New macro.
+	(SET_USE_IS_FPOP): New macro.
+	(SET_USE_NOT_FPOP): New macro.
+	(USE_IS_FPOP): New macro.
+	(SET_USE_IS_MEDIA): New macro.
+	(SET_USE_NOT_MEDIA): New macro.
+	(USE_IS_MEDIA_P1): New macro.
+	(SET_USE_IS_MEDIA_P1): New macro.
+	(SET_USE_NOT_MEDIA_P1): New macro.
+	(SET_USE_IS_MEDIA_P2): New macro.
+	(SET_USE_NOT_MEDIA_P2): New macro.
+	(USE_IS_MEDIA_P2): New macro.
+	(SET_ACC_USE_IS_MEDIA_P1): New macro.
+	(SET_ACC_USE_NOT_MEDIA_P1): New macro.
+	(ACC_USE_IS_MEDIA_P1): New macro.
+	(SET_ACC_USE_IS_MEDIA_P2): New macro.
+	(SET_ACC_USE_NOT_MEDIA_P2): New macro.
+	(ACC_USE_IS_MEDIA_P2): New macro.
+	(RESOURCE_IDIV): New macro.
+	(RESOURCE_FDIV): New macro.
+	(RESOURCE_SQRT): New macro.
+	(fr_busy_adjust): New array.
+	(acc_busy_adjust): New array.
+	(apply_latency_adjustments): New function.
+	(update_latencies): New function.
+	(handle_wait_cycles): New function.
+	(handle_resource_wait): New function.
+	(update_target_latencies): New function.
+	(frvbf_model_insn_before): Add resource latency to cycle counts.
+	(frvbf_model_insn_after): Add resource latency to cycle counts.
+	(update_GR_latency): New function.
+	(update_GRdouble_latency): New function.
+	(update_FR_latency): New function.
+	(update_FRdouble_latency): New function.
+	(decrease_ACC_busy): New function.
+	(decrease_FR_busy): New function.
+	(increase_FR_busy): New function.
+	(update_ACC_latency): New function.
+	(update_CCR_latency): New function.
+	(update_idiv_resource_latency): New function.
+	(update_fdiv_resource_latency): New function.
+	(update_fsqrt_resource_latency): New function.
+	(vliw_wait_for_GR): New function.
+	(vliw_wait_for_GRdouble): New function.
+	(vliw_wait_for_FR): New function.
+	(vliw_wait_for_FRdouble): New function.
+	(vliw_wait_for_CCR): New function.
+	(vliw_wait_for_ACC): New function.
+	(vliw_wait_for_idiv_resource): New function.
+	(vliw_wait_for_fdiv_resource): New function.
+	(vliw_wait_for_fsqrt_resource): New function.
+	(enforce_full_fr_latency): New function.
+	(frvbf_model_fr500_u_exec): New function.
+	(frvbf_model_fr500_u_integer): New function.
+	(frvbf_model_fr500_u_imul): New function.
+	(frvbf_model_fr500_u_idiv): New function.
+	(frvbf_model_fr500_u_branch): New function.
+	(frvbf_model_fr500_u_set_hilo): New function.
+	(frvbf_model_fr500_u_gr_load_store): New function.
+	(frvbf_model_fr500_u_fr_load_store): New function.
+	(frvbf_model_fr500_u_swap): New function.
+	(frvbf_model_fr500_u_fr2fr): New function.
+	(frvbf_model_fr500_u_fr2gr): New function.
+	(frvbf_model_fr500_u_spr2gr): New function.
+	(frvbf_model_fr500_u_gr2fr): New function.
+	(frvbf_model_fr500_u_gr2spr): New function.
+	(post_wait_for_FR): New function.
+	(post_wait_for_FRdouble): New function.
+	(post_wait_for_ACC): New function.
+	(post_wait_for_CCR): New function.
+	(post_wait_for_fdiv): New function.
+	(post_wait_for_fsqrt): New function.
+	(adjust_float_register_busy): New function.
+	(adjust_double_register_busy): New function.
+	(restore_float_register_busy): New function.
+	(restore_double_register_busy): New function.
+	(frvbf_model_fr500_u_float_arith): New function.
+	(frvbf_model_fr500_u_float_dual_arith): New function.
+	(frvbf_model_fr500_u_float_div): New function.
+	(frvbf_model_fr500_u_float_sqrt): New function.
+	(frvbf_model_fr500_u_float_compare): New function.
+	(frvbf_model_fr500_u_float_dual_compare): New function.
+	(frvbf_model_fr500_u_float_convert): New function.
+	(frvbf_model_fr500_u_media): New function.
+	(frvbf_model_fr500_u_barrier): New function.
+	(frvbf_model_fr500_u_membar): New function.
+	* frv-sim.h (LEUINT): New macro.
+	(GET_HSR0_SA): New macro.
+	(struct frv_interrupt_timer): New struct.
+	(struct frv_interrupt_state): Add timer fiield.
+	(frv_queue_external_interrupt): New function.
+	(frv_external_interrupt): New function.
+	(frv_profile_info): New function.
+	(PROFILE_CACHE_IDX): New enumerator.
+	(PROFILE_PARALLEL_IDX): New enumerator.
+	(PROFILE_cache): New macro.
+	(PROFILE_parallel): New macro.
+	(WITH_PROFILE_CACHE_P): New macro.
+	(WITH_PROFILE_PARALLEL_P): New macro.
+	* cache.h (FRV_CACHE): Add last_was_hit field.
+	* cache.c (get_tag): Use new last_was_hit field.
+	(frv_cache_read): Ditto.
+	(frv_cache_write): Ditto.
+	* arch.h,cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-12-13  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_h_spr_set_handler): Handle accumulator guards.
+	(frvbf_clear_all_accumulators): Pass frvbf_h_acc40S_set to
+	sim_queue_fn_di_write.
+	(frvbf_media_cut_ss): New function.
+	* frv-sim.h (frvbf_media_cut_ss): New function.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-12-13  Dave Brolley  <brolley@cygnus.com>
+
+	* pipeline.c (check_insn_major_constraints): F-4, F-8 and M-8 have
+	no constraints.
+	* interrupts.c (frv_queue_illegal_instruction_interrupt): Use
+	FRV_IS_FLOAT_INSN and FRV_IS_MEDIA_INSN.
+	(frv_detect_insn_access_interrupts): Use FRV_IS_FLOAT_INSN and
+	FRV_IS_MEDIA_INSN.
+	* frv.c (frvbf_model_simple_u_exec): New function.
+	* frv-sim.h (FRV_IS_FLOAT_INSN): Range includes F-8.
+	(FRV_IS_MEDIA_INSN): Range includes M-8.
+
+	* Makefile.in (stamp-cpu): add 'simple' to the list of machines.
+	* arch.c,arch.h,cpu.h,cpuall.h,decode.c,decode.h,model.c,sem.c:
+	Regenerate.
+
+1999-12-10  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (check_registers_available): New function.
+	(clear_ne_flags): Generate register_exception if register(s) not
+	available.
+	(frvbf_commit): Generate register_exception if register(s) not
+	available.
+	* interrupts.c (frv_program_or_software_interrupt): No need to copy
+	GR4-GR7 to SR0-SR4.
+	* frv.c (frvbf_h_psr_set_handler): Special handling for PSR.S and
+	PSR.ESR.
+	(frvbf_h_psr_s_set_handler): New function.
+	(frvbf_h_psr_esr_set_handler): New function.
+	(frvbf_switch_supervisor_user_context): New function.
+	(frvbf_scan_result): Reflect latest ISA.
+	* frv-sim.h (frvbf_h_psr_s_set_handler): New function.
+	(frvbf_h_psr_esr_set_handler): New function.
+	(frvbf_switch_supervisor_user_context): New function.
+	(GET_HSR0_FRN): New Macro.
+	(GET_HSR0_GRN): New Macro.
+	(GET_HSR0_FRHE): New Macro.
+	(GET_HSR0_FRLE): New Macro.
+	(GET_HSR0_GRHE): New Macro.
+	(GET_HSR0_GRLE): New Macro.
+	(frv_ec): New value for FRV_EC_COMMIT_EXCEPTION.
+	(GET_ESFR): New bit ordering.
+	(SET_ESFR): New bit ordering.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-12-10  Michael Meissner  <meissner@cygnus.com>
+
+	* Makefile.in (sim-if.o): Add eng.h dependency.
+
+1999-12-09  Dave Brolley  <brolley@cygnus.com>
+
+	* mloop.in (execute): Pass sc->first_insn_p to @cpu@_model_insn_before.
+	Pass sc->last_insn_p to @cpu@_model_insn_before.
+	(main loop): Compute sc->first_insn_p.
+	* frv.c (frvbf_model_insn_before): Set state variables.
+	(frvbf_model_insn_after): Count basic cycles. Set state variables.
+	(frvbf_model_fr500_u_integer): Remove.
+	* arch.h,cpu.h,decode.h,model.c: Regenerate.
+
+1999-12-07  Dave Brolley  <brolley@cygnus.com>
+
+	* sim-main.h (cache.h): Include it.
+	(insn_cache): New member.
+	(data_cache): New member.
+	(CPU_INSN_CACHE): New macro.
+	(CPU_DATA_CACHE): New macro.
+	* sim-if.c (WANT_CPU): New macro.
+	(WANT_CPU_FRVBF): New macro.
+	(sim_open): Call sim_add_option_table. Call frv_cache_init for the
+	data and insn caches for each cpu.
+	(sim_close): Call frv_cache_term for the insn and data caches of each
+	cpu.
+	* mloop.in (extract): Read insn from the cache.
+	(main loop): Access the insn cache in order to maintain stats.
+	* memory.c (data_non_cache_access): New function.
+	(insn_non_cache_access): New function.
+	(frvbf_read_mem_QI): Attempt to read from the cache first.
+	(frvbf_read_mem_UQI): Ditto.
+	(frvbf_read_mem_HI): Ditto.
+	(frvbf_read_mem_UHI): Ditto.
+	(frvbf_read_mem_SI): Ditto.
+	(frvbf_read_mem_DI): Ditto.
+	(frvbf_read_mem_DF): Ditto.
+	(frvbf_read_imem_USI): New function.
+	(frvbf_write_mem_QI): Write through the cache is it is enabled.
+	(frvbf_write_mem_UQI): Ditto.
+	(frvbf_write_mem_HI): Ditto.
+	(frvbf_write_mem_UHI): Ditto.
+	(frvbf_write_mem_SI): Ditto.
+	(frvbf_write_mem_DI): Ditto.
+	(frvbf_write_mem_DF): Ditto.
+	(frvbf_mem_set_QI): New function.
+	(frvbf_mem_set_HI): New function.
+	(frvbf_mem_set_SI): New function.
+	(frvbf_mem_set_DI): New function.
+	(frvbf_mem_set_DF): New function.
+	(frvbf_mem_set_XI): New function.
+	* interrupts.c (frv_save_data_written_for_interrupts): Handle
+	CGEN_FN_MEM_QI_WRITE,
+	CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, CGEN_FN_MEM_DI_WRITE,
+	CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE.
+	* frv.c (frvbf_load_quad_GR): Call frvbf_read_mem_SI.
+	Call sim_queue_fn_mem_xi_write.
+	(frvbf_load_quad_FRint): Call frvbf_read_mem_SI.
+	Call sim_queue_fn_mem_xi_write.
+	(frvbf_load_quad_CPR): Call frvbf_read_mem_SI.
+	Call sim_queue_fn_mem_xi_write.
+	(frvbf_insn_cache_preload): New function. 
+	(frvbf_data_cache_preload): New function. 
+	(frvbf_insn_cache_unlock): New function. 
+	(frvbf_data_cache_unlock): New function. 
+	(frvbf_insn_cache_invalidate): New function. 
+	(frvbf_data_cache_invalidate): New function. 
+	(frvbf_data_cache_flush): New function. 
+	* frv-sim.h (sim-options.h): Include it.
+	(GET_HSR0): New macro.
+	(SET_HSR0): New macro. 
+	(GET_HSR0_ICE): New macro. 
+	(SET_HSR0_ICE): New macro. 
+	(GET_HSR0_DCE): New macro. 
+	(SET_HSR0_DCE): New macro. 
+	(GET_HSR0_CBM): New macro. 
+	(GET_HSR0_RME): New macro. 
+	(GET_IHSR8): New macro. 
+	(GET_IHSR8_NBC): New macro. 
+	(frvbf_insn_cache_preload): New function.
+	(frvbf_data_cache_preload): New function.
+	(frvbf_insn_cache_unlock): New function.
+	(frvbf_data_cache_unlock): New function.
+	(frvbf_insn_cache_invalidate): New function.
+	(frvbf_data_cache_invalidate): New function.
+	(frvbf_data_cache_flush): New function.
+	(insn_non_cache_access): New function.
+	(frvbf_read_imem_USI): New function.
+	(frvbf_mem_set_QI): New function.
+	(frvbf_mem_set_HI): New function.
+	(frvbf_mem_set_SI): New function.
+	(frvbf_mem_set_DI): New function.
+	(frvbf_mem_set_DF): New function.
+	(frvbf_mem_set_XI): New function.
+	(frv_options): FRV specific command line options.
+	* Makefile.in (SIM_OBJS): Add options.o and cache.o.
+	(SIM_EXTRA_DEPS): Add $(sim-options_h).
+	(cache.o): New target.
+	(options.o): New target.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+	* cache.h: New file.
+	* cache.c: New file.
+	* options.c: New file.
+
+1999-11-29  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frvbf_check_non_excepting_load): Use new NE_FLAG macros.
+	(frvbf_check_non_excepting_divide): Ditto.
+	(clear_ne_flags): Ditto
+	(frvbf_commit): Ditto.
+	* pipeline.c (frv_pipeline_add_insn): Clear the NE index for all insns.
+	* mloop.in (_parallel_write_init): Clear NE flags here.
+	* interrupts.c (frv_queue_fp_exception_interrupt): Set NE flags here
+	for non excepting insns. Also check for masked interrupts here.
+	(frv_process_interrupts): Write NE flags here.
+	(set_fp_exception_registers): No longer check for masked interrupts
+	here.
+	(check_for_compound_interrupt): No need to worry about masked
+	interrupts.
+	* frv-sim.h (frv_interrupt_state): Add f_ne_flags member.
+	(GET_NE_FLAGS): New macro.
+	(SET_NE_FLAGS): New macro.
+	(GET_NE_FLAG): Operate on accumulated argument.
+	(SET_NE_FLAG): Operate on accumulated argument.
+	(CLEAR_NE_FLAG): Operate on accumulated argument.
+	* Makefile.in (FRVBF_INCLUDE_DEPS): Add $(SIM_EXTRA_DEPS)
+	(frv.o): Correct dependencies.
+	(traps.o): Ditto.
+	(pipeline.o): Ditto.
+	(interrupts.o): Ditto.
+	(memory.o): Ditto.
+	* sem.c: Regenerate.
+
+1999-11-26  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frvbf_fpu_error): Only call frv_queue_fp_exception if
+	there is an exception indicated in the mask.
+	* pipeline.c (frv_pipeline_add_insn): Clear ne_index in the interrupt
+	state when adding a floating point insn to the pipeline.
+	* interrupts.c (set_fp_exception_registers): Set NE flag for
+	non-excepting insns.
+	* frv-sim.h (frvbf_h_fr_double_get_handler): Mode of data is DF.
+	(frvbf_h_fr_double_set_handler): Mode of data is DF.
+	(frvbf_h_fr_int_get_handler): New function.
+	(frvbf_h_fr_int_set_handler): New function.
+	(frvbf_set_ne_index): New function.
+	(NE_NOFLAG): New macro.
+	(frv_interrupt_state): Add ne_index member.
+	* frv.c (frvbf_h_fr_double_get_handler): Mode of data is DF.
+	(frvbf_h_fr_double_set_handler): Mode of data is DF.
+	(frvbf_h_fr_int_get_handler): New function.
+	(frvbf_h_fr_int_set_handler): New function.
+	(frvbf_set_ne_index): New function.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-24  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-23  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (frvbf_media_cut): New function.
+	* frv.c (frvbf_media_cut): New function.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-22  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (frvbf_clear_all_accumulators): New function.
+	* frv.c.h (frvbf_clear_all_accumulators): New function.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-18  Dave Brolley  <brolley@cygnus.com>
+
+	* pipeline.c (frv_pipeline_add_insn): Only clear MSR0 and FSR0 fields
+	if this is the first insn of its class in the pipeline.
+	* frv-sim.h (frvbf_media_register_not_aligned): New function.
+	* traps.c (frvbf_media_register_not_aligned): New function.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-17  Dave Brolley  <brolley@cygnus.com>
+
+	* pipeline.c (frv_pipeline_add_insn): Clear MSRx.SIE fields.
+	* frv-sim.h (OR_MSR_SIE): New macro.
+	(CLEAR_MSR_SIE): New macro.
+	(frvbf_media_overflow): Now takes sie argument.
+	(frv_set_mp_exception_registers): Now takes sie argument.
+	* interrupts.c (frv_set_mp_exception_registers): Now takes sie argument.
+	Set MSRx.SIE field.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-15  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frv_mtrap): New function.
+	(frvbf_media_cr_not_aligned): New function.
+	(frvbf_media_acc_not_aligned): New function.
+	(frvbf_media_overflow): New function.
+	* pipeline.c (frv_pipeline_add_insn): Clear MSR fields.
+	* interrupts.c: Call frv_set_mp_exception_registers.
+	(frv_set_mp_exception_registers): New function.
+	* frv-sim.h (frv_msr_mtt): New enumeration.
+	(GET_MSR): New macro.
+	(SET_MSR): New macro.
+	(GET_MSR_AOVF): New macro.
+	(SET_MSR_AOVF): New macro.
+	(GET_MSR_OVF): New macro.
+	(SET_MSR_OVF): New macro.
+	(CLEAR_MSR_OVF): New macro.
+	(GET_MSR_MTT): New macro.
+	(SET_MSR_MTT): New macro.
+	(frv_set_mp_exception_registers): New function.
+	(frv_mtrap): New function.
+	(FRV_IS_MEDIA_INSN): New macro.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-10  Dave Brolley  <brolley@cygnus.com>
+
+	* sim-main.h (_sim_cpu): Add debug_state member.
+	* mloop.in (_parallel_write_queued): Clear data_written.length.
+	* interrupts.c (frv_interrupt_table): Offset of BREAK_EXCEPTION
+	handler is 0xff.
+	(frv_queue_break_interrupt): New function.
+	(frv_break_interrupt): New function.
+	(handle_interrupt): Handle break_interrupt.
+	(frv_non_operating_interrupt): Now takes interrupt_kind.
+	* frv-sim.h (frv_queue_break_interrupt): New function.
+	(frv_break_interrupt): New function.
+	(frv_break): New function.
+	(frv_non_operating_interrupt): Now takes interrupt_kind.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-11-09  Dave Brolley  <brolley@cygnus.com>
+
+	* pipeline.c (frv_pipeline_add_insn): Clear FSR0.FTT when adding
+	a floating point insn.
+	* traps.c (frvbf_fpu_error): Map fpu status to frv interrupts.
+	* interrupts.c (frv_queue_illegal_instruction_interrupt): Call
+	frv_queue_fp_exception_interrupt.
+	(frv_queue_fp_exception_interrupt): New function.
+	(next_available_fq): New function.
+	(set_fp_exception_registers): New function.
+	(set_exception_status_registers): Now returns 1 if interrupt not masked.
+	(check_for_compound_interrupt): Now returns NULL if interrupt masked.
+	(frv_program_interrupt): Don't process interrupt if it is masked.
+	* frv.c (frvbf_h_fr_double_get_handler): Call
+	frv_queue_fp_exception_interrupt.
+	(frvbf_h_fr_double_set_handler): Call frv_queue_fp_exception_interrupt.
+	(frvbf_h_fr_quad_set_handler): Call frv_queue_fp_exception_interrupt.
+	(frvbf_store_quad_FRint): Call frv_queue_fp_exception_interrupt.
+	* frv-sim.h: Get/set hardware directly in GET/SET macros.
+	(frv_fp_exception_info): New struct type.
+	(frv_interrupt_queue_element): Add fp_info member.
+	(frv_fsr_traps): New enumeration.
+	(frv_fsr_ftt): New enumeration.
+	(frv_sie): New enumeration.
+	(frv_miv): New enumeration.
+	(GET_FSR): New macro.
+	(SET_FSR): New macro.
+	(GET_FSR_TEM): New macro.
+	(SET_FSR_QNE): New macro.
+	(SET_FSR_FTT): New macro.
+	(GET_FSR_AEXC): New macro.
+	(SET_FSR_AEXC): New macro.
+	(GET_FQ): New macro.
+	(SET_FQ): New macro.
+	(SET_FQ_OPC): New macro.
+	(SET_FQ_MIV): New macro.
+	(SET_FQ_SIE): New macro.
+	(SET_FQ_FTT): New macro.
+	(SET_FQ_CEXC): New macro.
+	(GET_FQ_VALID): New macro.
+	(SET_FQ_VALID): New macro.
+	(frv_queue_fp_exception_interrupt): New function.
+	(FRV_IS_FLOAT_INSN): New macro.
+
+1999-11-04  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frvbf_fpu_error): No floating point errors need to be
+	detected.
+	* interrupts.c (clear_exception_status_registers): Clear 'valid' fields
+	of the ESR registers too.
+	(set_exception_status_registers): Don't set EAR for any precise
+	interrupts. Register index should be 1 for insns in PIPE_I1. Clear
+	ESR.EAV and ESR.EDV if not setting them. Set ESR.VALID.
+	(non_operating_interrupt): No need for return code.
+	(frv_program_or_software_interrupt): Process interrupt regardless
+	of operating mode. If PSR.ET was not set at the start of processing,
+	then stop the simulation with a message.
+	(frv_save_data_written_for_interrupts): Handle CGEN_FN_XI_WRITE and
+	CGEN_MEM_XI_WRITE.
+	* frv.c (frvbf_h_gr_quad_set_handler): New function.
+	(frvbf_h_fr_quad_set_handler): New function.
+	(frvbf_h_cpr_quad_set_handler): New function.
+	(frvbf_load_quad_GR): Renamed from frvbf_load_multiple_GR. Use new
+	sim_queue_fn_xi_write.
+	(frvbf_load_quad_FRint): Renamed from frvbf_load_multiple_GR. Use new
+	sim_queue_fn_xi_write.
+	(frvbf_load_quad_CPR): Renamed from frvbf_load_multiple_GR. Use new
+	sim_queue_fn_xi_write.
+	(frvbf_store_quad_GR): Renamed from frvbf_store_multiple_GR. Use new
+	sim_queue_mem_xi_write.
+	(frvbf_store_quad_FRint): Renamed from frvbf_store_multiple_GR. Use new
+	sim_queue_mem_xi_write.
+	(frvbf_store_quad_CPR): Renamed from frvbf_store_multiple_GR. Use new
+	sim_queue_mem_xi_write.
+	* frv-sim.h (frvbf_h_gr_quad_set_handler): New function.
+	(frvbf_h_fr_quad_set_handler): New function.
+	(frvbf_h_cpr_quad_set_handler): New function.
+	(SET_ESR_VALID): New macro.
+	(CLEAR_ESR_VALID): New macro.
+	(CLEAR_ESR_EAV): New macro.
+	(CLEAR_ESR_EDV): New macro.
+	* sem.c: Regenerate.
+
+1999-11-02  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frv_core_signal): Call
+	frv_queue_mem_address_not_aligned_interrupt.
+	* mloop.in (_parallel_write_queued): Call
+	frv_save_data_written_for_interrupts.
+	* frv.c (frvbf_h_gr_double_get_handler): Call
+	frv_queue_register_exception_interrupt.
+	(frvbf_h_cpr_double_get_handler): Call
+	frv_queue_register_exception_interrupt.
+	(frvbf_h_cpr_double_set_handler): Call
+	frv_queue_register_exception_interrupt.
+	(frvbf_load_multiple_GR): Call
+	frv_queue_register_exception_interrupt.
+	(frvbf_store_multiple_GR): Call
+	frv_queue_register_exception_interrupt.
+	(frvbf_load_multiple_CPR): Call
+	frv_queue_register_exception_interrupt.
+	(frvbf_store_multiple_CPR): Call
+	frv_queue_register_exception_interrupt.
+	(frvbf_h_tbr_get_handler): Fix TBR.TBA mask.
+	* interrupts.c (frv_queue_software_interrupt): Now returns interrupt
+	queue element.
+	(frv_queue_program_interrupt): Now returns interrupt queue element.
+	(frv_queue_illegal_instruction_interrupt): Now returns interrupt queue
+	element.
+	(frv_queue_interrupt): Now returns interrupt queue element.
+	(frv_queue_register_exception_interrupt): New function.
+	(frv_queue_mem_address_not_aligned_interrupt): New function.
+	(frv_save_data_written_for_interrupts): New function.
+	(next_available_edr): EDR registers available in blocks of 4.
+	(clear_exception_status_registers): New function.
+	(set_exception_status_registers): Pass esr to SET_ESR* macros.
+
+	* frv-sim.h (struct frv_data_written): New struct type.
+	(frv_interrupt_queue_element): Add data_written member.
+	(frv_queue_software_interrupt): Now returns interrupt queue element.
+	(frv_queue_program_interrupt): Now returns interrupt queue element.
+	(frv_queue_illegal_instruction_interrupt): Now returns interrupt queue
+	element.
+	(frv_queue_interrupt): Now returns interrupt queue element.
+	(frv_queue_register_exception_interrupt): New function.
+	(frv_queue_mem_address_not_aligned_interrupt): New function.
+	(frv_save_data_written_for_interrupts): New function.
+
+1999-10-27  Dave Brolley  <brolley@cygnus.com>
+
+	* interrupts.c (ITABLE_ENTRY): New macro.
+	(frv_interrupt_table): Add exception codes.
+	(next_available_esr): New function.
+	(next_available_edr): New function.
+	(set_edr_register): New function.
+	(set_exception_status_registers): New function.
+	(check_for_compound_interrupt): Record information on all interrupts
+	found.
+	(frv_program_interrupt): Always call check_for_compound_interrupt.
+	* frv.c (frvbf_h_pc_set_handler): Removed.
+	(frvbf_h_spr_get_handler): Handle LR register.
+	(frvbf_h_spr_set_handler): Handle LR register.
+	(frvbf_h_lr_get_handler): New function.
+	(frvbf_h_lr_set_handler): New function.
+	* frv-sim.h (frvbf_h_lr_get_handler): New function.
+	(frvbf_h_lr_set_handler): New function.
+	(frv_ec): New enumeration.
+	(frv_interrupt): Add frv_ec field.
+	(frv_rec): New enumeration.
+	(frv_daec): New enumeration.
+	(frv_interrupt_queue_element): Add eaddress, rec, iaec, daec fields.
+	(SET_ESR_EC): New macro.
+	(SET_ESR_REC): New macro.
+	(SET_ESR_IAEC): New macro.
+	(SET_ESR_DAEC): New macro.
+	(SET_ESR_EAV): New macro.
+	(GET_ESR_EDV): New macro.
+	(SET_ESR_EDV): New macro.
+	(GET_ESR_EDN): New macro.
+	(SET_ESR_EDN): New macro.
+	(GET_ESR): New macro.
+	(SET_ESR): New macro.
+	(SET_EPCR): New macro.
+	(SET_EAR): New macro.
+	(SET_EDR): New macro.
+	(GET_ESFR): New macro.
+	(SET_ESFR): New macro.
+	* cpu.c,cpu.h,sem.c: Rebuild.
+
+1999-10-26  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frvbf_check_non_excepting_load): Only set NESR, NECR, NEEAR
+	if mach is frv.
+	(clear_nesr_neear): Only execute if mach is frv.
+
+1999-10-22  Dave Brolley  <brolley@cygnus.com>
+
+	* sim-main.h (sim_cpu): Add pipeline.
+	(CPU_PIPELINE): New macro.
+	* mloop.in (_parallel_write_queued): Maintain pc in cpu during writes.
+	(main loop): Maintain pc in cpu.
+	* frv-sim.h (frv_queue_software_interrupt): New interface.
+	(frv_queue_program_interrupt): New interface.
+	(frv_queue_illegal_instruction_interrupt: New interface.
+	(frv_queue_interrupt): New interface.
+	(frv_detect_insn_access_interrupts): New interface.
+	(frv_process_interrupts): New interface.
+	(frv_program_interrupt): New interface.
+	(frv_software_interrupt): New interface.
+	(frv_program_or_software_interrupt): New interface.
+	(FRV_PIPELINE): Moved from pipline.c.
+	(frv_pipeline_reset): New interface.
+	(frv_pipeline_add_insn): New interface.
+	* interrupts.c (frv_queue_software_interrupt): New interface.
+	(frv_queue_program_interrupt): New interface.
+	(frv_queue_illegal_instruction_interrupt: New interface.
+	(frv_queue_interrupt): New interface.
+	(frv_detect_insn_access_interrupts): New interface.
+	(frv_process_interrupts): New interface.
+	(frv_program_interrupt): New interface.
+	(frv_software_interrupt): New interface.
+	(frv_program_or_software_interrupt): New interface.
+	* frv.c: Use new interfaces.
+	* pipeline.c: Use new interfaces.
+	* traps.c: Use new interfaces.
+	* memory.c: Use new interfaces.
+	(frv_address_forbidden): No longer static.
+
+1999-10-19  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frvbf_check_non_excepting_load): Set NESR.DAEC, NESR.REC and
+	NESR.EC.
+	* mloop.in (_parallel_write_queued): Handle CGEN_FN_PC_WRITE.
+	* frv.c (frvbf_h_pc_set_handler): New function.
+	* interrupts.c (frv_detect_data_interrupt): Removed.
+	(address_forbidden): Removed.
+	* frv-sim.h (frv_detect_data_interrupt): Removed.
+	(NESR_MEM_ADDRESS_NOT_ALIGNED): New macro.
+	(NESR_REGISTER_NOT_ALIGNED): New macro.
+	(NESR_UQI_SIZE): New macro.
+	(NESR_QI_SIZE): New macro.
+	(NESR_UHI_SIZE): New macro.
+	(NESR_HI_SIZE): New macro.
+	(NESR_SI_SIZE): New macro.
+	(NESR_DI_SIZE): New macro.
+	(NESR_XI_SIZE): New macro.
+	(GET_NESR_DAEC): New macro.
+	(SET_NESR_DAEC): New macro.
+	(GET_NESR_REC): New macro.
+	(SET_NESR_REC): New macro.
+	(GET_NESR_EC): New macro.
+	(SET_NESR_EC): New macro.
+	(frvbf_read_mem_QI): New function.
+	(frvbf_read_mem_UQI): New function.
+	(frvbf_read_mem_HI): New function.
+	(frvbf_read_mem_UHI): New function.
+	(frvbf_read_mem_SI): New function.
+	(frvbf_read_mem_WI): New function.
+	(frvbf_read_mem_DI): New function.
+	(frvbf_read_mem_DF): New function.
+	(frvbf_write_mem_QI): New function.
+	(frvbf_write_mem_UQI): New function.
+	(frvbf_write_mem_HI): New function.
+	(frvbf_write_mem_UHI): New function.
+	(frvbf_write_mem_SI): New function.
+	(frvbf_write_mem_WI): New function.
+	(frvbf_write_mem_DI): New function.
+	(frvbf_write_mem_DF): New function.
+	* Makefile.in (SIM_OBJS): Add memory.o.
+	* cpu.c,cpu.h,sem.c: Rebuild.
+
+1999-10-18  Dave Brolley  <brolley@cygnus.com>
+
+	* sim-if.c (sim_open): Use a real fpu error function.
+	* pipeline.c (frv_pipeline_add_insn): Don't add invalid insns.
+	* mloop.in (_parallel_write_queued): Clear queue after writing.
+	* interrupts.c (check_for_compound_interrupt): New function.
+	(non_operating_interrupt): New function.
+	* frv-sim.h (frvbf_h_gr_double_get_handler): New function.
+	(frvbf_h_gr_double_set_handler): New function.
+	(frvbf_h_fr_double_get_handler): New function.
+	(frvbf_h_fr_double_set_handler): New function.
+	(frvbf_h_cpr_double_get_handler): New function.
+	(frvbf_h_cpr_double_set_handler): New function.
+	(frv_interrupt_queue_element): New struct type.
+	(frv_queue_program_interrupt): Now takes pc.
+	(frv_queue_illegal_instruction_interrupt): Now takes pc.
+	(frv_queue_interrupt): Now takes pc.
+	(frv_program_interrupt): Now takes frv_interrupt_queue_element.
+	(frv_software_interrupt): Now takes frv_interrupt_queue_element.
+	(frvbf_division_exception): New function.
+	(frvbf_fpu_error): New function.
+	(frvbf_load_multiple_GR): New function.
+	(frvbf_load_multiple_FR): New function.
+	(frvbf_load_multiple_CPR): New function.
+	* frv.c (frvbf_h_gr_double_get_handler): New function.
+	(frvbf_h_gr_double_set_handler): New function.
+	(frvbf_h_fr_double_get_handler): New function.
+	(frvbf_h_fr_double_set_handler): New function.
+	(frvbf_h_cpr_double_get_handler): New function.
+	(frvbf_h_cpr_double_set_handler): New function.
+	(frv_interrupt_queue_element): New struct type.
+	(frv_queue_program_interrupt): Now takes pc.
+	(frv_queue_illegal_instruction_interrupt): Now takes pc.
+	(frv_queue_interrupt): Now takes pc.
+	(frv_program_interrupt): Now takes frv_interrupt_queue_element.
+	(frv_software_interrupt): Now takes frv_interrupt_queue_element.
+	(frvbf_fpu_error): New function.
+	(frvbf_load_multiple_GR): New function.
+	(frvbf_load_multiple_FR): New function.
+	(frvbf_load_multiple_CPR): New function.
+	* traps.c (frvbf_division_exception): New function.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+1999-10-12  Dave Brolley  <brolley@cygnus.com>
+
+	* mloop.in (new_vpc): New variable.
+	(main loop): Call frv_detect_insn_access_interrupts. Call
+	frv_detect_data_interrupts.
+	* interrupts.c (access_queued_to): New function.
+	(frv_detect_data_interrupts): New function.
+	(frv_detect_insn_access_interrupts): New function.
+	(frv_program_or_software_interrupt): Set PSR.S.
+	* frv-sim.h (frv_detect_data_interrupts): New function.
+	(frv_detect_insn_interrupts): New function.
+
+1999-10-07  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (frvbf_h_gr_hi_get_handler): New function.
+	(frvbf_h_gr_hi_set_handler): New function.
+	(frvbf_h_gr_lo_get_handler): New function.
+	(frvbf_h_gr_lo.set_handler): New function.
+	* frv.c (frvbf_h_gr_hi_get_handler): New function.
+	(frvbf_h_gr_hi_set_handler): New function.
+	(frvbf_h_gr_lo_get_handler): New function.
+	(frvbf_h_gr_lo.set_handler): New function.
+	(frvbf_model_fr500_u_integer): New function.
+	* arch.h,cpu.h,cpu.c,decode.h,decode.c,model.c,sem.c: Rebuild.
+
+1999-10-04  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c: Use sim_engine_abort.
+	* pipeline.c (frv_pipeline): Add field for insn major.
+	(add_next_to_pipe): Return address of matching pipeline.
+	(find_major_in_pipeline): New function.
+	(check_insn_major_constraints: New function.
+	(frv_pipeline_add_insn): Add checks for insn major constraints.
+	* interrupts.c (frv_process_interrupts): Use sim_engine_abort.
+	* frv.c (frvbf_h_spr_get_handler): No need to abort.
+
+Thu Sep 30 18:10:25 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* pipeline.c: New file.
+	* mloop.in (main loop): Call frv_pipeline_reset.
+ 	Call frv_pipeline_add_insn.
+	* frv-sim.h (frv_pipeline_reset): New function.
+	(frv_pipeline_add_insn): New function.
+	* Makefile.in (SIM_OBJS): Add pipeline.o
+
+1999-09-29  Doug Evans  <devans@casey.cygnus.com>
+
+	* sem.c: Rebuild.
+	* traps.c (sim_engine_invalid_insn): New arg `vpc'.  Change type of
+	result to SEM_PC.  Return vpc.
+
+Wed Sep 29 16:01:52 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* interrupts.c (frv_interrupt_table): DATA_STORE_ERROR is imprecise.
+	(frv_queue_interrupt): Don't detect identical interrupts here.
+
+Wed Sep 29 14:49:52 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* interrupts.c: New file.
+	* traps.c (sim_engine_invalid_insn): Return PC of next insn.
+	(frv_software_interrupt): Moved to interrupts.c.
+	(frv_itrap): New interface. Call frv_queue_software_interrupt.
+	* mloop.in (@cpu@_parallel_write_init): set previous_vliw_pc.
+	(@cpu@_perform_writeback): New function.
+	(main loop): Call frv_process_interrupts.
+	* frv-sim.h (frvbf_write_next_vliw_addr_to_PCSR): Removed.
+	(frv_itrap): New interface.
+	(frv_interrupt_class): New enumeration.
+	(frv_interrupt_kind): New enumeration.
+	(struct frv_interrupt): New struct type.
+	(frv_interrupt_table): New table of interrupt information.
+	(FRV_INTERRUPT_QUEUE_SIZE): New macro.
+	(struct frv_interrupt_state): New struct type.
+	(frv_interrupt_state): New global variable.
+	(previous_vliw_pc): New global variable.
+	(frv_queue_software_interrupt): New function.
+	(frv_queue_program_interrupt): New function.
+	(frv_queue_interrupt): New function.
+	(frv_process_interrupts): New function.
+	(frv_program_interrupt): New function.
+	(frv_software_interrupt): New function.
+	(frv_program_or_software_interrupt): New function.
+	(frv_clear_interrupt_classes): New function.
+	* frv.c (frvbf_write_next_vliw_addr_to_PCSR): Removed.
+	* Makefile.in (SIM_OBJS): Add interrupts.o
+	* sem.c: Rebuild.
+
+1999-09-25  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,cpuall.h,decode.c,sem.c: Rebuild.
+
+Tue Sep 21 17:16:47 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* mloop.in (main loop): Determine last insn from scache entry.
+	* cpu.h: Rebuild.
+	* cpuall.h: Rebuild.
+
+Tue Sep 14 14:21:31 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (frvbf_write_next_vliw_addr_to_PCSR): New flag.
+	(NECR_ELOS): Define as unshifted value.
+	(NECR_NEN): Define as unshifted value.
+	(NECR_VALID): Define as unshifted value.
+	(SET_NESR): Rewite to use post-write queue.
+	(SET_NESR_VALID): Rewite to operate on argument.
+	(SET_NESR_EAV): Rewite to operate on argument.
+	(SET_NESR_FR): Rewite to operate on argument.
+	(CLEAR_NESR_FR): Rewite to operate on argument.
+	(SET_NESR_DRN): Rewite to operate on argument.
+	(SET_NESR_SIZE): Rewite to operate on argument.
+	(SET_NESR_NEAN): Rewite to operate on argument.
+	(SET_NEEAR): Rewite to use post-write queue.
+	(SET_NE_FLAG): Rewite to use post-write queue.
+	(CLEAR_NE_FLAG): Rewite to use post-write queue.
+	* traps.c (frv_software_interrupt): Rewite to use post-write queue.
+	(frv_rett): Rewite to use post-write queue.
+	(next_available_nesr): Rewrite to use new macro interfaces.
+	(next_valid_nesr): Ditto.
+	(frvbf_check_non_excepting_load): Ditto.
+	(frvbf_check_recovering_store): Ditto.
+	(clear_nesr_neear): Ditto.
+	(clear_ne_flags): Ditto.
+	* mloop.in (main loop): Update PCSR with address of next VLIW insn
+	when flag is set.
+	* frv.c (frvbf_h_spr_get_handler): Shift register fields here now.
+	(frvbf_store_multiple_GR): Rewite to use post-write queue.
+	(frvbf_store_multiple_FRint): Rewite to use post-write queue.
+	(frvbf_store_multiple_CPR): Rewite to use post-write queue.
+	* Makefile.in (frv.o): Depend on cgen-par.h.
+
+Fri Sep 10 17:03:15 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (frvbf_set_write_next_vliw_addr_to_LR): New function.
+	(frvbf_write_next_vliw_addr_to_LR): New flag.
+	* frv.c (frvbf_set_write_next_vliw_addr_to_LR): New function.
+	* mloop.in: Only take the first branch in a VLIW insn. Set LR to the
+	address of the next VLIW insn if flag is set.
+	* cpu.h,decode.c,sem.c: Rebuild.
+
+Tue Sep  7 13:44:23 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* mloop.in: Limit parallel insns to MAX_PARALLEL_INSNS.
+	* sem.c: Rebuild.
+
+1999-09-02  Doug Evans  <devans@casey.cygnus.com>
+
+	* configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-09-01  Doug Evans  <devans@casey.cygnus.com>
+
+	* decode.c: Rebuild.
+
+Mon Aug 30 17:54:57 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frv_rett): New function.
+	* frv.c (frvbf_h_spr_get_handler): Handle bpsr.
+	(frvbf_h_spr_set_handler): Handle bpsr.
+	(frvbf_h_bpsr_get_handler): New function.
+	(frvbf_h_bpsr_set_handler): New function.
+	* frv-sim.h (frv_rett): New function.
+	(frvbf_h_bpsr_get_handler): New function.
+	(frvbf_h_bpsr_set_handler): New function.
+	* mloop.in: Read actual packing bit.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+Tue Aug 31 16:04:37 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (WANT_CPU): New macro.
+	(WANT_CPU_FRVBF): New macro.
+	(frvbf_check_recovering_store): Use registers for source and queue
+ 	writes.
+	* mloop.in: New main loop for parallel support.
+	(@cpu@_parallel_write_init): New function.
+	(@cpu@_parallel_write_queued): New function.
+	* frv-sim.h (set_icc_for_shift_left): New interface.
+	(set_icc_for_shift_right): New interface.
+	(frvbf_check_recovering_store): New interface.
+	* frv.c (set_icc_for_shift_left): Pass and return icc value.
+	(set_icc_for_shift_right): Pass and return icc value.
+	(frvbf_check_recovering_store): New interface.
+	* Makefile.in (FRV_OBJS): Add cgen-par.o.
+	(stamp-mloop): Add cgen parallel options.
+	(stamp-arch): Remove with-profile option.
+	(stamp-cpu): Add cgen parallel options.
+	* arch.h,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+1999-08-28  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.c,sem.c: Rebuild.
+
+Wed Aug 25 12:25:04 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.h,cpu.h,decode.h,model.c,sem.c: Rebuild.
+
+Thu Aug 19 17:59:00 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* configure.in: fr500 now the default model.
+	* configure: Regenerate.
+	* frv.c: Change frv-1 to frv-gen.
+	(frvbf_model_fr500_u_exec): New function.
+	* Makefile.in (stamp-cpu): Use 'mach=frv,fr500' to build decoder.
+	* mloop.in: Fix typos in comments.
+	* arch.c,arch.h,cpu.h,cpuall.h,decode.h,model.c,sem.c: Rebuild.
+
+1999-08-17  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+1999-08-09  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+1999-08-04  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,cpuall.h,decode.c,model.c,sem.c: Rebuild.
+
+Fri Jul 16 14:50:15 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_fetch_register): Use GDB register number macros.
+	(frvbf_store_register): Use GDB register number macros.
+	(frvbf_cut): New function.
+	* frv-sim.h (GR_REGNUM_MAX): New macro.
+	(FR_REGNUM_MAX): New macro.
+	(PC_REGNUM): New macro.
+	(LR_REGNUM): New macro.
+	(frvbf_cut): New function.
+	* cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+
+1999-07-15  Stan Shebs  <shebs@andros.cygnus.com>
+
+	* frv.c (frvbf_fetch_register): Add ability to get LR register,
+ 	add default for unhandled registers.
+	(frvbf_store_register): Add ability to set LR register.
+
+1999-07-14  Stan Shebs  <shebs@andros.cygnus.com>
+
+	* frv.c (frvbf_fetch_register, frvbf_store_register): Fill in.
+	(decode_gdb_dr_regnum): Remove, not used.
+
+1999-07-13  Michael Meissner  <meissner@cygnus.com>
+
+	* Makefile.in (SIM_EXTRA_FLAGS): Incorporate @sim_trapdump@.
+
+	* configure.in (--enable-sim-trapdump): New switch to make unknown
+	traps dump the register contents, instead of doing the trap thing.
+	* configure: Regenerate.
+
+	* frv-sim.h (TRAP_BREAKPOINT): Define as 81, so it can be used.
+	(TRAP_REGDUMP{1,2}): Define to provide register dumping support
+	temporarily.
+
+	* traps.h (toplevel): Include bfd.h, libiberity.h.
+	(frv_itrap): Add support for --enable-sim-trapdump and traps 2,3
+	dumping the registers.
+
+Thu Jul  8 10:57:39 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* Makefile.in (SIM_EXTRA_LIBS): Removed. libm no longer needed.
+
+Wed Jul  7 17:01:12 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.c,cpu.h,decode.c,model.c,sem.c: Rebuild.
+
+Tue Jul  6 16:12:18 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_square_root_SF): Removed.
+	(frvbf_square_root_DF): Removed.
+	(frvbf_h_fr_double_get_handler): Removed.
+	(frvbf_h_fr_double_set_handler): Removed.
+	(frvbf_h_fr_int_get_handler): Removed.
+	(frvbf_h_fr_int_set_handler): Removed.
+	* frv-sim.h (frvbf_square_root_SF): Removed.
+	(frvbf_square_root_DF): Removed.
+	(frvbf_h_fr_double_get_handler): Removed.
+	(frvbf_h_fr_double_set_handler): Removed.
+	(frvbf_h_fr_int_get_handler): Removed.
+	(frvbf_h_fr_int_set_handler): Removed.
+	* decode.c,decode.h,model.c,sem.c: Rebuild.
+
+1999-07-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (SIM_OBJS): Add cgen-fpu.o, cgen-accfp.o.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Rebuild.
+	* sim-if.c (sim_open): Initialize fpu.
+	* frv-sim.h (SETMEMSF,SETMEMDF): Delete.
+	* frv.c (frvbf_store_multiple_FRint): Replace frvbf_h_fr_int_get
+	with frvbf_h_fr_get.
+
+Wed Jun 30 15:56:56 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (NESR_RANGE): New macro.
+	(NO_NESR): New macro.
+	(GET_NESR_VALID): New macro.
+	(next_ne_index): Removed.
+	* traps.c (next_available_nesr): New function.
+	(next_valid_nesr): New function.
+	(frvbf_check_non_excepting_load): Use next_available_nesr.
+	(frvbf_check_recovering_store): Use next_available_nesr and
+	next_valid_nesr.
+	(clear_nesr_neear): Use next_available_nesr and	next_valid_nesr.
+	(frvbf_check_recovering_store): Only consider one matching register.
+	* sem.c: Rebuild.
+
+Tue Jun 29 16:54:32 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_square_root_SF): New function.
+	(frvbf_square_root_DF): New function.
+	(frvbf_h_fr_double_get_handler): New function.
+	(frvbf_h_fr_double_set_handler): New function.
+	* frv-sim.h (frvbf_square_root_SF): New function.
+	(frvbf_square_root_DF): New function.
+	(frvbf_h_fr_double_get_handler): New function.
+	(frvbf_h_fr_double_set_handler): New function.
+	* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c: Rebuild.
+
+1999-06-28  Dave Brolley  <brolley@cygnus.com>
+
+	* decode.c,decode.h,model.c,sem.c: Regenerate.
+
+Thu Jun 24 17:26:32 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* Makefile.in (SIM_EXTRA_LIBS): Add -lm.
+	* frv-sim.h (frvbf_h_fr_int_get_handler): New function.
+	(frvbf_h_fr_int_set_handler): New function.
+	(frvbf_store_multiple_FRint): New function.
+	(frvbf_square_root_SF): New function.
+	* frv.c (frvbf_h_fr_int_get_handler): New function.
+	(frvbf_h_fr_int_set_handler): New function.
+	(frvbf_store_multiple_FRint): New function.
+	(frvbf_square_root_SF): New function.
+	* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+1999-06-23  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (stamp-mloop): Delete -fast -pbb -switch args
+	to genmloop.sh.  Pass -scache instead.
+	(mloop.o): Delete sem-switch.c dependency.
+	(sem-switch.c): Delete rule.
+	(stamp-cpu): Don't build sem-switch.c.
+	* sem-switch.c: Delete.
+	* mloop.in (xfull-exec-*): Fix call to execute.
+	* tconfig.in (WITH_SCACHE_PBB): Define as 0.
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+
+Tue Jun 22 16:23:57 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,sem.c,sem-switch.c: Regenerate.
+
+Mon Jun 21 17:34:10 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* mloop.in (execute): Force gr0 to zero before each insn.
+	* cpu.h,cpu.c,decode.c,sem.c,sem-switch.c: Regenerate.
+
+1999-06-18  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+
+Fri Jun 18 17:49:23 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_h_gr_get_handler): New function.
+	(frvbf_h_gr_set_handler): New function:
+	(frvbf_store-multiple_GR): New function:
+	(frvbf_store-multiple_FR): New function:
+	(frvbf_store-multiple_CPR): New function:
+	* frv-sim.h (frvbf_h_gr_get_handler): New function.
+	(frvbf_h_gr_set_handler): New function:
+	(frvbf_store-multiple_GR): New function:
+	(frvbf_store-multiple_FR): New function:
+	(frvbf_store-multiple_CPR): New function:
+	* traps.c (frv_itrap): Implement proper syscalls interface.
+	* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Fri Jun 18 14:36:23 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frvbf_check_non_excepting_divide): New function.
+	(frvbf_check_recovering_store): New function.
+	(clear_nesr_neear): New function.
+	(clear_ne_flags): New function.
+	(frvbf_commit): New function.
+
+	* frv-sim.h (frvbf_check_non_excepting_divide): New function.
+	(frvbf_check_recovering_store): New function.
+	(clear_nesr_neear): New function.
+	(clear_ne_flags): New function.
+	(frvbf_commit): New function.
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+1999-06-16  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_h_spr_get_handler): Handle SPR_NECR.
+	(frvbf_h_spr_set_handler): Handle SPR_NECR.
+	* traps.c (next_ne_index): New variable.
+	(frvbf_check_non_excepting_load): New function.
+	* frv-sim.h (NECR_ELOS): New macro.
+	(NECR_NEN): New macro.
+	(NECR_VALID): New macro.
+	(SET_NESR_VALID): New macro.
+	(SET_NESR_EAV): New macro.
+	(SET_NESR_FR): New macro.
+	(CLEAR_NESR_FR): New macro.
+	(SET_NESR_DRN): New macro.
+	(SET_NESR_SIZE): New macro.
+	(SET_NESR_NEAN): New macro.
+	(SET_NEEAR): New macro.
+	(GET_NE_FLAG): New macro.
+	(SET_NE_FLAG): New macro.
+	(CLEAR_NE_FLAG): New macro.
+	(frvbf_check_non_excepting_load): New function:
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Wed Jun  9 18:12:49 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
+
+Tue Jun  8 18:13:51 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (cr_logic): Correct andcr, nandcr, andncr and nandncr.
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Mon Jun  7 17:09:15 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+1999-06-07  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Thu Jun  3 17:33:31 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Wed Jun  2 17:50:21 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Tue Jun  1 17:58:53 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
+
+Mon May 31 17:57:25 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frv_software_interrupt): Pass current_cpu to
+	frvbf_h_psr_esr_get.
+	(frv_software_interrupt): Calculate the new PC based on TBR.
+	* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
+
+1999-05-31  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
+
+Thu May 27 17:42:00 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (frvbf_h_cccr_get_handler): New function.
+	(frvbf_h_cccr_set_handler): New function.
+	(frvbf_scan_result): New function.
+	(frvbf_cr_logic): New function.
+	* frv.c (frvbf_h_cccr_get_handler): New function.
+	(frvbf_h_cccr_set_handler): New function.
+	(frvbf_scan_result): New function.
+	(frvbf_cr_logic): New function.
+	(cr_ops,cr_result,cr_logic): New table.
+	* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
+
+1999-05-25  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_h_spr_get_handler): Add support for TBR and PSR.
+	(frvbf_h_spr_set_handler): Add support for TBR and PSR.
+	(frv_psr_get_handler): New function.
+	(frv_psr_set_handler): New function.
+	(frv_tbr_get_handler): New function.
+	(frv_tbr_set_handler): New function.
+	(frvbf_h_ccr_get_handler): Add support for fCC.
+	(frvbf_h_ccr_set_handler): Add support for fCC.
+	* frv-sim.h (frv_psr_get_handler): New function.
+	(frv_psr_set_handler): New function.
+	(frv_tbr_get_handler): New function.
+	(frv_tbr_set_handler): New function.
+	* traps.c (frv_software_interrupt): Implement.
+	* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Thu May 20 16:39:27 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+1999-05-18  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c: (frvbf_set_icc_for_shift_left): New function.
+	(frvbf_set_icc_for_shift_right): New function.
+	* frv-sim.h (frvbf_set_icc_for_shift_left): New function.
+	(frvbf_set_icc_for_shift_right): New function.
+	(SETMEMSF): New Macro.
+	(SETMEMDF): New Macro.
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Thu May 13 17:14:49 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv.c (frvbf_h_ccr_get_handler): New function.
+	(frvbf_h_ccr_set_handler): New function.
+	* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Tue May 11 16:13:15 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* frv-sim.h (frvbf_h_spr_get_handler,frvbf_h_spr_set_handler,
+ 	frvbf_h_isr_get_handler, frvbf_h_isr_set_handler): New functions.
+	* frv.c: Likewise.
+	* cpu.h,cpu.c,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+1999-05-10  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,cpu.c,decode.c,model.c,sem.c,sem-switch.c: Regenerate.
+
+Thu May  6 16:48:21 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,sem.c,sem-switch.c: Regenerate.
+	* frv-sim.h (TRAP_SYSCALL): Define as 0x80.
+
+Wed May  5 11:52:24 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (frv_software_interrupt): New function.
+	(frv_itrap): New function.
+	* frv-sim.h (TRAP_SYSCALL): define as 0.
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Mon May  3 13:49:21 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem.c,sem-switch.c: Regenerate.
+
+Thu Apr 29 17:37:06 1999  Dave Brolley  <brolley@cygnus.com>
+
+	* Directory created.
diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in
new file mode 100644
index 00000000000..f01d421fe8c
--- /dev/null
+++ b/sim/frv/Makefile.in
@@ -0,0 +1,133 @@
+# Makefile template for Configure for the frv simulator
+# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+# Contributed by Red Hat.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+FRV_OBJS = frv.o cpu.o decode.o sem.o model.o mloop.o cgen-par.o
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+	$(SIM_NEW_COMMON_OBJS) \
+	sim-cpu.o \
+	sim-hload.o \
+	sim-hrw.o \
+	sim-model.o \
+	sim-reg.o \
+	cgen-utils.o cgen-trace.o cgen-scache.o cgen-fpu.o cgen-accfp.o \
+	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+	sim-if.o arch.o \
+	$(FRV_OBJS) \
+	traps.o interrupts.o memory.o cache.o pipeline.o \
+	profile.o profile-fr400.o profile-fr500.o options.o \
+	devices.o reset.o registers.o \
+	$(CONFIG_DEVICES)
+
+# Extra headers included by sim-main.h.
+SIM_EXTRA_DEPS = \
+	$(CGEN_INCLUDE_DEPS) \
+	arch.h cpuall.h frv-sim.h $(srcdir)/../../opcodes/frv-desc.h cache.h \
+	registers.h profile.h \
+	$(sim-options_h)
+
+SIM_EXTRA_CFLAGS = @sim_trapdump@
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = frv-clean
+
+# This selects the frv newlib/libgloss syscall definitions.
+NL_TARGET = -DNL_TARGET_frv
+
+## COMMON_POST_CONFIG_FRAG
+
+arch = frv
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+
+devices.o: devices.c $(SIM_MAIN_DEPS)
+
+# FRV objs
+
+FRVBF_INCLUDE_DEPS = \
+	$(CGEN_MAIN_CPU_DEPS) \
+	$(SIM_EXTRA_DEPS) \
+	cpu.h decode.h eng.h
+
+frv.o: frv.c $(FRVBF_INCLUDE_DEPS)
+traps.o: traps.c $(FRVBF_INCLUDE_DEPS)
+pipeline.o: pipeline.c $(FRVBF_INCLUDE_DEPS)
+interrupts.o: interrupts.c $(FRVBF_INCLUDE_DEPS)
+memory.o: memory.c $(FRVBF_INCLUDE_DEPS)
+cache.o: cache.c $(FRVBF_INCLUDE_DEPS)
+options.o: options.c $(FRVBF_INCLUDE_DEPS)
+reset.o: reset.c $(FRVBF_INCLUDE_DEPS)
+registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
+profile.o: profile.c profile-fr400.h profile-fr500.h $(FRVBF_INCLUDE_DEPS)
+profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
+profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
+sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
+
+
+# FIXME: Use of `mono' is wip.
+mloop.c eng.h: stamp-mloop
+stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+	$(SHELL) $(srccom)/genmloop.sh \
+		-mono -scache -parallel-generic-write -parallel-only \
+		-cpu frvbf -infile $(srcdir)/mloop.in
+	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
+	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
+	touch stamp-mloop
+mloop.o: mloop.c $(FRVBF_INCLUDE_DEPS)
+
+cpu.o: cpu.c $(FRVBF_INCLUDE_DEPS)
+decode.o: decode.c $(FRVBF_INCLUDE_DEPS)
+sem.o: sem.c $(FRVBF_INCLUDE_DEPS)
+model.o: model.c $(FRVBF_INCLUDE_DEPS)
+
+frv-clean:
+	rm -f mloop.c eng.h stamp-mloop
+	rm -f tmp-*
+	rm -f stamp-arch stamp-cpu
+
+# cgen support, enable with --enable-cgen-maint
+CGEN_MAINT = ; @true
+# The following line is commented in or out depending upon --enable-cgen-maint.
+@CGEN_MAINT@CGEN_MAINT =
+
+stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(srcdir)/../../cpu/frv.cpu
+	cp -fp $(srcdir)/../../cpu/frv.cpu $(CGEN_CPU_DIR)/frv.cpu
+	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
+	  FLAGS="with-scache"
+	rm -f $(CGEN_CPU_DIR)/frv.cpu
+	touch stamp-arch
+arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
+#	@true
+
+# .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so
+# copy those file to the regular place.
+stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
+	cp -fp $(srcdir)/../../cpu/frv.cpu $(CGEN_CPU_DIR)/frv.cpu
+	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+	  cpu=frvbf mach=frv,fr500,fr400,tomcat,simple SUFFIX= \
+	  FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
+	  EXTRAFILES="$(CGEN_CPU_SEM)"
+	rm -f $(CGEN_CPU_DIR)/frv.cpu
+	touch stamp-cpu
+cpu.h sem.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
+#	@true
diff --git a/sim/frv/README b/sim/frv/README
new file mode 100644
index 00000000000..a88ea1922c0
--- /dev/null
+++ b/sim/frv/README
@@ -0,0 +1,10 @@
+This is the frv simulator directory.
+
+It is still work-in-progress.  The current sources are
+well tested and lots of features are in.
+
+There are lots of machine generated files in the source directory!
+They are only generated if you configure with --enable-cgen-maint,
+similar in behaviour to Makefile.in, configure under automake/autoconf.
+
+For details on the generator, see ../../cgen.
diff --git a/sim/frv/TODO b/sim/frv/TODO
new file mode 100644
index 00000000000..6aa400b045d
--- /dev/null
+++ b/sim/frv/TODO
@@ -0,0 +1,8 @@
+- header file dependencies revisit
+- hooks cleanup
+- testsuites
+- FIXME's
+- memory accesses still test if profiling is on even in fast mode
+- have semantic code use G/SET_H_FOO if not default [incl fun-access]
+- have G/SET_H_FOO macros call function if fun-access
+- --> can always use G/S_H_FOO macros
diff --git a/sim/frv/arch.c b/sim/frv/arch.c
new file mode 100644
index 00000000000..5161fb2ae2d
--- /dev/null
+++ b/sim/frv/arch.c
@@ -0,0 +1,47 @@
+/* Simulator support for frv.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_FRVBF
+  & frv_mach,
+#endif
+#ifdef HAVE_CPU_FRVBF
+  & fr500_mach,
+#endif
+#ifdef HAVE_CPU_FRVBF
+  & tomcat_mach,
+#endif
+#ifdef HAVE_CPU_FRVBF
+  & fr400_mach,
+#endif
+#ifdef HAVE_CPU_FRVBF
+  & simple_mach,
+#endif
+  0
+};
+
diff --git a/sim/frv/arch.h b/sim/frv/arch.h
new file mode 100644
index 00000000000..e2517d7646b
--- /dev/null
+++ b/sim/frv/arch.h
@@ -0,0 +1,69 @@
+/* Simulator header for frv.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FRV_ARCH_H
+#define FRV_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Enum declaration for model types.  */
+typedef enum model_type {
+  MODEL_FRV, MODEL_FR500, MODEL_TOMCAT, MODEL_FR400
+ , MODEL_SIMPLE, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types.  */
+typedef enum unit_type {
+  UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR500_U_DCUL, UNIT_FR500_U_ICUL
+ , UNIT_FR500_U_DCPL, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF, UNIT_FR500_U_DCI
+ , UNIT_FR500_U_ICI, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER, UNIT_FR500_U_MEDIA_DUAL_BTOHE
+ , UNIT_FR500_U_MEDIA_DUAL_HTOB, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK, UNIT_FR500_U_MEDIA_DUAL_EXPAND
+ , UNIT_FR500_U_MEDIA_QUAD_COMPLEX, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL, UNIT_FR500_U_MEDIA_QUAD_ARITH
+ , UNIT_FR500_U_MEDIA, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT, UNIT_FR500_U_FLOAT_DUAL_COMPARE
+ , UNIT_FR500_U_FLOAT_COMPARE, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT, UNIT_FR500_U_FLOAT_DIV
+ , UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR, UNIT_FR500_U_GR2FR
+ , UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR, UNIT_FR500_U_SWAP
+ , UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD, UNIT_FR500_U_GR_R_STORE
+ , UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CHECK
+ , UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL
+ , UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL
+ , UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF
+ , UNIT_FR400_U_DCI, UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER
+ , UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6
+ , UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD
+ , UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB
+ , UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2
+ , UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR
+ , UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP
+ , UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD
+ , UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH
+ , UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC
+ , UNIT_SIMPLE_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+#endif /* FRV_ARCH_H */
diff --git a/sim/frv/cache.c b/sim/frv/cache.c
new file mode 100644
index 00000000000..5093f16b5ef
--- /dev/null
+++ b/sim/frv/cache.c
@@ -0,0 +1,1561 @@
+/* frv cache model.
+   Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "libiberty.h"
+#include "sim-main.h"
+#include "cache.h"
+#include "bfd.h"
+
+void
+frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
+{
+  int elements;
+  int i, j;
+  SIM_DESC sd;
+
+  /* Set defaults for fields which are not initialized.  */
+  sd = CPU_STATE (cpu);
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      if (cache->sets == 0)
+	cache->sets = 128;
+      if (cache->ways == 0)
+	cache->ways = 2;
+      if (cache->line_size == 0)
+	cache->line_size = 32;
+      if (cache->memory_latency == 0)
+	cache->memory_latency = 20;
+      break;
+    default:
+      if (cache->sets == 0)
+	cache->sets = 64;
+      if (cache->ways == 0)
+	cache->ways = 4;
+      if (cache->line_size == 0)
+	cache->line_size = 64;
+      if (cache->memory_latency == 0)
+	cache->memory_latency = 20;
+      break;
+    }
+
+  /* First allocate the cache storage based on the given dimensions.  */
+  elements = cache->sets * cache->ways;
+  cache->tag_storage = (FRV_CACHE_TAG *)
+    zalloc (elements * sizeof (*cache->tag_storage));
+  cache->data_storage = (char *) xmalloc (elements * cache->line_size);
+
+  /* Initialize the pipelines and status buffers.  */
+  for (i = LS; i < FRV_CACHE_PIPELINES; ++i)
+    {
+      cache->pipeline[i].requests = NULL;
+      cache->pipeline[i].status.flush.valid = 0;
+      cache->pipeline[i].status.return_buffer.valid = 0;
+      cache->pipeline[i].status.return_buffer.data
+	= (char *) xmalloc (cache->line_size);
+      for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j)
+	cache->pipeline[i].stages[j].request = NULL;
+    }
+  cache->BARS.valid = 0;
+  cache->NARS.valid = 0;
+
+  /* Now set the cache state.  */
+  cache->cpu = cpu;
+  cache->statistics.accesses = 0;
+  cache->statistics.hits = 0;
+}
+
+void
+frv_cache_term (FRV_CACHE *cache)
+{
+  /* Free the cache storage.  */
+  free (cache->tag_storage);
+  free (cache->data_storage);
+  free (cache->pipeline[LS].status.return_buffer.data);
+  free (cache->pipeline[LD].status.return_buffer.data);
+}
+
+/* Determine whether the given cache is enabled.  */
+int
+frv_cache_enabled (FRV_CACHE *cache)
+{
+  SIM_CPU *current_cpu = cache->cpu;
+  int hsr0 = GET_HSR0 ();
+  if (GET_HSR0_ICE (hsr0) && cache == CPU_INSN_CACHE (current_cpu))
+    return 1;
+  if (GET_HSR0_DCE (hsr0) && cache == CPU_DATA_CACHE (current_cpu))
+    return 1;
+  return 0;
+}
+
+/* Determine whether the given address should be accessed without using
+   the cache.  */
+static int
+non_cache_access (FRV_CACHE *cache, USI address) 
+{
+  int hsr0;
+  SIM_DESC sd;
+  SIM_CPU *current_cpu = cache->cpu;
+
+  sd = CPU_STATE (current_cpu);
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      if (address >= 0xff000000
+	  || address >= 0xfe000000 && address <= 0xfeffffff)
+	return 1; /* non-cache access */
+    default:
+      if (address >= 0xff000000
+	  || address >= 0xfeff0000 && address <= 0xfeffffff)
+	return 1; /* non-cache access */
+      if (cache == CPU_INSN_CACHE (current_cpu))
+	{
+	  if (address >= 0xfe000000 && address <= 0xfe003fff)
+	    return 1; /* non-cache access */
+	}
+      else if (address >= 0xfe400000 && address <= 0xfe403fff)
+	return 1; /* non-cache access */
+    }
+
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_RME (hsr0))
+    return 1; /* non-cache access */
+
+  return 0; /* cache-access */
+}
+
+/* Find the cache line corresponding to the given address.
+   If it is found then 'return_tag' is set to point to the tag for that line
+   and 1 is returned.
+   If it is not found, 'return_tag' is set to point to the tag for the least
+   recently used line and 0 is returned.
+*/
+static int
+get_tag (FRV_CACHE *cache, SI address, FRV_CACHE_TAG **return_tag)
+{
+  int set;
+  int way;
+  int bits;
+  USI tag;
+  FRV_CACHE_TAG *found;
+  FRV_CACHE_TAG *available;
+
+  ++cache->statistics.accesses;
+
+  /* First calculate which set this address will fall into. Do this by
+     shifting out the bits representing the offset within the line and
+     then keeping enough bits to index the set.  */
+  set = address & ~(cache->line_size - 1);
+  for (bits = cache->line_size - 1; bits != 0; bits >>= 1)
+    set >>= 1;
+  set &= (cache->sets - 1);
+  
+  /* Now search the set for a valid tag which matches this address.  At the
+     same time make note of the least recently used tag, which we will return
+     if no match is found.  */
+  available = NULL;
+  tag = CACHE_ADDRESS_TAG (cache, address);
+  for (way = 0; way < cache->ways; ++way)
+    {
+      found = CACHE_TAG (cache, set, way);
+      /* This tag is available as the least recently used if it is the
+	 least recently used seen so far and it is not locked.  */
+      if (! found->locked && (available == NULL || available->lru > found->lru))
+	available = found;
+      if (found->valid && found->tag == tag)
+	{
+	  *return_tag = found;
+	  ++cache->statistics.hits;
+	  return 1; /* found it */
+	}
+    }
+
+  *return_tag = available;
+  return 0; /* not found */
+}
+
+/* Write the given data out to memory.  */
+static void
+write_data_to_memory (FRV_CACHE *cache, SI address, char *data, int length)
+{
+  SIM_CPU *cpu = cache->cpu;
+  IADDR pc = CPU_PC_GET (cpu);
+  int write_index = 0;
+
+  switch (length)
+    {
+    case 1:
+    default:
+      PROFILE_COUNT_WRITE (cpu, address, MODE_QI);
+      break;
+    case 2:
+      PROFILE_COUNT_WRITE (cpu, address, MODE_HI);
+      break;
+    case 4:
+      PROFILE_COUNT_WRITE (cpu, address, MODE_SI);
+      break;
+    case 8:
+      PROFILE_COUNT_WRITE (cpu, address, MODE_DI);
+      break;
+    }
+
+  for (write_index = 0; write_index < length; ++write_index)
+    {
+      /* TODO: Better way to copy memory than a byte at a time?  */
+      sim_core_write_unaligned_1 (cpu, pc, write_map, address + write_index,
+				  data[write_index]);
+    }
+}
+
+/* Write a cache line out to memory.  */
+static void
+write_line_to_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag)
+{
+  SI address = tag->tag;
+  int set = CACHE_TAG_SET_NUMBER (cache, tag);
+  int bits;
+  for (bits = cache->line_size - 1; bits != 0; bits >>= 1)
+    set <<= 1;
+  address |= set;
+  write_data_to_memory (cache, address, tag->line, cache->line_size);
+}
+
+static void
+read_data_from_memory (SIM_CPU *current_cpu, SI address, char *buffer,
+		       int length)
+{
+  PCADDR pc = CPU_PC_GET (current_cpu);
+  int i;
+  PROFILE_COUNT_READ (current_cpu, address, MODE_QI);
+  for (i = 0; i < length; ++i)
+    {
+      /* TODO: Better way to copy memory than a byte at a time?  */
+      buffer[i] = sim_core_read_unaligned_1 (current_cpu, pc, read_map,
+					     address + i);
+    }
+}
+
+/* Fill the given cache line from memory.  */
+static void
+fill_line_from_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag, SI address)
+{
+  PCADDR pc;
+  int line_alignment;
+  SI read_address;
+  SIM_CPU *current_cpu = cache->cpu;
+
+  /* If this line is already valid and the cache is in copy-back mode, then
+     write this line to memory before refilling it.
+     Check the dirty bit first, since it is less likely to be set.  */
+  if (tag->dirty && tag->valid)
+    {
+      int hsr0 = GET_HSR0 ();
+      if (GET_HSR0_CBM (hsr0))
+	write_line_to_memory (cache, tag);
+    }
+  else if (tag->line == NULL)
+    {
+      int line_index = tag - cache->tag_storage;
+      tag->line = cache->data_storage + (line_index * cache->line_size);
+    }
+
+  pc = CPU_PC_GET (current_cpu);
+  line_alignment = cache->line_size - 1;
+  read_address = address & ~line_alignment;
+  read_data_from_memory (current_cpu, read_address, tag->line,
+			 cache->line_size);
+  tag->tag = CACHE_ADDRESS_TAG (cache, address);
+  tag->valid = 1;
+}
+
+/* Update the LRU information for the tags in the same set as the given tag.  */
+static void
+set_most_recently_used (FRV_CACHE *cache, FRV_CACHE_TAG *tag)
+{
+  /* All tags in the same set are contiguous, so find the beginning of the
+     set by aligning to the size of a set.  */
+  FRV_CACHE_TAG *item = cache->tag_storage + CACHE_TAG_SET_START (cache, tag);
+  FRV_CACHE_TAG *limit = item + cache->ways;
+
+  while (item < limit)
+    {
+      if (item->lru > tag->lru)
+	--item->lru;
+      ++item;
+    }
+  tag->lru = cache->ways; /* Mark as most recently used.  */
+}
+
+/* Update the LRU information for the tags in the same set as the given tag.  */
+static void
+set_least_recently_used (FRV_CACHE *cache, FRV_CACHE_TAG *tag)
+{
+  /* All tags in the same set are contiguous, so find the beginning of the
+     set by aligning to the size of a set.  */
+  FRV_CACHE_TAG *item = cache->tag_storage + CACHE_TAG_SET_START (cache, tag);
+  FRV_CACHE_TAG *limit = item + cache->ways;
+
+  while (item < limit)
+    {
+      if (item->lru != 0 && item->lru < tag->lru)
+	++item->lru;
+      ++item;
+    }
+  tag->lru = 0; /* Mark as least recently used.  */
+}
+
+/* Find the line containing the given address and load it if it is not
+   already loaded.
+   Returns the tag of the requested line.  */
+static FRV_CACHE_TAG *
+find_or_retrieve_cache_line (FRV_CACHE *cache, SI address)
+{
+  /* See if this data is already in the cache.  */
+  FRV_CACHE_TAG *tag;
+  int found = get_tag (cache, address, &tag);
+
+  /* Fill the line from memory, if it is not valid.  */
+  if (! found)
+    {
+      /* The tag could be NULL is all ways in the set were used and locked.  */
+      if (tag == NULL)
+	return tag;
+
+      fill_line_from_memory (cache, tag, address);
+      tag->dirty = 0;
+    }
+
+  /* Update the LRU information for the tags in this set.  */
+  set_most_recently_used (cache, tag);
+
+  return tag;
+}
+
+static void
+copy_line_to_return_buffer (FRV_CACHE *cache, int pipe, FRV_CACHE_TAG *tag,
+			    SI address)
+{
+  /* A cache line was available for the data.
+     Copy the data from the cache line to the output buffer.  */
+  memcpy (cache->pipeline[pipe].status.return_buffer.data,
+	  tag->line, cache->line_size);
+  cache->pipeline[pipe].status.return_buffer.address
+    = address & ~(cache->line_size - 1);
+  cache->pipeline[pipe].status.return_buffer.valid = 1;
+}
+
+static void
+copy_memory_to_return_buffer (FRV_CACHE *cache, int pipe, SI address)
+{
+  address &= ~(cache->line_size - 1);
+  read_data_from_memory (cache->cpu, address,
+			 cache->pipeline[pipe].status.return_buffer.data,
+			 cache->line_size);
+  cache->pipeline[pipe].status.return_buffer.address = address;
+  cache->pipeline[pipe].status.return_buffer.valid = 1;
+}
+
+static void
+set_return_buffer_reqno (FRV_CACHE *cache, int pipe, unsigned reqno)
+{
+  cache->pipeline[pipe].status.return_buffer.reqno = reqno;
+}
+
+/* Read data from the given cache.
+   Returns the number of cycles required to obtain the data.  */
+int
+frv_cache_read (FRV_CACHE *cache, int pipe, SI address)
+{
+  FRV_CACHE_TAG *tag;
+
+  if (non_cache_access (cache, address))
+    {
+      copy_memory_to_return_buffer (cache, pipe, address);
+      return 1;
+    }
+	
+  tag = find_or_retrieve_cache_line (cache, address);
+
+  if (tag == NULL)
+    return 0; /* Indicate non-cache-access.  */
+
+  /* A cache line was available for the data.
+     Copy the data from the cache line to the output buffer.  */
+  copy_line_to_return_buffer (cache, pipe, tag, address);
+
+  return 1; /* TODO - number of cycles unknown */
+}
+
+/* Writes data through the given cache.
+   The data is assumed to be in target endian order.
+   Returns the number of cycles required to write the data.  */
+int
+frv_cache_write (FRV_CACHE *cache, SI address, char *data, unsigned length)
+{
+  int copy_back;
+
+  /* See if this data is already in the cache.  */
+  SIM_CPU *current_cpu = cache->cpu;
+  USI hsr0 = GET_HSR0 ();
+  FRV_CACHE_TAG *tag;
+  int found;
+
+  if (non_cache_access (cache, address))
+    {
+      write_data_to_memory (cache, address, data, length);
+      return 1;
+    }
+
+  found = get_tag (cache, address, &tag);
+
+  /* Write the data to the cache line if one was available and if it is
+     either a hit or a miss in copy-back mode.
+     The tag may be NULL if all ways were in use and locked on a miss.
+  */
+  copy_back = GET_HSR0_CBM (GET_HSR0 ());
+  if (tag != NULL && (found || copy_back))
+    {
+      int line_offset;
+      /* Load the line from memory first, if it was a miss.  */
+      if (! found)
+	fill_line_from_memory (cache, tag, address);
+      line_offset = address & (cache->line_size - 1);
+      memcpy (tag->line + line_offset, data, length);
+      tag->dirty = 1;
+
+      /* Update the LRU information for the tags in this set.  */
+      set_most_recently_used (cache, tag);
+    }
+
+  /* Write the data to memory if there was no line available or we are in
+     write-through (not copy-back mode).  */
+  if (tag == NULL || ! copy_back)
+    {
+      write_data_to_memory (cache, address, data, length);
+      if (tag != NULL)
+	tag->dirty = 0;
+    }
+
+  return 1; /* TODO - number of cycles unknown */
+}
+
+/* Preload the cache line containing the given address. Lock the
+   data if requested.
+   Returns the number of cycles required to write the data.  */
+int
+frv_cache_preload (FRV_CACHE *cache, SI address, USI length, int lock)
+{
+  int offset;
+  int lines;
+
+  if (non_cache_access (cache, address))
+    return 1;
+
+  /* preload at least 1 line.  */
+  if (length == 0)
+    length = 1;
+
+  offset = address & (cache->line_size - 1);
+  lines = 1 + (offset + length - 1) / cache->line_size;
+
+  /* Careful with this loop -- length is unsigned.  */
+  for (/**/; lines > 0; --lines)
+    {
+      FRV_CACHE_TAG *tag = find_or_retrieve_cache_line (cache, address);
+      if (lock && tag != NULL)
+	tag->locked = 1;
+      address += cache->line_size;
+    }
+
+  return 1; /* TODO - number of cycles unknown */
+}
+
+/* Unlock the cache line containing the given address.
+   Returns the number of cycles required to unlock the line.  */
+int
+frv_cache_unlock (FRV_CACHE *cache, SI address)
+{
+  FRV_CACHE_TAG *tag;
+  int found;
+
+  if (non_cache_access (cache, address))
+    return 1;
+
+  found = get_tag (cache, address, &tag);
+
+  if (found)
+    tag->locked = 0;
+
+  return 1; /* TODO - number of cycles unknown */
+}
+
+static void
+invalidate_return_buffer (FRV_CACHE *cache, SI address)
+{
+  /* If this address is in one of the return buffers, then invalidate that
+     return buffer.  */
+  address &= ~(cache->line_size - 1);
+  if (address == cache->pipeline[LS].status.return_buffer.address)
+    cache->pipeline[LS].status.return_buffer.valid = 0;
+  if (address == cache->pipeline[LD].status.return_buffer.address)
+    cache->pipeline[LD].status.return_buffer.valid = 0;
+}
+
+/* Invalidate the cache line containing the given address. Flush the
+   data if requested.
+   Returns the number of cycles required to write the data.  */
+int
+frv_cache_invalidate (FRV_CACHE *cache, SI address, int flush)
+{
+  /* See if this data is already in the cache.  */
+  FRV_CACHE_TAG *tag;
+  int found;
+
+  /* Check for non-cache access.  This operation is still perfromed even if
+     the cache is not currently enabled.  */
+  if (non_cache_access (cache, address))
+    return 1;
+
+  /* If the line is found, invalidate it. If a flush is requested, then flush
+     it if it is dirty.  */
+  found = get_tag (cache, address, &tag);
+  if (found)
+    {
+      SIM_CPU *cpu;
+      /* If a flush is requested, then flush it if it is dirty.  */
+      if (tag->dirty && flush)
+	write_line_to_memory (cache, tag);
+      set_least_recently_used (cache, tag);
+      tag->valid = 0;
+      tag->locked = 0;
+
+      /* If this is the insn cache, then flush the cpu's scache as well.  */
+      cpu = cache->cpu;
+      if (cache == CPU_INSN_CACHE (cpu))
+	scache_flush_cpu (cpu);
+    }
+
+  invalidate_return_buffer (cache, address);
+
+  return 1; /* TODO - number of cycles unknown */
+}
+
+/* Invalidate the entire cache. Flush the data if requested.  */
+int
+frv_cache_invalidate_all (FRV_CACHE *cache, int flush)
+{
+  /* See if this data is already in the cache.  */
+  int elements = cache->sets * cache->ways;
+  FRV_CACHE_TAG *tag = cache->tag_storage;
+  SIM_CPU *cpu;
+  int i;
+
+  for(i = 0; i < elements; ++i, ++tag)
+    {
+      /* If a flush is requested, then flush it if it is dirty.  */
+      if (tag->valid && tag->dirty && flush)
+	write_line_to_memory (cache, tag);
+      tag->valid = 0;
+      tag->locked = 0;
+    }
+
+
+  /* If this is the insn cache, then flush the cpu's scache as well.  */
+  cpu = cache->cpu;
+  if (cache == CPU_INSN_CACHE (cpu))
+    scache_flush_cpu (cpu);
+
+  /* Invalidate both return buffers.  */
+  cache->pipeline[LS].status.return_buffer.valid = 0;
+  cache->pipeline[LD].status.return_buffer.valid = 0;
+
+  return 1; /* TODO - number of cycles unknown */
+}
+
+/* ---------------------------------------------------------------------------
+   Functions for operating the cache in cycle accurate mode.
+   -------------------------------------------------------------------------  */
+/* Convert a VLIW slot to a cache pipeline index.  */
+static int
+convert_slot_to_index (int slot)
+{
+  switch (slot)
+    {
+    case UNIT_I0:
+    case UNIT_C:
+      return LS;
+    case UNIT_I1:
+      return LD;
+    default:
+      abort ();
+    }
+  return 0;
+}
+
+/* Allocate free chains of cache requests.  */
+#define FREE_CHAIN_SIZE 16
+static FRV_CACHE_REQUEST *frv_cache_request_free_chain = NULL;
+static FRV_CACHE_REQUEST *frv_store_request_free_chain = NULL;
+
+static void
+allocate_new_cache_requests (void)
+{
+  int i;
+  frv_cache_request_free_chain = xmalloc (FREE_CHAIN_SIZE
+					  * sizeof (FRV_CACHE_REQUEST));
+  for (i = 0; i < FREE_CHAIN_SIZE - 1; ++i)
+    {
+      frv_cache_request_free_chain[i].next
+	= & frv_cache_request_free_chain[i + 1]; 
+    }
+
+  frv_cache_request_free_chain[FREE_CHAIN_SIZE - 1].next = NULL;
+}
+
+/* Return the next free request in the queue for the given cache pipeline.  */
+static FRV_CACHE_REQUEST *
+new_cache_request (void)
+{
+  FRV_CACHE_REQUEST *req;
+
+  /* Allocate new elements for the free chain if necessary.  */
+  if (frv_cache_request_free_chain == NULL)
+    allocate_new_cache_requests ();
+
+  req = frv_cache_request_free_chain;
+  frv_cache_request_free_chain = req->next;
+
+  return req;
+}
+
+/* Return the given cache request to the free chain.  */
+static void
+free_cache_request (FRV_CACHE_REQUEST *req)
+{
+  if (req->kind == req_store)
+    {
+      req->next = frv_store_request_free_chain;
+      frv_store_request_free_chain = req;
+    }
+  else
+    {
+      req->next = frv_cache_request_free_chain;
+      frv_cache_request_free_chain = req;
+    }
+}
+
+/* Search the free chain for an existing store request with a buffer that's
+   large enough.  */
+static FRV_CACHE_REQUEST *
+new_store_request (int length)
+{
+  FRV_CACHE_REQUEST *prev = NULL;
+  FRV_CACHE_REQUEST *req;
+  for (req = frv_store_request_free_chain; req != NULL; req = req->next)
+    {
+      if (req->u.store.length == length)
+	break;
+      prev = req;
+    }
+  if (req != NULL)
+    {
+      if (prev == NULL)
+	frv_store_request_free_chain = req->next;
+      else
+	prev->next = req->next;
+      return req;
+    }
+
+  /* No existing request buffer was found, so make a new one.  */
+  req = new_cache_request ();
+  req->kind = req_store;
+  req->u.store.data = xmalloc (length);
+  req->u.store.length = length;
+  return req;
+}
+
+/* Remove the given request from the given pipeline.  */
+static void
+pipeline_remove_request (FRV_CACHE_PIPELINE *p, FRV_CACHE_REQUEST *request)
+{
+  FRV_CACHE_REQUEST *next = request->next;
+  FRV_CACHE_REQUEST *prev = request->prev;
+
+  if (prev == NULL)
+    p->requests = next;
+  else
+    prev->next = next;
+
+  if (next != NULL)
+    next->prev = prev;
+}
+
+/* Add the given request to the given pipeline.  */
+static void
+pipeline_add_request (FRV_CACHE_PIPELINE *p, FRV_CACHE_REQUEST *request)
+{
+  FRV_CACHE_REQUEST *prev = NULL;
+  FRV_CACHE_REQUEST *item;
+
+  /* Add the request in priority order.  0 is the highest priority.  */
+  for (item = p->requests; item != NULL; item = item->next)
+    {
+      if (item->priority > request->priority)
+	break;
+      prev = item;
+    }
+
+  request->next = item;
+  request->prev = prev;
+  if (prev == NULL)
+    p->requests = request;
+  else
+    prev->next = request;
+  if (item != NULL)
+    item->prev = request;
+}
+
+/* Requeu the given request from the last of the given pipeline.  */
+static void
+pipeline_requeue_request (FRV_CACHE_PIPELINE *p)
+{
+  FRV_CACHE_STAGE *stage = & p->stages[LAST_STAGE];
+  FRV_CACHE_REQUEST *req = stage->request;
+  stage->request = NULL;
+  pipeline_add_request (p, req);
+}
+
+/* Return the priority lower than the lowest one in this cache pipeline.
+   0 is the highest priority.  */
+static int
+next_priority (FRV_CACHE *cache, FRV_CACHE_PIPELINE *pipeline)
+{
+  int i, j;
+  int pipe;
+  int lowest = 0;
+  FRV_CACHE_REQUEST *req;
+
+  /* Check the priorities of any queued items.  */
+  for (req = pipeline->requests; req != NULL; req = req->next)
+    if (req->priority > lowest)
+      lowest = req->priority;
+
+  /* Check the priorities of items in the pipeline stages.  */
+  for (i = FIRST_STAGE; i < FRV_CACHE_STAGES; ++i)
+    {
+      FRV_CACHE_STAGE *stage = & pipeline->stages[i];
+      if (stage->request != NULL && stage->request->priority > lowest)
+        lowest = stage->request->priority;
+    }
+
+  /* Check the priorities of load requests waiting in WAR.  These are one
+     higher than the request that spawned them.  */
+  for (i = 0; i < NUM_WARS; ++i)
+    {
+      FRV_CACHE_WAR *war = & pipeline->WAR[i];
+      if (war->valid && war->priority > lowest)
+	lowest = war->priority + 1;
+    }
+
+  /* Check the priorities of any BARS or NARS associated with this pipeline.
+     These are one higher than the request that spawned them.  */
+  pipe = pipeline - cache->pipeline;
+  if (cache->BARS.valid && cache->BARS.pipe == pipe 
+      && cache->BARS.priority > lowest)
+    lowest = cache->BARS.priority + 1;
+  if (cache->NARS.valid && cache->NARS.pipe == pipe 
+      && cache->NARS.priority > lowest)
+    lowest = cache->NARS.priority + 1;
+
+  /* Return a priority 2 lower than the lowest found.  This allows a WAR
+     request to be generated with a priority greater than this but less than
+     the next higher priority request.  */
+  return lowest + 2;
+}
+
+static void
+add_WAR_request (FRV_CACHE_PIPELINE* pipeline, FRV_CACHE_WAR *war)
+{
+  /* Add the load request to the indexed pipeline.  */
+  FRV_CACHE_REQUEST *req = new_cache_request ();
+  req->kind = req_WAR;
+  req->reqno = war->reqno;
+  req->priority = war->priority;
+  req->address = war->address;
+  req->u.WAR.preload = war->preload;
+  req->u.WAR.lock = war->lock;
+  pipeline_add_request (pipeline, req);
+}
+
+/* Remove the next request from the given pipeline and return it.  */
+static FRV_CACHE_REQUEST *
+pipeline_next_request (FRV_CACHE_PIPELINE *p)
+{
+  FRV_CACHE_REQUEST *first = p->requests;
+  if (first != NULL)
+    pipeline_remove_request (p, first);
+  return first;
+}
+
+/* Return the request which is at the given stage of the given pipeline.  */
+static FRV_CACHE_REQUEST *
+pipeline_stage_request (FRV_CACHE_PIPELINE *p, int stage)
+{
+  return p->stages[stage].request;
+}
+
+static void
+advance_pipelines (FRV_CACHE *cache)
+{
+  int stage;
+  int pipe;
+  FRV_CACHE_PIPELINE *pipelines = cache->pipeline;
+
+  /* Free the final stage requests.  */
+  for (pipe = 0; pipe < FRV_CACHE_PIPELINES; ++pipe)
+    {
+      FRV_CACHE_REQUEST *req = pipelines[pipe].stages[LAST_STAGE].request;
+      if (req != NULL)
+	free_cache_request (req);
+    }
+
+  /* Shuffle the requests along the pipeline.  */
+  for (stage = LAST_STAGE; stage > FIRST_STAGE; --stage)
+    {
+      for (pipe = 0; pipe < FRV_CACHE_PIPELINES; ++pipe)
+	pipelines[pipe].stages[stage] = pipelines[pipe].stages[stage - 1];
+    }
+
+  /* Add a new request to the pipeline.  */
+  for (pipe = 0; pipe < FRV_CACHE_PIPELINES; ++pipe)
+    pipelines[pipe].stages[FIRST_STAGE].request
+      = pipeline_next_request (& pipelines[pipe]);
+}
+
+/* Handle a request for a load from the given address.  */
+void
+frv_cache_request_load (FRV_CACHE *cache, unsigned reqno, SI address, int slot)
+{
+  FRV_CACHE_REQUEST *req;
+
+  /* slot is a UNIT_*.  Convert it to a cache pipeline index.  */
+  int pipe = convert_slot_to_index (slot);
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+
+  /* Add the load request to the indexed pipeline.  */
+  req = new_cache_request ();
+  req->kind = req_load;
+  req->reqno = reqno;
+  req->priority = next_priority (cache, pipeline);
+  req->address = address;
+
+  pipeline_add_request (pipeline, req);
+}
+
+void
+frv_cache_request_store (FRV_CACHE *cache, SI address,
+			 int slot, char *data, unsigned length)
+{
+  FRV_CACHE_REQUEST *req;
+
+  /* slot is a UNIT_*.  Convert it to a cache pipeline index.  */
+  int pipe = convert_slot_to_index (slot);
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+
+  /* Add the load request to the indexed pipeline.  */
+  req = new_store_request (length);
+  req->kind = req_store;
+  req->reqno = NO_REQNO;
+  req->priority = next_priority (cache, pipeline);
+  req->address = address;
+  req->u.store.length = length;
+  memcpy (req->u.store.data, data, length);
+
+  pipeline_add_request (pipeline, req);
+  invalidate_return_buffer (cache, address);
+}
+
+/* Handle a request to invalidate the cache line containing the given address.
+   Flush the data if requested.  */
+void
+frv_cache_request_invalidate (FRV_CACHE *cache, unsigned reqno, SI address,
+			      int slot, int all, int flush)
+{
+  FRV_CACHE_REQUEST *req;
+
+  /* slot is a UNIT_*.  Convert it to a cache pipeline index.  */
+  int pipe = convert_slot_to_index (slot);
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+
+  /* Add the load request to the indexed pipeline.  */
+  req = new_cache_request ();
+  req->kind = req_invalidate;
+  req->reqno = reqno;
+  req->priority = next_priority (cache, pipeline);
+  req->address = address;
+  req->u.invalidate.all = all;
+  req->u.invalidate.flush = flush;
+
+  pipeline_add_request (pipeline, req);
+}
+
+/* Handle a request to preload the cache line containing the given address.  */
+void
+frv_cache_request_preload (FRV_CACHE *cache, SI address,
+			   int slot, int length, int lock)
+{
+  FRV_CACHE_REQUEST *req;
+
+  /* slot is a UNIT_*.  Convert it to a cache pipeline index.  */
+  int pipe = convert_slot_to_index (slot);
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+
+  /* Add the load request to the indexed pipeline.  */
+  req = new_cache_request ();
+  req->kind = req_preload;
+  req->reqno = NO_REQNO;
+  req->priority = next_priority (cache, pipeline);
+  req->address = address;
+  req->u.preload.length = length;
+  req->u.preload.lock = lock;
+
+  pipeline_add_request (pipeline, req);
+  invalidate_return_buffer (cache, address);
+}
+
+/* Handle a request to unlock the cache line containing the given address.  */
+void
+frv_cache_request_unlock (FRV_CACHE *cache, SI address, int slot)
+{
+  FRV_CACHE_REQUEST *req;
+
+  /* slot is a UNIT_*.  Convert it to a cache pipeline index.  */
+  int pipe = convert_slot_to_index (slot);
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+
+  /* Add the load request to the indexed pipeline.  */
+  req = new_cache_request ();
+  req->kind = req_unlock;
+  req->reqno = NO_REQNO;
+  req->priority = next_priority (cache, pipeline);
+  req->address = address;
+
+  pipeline_add_request (pipeline, req);
+}
+
+/* Check whether this address interferes with a pending request of
+   higher priority.  */
+static int
+address_interference (FRV_CACHE *cache, SI address, FRV_CACHE_REQUEST *req,
+		      int pipe)
+{
+  int i, j;
+  int line_mask = ~(cache->line_size - 1);
+  int other_pipe;
+  int priority = req->priority;
+  FRV_CACHE_REQUEST *other_req;
+  SI other_address;
+  SI all_address;
+
+  address &= line_mask;
+  all_address = -1 & line_mask;
+
+  /* Check for collisions in the queue for this pipeline.  */
+  for (other_req = cache->pipeline[pipe].requests;
+       other_req != NULL;
+       other_req = other_req->next)
+    {
+      other_address = other_req->address & line_mask;
+      if ((address == other_address || address == all_address)
+	  && priority > other_req->priority)
+	return 1;
+    }
+
+  /* Check for a collision in the the other pipeline.  */
+  other_pipe = pipe ^ 1;
+  other_req = cache->pipeline[other_pipe].stages[LAST_STAGE].request;
+  if (other_req != NULL)
+    {
+      other_address = other_req->address & line_mask;
+      if (address == other_address || address == all_address)
+	return 1;
+    }
+
+  /* Check for a collision with load requests waiting in WAR.  */
+  for (i = LS; i < FRV_CACHE_PIPELINES; ++i)
+    {
+      for (j = 0; j < NUM_WARS; ++j)
+	{
+	  FRV_CACHE_WAR *war = & cache->pipeline[i].WAR[j];
+	  if (war->valid
+	      && (address == (war->address & line_mask) 
+		  || address == all_address)
+	      && priority > war->priority)
+	    return 1;
+	}
+      /* If this is not a WAR request, then yield to any WAR requests in
+	 either pipeline.  */
+      if (req->kind != req_WAR)
+	{
+	  for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j)
+	    {
+	      other_req = cache->pipeline[i].stages[j].request;
+	      if (other_req != NULL && other_req->kind == req_WAR)
+		return 1;
+	    }
+	}
+    }
+
+  /* Check for a collision with load requests waiting in ARS.  */
+  if (cache->BARS.valid
+      && (address == (cache->BARS.address & line_mask)
+	  || address == all_address)
+      && priority > cache->BARS.priority)
+    return 1;
+  if (cache->NARS.valid
+      && (address == (cache->NARS.address & line_mask)
+	  || address == all_address)
+      && priority > cache->NARS.priority)
+    return 1;
+
+  return 0;
+}
+
+/* Wait for a free WAR register in BARS or NARS.  */
+static void
+wait_for_WAR (FRV_CACHE* cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  FRV_CACHE_WAR war;
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+
+  if (! cache->BARS.valid)
+    {
+      cache->BARS.pipe = pipe;
+      cache->BARS.reqno = req->reqno;
+      cache->BARS.address = req->address;
+      cache->BARS.priority = req->priority - 1;
+      switch (req->kind)
+	{
+	case req_load:
+	  cache->BARS.preload = 0;
+	  cache->BARS.lock = 0;
+	  break;
+	case req_store:
+	  cache->BARS.preload = 1;
+	  cache->BARS.lock = 0;
+	  break;
+	case req_preload:
+	  cache->BARS.preload = 1;
+	  cache->BARS.lock = req->u.preload.lock;
+	  break;
+	}
+      cache->BARS.valid = 1;
+      return;
+    }
+  if (! cache->NARS.valid)
+    {
+      cache->NARS.pipe = pipe;
+      cache->NARS.reqno = req->reqno;
+      cache->NARS.address = req->address;
+      cache->NARS.priority = req->priority - 1;
+      switch (req->kind)
+	{
+	case req_load:
+	  cache->NARS.preload = 0;
+	  cache->NARS.lock = 0;
+	  break;
+	case req_store:
+	  cache->NARS.preload = 1;
+	  cache->NARS.lock = 0;
+	  break;
+	case req_preload:
+	  cache->NARS.preload = 1;
+	  cache->NARS.lock = req->u.preload.lock;
+	  break;
+	}
+      cache->NARS.valid = 1;
+      return;
+    }
+  /* All wait registers are busy, so resubmit this request.  */
+  pipeline_requeue_request (pipeline);
+}
+
+/* Find a free WAR register and wait for memory to fetch the data.  */
+static void
+wait_in_WAR (FRV_CACHE* cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  int war;
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+
+  /* Find a valid WAR to  hold this request.  */
+  for (war = 0; war < NUM_WARS; ++war)
+    if (! pipeline->WAR[war].valid)
+      break;
+  if (war >= NUM_WARS)
+    {
+      wait_for_WAR (cache, pipe, req);
+      return;
+    }
+
+  pipeline->WAR[war].address = req->address;
+  pipeline->WAR[war].reqno = req->reqno;
+  pipeline->WAR[war].priority = req->priority - 1;
+  pipeline->WAR[war].latency = cache->memory_latency + 1;
+  switch (req->kind)
+    {
+    case req_load:
+      pipeline->WAR[war].preload = 0;
+      pipeline->WAR[war].lock = 0;
+      break;
+    case req_store:
+      pipeline->WAR[war].preload = 1;
+      pipeline->WAR[war].lock = 0;
+      break;
+    case req_preload:
+      pipeline->WAR[war].preload = 1;
+      pipeline->WAR[war].lock = req->u.preload.lock;
+      break;
+    }
+  pipeline->WAR[war].valid = 1;
+}
+
+static void
+handle_req_load (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  FRV_CACHE_TAG *tag;
+  SI address = req->address;
+
+  /* If this address interferes with an existing request, then requeue it.  */
+  if (address_interference (cache, address, req, pipe))
+    {
+      pipeline_requeue_request (& cache->pipeline[pipe]);
+      return;
+    }
+
+  if (frv_cache_enabled (cache) && ! non_cache_access (cache, address))
+    {
+      int found = get_tag (cache, address, &tag);
+
+      /* If the data was found, return it to the caller.  */
+      if (found)
+	{
+	  set_most_recently_used (cache, tag);
+	  copy_line_to_return_buffer (cache, pipe, tag, address);
+	  set_return_buffer_reqno (cache, pipe, req->reqno);
+	  return;
+	}
+    }
+
+  /* The data is not in the cache or this is a non-cache access.  We need to
+     wait for the memory unit to fetch it.  Store this request in the WAR in
+     the meantime.  */
+  wait_in_WAR (cache, pipe, req);
+}
+
+static void
+handle_req_preload (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  int found;
+  FRV_CACHE_WAR war;
+  FRV_CACHE_TAG *tag;
+  int length;
+  int lock;
+  int offset;
+  int lines;
+  int line;
+  SI address = req->address;
+  SI cur_address;
+
+  if (! frv_cache_enabled (cache) || non_cache_access (cache, address))
+    return;
+
+  /* preload at least 1 line.  */
+  length = req->u.preload.length;
+  if (length == 0)
+    length = 1;
+
+  /* Make sure that this request does not interfere with a pending request.  */
+  offset = address & (cache->line_size - 1);
+  lines = 1 + (offset + length - 1) / cache->line_size;
+  cur_address = address & ~(cache->line_size - 1);
+  for (line = 0; line < lines; ++line)
+    {
+      /* If this address interferes with an existing request,
+	 then requeue it.  */
+      if (address_interference (cache, cur_address, req, pipe))
+	{
+	  pipeline_requeue_request (& cache->pipeline[pipe]);
+	  return;
+	}
+      cur_address += cache->line_size;
+    }
+
+  /* Now process each cache line.  */
+  /* Careful with this loop -- length is unsigned.  */
+  lock = req->u.preload.lock;
+  cur_address = address & ~(cache->line_size - 1);
+  for (line = 0; line < lines; ++line)
+    {
+      /* If the data was found, then lock it if requested.  */
+      found = get_tag (cache, cur_address, &tag);
+      if (found)
+	{
+	  if (lock)
+	    tag->locked = 1;
+	}
+      else
+	{
+	  /* The data is not in the cache.  We need to wait for the memory
+	     unit to fetch it.  Store this request in the WAR in the meantime.
+	  */
+	  wait_in_WAR (cache, pipe, req);
+	}
+      cur_address += cache->line_size;
+    }
+}
+
+static void
+handle_req_store (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  SIM_CPU *current_cpu;
+  FRV_CACHE_TAG *tag;
+  int found;
+  int copy_back;
+  SI address = req->address;
+  char *data = req->u.store.data;
+  int length = req->u.store.length;
+
+  /* If this address interferes with an existing request, then requeue it.  */
+  if (address_interference (cache, address, req, pipe))
+    {
+      pipeline_requeue_request (& cache->pipeline[pipe]);
+      return;
+    }
+
+  /* Non-cache access. Write the data directly to memory.  */
+  if (! frv_cache_enabled (cache) || non_cache_access (cache, address))
+    {
+      write_data_to_memory (cache, address, data, length);
+      return;
+    }
+
+  /* See if the data is in the cache.  */
+  found = get_tag (cache, address, &tag);
+
+  /* Write the data to the cache line if one was available and if it is
+     either a hit or a miss in copy-back mode.
+     The tag may be NULL if all ways were in use and locked on a miss.
+  */
+  current_cpu = cache->cpu;
+  copy_back = GET_HSR0_CBM (GET_HSR0 ());
+  if (tag != NULL && (found || copy_back))
+    {
+      int line_offset;
+      /* Load the line from memory first, if it was a miss.  */
+      if (! found)
+	{
+	  /* We need to wait for the memory unit to fetch the data.  
+	     Store this request in the WAR and requeue the store request.  */
+	  wait_in_WAR (cache, pipe, req);
+	  pipeline_requeue_request (& cache->pipeline[pipe]);
+	  /* Decrement the counts of accesses and hits because when the requeued
+	     request is processed again, it will appear to be a new access and
+	     a hit.  */
+	  --cache->statistics.accesses;
+	  --cache->statistics.hits;
+	  return;
+	}
+      line_offset = address & (cache->line_size - 1);
+      memcpy (tag->line + line_offset, data, length);
+      invalidate_return_buffer (cache, address);
+      tag->dirty = 1;
+
+      /* Update the LRU information for the tags in this set.  */
+      set_most_recently_used (cache, tag);
+    }
+
+  /* Write the data to memory if there was no line available or we are in
+     write-through (not copy-back mode).  */
+  if (tag == NULL || ! copy_back)
+    {
+      write_data_to_memory (cache, address, data, length);
+      if (tag != NULL)
+	tag->dirty = 0;
+    }
+}
+
+static void
+handle_req_invalidate (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+  SI address = req->address;
+  SI interfere_address = req->u.invalidate.all ? -1 : address;
+
+  /* If this address interferes with an existing request, then requeue it.  */
+  if (address_interference (cache, interfere_address, req, pipe))
+    {
+      pipeline_requeue_request (pipeline);
+      return;
+    }
+
+  /* Invalidate the cache line now.  This function already checks for
+     non-cache access.  */
+  if (req->u.invalidate.all)
+    frv_cache_invalidate_all (cache, req->u.invalidate.flush);
+  else
+    frv_cache_invalidate (cache, address, req->u.invalidate.flush);
+  if (req->u.invalidate.flush)
+    {
+      pipeline->status.flush.reqno = req->reqno;
+      pipeline->status.flush.address = address;
+      pipeline->status.flush.valid = 1;
+    }
+}
+
+static void
+handle_req_unlock (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+  SI address = req->address;
+
+  /* If this address interferes with an existing request, then requeue it.  */
+  if (address_interference (cache, address, req, pipe))
+    {
+      pipeline_requeue_request (pipeline);
+      return;
+    }
+
+  /* Unlock the cache line.  This function checks for non-cache access.  */
+  frv_cache_unlock (cache, address);
+}
+
+static void
+handle_req_WAR (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req)
+{
+  char *buffer;
+  FRV_CACHE_TAG *tag;
+  SI address = req->address;
+
+  if (frv_cache_enabled (cache) && ! non_cache_access (cache, address))
+    {
+      /* Look for the data in the cache.  The statistics of cache hit or
+	 miss have already been recorded, so save and restore the stats before
+	 and after obtaining the cache line.  */
+      FRV_CACHE_STATISTICS save_stats = cache->statistics;
+      tag = find_or_retrieve_cache_line (cache, address);
+      cache->statistics = save_stats;
+      if (tag != NULL)
+	{
+	  if (! req->u.WAR.preload)
+	    {
+	      copy_line_to_return_buffer (cache, pipe, tag, address);
+	      set_return_buffer_reqno (cache, pipe, req->reqno);
+	    }
+	  else 
+	    {
+	      invalidate_return_buffer (cache, address);
+	      if (req->u.WAR.lock)
+		tag->locked = 1;
+	    }
+	  return;
+	}
+    }
+
+  /* All cache lines in the set were locked, so just copy the data to the
+     return buffer directly.  */
+  if (! req->u.WAR.preload)
+    {
+      copy_memory_to_return_buffer (cache, pipe, address);
+      set_return_buffer_reqno (cache, pipe, req->reqno);
+    }
+}
+
+/* Resolve any conflicts and/or execute the given requests.  */
+static void
+arbitrate_requests (FRV_CACHE *cache)
+{
+  int pipe;
+  /* Simply execute the requests in the final pipeline stages.  */
+  for (pipe = LS; pipe < FRV_CACHE_PIPELINES; ++pipe)
+    {
+      FRV_CACHE_REQUEST *req
+	= pipeline_stage_request (& cache->pipeline[pipe], LAST_STAGE);
+      /* Make sure that there is a request to handle.  */
+      if (req == NULL)
+	continue;
+
+      /* Handle the request.  */
+      switch (req->kind)
+	{
+	case req_load:
+	  handle_req_load (cache, pipe, req);
+	  break;
+	case req_store:
+	  handle_req_store (cache, pipe, req);
+	  break;
+	case req_invalidate:
+	  handle_req_invalidate (cache, pipe, req);
+	  break;
+	case req_preload:
+	  handle_req_preload (cache, pipe, req);
+	  break;
+	case req_unlock:
+	  handle_req_unlock (cache, pipe, req);
+	  break;
+	case req_WAR:
+	  handle_req_WAR (cache, pipe, req);
+	  break;
+	default:
+	  abort ();
+	}
+    }
+}
+
+/* Move a waiting ARS register to a free WAR register.  */
+static void
+move_ARS_to_WAR (FRV_CACHE *cache, int pipe, FRV_CACHE_WAR *war)
+{
+  /* If BARS is valid for this pipe, then move it to the given WAR. Move
+     NARS to BARS if it is valid.  */
+  if (cache->BARS.valid && cache->BARS.pipe == pipe)
+    {
+      war->address = cache->BARS.address;
+      war->reqno = cache->BARS.reqno;
+      war->priority = cache->BARS.priority;
+      war->preload = cache->BARS.preload;
+      war->lock = cache->BARS.lock;
+      war->latency = cache->memory_latency + 1;
+      war->valid = 1;
+      if (cache->NARS.valid)
+	{
+	  cache->BARS = cache->NARS;
+	  cache->NARS.valid = 0;
+	}
+      else
+	cache->BARS.valid = 0;
+      return;
+    }
+  /* If NARS is valid for this pipe, then move it to the given WAR.  */
+  if (cache->NARS.valid && cache->NARS.pipe == pipe)
+    {
+      war->address = cache->NARS.address;
+      war->reqno = cache->NARS.reqno;
+      war->priority = cache->NARS.priority;
+      war->preload = cache->NARS.preload;
+      war->lock = cache->NARS.lock;
+      war->latency = cache->memory_latency + 1;
+      war->valid = 1;
+      cache->NARS.valid = 0;
+    }
+}
+
+/* Decrease the latencies of the various states in the cache.  */
+static void
+decrease_latencies (FRV_CACHE *cache)
+{
+  int pipe, j;
+  /* Check the WAR registers.  */
+  for (pipe = LS; pipe < FRV_CACHE_PIPELINES; ++pipe)
+    {
+      FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
+      for (j = 0; j < NUM_WARS; ++j)
+	{
+	  FRV_CACHE_WAR *war = & pipeline->WAR[j];
+	  if (war->valid)
+	    {
+	      --war->latency;
+	      /* If the latency has expired, then submit a WAR request to the
+		 pipeline.  */
+	      if (war->latency <= 0)
+		{
+		  add_WAR_request (pipeline, war);
+		  war->valid = 0;
+		  move_ARS_to_WAR (cache, pipe, war);
+		}
+	    }
+	}
+    }
+}
+
+/* Run the cache for the given number of cycles.  */
+void
+frv_cache_run (FRV_CACHE *cache, int cycles)
+{
+  int i;
+  for (i = 0; i < cycles; ++i)
+    {
+      advance_pipelines (cache);
+      arbitrate_requests (cache);
+      decrease_latencies (cache);
+    }
+}
+
+int
+frv_cache_read_passive_SI (FRV_CACHE *cache, SI address, SI *value)
+{
+  SI offset;
+  FRV_CACHE_TAG *tag;
+
+  if (non_cache_access (cache, address))
+    return 0;
+
+  {
+    FRV_CACHE_STATISTICS save_stats = cache->statistics;
+    int found = get_tag (cache, address, &tag);
+    cache->statistics = save_stats;
+
+    if (! found)
+      return 0; /* Indicate non-cache-access.  */
+  }
+
+  /* A cache line was available for the data.
+     Extract the target data from the line.  */
+  offset = address & (cache->line_size - 1);
+  offset &= ~3;
+  *value = T2H_4 (*(SI *)(tag->line + offset));
+  return 1;
+}
+
+/* Check the return buffers of the data cache to see if the requested data is
+   available.  */
+int
+frv_cache_data_in_buffer (FRV_CACHE* cache, int pipe, SI address,
+			  unsigned reqno)
+{
+  return cache->pipeline[pipe].status.return_buffer.valid
+    && cache->pipeline[pipe].status.return_buffer.reqno == reqno
+    && cache->pipeline[pipe].status.return_buffer.address <= address
+    && cache->pipeline[pipe].status.return_buffer.address + cache->line_size
+       > address;
+}
+
+/* Check to see if the requested data has been flushed.  */
+int
+frv_cache_data_flushed (FRV_CACHE* cache, int pipe, SI address, unsigned reqno)
+{
+  return cache->pipeline[pipe].status.flush.valid
+    && cache->pipeline[pipe].status.flush.reqno == reqno
+    && cache->pipeline[pipe].status.flush.address <= address
+    && cache->pipeline[pipe].status.flush.address + cache->line_size
+       > address;
+}
diff --git a/sim/frv/cache.h b/sim/frv/cache.h
new file mode 100644
index 00000000000..e45ae948f79
--- /dev/null
+++ b/sim/frv/cache.h
@@ -0,0 +1,262 @@
+/* Cache support for the FRV simulator
+   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef CACHE_H
+#define CACHE_H
+
+/* A representation of a set-associative cache with LRU replacement,
+   cache line locking, non-blocking support and multiple read ports.  */
+
+/* An enumeration of cache pipeline request kinds.  */
+typedef enum
+{
+  req_load,
+  req_store,
+  req_invalidate,
+  req_flush,
+  req_preload,
+  req_unlock,
+  req_WAR
+} FRV_CACHE_REQUEST_KIND;
+
+/* The cache pipeline requests.  */
+typedef struct {
+  int preload;
+  int lock;
+} FRV_CACHE_WAR_REQUEST;
+
+typedef struct {
+  char *data;
+  int length;
+} FRV_CACHE_STORE_REQUEST;
+
+typedef struct {
+  int flush;
+  int all;
+} FRV_CACHE_INVALIDATE_REQUEST;
+
+typedef struct {
+  int lock;
+  int length;
+} FRV_CACHE_PRELOAD_REQUEST;
+
+/* A cache pipeline request.  */
+typedef struct frv_cache_request
+{
+  struct frv_cache_request *next;
+  struct frv_cache_request *prev;
+  FRV_CACHE_REQUEST_KIND kind;
+  unsigned reqno;
+  unsigned priority;
+  SI address;
+  union {
+    FRV_CACHE_STORE_REQUEST store;
+    FRV_CACHE_INVALIDATE_REQUEST invalidate;
+    FRV_CACHE_PRELOAD_REQUEST preload;
+    FRV_CACHE_WAR_REQUEST WAR;
+  } u;
+} FRV_CACHE_REQUEST;
+
+/* The buffer for returning data to the caller.  */
+typedef struct {
+  unsigned reqno;
+  SI address;
+  char *data;
+  int valid;
+} FRV_CACHE_RETURN_BUFFER;
+
+/* The status of flush requests.  */
+typedef struct {
+  unsigned reqno;
+  SI address;
+  int valid;
+} FRV_CACHE_FLUSH_STATUS;
+
+/* Communicate status of requests to the caller.  */
+typedef struct {
+  FRV_CACHE_FLUSH_STATUS  flush;
+  FRV_CACHE_RETURN_BUFFER return_buffer;
+} FRV_CACHE_STATUS;
+
+/* A cache pipeline stage.  */
+typedef struct {
+  FRV_CACHE_REQUEST *request;
+} FRV_CACHE_STAGE;
+
+enum {
+  FIRST_STAGE,
+  A_STAGE = FIRST_STAGE, /* Addressing stage */
+  I_STAGE,               /* Interference stage */
+  LAST_STAGE = I_STAGE,
+  FRV_CACHE_STAGES
+};
+
+/* Representation of the WAR register.  */
+typedef struct {
+  unsigned reqno;
+  unsigned priority;
+  SI address;
+  int preload;
+  int lock;
+  int latency;
+  int valid;
+} FRV_CACHE_WAR;
+
+/* A cache pipeline.  */
+#define NUM_WARS 2
+typedef struct {
+  FRV_CACHE_REQUEST      *requests;
+  FRV_CACHE_STAGE         stages[FRV_CACHE_STAGES];
+  FRV_CACHE_WAR           WAR[NUM_WARS];
+  FRV_CACHE_STATUS        status;
+} FRV_CACHE_PIPELINE;
+
+enum {LS, LD, FRV_CACHE_PIPELINES};
+
+/* Representation of the xARS registers.  */
+typedef struct {
+  int pipe;
+  unsigned reqno;
+  unsigned priority;
+  SI address;
+  int preload;
+  int lock;
+  int valid;
+} FRV_CACHE_ARS;
+
+/* A cache tag.  */
+typedef struct {
+  USI   tag;    /* Address tag.  */
+  int   lru;    /* Lower values indicates less recently used.  */
+  char *line;   /* Points to storage for line in data_storage.  */
+  char  dirty;  /* line has been written to since last stored?  */
+  char  locked; /* line is locked?  */
+  char  valid;  /* tag is valid?  */
+} FRV_CACHE_TAG;
+
+/* Cache statistics.  */
+typedef struct {
+  unsigned long accesses;   /* number of cache accesses.  */
+  unsigned long hits;       /* number of cache hits.  */
+} FRV_CACHE_STATISTICS;
+
+/* The cache itself.
+   Notes:
+   - line_size must be a power of 2
+   - sets must be a power of 2
+   - ways must be a power of 2
+*/
+typedef struct {
+  SIM_CPU *cpu;
+  unsigned ways;              /* Number of ways in each set.  */
+  unsigned sets;              /* Number of sets in the cache.  */
+  unsigned line_size;         /* Size of each cache line.  */
+  unsigned memory_latency;    /* Latency of main memory in cycles.  */
+  FRV_CACHE_TAG *tag_storage; /* Storage for tags.  */
+  char *data_storage;         /* Storage for data (cache lines).  */
+  FRV_CACHE_PIPELINE pipeline[2];  /* Cache pipelines.  */
+  FRV_CACHE_ARS BARS;         /* BARS register.  */
+  FRV_CACHE_ARS NARS;         /* BARS register.  */
+  FRV_CACHE_STATISTICS statistics; /* Operation statistics.  */
+} FRV_CACHE;
+
+/* The tags are stored by ways within sets in order to make computations
+   easier.  */
+#define CACHE_TAG(cache, set, way) ( \
+  & ((cache)->tag_storage[(set) * (cache)->ways + (way)]) \
+)
+
+/* Compute the address tag corresponding to the given address.  */
+#define CACHE_ADDRESS_TAG(cache, address) ( \
+  (address) & ~(((cache)->line_size * (cache)->sets) - 1) \
+)
+
+/* Determine the index at which the set containing this tag starts.  */
+#define CACHE_TAG_SET_START(cache, tag) ( \
+  ((tag) - (cache)->tag_storage) & ~((cache)->ways - 1) \
+)
+
+/* Determine the number of the set which this cache tag is in.  */
+#define CACHE_TAG_SET_NUMBER(cache, tag) ( \
+  CACHE_TAG_SET_START ((cache), (tag)) / (cache)->ways \
+)
+
+#define CACHE_RETURN_DATA(cache, slot, address, mode, N) (               \
+  T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
+		     [((address) & ((cache)->line_size - 1)              \
+		       & ~(sizeof (mode) - 1))]))                        \
+)
+
+#define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) (              \
+  ((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address)  \
+			                       & ((cache)->line_size - 1) \
+				               & ~((N) - 1)])             \
+)
+
+#define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL)
+
+/* These functions are used to initialize and terminate a cache.  */
+void
+frv_cache_init (SIM_CPU *, FRV_CACHE *);
+void
+frv_cache_term (FRV_CACHE *);
+int
+frv_cache_enabled (FRV_CACHE *);
+
+/* These functions are used to operate the cache in non-cycle-accurate mode.
+   Each request is handled individually and immediately using the current
+   cache internal state.  */
+int
+frv_cache_read (FRV_CACHE *, int, SI);
+int
+frv_cache_write (FRV_CACHE *, SI, char *, unsigned);
+int
+frv_cache_preload (FRV_CACHE *, SI, USI, int);
+int
+frv_cache_invalidate (FRV_CACHE *, SI, int);
+int
+frv_cache_invalidate_all (FRV_CACHE *, int);
+
+/* These functions are used to operate the cache in cycle-accurate mode.
+   The internal operation of the cache is simulated down to the cycle level.  */
+#define NO_REQNO 0xffffffff
+void
+frv_cache_request_load (FRV_CACHE *, unsigned, SI, int);
+void
+frv_cache_request_store (FRV_CACHE *, SI, int, char *, unsigned);
+void
+frv_cache_request_invalidate (FRV_CACHE *, unsigned, SI, int, int, int);
+void
+frv_cache_request_preload (FRV_CACHE *, SI, int, int, int);
+void
+frv_cache_request_unlock (FRV_CACHE *, SI, int);
+
+void
+frv_cache_run (FRV_CACHE *, int);
+
+int
+frv_cache_data_in_buffer (FRV_CACHE*, int, SI, unsigned);
+int
+frv_cache_data_flushed (FRV_CACHE*, int, SI, unsigned);
+
+int
+frv_cache_read_passive_SI (FRV_CACHE *, SI, SI *);
+
+#endif /* CACHE_H */
diff --git a/sim/frv/config.in b/sim/frv/config.in
new file mode 100644
index 00000000000..9723b8662c9
--- /dev/null
+++ b/sim/frv/config.in
@@ -0,0 +1,162 @@
+/* config.in.  Generated automatically from configure.in by autoheader.  */
+
+/* Define if using alloca.c.  */
+#undef C_ALLOCA
+
+/* Define to empty if the keyword does not work.  */
+#undef const
+
+/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
+   This function is required for alloca.c support on those systems.  */
+#undef CRAY_STACKSEG_END
+
+/* Define if you have alloca, as a function or macro.  */
+#undef HAVE_ALLOCA
+
+/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
+#undef HAVE_ALLOCA_H
+
+/* Define if you have a working `mmap' system call.  */
+#undef HAVE_MMAP
+
+/* Define as __inline if that's what the C compiler calls it.  */
+#undef inline
+
+/* Define to `long' if <sys/types.h> doesn't define.  */
+#undef off_t
+
+/* Define if you need to in order for stat and other things to work.  */
+#undef _POSIX_SOURCE
+
+/* Define as the return type of signal handlers (int or void).  */
+#undef RETSIGTYPE
+
+/* Define to `unsigned' if <sys/types.h> doesn't define.  */
+#undef size_t
+
+/* If using the C implementation of alloca, define if you know the
+   direction of stack growth for your system; otherwise it will be
+   automatically deduced at run-time.
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown
+ */
+#undef STACK_DIRECTION
+
+/* Define if you have the ANSI C header files.  */
+#undef STDC_HEADERS
+
+/* Define if your processor stores words with the most significant
+   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
+#undef WORDS_BIGENDIAN
+
+/* Define to 1 if NLS is requested.  */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES.  */
+#undef HAVE_LC_MESSAGES
+
+/* Define if you have the __argz_count function.  */
+#undef HAVE___ARGZ_COUNT
+
+/* Define if you have the __argz_next function.  */
+#undef HAVE___ARGZ_NEXT
+
+/* Define if you have the __argz_stringify function.  */
+#undef HAVE___ARGZ_STRINGIFY
+
+/* Define if you have the __setfpucw function.  */
+#undef HAVE___SETFPUCW
+
+/* Define if you have the dcgettext function.  */
+#undef HAVE_DCGETTEXT
+
+/* Define if you have the getcwd function.  */
+#undef HAVE_GETCWD
+
+/* Define if you have the getpagesize function.  */
+#undef HAVE_GETPAGESIZE
+
+/* Define if you have the getrusage function.  */
+#undef HAVE_GETRUSAGE
+
+/* Define if you have the munmap function.  */
+#undef HAVE_MUNMAP
+
+/* Define if you have the putenv function.  */
+#undef HAVE_PUTENV
+
+/* Define if you have the setenv function.  */
+#undef HAVE_SETENV
+
+/* Define if you have the setlocale function.  */
+#undef HAVE_SETLOCALE
+
+/* Define if you have the sigaction function.  */
+#undef HAVE_SIGACTION
+
+/* Define if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if you have the strcasecmp function.  */
+#undef HAVE_STRCASECMP
+
+/* Define if you have the strchr function.  */
+#undef HAVE_STRCHR
+
+/* Define if you have the time function.  */
+#undef HAVE_TIME
+
+/* Define if you have the <argz.h> header file.  */
+#undef HAVE_ARGZ_H
+
+/* Define if you have the <fcntl.h> header file.  */
+#undef HAVE_FCNTL_H
+
+/* Define if you have the <fpu_control.h> header file.  */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define if you have the <limits.h> header file.  */
+#undef HAVE_LIMITS_H
+
+/* Define if you have the <locale.h> header file.  */
+#undef HAVE_LOCALE_H
+
+/* Define if you have the <malloc.h> header file.  */
+#undef HAVE_MALLOC_H
+
+/* Define if you have the <nl_types.h> header file.  */
+#undef HAVE_NL_TYPES_H
+
+/* Define if you have the <stdlib.h> header file.  */
+#undef HAVE_STDLIB_H
+
+/* Define if you have the <string.h> header file.  */
+#undef HAVE_STRING_H
+
+/* Define if you have the <strings.h> header file.  */
+#undef HAVE_STRINGS_H
+
+/* Define if you have the <sys/param.h> header file.  */
+#undef HAVE_SYS_PARAM_H
+
+/* Define if you have the <sys/resource.h> header file.  */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define if you have the <sys/time.h> header file.  */
+#undef HAVE_SYS_TIME_H
+
+/* Define if you have the <time.h> header file.  */
+#undef HAVE_TIME_H
+
+/* Define if you have the <unistd.h> header file.  */
+#undef HAVE_UNISTD_H
+
+/* Define if you have the <values.h> header file.  */
+#undef HAVE_VALUES_H
diff --git a/sim/frv/configure b/sim/frv/configure
new file mode 100755
index 00000000000..38b2b7dfb6d
--- /dev/null
+++ b/sim/frv/configure
@@ -0,0 +1,4315 @@
+#! /bin/sh
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+sim_inline="-DDEFAULT_INLINE=0"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# This file is derived from `gettext.m4'.  The difference is that the
+# included macros assume Cygnus-style source and build trees.
+
+# Macro to add for using GNU gettext.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 3
+
+
+
+
+
+# Search path for a program which passes the given test.
+# Ulrich Drepper <drepper@cygnus.com>, 1996.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+# Check whether LC_MESSAGES is available in <locale.h>.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions.  It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+
+
+
+# Guess values for system-dependent variables and create Makefiles.
+# Generated automatically using autoconf version 2.13 
+# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+
+# Defaults:
+ac_help=
+ac_default_prefix=/usr/local
+# Any additions from configure.in:
+ac_help="$ac_help
+  --disable-nls           do not use Native Language Support"
+ac_help="$ac_help
+  --with-included-gettext use the GNU gettext library included here"
+ac_help="$ac_help
+  --enable-maintainer-mode		Enable developer functionality."
+ac_help="$ac_help
+  --enable-sim-bswap			Use Host specific BSWAP instruction."
+ac_help="$ac_help
+  --enable-sim-cflags=opts		Extra CFLAGS for use in building simulator"
+ac_help="$ac_help
+  --enable-sim-debug=opts		Enable debugging flags"
+ac_help="$ac_help
+  --enable-sim-stdio			Specify whether to use stdio for console input/output."
+ac_help="$ac_help
+  --enable-sim-trace=opts		Enable tracing flags"
+ac_help="$ac_help
+  --enable-sim-profile=opts		Enable profiling flags"
+ac_help="$ac_help
+  --enable-sim-endian=endian		Specify target byte endian orientation."
+ac_help="$ac_help
+  --enable-sim-alignment=align		Specify strict,  nonstrict or forced alignment of memory accesses."
+ac_help="$ac_help
+  --enable-sim-hostendian=end		Specify host byte endian orientation."
+ac_help="$ac_help
+  --enable-sim-scache=size		Specify simulator execution cache size."
+ac_help="$ac_help
+  --enable-sim-default-model=model	Specify default model to simulate."
+ac_help="$ac_help
+  --enable-sim-environment=environment	Specify mixed, user, virtual or operating environment."
+ac_help="$ac_help
+  --enable-cgen-maint[=DIR]    build cgen generated files"
+ac_help="$ac_help
+  --enable-sim-trapdump		Make unknown traps dump the registers"
+
+# Initialize some variables set by options.
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+build=NONE
+cache_file=./config.cache
+exec_prefix=NONE
+host=NONE
+no_create=
+nonopt=NONE
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+sitefile=
+srcdir=
+target=NONE
+verbose=
+x_includes=NONE
+x_libraries=NONE
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
+mandir='${prefix}/man'
+
+# Initialize some other variables.
+subdirs=
+MFLAGS= MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+# Maximum number of lines to put in a shell here document.
+ac_max_here_lines=12
+
+ac_prev=
+for ac_option
+do
+
+  # If the previous option needs an argument, assign it.
+  if test -n "$ac_prev"; then
+    eval "$ac_prev=\$ac_option"
+    ac_prev=
+    continue
+  fi
+
+  case "$ac_option" in
+  -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
+  *) ac_optarg= ;;
+  esac
+
+  # Accept the important Cygnus configure options, so we can diagnose typos.
+
+  case "$ac_option" in
+
+  -bindir | --bindir | --bindi | --bind | --bin | --bi)
+    ac_prev=bindir ;;
+  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+    bindir="$ac_optarg" ;;
+
+  -build | --build | --buil | --bui | --bu)
+    ac_prev=build ;;
+  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+    build="$ac_optarg" ;;
+
+  -cache-file | --cache-file | --cache-fil | --cache-fi \
+  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+    ac_prev=cache_file ;;
+  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+    cache_file="$ac_optarg" ;;
+
+  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+    ac_prev=datadir ;;
+  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
+  | --da=*)
+    datadir="$ac_optarg" ;;
+
+  -disable-* | --disable-*)
+    ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
+      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+    fi
+    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+    eval "enable_${ac_feature}=no" ;;
+
+  -enable-* | --enable-*)
+    ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
+      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+    fi
+    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+    case "$ac_option" in
+      *=*) ;;
+      *) ac_optarg=yes ;;
+    esac
+    eval "enable_${ac_feature}='$ac_optarg'" ;;
+
+  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+  | --exec | --exe | --ex)
+    ac_prev=exec_prefix ;;
+  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+  | --exec=* | --exe=* | --ex=*)
+    exec_prefix="$ac_optarg" ;;
+
+  -gas | --gas | --ga | --g)
+    # Obsolete; use --with-gas.
+    with_gas=yes ;;
+
+  -help | --help | --hel | --he)
+    # Omit some internal or obsolete options to make the list less imposing.
+    # This message is too long to be a string in the A/UX 3.1 sh.
+    cat << EOF
+Usage: configure [options] [host]
+Options: [defaults in brackets after descriptions]
+Configuration:
+  --cache-file=FILE       cache test results in FILE
+  --help                  print this message
+  --no-create             do not create output files
+  --quiet, --silent       do not print \`checking...' messages
+  --site-file=FILE        use FILE as the site file
+  --version               print the version of autoconf that created configure
+Directory and file names:
+  --prefix=PREFIX         install architecture-independent files in PREFIX
+                          [$ac_default_prefix]
+  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
+                          [same as prefix]
+  --bindir=DIR            user executables in DIR [EPREFIX/bin]
+  --sbindir=DIR           system admin executables in DIR [EPREFIX/sbin]
+  --libexecdir=DIR        program executables in DIR [EPREFIX/libexec]
+  --datadir=DIR           read-only architecture-independent data in DIR
+                          [PREFIX/share]
+  --sysconfdir=DIR        read-only single-machine data in DIR [PREFIX/etc]
+  --sharedstatedir=DIR    modifiable architecture-independent data in DIR
+                          [PREFIX/com]
+  --localstatedir=DIR     modifiable single-machine data in DIR [PREFIX/var]
+  --libdir=DIR            object code libraries in DIR [EPREFIX/lib]
+  --includedir=DIR        C header files in DIR [PREFIX/include]
+  --oldincludedir=DIR     C header files for non-gcc in DIR [/usr/include]
+  --infodir=DIR           info documentation in DIR [PREFIX/info]
+  --mandir=DIR            man documentation in DIR [PREFIX/man]
+  --srcdir=DIR            find the sources in DIR [configure dir or ..]
+  --program-prefix=PREFIX prepend PREFIX to installed program names
+  --program-suffix=SUFFIX append SUFFIX to installed program names
+  --program-transform-name=PROGRAM
+                          run sed PROGRAM on installed program names
+EOF
+    cat << EOF
+Host type:
+  --build=BUILD           configure for building on BUILD [BUILD=HOST]
+  --host=HOST             configure for HOST [guessed]
+  --target=TARGET         configure for TARGET [TARGET=HOST]
+Features and packages:
+  --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
+  --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
+  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
+  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
+  --x-includes=DIR        X include files are in DIR
+  --x-libraries=DIR       X library files are in DIR
+EOF
+    if test -n "$ac_help"; then
+      echo "--enable and --with options recognized:$ac_help"
+    fi
+    exit 0 ;;
+
+  -host | --host | --hos | --ho)
+    ac_prev=host ;;
+  -host=* | --host=* | --hos=* | --ho=*)
+    host="$ac_optarg" ;;
+
+  -includedir | --includedir | --includedi | --included | --include \
+  | --includ | --inclu | --incl | --inc)
+    ac_prev=includedir ;;
+  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+  | --includ=* | --inclu=* | --incl=* | --inc=*)
+    includedir="$ac_optarg" ;;
+
+  -infodir | --infodir | --infodi | --infod | --info | --inf)
+    ac_prev=infodir ;;
+  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+    infodir="$ac_optarg" ;;
+
+  -libdir | --libdir | --libdi | --libd)
+    ac_prev=libdir ;;
+  -libdir=* | --libdir=* | --libdi=* | --libd=*)
+    libdir="$ac_optarg" ;;
+
+  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+  | --libexe | --libex | --libe)
+    ac_prev=libexecdir ;;
+  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+  | --libexe=* | --libex=* | --libe=*)
+    libexecdir="$ac_optarg" ;;
+
+  -localstatedir | --localstatedir | --localstatedi | --localstated \
+  | --localstate | --localstat | --localsta | --localst \
+  | --locals | --local | --loca | --loc | --lo)
+    ac_prev=localstatedir ;;
+  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+  | --localstate=* | --localstat=* | --localsta=* | --localst=* \
+  | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+    localstatedir="$ac_optarg" ;;
+
+  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+    ac_prev=mandir ;;
+  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+    mandir="$ac_optarg" ;;
+
+  -nfp | --nfp | --nf)
+    # Obsolete; use --without-fp.
+    with_fp=no ;;
+
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c)
+    no_create=yes ;;
+
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+    no_recursion=yes ;;
+
+  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+  | --oldin | --oldi | --old | --ol | --o)
+    ac_prev=oldincludedir ;;
+  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+    oldincludedir="$ac_optarg" ;;
+
+  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+    ac_prev=prefix ;;
+  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+    prefix="$ac_optarg" ;;
+
+  -program-prefix | --program-prefix | --program-prefi | --program-pref \
+  | --program-pre | --program-pr | --program-p)
+    ac_prev=program_prefix ;;
+  -program-prefix=* | --program-prefix=* | --program-prefi=* \
+  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+    program_prefix="$ac_optarg" ;;
+
+  -program-suffix | --program-suffix | --program-suffi | --program-suff \
+  | --program-suf | --program-su | --program-s)
+    ac_prev=program_suffix ;;
+  -program-suffix=* | --program-suffix=* | --program-suffi=* \
+  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+    program_suffix="$ac_optarg" ;;
+
+  -program-transform-name | --program-transform-name \
+  | --program-transform-nam | --program-transform-na \
+  | --program-transform-n | --program-transform- \
+  | --program-transform | --program-transfor \
+  | --program-transfo | --program-transf \
+  | --program-trans | --program-tran \
+  | --progr-tra | --program-tr | --program-t)
+    ac_prev=program_transform_name ;;
+  -program-transform-name=* | --program-transform-name=* \
+  | --program-transform-nam=* | --program-transform-na=* \
+  | --program-transform-n=* | --program-transform-=* \
+  | --program-transform=* | --program-transfor=* \
+  | --program-transfo=* | --program-transf=* \
+  | --program-trans=* | --program-tran=* \
+  | --progr-tra=* | --program-tr=* | --program-t=*)
+    program_transform_name="$ac_optarg" ;;
+
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil)
+    silent=yes ;;
+
+  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+    ac_prev=sbindir ;;
+  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+  | --sbi=* | --sb=*)
+    sbindir="$ac_optarg" ;;
+
+  -sharedstatedir | --sharedstatedir | --sharedstatedi \
+  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+  | --sharedst | --shareds | --shared | --share | --shar \
+  | --sha | --sh)
+    ac_prev=sharedstatedir ;;
+  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+  | --sha=* | --sh=*)
+    sharedstatedir="$ac_optarg" ;;
+
+  -site | --site | --sit)
+    ac_prev=site ;;
+  -site=* | --site=* | --sit=*)
+    site="$ac_optarg" ;;
+
+  -site-file | --site-file | --site-fil | --site-fi | --site-f)
+    ac_prev=sitefile ;;
+  -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*)
+    sitefile="$ac_optarg" ;;
+
+  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+    ac_prev=srcdir ;;
+  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+    srcdir="$ac_optarg" ;;
+
+  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+  | --syscon | --sysco | --sysc | --sys | --sy)
+    ac_prev=sysconfdir ;;
+  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+    sysconfdir="$ac_optarg" ;;
+
+  -target | --target | --targe | --targ | --tar | --ta | --t)
+    ac_prev=target ;;
+  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+    target="$ac_optarg" ;;
+
+  -v | -verbose | --verbose | --verbos | --verbo | --verb)
+    verbose=yes ;;
+
+  -version | --version | --versio | --versi | --vers)
+    echo "configure generated by autoconf version 2.13"
+    exit 0 ;;
+
+  -with-* | --with-*)
+    ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then
+      { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+    fi
+    ac_package=`echo $ac_package| sed 's/-/_/g'`
+    case "$ac_option" in
+      *=*) ;;
+      *) ac_optarg=yes ;;
+    esac
+    eval "with_${ac_package}='$ac_optarg'" ;;
+
+  -without-* | --without-*)
+    ac_package=`echo $ac_option|sed -e 's/-*without-//'`
+    # Reject names that are not valid shell variable names.
+    if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then
+      { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+    fi
+    ac_package=`echo $ac_package| sed 's/-/_/g'`
+    eval "with_${ac_package}=no" ;;
+
+  --x)
+    # Obsolete; use --with-x.
+    with_x=yes ;;
+
+  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+  | --x-incl | --x-inc | --x-in | --x-i)
+    ac_prev=x_includes ;;
+  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+    x_includes="$ac_optarg" ;;
+
+  -x-libraries | --x-libraries | --x-librarie | --x-librari \
+  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+    ac_prev=x_libraries ;;
+  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+    x_libraries="$ac_optarg" ;;
+
+  -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; }
+    ;;
+
+  *)
+    if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then
+      echo "configure: warning: $ac_option: invalid host type" 1>&2
+    fi
+    if test "x$nonopt" != xNONE; then
+      { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; }
+    fi
+    nonopt="$ac_option"
+    ;;
+
+  esac
+done
+
+if test -n "$ac_prev"; then
+  { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; }
+fi
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+# File descriptor usage:
+# 0 standard input
+# 1 file creation
+# 2 errors and warnings
+# 3 some systems may open it to /dev/tty
+# 4 used on the Kubota Titan
+# 6 checking for... messages and results
+# 5 compiler messages saved in config.log
+if test "$silent" = yes; then
+  exec 6>/dev/null
+else
+  exec 6>&1
+fi
+exec 5>./config.log
+
+echo "\
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+" 1>&5
+
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Also quote any args containing shell metacharacters.
+ac_configure_args=
+for ac_arg
+do
+  case "$ac_arg" in
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c) ;;
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;;
+  *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*)
+  ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+  *) ac_configure_args="$ac_configure_args $ac_arg" ;;
+  esac
+done
+
+# NLS nuisances.
+# Only set these to C if already set.  These must not be set unconditionally
+# because not all systems understand e.g. LANG=C (notably SCO).
+# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!
+# Non-C LC_CTYPE values break the ctype check.
+if test "${LANG+set}"   = set; then LANG=C;   export LANG;   fi
+if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi
+if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi
+if test "${LC_CTYPE+set}"    = set; then LC_CTYPE=C;    export LC_CTYPE;    fi
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -rf conftest* confdefs.h
+# AIX cpp loses on an empty file, so make sure it contains at least a newline.
+echo > confdefs.h
+
+# A filename unique to this package, relative to the directory that
+# configure is in, which we can look for to find out if srcdir is correct.
+ac_unique_file=Makefile.in
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+  ac_srcdir_defaulted=yes
+  # Try the directory containing this script, then its parent.
+  ac_prog=$0
+  ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
+  test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
+  srcdir=$ac_confdir
+  if test ! -r $srcdir/$ac_unique_file; then
+    srcdir=..
+  fi
+else
+  ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+  if test "$ac_srcdir_defaulted" = yes; then
+    { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
+  else
+    { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
+  fi
+fi
+srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
+
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$sitefile"; then
+  if test -z "$CONFIG_SITE"; then
+    if test "x$prefix" != xNONE; then
+      CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+    else
+      CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+    fi
+  fi
+else
+  CONFIG_SITE="$sitefile"
+fi
+for ac_site_file in $CONFIG_SITE; do
+  if test -r "$ac_site_file"; then
+    echo "loading site script $ac_site_file"
+    . "$ac_site_file"
+  fi
+done
+
+if test -r "$cache_file"; then
+  echo "loading cache $cache_file"
+  . $cache_file
+else
+  echo "creating cache $cache_file"
+  > $cache_file
+fi
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+ac_exeext=
+ac_objext=o
+if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
+  # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
+  if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
+    ac_n= ac_c='
+' ac_t='	'
+  else
+    ac_n=-n ac_c= ac_t=
+  fi
+else
+  ac_n= ac_c='\c' ac_t=
+fi
+
+
+
+echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
+echo "configure:695: checking how to run the C preprocessor" >&5
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+  CPP=
+fi
+if test -z "$CPP"; then
+if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+    # This must be in double quotes, not single quotes, because CPP may get
+  # substituted into the Makefile and "${CC-cc}" will confuse make.
+  CPP="${CC-cc} -E"
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp.
+  cat > conftest.$ac_ext <<EOF
+#line 710 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:716: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP="${CC-cc} -E -traditional-cpp"
+  cat > conftest.$ac_ext <<EOF
+#line 727 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:733: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP="${CC-cc} -nologo -E"
+  cat > conftest.$ac_ext <<EOF
+#line 744 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:750: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  :
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CPP=/lib/cpp
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+  ac_cv_prog_CPP="$CPP"
+fi
+  CPP="$ac_cv_prog_CPP"
+else
+  ac_cv_prog_CPP="$CPP"
+fi
+echo "$ac_t""$CPP" 1>&6
+
+echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6
+echo "configure:775: checking whether ${MAKE-make} sets \${MAKE}" >&5
+set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftestmake <<\EOF
+all:
+	@echo 'ac_maketemp="${MAKE}"'
+EOF
+# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
+eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=`
+if test -n "$ac_maketemp"; then
+  eval ac_cv_prog_make_${ac_make}_set=yes
+else
+  eval ac_cv_prog_make_${ac_make}_set=no
+fi
+rm -f conftestmake
+fi
+if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  SET_MAKE=
+else
+  echo "$ac_t""no" 1>&6
+  SET_MAKE="MAKE=${MAKE-make}"
+fi
+
+echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6
+echo "configure:802: checking for POSIXized ISC" >&5
+if test -d /etc/conf/kconfig.d &&
+  grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1
+then
+  echo "$ac_t""yes" 1>&6
+  ISC=yes # If later tests want to check for ISC.
+  cat >> confdefs.h <<\EOF
+#define _POSIX_SOURCE 1
+EOF
+
+  if test "$GCC" = yes; then
+    CC="$CC -posix"
+  else
+    CC="$CC -Xp"
+  fi
+else
+  echo "$ac_t""no" 1>&6
+  ISC=
+fi
+
+echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
+echo "configure:823: checking for ANSI C header files" >&5
+if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 828 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:836: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  ac_cv_header_stdc=yes
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+if test $ac_cv_header_stdc = yes; then
+  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 853 "configure"
+#include "confdefs.h"
+#include <string.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "memchr" >/dev/null 2>&1; then
+  :
+else
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 871 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "free" >/dev/null 2>&1; then
+  :
+else
+  rm -rf conftest*
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+if test "$cross_compiling" = yes; then
+  :
+else
+  cat > conftest.$ac_ext <<EOF
+#line 892 "configure"
+#include "confdefs.h"
+#include <ctype.h>
+#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int main () { int i; for (i = 0; i < 256; i++)
+if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
+exit (0); }
+
+EOF
+if { (eval echo configure:903: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  :
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_header_stdc=no
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_header_stdc" 1>&6
+if test $ac_cv_header_stdc = yes; then
+  cat >> confdefs.h <<\EOF
+#define STDC_HEADERS 1
+EOF
+
+fi
+
+echo $ac_n "checking for working const""... $ac_c" 1>&6
+echo "configure:927: checking for working const" >&5
+if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 932 "configure"
+#include "confdefs.h"
+
+int main() {
+
+/* Ultrix mips cc rejects this.  */
+typedef int charset[2]; const charset x;
+/* SunOS 4.1.1 cc rejects this.  */
+char const *const *ccp;
+char **p;
+/* NEC SVR4.0.2 mips cc rejects this.  */
+struct point {int x, y;};
+static struct point const zero = {0,0};
+/* AIX XL C 1.02.0.0 rejects this.
+   It does not let you subtract one const X* pointer from another in an arm
+   of an if-expression whose if-part is not a constant expression */
+const char *g = "string";
+ccp = &g + (g ? g-g : 0);
+/* HPUX 7.0 cc rejects these. */
+++ccp;
+p = (char**) ccp;
+ccp = (char const *const *) p;
+{ /* SCO 3.2v4 cc rejects this.  */
+  char *t;
+  char const *s = 0 ? (char *) 0 : (char const *) 0;
+
+  *t++ = 0;
+}
+{ /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
+  int x[] = {25, 17};
+  const int *foo = &x[0];
+  ++foo;
+}
+{ /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
+  typedef const int *iptr;
+  iptr p = 0;
+  ++p;
+}
+{ /* AIX XL C 1.02.0.0 rejects this saying
+     "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
+  struct s { int j; const int *ap[3]; };
+  struct s *b; b->j = 5;
+}
+{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
+  const int foo = 10;
+}
+
+; return 0; }
+EOF
+if { (eval echo configure:981: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_const=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_c_const=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_c_const" 1>&6
+if test $ac_cv_c_const = no; then
+  cat >> confdefs.h <<\EOF
+#define const 
+EOF
+
+fi
+
+echo $ac_n "checking for inline""... $ac_c" 1>&6
+echo "configure:1002: checking for inline" >&5
+if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_cv_c_inline=no
+for ac_kw in inline __inline__ __inline; do
+  cat > conftest.$ac_ext <<EOF
+#line 1009 "configure"
+#include "confdefs.h"
+
+int main() {
+} $ac_kw foo() {
+; return 0; }
+EOF
+if { (eval echo configure:1016: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_inline=$ac_kw; break
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+done
+
+fi
+
+echo "$ac_t""$ac_cv_c_inline" 1>&6
+case "$ac_cv_c_inline" in
+  inline | yes) ;;
+  no) cat >> confdefs.h <<\EOF
+#define inline 
+EOF
+ ;;
+  *)  cat >> confdefs.h <<EOF
+#define inline $ac_cv_c_inline
+EOF
+ ;;
+esac
+
+echo $ac_n "checking for off_t""... $ac_c" 1>&6
+echo "configure:1042: checking for off_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1047 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_type_off_t=yes
+else
+  rm -rf conftest*
+  ac_cv_type_off_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_off_t" 1>&6
+if test $ac_cv_type_off_t = no; then
+  cat >> confdefs.h <<\EOF
+#define off_t long
+EOF
+
+fi
+
+echo $ac_n "checking for size_t""... $ac_c" 1>&6
+echo "configure:1075: checking for size_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1080 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_type_size_t=yes
+else
+  rm -rf conftest*
+  ac_cv_type_size_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_size_t" 1>&6
+if test $ac_cv_type_size_t = no; then
+  cat >> confdefs.h <<\EOF
+#define size_t unsigned
+EOF
+
+fi
+
+# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
+# for constant arguments.  Useless!
+echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
+echo "configure:1110: checking for working alloca.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1115 "configure"
+#include "confdefs.h"
+#include <alloca.h>
+int main() {
+char *p = alloca(2 * sizeof(int));
+; return 0; }
+EOF
+if { (eval echo configure:1122: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  ac_cv_header_alloca_h=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_header_alloca_h=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_header_alloca_h" 1>&6
+if test $ac_cv_header_alloca_h = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA_H 1
+EOF
+
+fi
+
+echo $ac_n "checking for alloca""... $ac_c" 1>&6
+echo "configure:1143: checking for alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1148 "configure"
+#include "confdefs.h"
+
+#ifdef __GNUC__
+# define alloca __builtin_alloca
+#else
+# ifdef _MSC_VER
+#  include <malloc.h>
+#  define alloca _alloca
+# else
+#  if HAVE_ALLOCA_H
+#   include <alloca.h>
+#  else
+#   ifdef _AIX
+ #pragma alloca
+#   else
+#    ifndef alloca /* predefined by HP cc +Olibcalls */
+char *alloca ();
+#    endif
+#   endif
+#  endif
+# endif
+#endif
+
+int main() {
+char *p = (char *) alloca(1);
+; return 0; }
+EOF
+if { (eval echo configure:1176: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  ac_cv_func_alloca_works=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_func_alloca_works=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_func_alloca_works" 1>&6
+if test $ac_cv_func_alloca_works = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA 1
+EOF
+
+fi
+
+if test $ac_cv_func_alloca_works = no; then
+  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
+  # that cause trouble.  Some versions do not even contain alloca or
+  # contain a buggy version.  If you still want to use their alloca,
+  # use ar to extract alloca.o from them instead of compiling alloca.c.
+  ALLOCA=alloca.${ac_objext}
+  cat >> confdefs.h <<\EOF
+#define C_ALLOCA 1
+EOF
+
+
+echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
+echo "configure:1208: checking whether alloca needs Cray hooks" >&5
+if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1213 "configure"
+#include "confdefs.h"
+#if defined(CRAY) && ! defined(CRAY2)
+webecray
+#else
+wenotbecray
+#endif
+
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  egrep "webecray" >/dev/null 2>&1; then
+  rm -rf conftest*
+  ac_cv_os_cray=yes
+else
+  rm -rf conftest*
+  ac_cv_os_cray=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_os_cray" 1>&6
+if test $ac_cv_os_cray = yes; then
+for ac_func in _getb67 GETB67 getb67; do
+  echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1238: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1243 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1266: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  cat >> confdefs.h <<EOF
+#define CRAY_STACKSEG_END $ac_func
+EOF
+
+  break
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+done
+fi
+
+echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
+echo "configure:1293: checking stack direction for C alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$cross_compiling" = yes; then
+  ac_cv_c_stack_direction=0
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1301 "configure"
+#include "confdefs.h"
+find_stack_direction ()
+{
+  static char *addr = 0;
+  auto char dummy;
+  if (addr == 0)
+    {
+      addr = &dummy;
+      return find_stack_direction ();
+    }
+  else
+    return (&dummy > addr) ? 1 : -1;
+}
+main ()
+{
+  exit (find_stack_direction() < 0);
+}
+EOF
+if { (eval echo configure:1320: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_c_stack_direction=1
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_c_stack_direction=-1
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_c_stack_direction" 1>&6
+cat >> confdefs.h <<EOF
+#define STACK_DIRECTION $ac_cv_c_stack_direction
+EOF
+
+fi
+
+for ac_hdr in unistd.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:1345: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1350 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1355: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getpagesize
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1384: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1389 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1412: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+echo $ac_n "checking for working mmap""... $ac_c" 1>&6
+echo "configure:1437: checking for working mmap" >&5
+if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$cross_compiling" = yes; then
+  ac_cv_func_mmap_fixed_mapped=no
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1445 "configure"
+#include "confdefs.h"
+
+/* Thanks to Mike Haertel and Jim Avera for this test.
+   Here is a matrix of mmap possibilities:
+	mmap private not fixed
+	mmap private fixed at somewhere currently unmapped
+	mmap private fixed at somewhere already mapped
+	mmap shared not fixed
+	mmap shared fixed at somewhere currently unmapped
+	mmap shared fixed at somewhere already mapped
+   For private mappings, we should verify that changes cannot be read()
+   back from the file, nor mmap's back from the file at a different
+   address.  (There have been systems where private was not correctly
+   implemented like the infamous i386 svr4.0, and systems where the
+   VM page cache was not coherent with the filesystem buffer cache
+   like early versions of FreeBSD and possibly contemporary NetBSD.)
+   For shared mappings, we should conversely verify that changes get
+   propogated back to all the places they're supposed to be.
+
+   Grep wants private fixed already mapped.
+   The main things grep needs to know about mmap are:
+   * does it exist and is it safe to write into the mmap'd area
+   * how to use it (BSD variants)  */
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+/* This mess was copied from the GNU getpagesize.h.  */
+#ifndef HAVE_GETPAGESIZE
+# ifdef HAVE_UNISTD_H
+#  include <unistd.h>
+# endif
+
+/* Assume that all systems that can run configure have sys/param.h.  */
+# ifndef HAVE_SYS_PARAM_H
+#  define HAVE_SYS_PARAM_H 1
+# endif
+
+# ifdef _SC_PAGESIZE
+#  define getpagesize() sysconf(_SC_PAGESIZE)
+# else /* no _SC_PAGESIZE */
+#  ifdef HAVE_SYS_PARAM_H
+#   include <sys/param.h>
+#   ifdef EXEC_PAGESIZE
+#    define getpagesize() EXEC_PAGESIZE
+#   else /* no EXEC_PAGESIZE */
+#    ifdef NBPG
+#     define getpagesize() NBPG * CLSIZE
+#     ifndef CLSIZE
+#      define CLSIZE 1
+#     endif /* no CLSIZE */
+#    else /* no NBPG */
+#     ifdef NBPC
+#      define getpagesize() NBPC
+#     else /* no NBPC */
+#      ifdef PAGESIZE
+#       define getpagesize() PAGESIZE
+#      endif /* PAGESIZE */
+#     endif /* no NBPC */
+#    endif /* no NBPG */
+#   endif /* no EXEC_PAGESIZE */
+#  else /* no HAVE_SYS_PARAM_H */
+#   define getpagesize() 8192	/* punt totally */
+#  endif /* no HAVE_SYS_PARAM_H */
+# endif /* no _SC_PAGESIZE */
+
+#endif /* no HAVE_GETPAGESIZE */
+
+#ifdef __cplusplus
+extern "C" { void *malloc(unsigned); }
+#else
+char *malloc();
+#endif
+
+int
+main()
+{
+	char *data, *data2, *data3;
+	int i, pagesize;
+	int fd;
+
+	pagesize = getpagesize();
+
+	/*
+	 * First, make a file with some known garbage in it.
+	 */
+	data = malloc(pagesize);
+	if (!data)
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		*(data + i) = rand();
+	umask(0);
+	fd = creat("conftestmmap", 0600);
+	if (fd < 0)
+		exit(1);
+	if (write(fd, data, pagesize) != pagesize)
+		exit(1);
+	close(fd);
+
+	/*
+	 * Next, try to mmap the file at a fixed address which
+	 * already has something else allocated at it.  If we can,
+	 * also make sure that we see the same garbage.
+	 */
+	fd = open("conftestmmap", O_RDWR);
+	if (fd < 0)
+		exit(1);
+	data2 = malloc(2 * pagesize);
+	if (!data2)
+		exit(1);
+	data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1);
+	if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE,
+	    MAP_PRIVATE | MAP_FIXED, fd, 0L))
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		if (*(data + i) != *(data2 + i))
+			exit(1);
+
+	/*
+	 * Finally, make sure that changes to the mapped area
+	 * do not percolate back to the file as seen by read().
+	 * (This is a bug on some variants of i386 svr4.0.)
+	 */
+	for (i = 0; i < pagesize; ++i)
+		*(data2 + i) = *(data2 + i) + 1;
+	data3 = malloc(pagesize);
+	if (!data3)
+		exit(1);
+	if (read(fd, data3, pagesize) != pagesize)
+		exit(1);
+	for (i = 0; i < pagesize; ++i)
+		if (*(data + i) != *(data3 + i))
+			exit(1);
+	close(fd);
+	unlink("conftestmmap");
+	exit(0);
+}
+
+EOF
+if { (eval echo configure:1585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_func_mmap_fixed_mapped=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_func_mmap_fixed_mapped=no
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6
+if test $ac_cv_func_mmap_fixed_mapped = yes; then
+  cat >> confdefs.h <<\EOF
+#define HAVE_MMAP 1
+EOF
+
+fi
+
+echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
+echo "configure:1608: checking for Cygwin environment" >&5
+if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1613 "configure"
+#include "confdefs.h"
+
+int main() {
+
+#ifndef __CYGWIN__
+#define __CYGWIN__ __CYGWIN32__
+#endif
+return __CYGWIN__;
+; return 0; }
+EOF
+if { (eval echo configure:1624: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_cygwin=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_cygwin=no
+fi
+rm -f conftest*
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_cygwin" 1>&6
+CYGWIN=
+test "$ac_cv_cygwin" = yes && CYGWIN=yes
+echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
+echo "configure:1641: checking for mingw32 environment" >&5
+if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 1646 "configure"
+#include "confdefs.h"
+
+int main() {
+return __MINGW32__;
+; return 0; }
+EOF
+if { (eval echo configure:1653: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_mingw32=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_mingw32=no
+fi
+rm -f conftest*
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_mingw32" 1>&6
+MINGW32=
+test "$ac_cv_mingw32" = yes && MINGW32=yes
+
+# autoconf.info says this should be called right after AC_INIT.
+
+
+ac_aux_dir=
+for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do
+  if test -f $ac_dir/install-sh; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install-sh -c"
+    break
+  elif test -f $ac_dir/install.sh; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install.sh -c"
+    break
+  fi
+done
+if test -z "$ac_aux_dir"; then
+  { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; }
+fi
+ac_config_guess=$ac_aux_dir/config.guess
+ac_config_sub=$ac_aux_dir/config.sub
+ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
+
+
+# Do some error checking and defaulting for the host and target type.
+# The inputs are:
+#    configure --host=HOST --target=TARGET --build=BUILD NONOPT
+#
+# The rules are:
+# 1. You are not allowed to specify --host, --target, and nonopt at the
+#    same time.
+# 2. Host defaults to nonopt.
+# 3. If nonopt is not specified, then host defaults to the current host,
+#    as determined by config.guess.
+# 4. Target and build default to nonopt.
+# 5. If nonopt is not specified, then target and build default to host.
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+case $host---$target---$nonopt in
+NONE---*---* | *---NONE---* | *---*---NONE) ;;
+*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;;
+esac
+
+
+# Make sure we can run config.sub.
+if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then :
+else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking host system type""... $ac_c" 1>&6
+echo "configure:1720: checking host system type" >&5
+
+host_alias=$host
+case "$host_alias" in
+NONE)
+  case $nonopt in
+  NONE)
+    if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then :
+    else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
+    fi ;;
+  *) host_alias=$nonopt ;;
+  esac ;;
+esac
+
+host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias`
+host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$host" 1>&6
+
+echo $ac_n "checking target system type""... $ac_c" 1>&6
+echo "configure:1741: checking target system type" >&5
+
+target_alias=$target
+case "$target_alias" in
+NONE)
+  case $nonopt in
+  NONE) target_alias=$host_alias ;;
+  *) target_alias=$nonopt ;;
+  esac ;;
+esac
+
+target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias`
+target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$target" 1>&6
+
+echo $ac_n "checking build system type""... $ac_c" 1>&6
+echo "configure:1759: checking build system type" >&5
+
+build_alias=$build
+case "$build_alias" in
+NONE)
+  case $nonopt in
+  NONE) build_alias=$host_alias ;;
+  *) build_alias=$nonopt ;;
+  esac ;;
+esac
+
+build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias`
+build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$build" 1>&6
+
+test "$host_alias" != "$target_alias" &&
+  test "$program_prefix$program_suffix$program_transform_name" = \
+    NONENONEs,x,x, &&
+  program_prefix=${target_alias}-
+
+if test "$program_transform_name" = s,x,x,; then
+  program_transform_name=
+else
+  # Double any \ or $.  echo might interpret backslashes.
+  cat <<\EOF_SED > conftestsed
+s,\\,\\\\,g; s,\$,$$,g
+EOF_SED
+  program_transform_name="`echo $program_transform_name|sed -f conftestsed`"
+  rm -f conftestsed
+fi
+test "$program_prefix" != NONE &&
+  program_transform_name="s,^,${program_prefix},; $program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+  program_transform_name="s,\$\$,${program_suffix},; $program_transform_name"
+
+# sed with no file args requires a program.
+test "$program_transform_name" = "" && program_transform_name="s,x,x,"
+
+# Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1803: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_CC="gcc"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+if test -z "$CC"; then
+  # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1833: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_prog_rejected=no
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
+        ac_prog_rejected=yes
+	continue
+      fi
+      ac_cv_prog_CC="cc"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+if test $ac_prog_rejected = yes; then
+  # We found a bogon in the path, so make sure we never use it.
+  set dummy $ac_cv_prog_CC
+  shift
+  if test $# -gt 0; then
+    # We chose a different compiler from the bogus one.
+    # However, it has the same basename, so the bogon will be chosen
+    # first if we set CC to just the basename; use the full file name.
+    shift
+    set dummy "$ac_dir/$ac_word" "$@"
+    shift
+    ac_cv_prog_CC="$@"
+  fi
+fi
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+  if test -z "$CC"; then
+    case "`uname -s`" in
+    *win32* | *WIN32*)
+      # Extract the first word of "cl", so it can be a program name with args.
+set dummy cl; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1884: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_CC="cl"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+  echo "$ac_t""$CC" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+ ;;
+    esac
+  fi
+  test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
+echo "configure:1916: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+cat > conftest.$ac_ext << EOF
+
+#line 1927 "configure"
+#include "confdefs.h"
+
+main(){return(0);}
+EOF
+if { (eval echo configure:1932: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  ac_cv_prog_cc_works=yes
+  # If we can't run a trivial program, we are probably using a cross compiler.
+  if (./conftest; exit) 2>/dev/null; then
+    ac_cv_prog_cc_cross=no
+  else
+    ac_cv_prog_cc_cross=yes
+  fi
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  ac_cv_prog_cc_works=no
+fi
+rm -fr conftest*
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
+if test $ac_cv_prog_cc_works = no; then
+  { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
+fi
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
+echo "configure:1958: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
+echo "configure:1963: checking whether we are using GNU C" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.c <<EOF
+#ifdef __GNUC__
+  yes;
+#endif
+EOF
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1972: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+  ac_cv_prog_gcc=yes
+else
+  ac_cv_prog_gcc=no
+fi
+fi
+
+echo "$ac_t""$ac_cv_prog_gcc" 1>&6
+
+if test $ac_cv_prog_gcc = yes; then
+  GCC=yes
+else
+  GCC=
+fi
+
+ac_test_CFLAGS="${CFLAGS+set}"
+ac_save_CFLAGS="$CFLAGS"
+CFLAGS=
+echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
+echo "configure:1991: checking whether ${CC-cc} accepts -g" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  echo 'void f(){}' > conftest.c
+if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
+  ac_cv_prog_cc_g=yes
+else
+  ac_cv_prog_cc_g=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
+if test "$ac_test_CFLAGS" = set; then
+  CFLAGS="$ac_save_CFLAGS"
+elif test $ac_cv_prog_cc_g = yes; then
+  if test "$GCC" = yes; then
+    CFLAGS="-g -O2"
+  else
+    CFLAGS="-g"
+  fi
+else
+  if test "$GCC" = yes; then
+    CFLAGS="-O2"
+  else
+    CFLAGS=
+  fi
+fi
+
+# Find a good install program.  We prefer a C program (faster),
+# so one script is as good as another.  But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# ./install, which can be erroneously created by make from ./install.sh.
+echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
+echo "configure:2034: checking for a BSD compatible install" >&5
+if test -z "$INSTALL"; then
+if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+    IFS="${IFS= 	}"; ac_save_IFS="$IFS"; IFS=":"
+  for ac_dir in $PATH; do
+    # Account for people who put trailing slashes in PATH elements.
+    case "$ac_dir/" in
+    /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
+    *)
+      # OSF1 and SCO ODT 3.0 have their own names for install.
+      # Don't use installbsd from OSF since it installs stuff as root
+      # by default.
+      for ac_prog in ginstall scoinst install; do
+        if test -f $ac_dir/$ac_prog; then
+	  if test $ac_prog = install &&
+            grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
+	    # AIX install.  It has an incompatible calling convention.
+	    :
+	  else
+	    ac_cv_path_install="$ac_dir/$ac_prog -c"
+	    break 2
+	  fi
+	fi
+      done
+      ;;
+    esac
+  done
+  IFS="$ac_save_IFS"
+
+fi
+  if test "${ac_cv_path_install+set}" = set; then
+    INSTALL="$ac_cv_path_install"
+  else
+    # As a last resort, use the slow shell script.  We don't cache a
+    # path for INSTALL within a source directory, because that will
+    # break other packages using the cache if that directory is
+    # removed, or if the path is relative.
+    INSTALL="$ac_install_sh"
+  fi
+fi
+echo "$ac_t""$INSTALL" 1>&6
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+  CC_FOR_BUILD='$(CC)'
+else
+  CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+# Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2102: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_RANLIB="ranlib"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
+fi
+fi
+RANLIB="$ac_cv_prog_RANLIB"
+if test -n "$RANLIB"; then
+  echo "$ac_t""$RANLIB" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+ALL_LINGUAS=
+                              
+   for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \
+unistd.h values.h sys/param.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2137: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2142 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2147: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+   for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
+__argz_count __argz_stringify __argz_next
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2177: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2182 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2205: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+
+   if test "${ac_cv_func_stpcpy+set}" != "set"; then
+     for ac_func in stpcpy
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2234: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2239 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2262: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+   fi
+   if test "${ac_cv_func_stpcpy}" = "yes"; then
+     cat >> confdefs.h <<\EOF
+#define HAVE_STPCPY 1
+EOF
+
+   fi
+
+   if test $ac_cv_header_locale_h = yes; then
+    echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
+echo "configure:2296: checking for LC_MESSAGES" >&5
+if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2301 "configure"
+#include "confdefs.h"
+#include <locale.h>
+int main() {
+return LC_MESSAGES
+; return 0; }
+EOF
+if { (eval echo configure:2308: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  am_cv_val_LC_MESSAGES=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  am_cv_val_LC_MESSAGES=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6
+    if test $am_cv_val_LC_MESSAGES = yes; then
+      cat >> confdefs.h <<\EOF
+#define HAVE_LC_MESSAGES 1
+EOF
+
+    fi
+  fi
+   echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
+echo "configure:2329: checking whether NLS is requested" >&5
+        # Check whether --enable-nls or --disable-nls was given.
+if test "${enable_nls+set}" = set; then
+  enableval="$enable_nls"
+  USE_NLS=$enableval
+else
+  USE_NLS=yes
+fi
+
+    echo "$ac_t""$USE_NLS" 1>&6
+    
+
+    USE_INCLUDED_LIBINTL=no
+
+        if test "$USE_NLS" = "yes"; then
+      cat >> confdefs.h <<\EOF
+#define ENABLE_NLS 1
+EOF
+
+      echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
+echo "configure:2349: checking whether included gettext is requested" >&5
+      # Check whether --with-included-gettext or --without-included-gettext was given.
+if test "${with_included_gettext+set}" = set; then
+  withval="$with_included_gettext"
+  nls_cv_force_use_gnu_gettext=$withval
+else
+  nls_cv_force_use_gnu_gettext=no
+fi
+
+      echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6
+
+      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
+      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
+                        		nls_cv_header_intl=
+	nls_cv_header_libgt=
+	CATOBJEXT=NONE
+
+	ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
+echo "configure:2368: checking for libintl.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2373 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2378: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
+echo "configure:2395: checking for gettext in libc" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2400 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2407: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  gt_cv_func_gettext_libc=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  gt_cv_func_gettext_libc=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
+
+	   if test "$gt_cv_func_gettext_libc" != "yes"; then
+	     echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
+echo "configure:2423: checking for bindtextdomain in -lintl" >&5
+ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lintl  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 2431 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char bindtextdomain();
+
+int main() {
+bindtextdomain()
+; return 0; }
+EOF
+if { (eval echo configure:2442: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
+echo "configure:2458: checking for gettext in libintl" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2463 "configure"
+#include "confdefs.h"
+
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2470: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  gt_cv_func_gettext_libintl=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  gt_cv_func_gettext_libintl=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+	   fi
+
+	   if test "$gt_cv_func_gettext_libc" = "yes" \
+	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
+	      cat >> confdefs.h <<\EOF
+#define HAVE_GETTEXT 1
+EOF
+
+	      # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2498: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MSGFMT" in
+  /*)
+  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
+  ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+  echo "$ac_t""$MSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+	      if test "$MSGFMT" != "no"; then
+		for ac_func in dcgettext
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2532: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2537 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2560: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+		# Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2587: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$GMSGFMT" in
+  /*)
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+  ;;
+  ?:/*)			 
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do 
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+  ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+  echo "$ac_t""$GMSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+		# Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2623: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$XGETTEXT" in
+  /*)
+  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+  ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+  echo "$ac_t""$XGETTEXT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+		cat > conftest.$ac_ext <<EOF
+#line 2655 "configure"
+#include "confdefs.h"
+
+int main() {
+extern int _nl_msg_cat_cntr;
+			       return _nl_msg_cat_cntr
+; return 0; }
+EOF
+if { (eval echo configure:2663: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  CATOBJEXT=.gmo
+		   DATADIRNAME=share
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  CATOBJEXT=.mo
+		   DATADIRNAME=lib
+fi
+rm -f conftest*
+		INSTOBJEXT=.mo
+	      fi
+	    fi
+	
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+	        
+        if test "$CATOBJEXT" = "NONE"; then
+	  	  	  nls_cv_use_gnu_gettext=yes
+        fi
+      fi
+
+      if test "$nls_cv_use_gnu_gettext" = "yes"; then
+                INTLOBJS="\$(GETTOBJS)"
+        # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2695: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MSGFMT" in
+  /*)
+  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
+  ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+  echo "$ac_t""$MSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        # Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2729: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$GMSGFMT" in
+  /*)
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+  ;;
+  ?:/*)			 
+  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do 
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+  ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+  echo "$ac_t""$GMSGFMT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        # Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2765: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$XGETTEXT" in
+  /*)
+  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+  ;;
+  *)
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+  for ac_dir in $PATH; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+	break
+      fi
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+  ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+  echo "$ac_t""$XGETTEXT" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+        
+	USE_INCLUDED_LIBINTL=yes
+        CATOBJEXT=.gmo
+        INSTOBJEXT=.mo
+        DATADIRNAME=share
+	INTLDEPS='$(top_builddir)/../intl/libintl.a'
+	INTLLIBS=$INTLDEPS
+	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
+        nls_cv_header_intl=libintl.h
+        nls_cv_header_libgt=libgettext.h
+      fi
+
+            if test "$XGETTEXT" != ":"; then
+			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
+	  : ;
+	else
+	  echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6
+	  XGETTEXT=":"
+	fi
+      fi
+
+      # We need to process the po/ directory.
+      POSUB=po
+    else
+      DATADIRNAME=share
+      nls_cv_header_intl=libintl.h
+      nls_cv_header_libgt=libgettext.h
+    fi
+
+    # If this is used in GNU gettext we have to set USE_NLS to `yes'
+    # because some of the sources are only built for this goal.
+    if test "$PACKAGE" = gettext; then
+      USE_NLS=yes
+      USE_INCLUDED_LIBINTL=yes
+    fi
+
+                for lang in $ALL_LINGUAS; do
+      GMOFILES="$GMOFILES $lang.gmo"
+      POFILES="$POFILES $lang.po"
+    done
+
+        
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+
+   if test "x$CATOBJEXT" != "x"; then
+     if test "x$ALL_LINGUAS" = "x"; then
+       LINGUAS=
+     else
+       echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
+echo "configure:2855: checking for catalogs to be installed" >&5
+       NEW_LINGUAS=
+       for lang in ${LINGUAS=$ALL_LINGUAS}; do
+         case "$ALL_LINGUAS" in
+          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
+         esac
+       done
+       LINGUAS=$NEW_LINGUAS
+       echo "$ac_t""$LINGUAS" 1>&6
+     fi
+
+          if test -n "$LINGUAS"; then
+       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
+     fi
+   fi
+
+            if test $ac_cv_header_locale_h = yes; then
+     INCLUDE_LOCALE_H="#include <locale.h>"
+   else
+     INCLUDE_LOCALE_H="\
+/* The system does not provide the header <locale.h>.  Take care yourself.  */"
+   fi
+   
+
+            if test -f $srcdir/po2tbl.sed.in; then
+      if test "$CATOBJEXT" = ".cat"; then
+	 ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
+echo "configure:2883: checking for linux/version.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2888 "configure"
+#include "confdefs.h"
+#include <linux/version.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2893: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+  msgformat=linux
+else
+  echo "$ac_t""no" 1>&6
+msgformat=xopen
+fi
+
+
+	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
+      fi
+            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
+	 $srcdir/po2tbl.sed.in > po2tbl.sed
+   fi
+
+            if test "$PACKAGE" = "gettext"; then
+     GT_NO="#NO#"
+     GT_YES=
+   else
+     GT_NO=
+     GT_YES="#YES#"
+   fi
+   
+   
+
+   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
+   
+
+      l=
+   
+
+            if test -d $srcdir/po; then
+      test -d po || mkdir po
+      if test "x$srcdir" != "x."; then
+	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
+	    posrcprefix="$srcdir/"
+	 else
+	    posrcprefix="../$srcdir/"
+	 fi
+      else
+	 posrcprefix="../"
+      fi
+      rm -f po/POTFILES
+      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
+	 < $srcdir/po/POTFILES.in > po/POTFILES
+   fi
+  
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+for ac_hdr in stdlib.h string.h strings.h unistd.h time.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2962: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 2967 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2972: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in sys/time.h sys/resource.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3002: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3007 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3012: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in fcntl.h fpu_control.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3042: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3047 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3052: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in dlfcn.h errno.h sys/stat.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3082: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3087 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3092: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=yes"
+else
+  echo "$ac_err" >&5
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getrusage time sigaction __setfpucw
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:3121: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3126 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char $ac_func(); below.  */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:3149: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+ 
+else
+  echo "$ac_t""no" 1>&6
+fi
+done
+
+
+# Check for socket libraries
+echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6
+echo "configure:3176: checking for bind in -lsocket" >&5
+ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lsocket  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3184 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char bind();
+
+int main() {
+bind()
+; return 0; }
+EOF
+if { (eval echo configure:3195: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+  LIBS="-lsocket $LIBS"
+
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6
+echo "configure:3223: checking for gethostbyname in -lnsl" >&5
+ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_save_LIBS="$LIBS"
+LIBS="-lnsl  $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3231 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error.  */
+/* We use char because int might match the return type of a gcc2
+    builtin and then its argument prototype would still apply.  */
+char gethostbyname();
+
+int main() {
+gethostbyname()
+; return 0; }
+EOF
+if { (eval echo configure:3242: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=yes"
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+  echo "$ac_t""yes" 1>&6
+    ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+  cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+  LIBS="-lnsl $LIBS"
+
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then
+  enableval="$enable_maintainer_mode"
+  case "${enableval}" in
+  yes)	MAINT="" USE_MAINTAINER_MODE=yes ;;
+  no)	MAINT="#" ;;
+  *)	{ echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+  echo "Setting maintainer mode" 6>&1
+fi
+else
+  MAINT="#"
+fi
+
+
+
+# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then
+  enableval="$enable_sim_bswap"
+  case "${enableval}" in
+  yes)	sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+  no)	sim_bswap="-DWITH_BSWAP=0";;
+  *)	{ echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+  echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+  sim_bswap=""
+fi
+
+
+
+# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then
+  enableval="$enable_sim_cflags"
+  case "${enableval}" in
+  yes)	 sim_cflags="-O2 -fomit-frame-pointer";;
+  trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";;
+  no)	 sim_cflags="";;
+  *)	 sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+  echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+  sim_cflags=""
+fi
+
+
+
+# Check whether --enable-sim-debug or --disable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then
+  enableval="$enable_sim_debug"
+  case "${enableval}" in
+  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+  echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+  sim_debug=""
+fi
+
+
+
+# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then
+  enableval="$enable_sim_stdio"
+  case "${enableval}" in
+  yes)	sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+  no)	sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+  *)	{ echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+  echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+  sim_stdio=""
+fi
+
+
+
+# Check whether --enable-sim-trace or --disable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then
+  enableval="$enable_sim_trace"
+  case "${enableval}" in
+  yes)	sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+  no)	sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+  [-0-9]*)
+	sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+  [a-z]*)
+	sim_trace=""
+	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+	  if test x"$sim_trace" = x; then
+	    sim_trace="-DWITH_TRACE='(TRACE_$x"
+	  else
+	    sim_trace="${sim_trace}|TRACE_$x"
+	  fi
+	done
+	sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+  echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+  sim_trace=""
+fi
+
+
+
+# Check whether --enable-sim-profile or --disable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then
+  enableval="$enable_sim_profile"
+  case "${enableval}" in
+  yes)	sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+  no)	sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+  [-0-9]*)
+	sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+  [a-z]*)
+	sim_profile=""
+	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+	  if test x"$sim_profile" = x; then
+	    sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+	  else
+	    sim_profile="${sim_profile}|PROFILE_$x"
+	  fi
+	done
+	sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+  echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+  sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
+fi
+
+
+
+echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6
+echo "configure:3418: checking return type of signal handlers" >&5
+if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3423 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <signal.h>
+#ifdef signal
+#undef signal
+#endif
+#ifdef __cplusplus
+extern "C" void (*signal (int, void (*)(int)))(int);
+#else
+void (*signal ()) ();
+#endif
+
+int main() {
+int i;
+; return 0; }
+EOF
+if { (eval echo configure:3440: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_type_signal=void
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_type_signal=int
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_type_signal" 1>&6
+cat >> confdefs.h <<EOF
+#define RETSIGTYPE $ac_cv_type_signal
+EOF
+
+
+
+
+
+echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
+echo "configure:3462: checking for executable suffix" >&5
+if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$CYGWIN" = yes || test "$MINGW32" = yes; then
+  ac_cv_exeext=.exe
+else
+  rm -f conftest*
+  echo 'int main () { return 0; }' > conftest.$ac_ext
+  ac_cv_exeext=
+  if { (eval echo configure:3472: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+    for file in conftest.*; do
+      case $file in
+      *.c | *.o | *.obj | *.ilk | *.pdb) ;;
+      *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
+      esac
+    done
+  else
+    { echo "configure: error: installation or configuration problem: compiler cannot create executables." 1>&2; exit 1; }
+  fi
+  rm -f conftest*
+  test x"${ac_cv_exeext}" = x && ac_cv_exeext=no
+fi
+fi
+
+EXEEXT=""
+test x"${ac_cv_exeext}" != xno && EXEEXT=${ac_cv_exeext}
+echo "$ac_t""${ac_cv_exeext}" 1>&6
+ac_exeext=$EXEEXT
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+  sim_link_files=tconfig.in
+else
+  sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+
+
+wire_endian="BIG_ENDIAN"
+default_endian=""
+# Check whether --enable-sim-endian or --disable-sim-endian was given.
+if test "${enable_sim_endian+set}" = set; then
+  enableval="$enable_sim_endian"
+  case "${enableval}" in
+  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
+  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
+  yes)	 if test x"$wire_endian" != x; then
+	   sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+	 else
+           if test x"$default_endian" != x; then
+	     sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
+	   else
+	     echo "No hard-wired endian for target $target" 1>&6
+	     sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
+	   fi
+	 fi;;
+  no)	 if test x"$default_endian" != x; then
+	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+	 else
+	   if test x"$wire_endian" != x; then
+	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
+	   else
+	     echo "No default endian for target $target" 1>&6
+	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
+	   fi
+	 fi;;
+  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
+  echo "Setting endian flags = $sim_endian" 6>&1
+fi
+else
+  if test x"$default_endian" != x; then
+  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+else
+  if test x"$wire_endian" != x; then
+    sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+  else
+    sim_endian=
+  fi
+fi
+fi
+
+wire_alignment="STRICT_ALIGNMENT"
+default_alignment=""
+
+# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
+if test "${enable_sim_alignment+set}" = set; then
+  enableval="$enable_sim_alignment"
+  case "${enableval}" in
+  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
+  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
+  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
+  yes) if test x"$wire_alignment" != x; then
+	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+       else
+         if test x"$default_alignment" != x; then
+           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
+         else
+	   echo "No hard-wired alignment for target $target" 1>&6
+	   sim_alignment="-DWITH_ALIGNMENT=0"
+         fi
+       fi;;
+  no)  if test x"$default_alignment" != x; then
+	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+       else
+         if test x"$wire_alignment" != x; then
+	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
+         else
+           echo "No default alignment for target $target" 1>&6
+           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
+         fi
+       fi;;
+  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
+  echo "Setting alignment flags = $sim_alignment" 6>&1
+fi
+else
+  if test x"$default_alignment" != x; then
+  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+else
+  if test x"$wire_alignment" != x; then
+    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+  else
+    sim_alignment=
+  fi
+fi
+fi
+
+
+# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
+if test "${enable_sim_hostendian+set}" = set; then
+  enableval="$enable_sim_hostendian"
+  case "${enableval}" in
+  no)	 sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
+  b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
+  l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
+  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
+  echo "Setting hostendian flags = $sim_hostendian" 6>&1
+fi
+else
+  
+if test "x$cross_compiling" = "xno"; then
+  echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
+echo "configure:3623: checking whether byte ordering is bigendian" >&5
+if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  ac_cv_c_bigendian=unknown
+# See if sys/param.h defines the BYTE_ORDER macro.
+cat > conftest.$ac_ext <<EOF
+#line 3630 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
+ bogus endian macros
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3641: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  # It does; now see whether it defined to BIG_ENDIAN or not.
+cat > conftest.$ac_ext <<EOF
+#line 3645 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3656: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_c_bigendian=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_c_bigendian=no
+fi
+rm -f conftest*
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+if test $ac_cv_c_bigendian = unknown; then
+if test "$cross_compiling" = yes; then
+    { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
+else
+  cat > conftest.$ac_ext <<EOF
+#line 3676 "configure"
+#include "confdefs.h"
+main () {
+  /* Are we little or big endian?  From Harbison&Steele.  */
+  union
+  {
+    long l;
+    char c[sizeof (long)];
+  } u;
+  u.l = 1;
+  exit (u.c[sizeof (long) - 1] == 1);
+}
+EOF
+if { (eval echo configure:3689: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+  ac_cv_c_bigendian=no
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -fr conftest*
+  ac_cv_c_bigendian=yes
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_c_bigendian" 1>&6
+if test $ac_cv_c_bigendian = yes; then
+  cat >> confdefs.h <<\EOF
+#define WORDS_BIGENDIAN 1
+EOF
+
+fi
+
+  if test $ac_cv_c_bigendian = yes; then
+    sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
+  else
+    sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
+  fi
+else
+  sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
+fi
+fi
+
+
+default_sim_scache="16384"
+# Check whether --enable-sim-scache or --disable-sim-scache was given.
+if test "${enable_sim_scache+set}" = set; then
+  enableval="$enable_sim_scache"
+  case "${enableval}" in
+  yes)	sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
+  no)	sim_scache="-DWITH_SCACHE=0" ;;
+  [0-9]*) sim_cache=${enableval};;
+  *)	{ echo "configure: error: "Bad value $enableval passed to --enable-sim-scache"" 1>&2; exit 1; };
+	sim_scache="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
+  echo "Setting scache size = $sim_scache" 6>&1
+fi
+else
+  sim_scache="-DWITH_SCACHE=${default_sim_scache}"
+fi
+
+
+
+default_sim_default_model="fr500"
+# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
+if test "${enable_sim_default_model+set}" = set; then
+  enableval="$enable_sim_default_model"
+  case "${enableval}" in
+  yes|no) { echo "configure: error: "Missing argument to --enable-sim-default-model"" 1>&2; exit 1; };;
+  *)	sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
+  echo "Setting default model = $sim_default_model" 6>&1
+fi
+else
+  sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
+fi
+
+
+
+# Check whether --enable-sim-environment or --disable-sim-environment was given.
+if test "${enable_sim_environment+set}" = set; then
+  enableval="$enable_sim_environment"
+  case "${enableval}" in
+  all | ALL)             sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
+  user | USER)           sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
+  virtual | VIRTUAL)     sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
+  operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
+  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-environment"" 1>&2; exit 1; };
+       sim_environment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
+  echo "Setting sim environment = $sim_environment" 6>&1
+fi
+else
+  sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
+fi
+
+
+cgen_maint=no
+cgendir='$(srcdir)/../../cgen'
+
+# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
+if test "${enable_cgen_maint+set}" = set; then
+  enableval="$enable_cgen_maint"
+  case "${enableval}" in
+  yes)	cgen_maint=yes ;;
+  no)	cgen_maint=no ;;
+  *)
+	# argument is cgen install directory (not implemented yet).
+	# Having a `share' directory might be more appropriate for the .scm,
+	# .cpu, etc. files.
+	cgendir=${cgen_maint}/lib/cgen
+	;;
+esac
+fi
+if test x${cgen_maint} != xno ; then
+  CGEN_MAINT=''
+else
+  CGEN_MAINT='#'
+fi
+
+
+
+
+
+#
+# Enable making unknown traps dump out registers
+#
+# Check whether --enable-sim-trapdump or --disable-sim-trapdump was given.
+if test "${enable_sim_trapdump+set}" = set; then
+  enableval="$enable_sim_trapdump"
+  case "${enableval}" in
+  yes) sim_trapdump="-DTRAPDUMP=1";;
+  no)  sim_trapdump="-DTRAPDUMP=0";;
+  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-trapdump"" 1>&2; exit 1; }; sim_trapdump="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trapdump" != x""; then
+  echo "Setting sim_trapdump = $sim_trapdump" 6>&1
+fi
+else
+  sim_trapdump=""
+fi
+
+
+
+
+trap '' 1 2 15
+cat > confcache <<\EOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs.  It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already.  You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+EOF
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(set) 2>&1 |
+  case `(ac_space=' '; set | grep ac_space) 2>&1` in
+  *ac_space=\ *)
+    # `set' does not quote correctly, so add quotes (double-quote substitution
+    # turns \\\\ into \\, and sed turns \\ into \).
+    sed -n \
+      -e "s/'/'\\\\''/g" \
+      -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
+    ;;
+  *)
+    # `set' quotes correctly as required by POSIX, so do not add quotes.
+    sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
+    ;;
+  esac >> confcache
+if cmp -s $cache_file confcache; then
+  :
+else
+  if test -w $cache_file; then
+    echo "updating cache $cache_file"
+    cat confcache > $cache_file
+  else
+    echo "not updating unwritable cache $cache_file"
+  fi
+fi
+rm -f confcache
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# Any assignment to VPATH causes Sun make to only execute
+# the first set of double-colon rules, so remove it if not needed.
+# If there is a colon in the path, we need to keep it.
+if test "x$srcdir" = x.; then
+  ac_vpsub='/^[ 	]*VPATH[ 	]*=[^:]*$/d'
+fi
+
+trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
+
+DEFS=-DHAVE_CONFIG_H
+
+# Without the "./", some shells look in PATH for config.status.
+: ${CONFIG_STATUS=./config.status}
+
+echo creating $CONFIG_STATUS
+rm -f $CONFIG_STATUS
+cat > $CONFIG_STATUS <<EOF
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+#
+# $0 $ac_configure_args
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
+for ac_option
+do
+  case "\$ac_option" in
+  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+    echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
+    exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
+  -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+    echo "$CONFIG_STATUS generated by autoconf version 2.13"
+    exit 0 ;;
+  -help | --help | --hel | --he | --h)
+    echo "\$ac_cs_usage"; exit 0 ;;
+  *) echo "\$ac_cs_usage"; exit 1 ;;
+  esac
+done
+
+ac_given_srcdir=$srcdir
+ac_given_INSTALL="$INSTALL"
+
+trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
+$ac_vpsub
+$extrasub
+s%@sim_environment@%$sim_environment%g
+s%@sim_alignment@%$sim_alignment%g
+s%@sim_assert@%$sim_assert%g
+s%@sim_bitsize@%$sim_bitsize%g
+s%@sim_endian@%$sim_endian%g
+s%@sim_hostendian@%$sim_hostendian%g
+s%@sim_float@%$sim_float%g
+s%@sim_scache@%$sim_scache%g
+s%@sim_default_model@%$sim_default_model%g
+s%@sim_hw_cflags@%$sim_hw_cflags%g
+s%@sim_hw_objs@%$sim_hw_objs%g
+s%@sim_hw@%$sim_hw%g
+s%@sim_inline@%$sim_inline%g
+s%@sim_packages@%$sim_packages%g
+s%@sim_regparm@%$sim_regparm%g
+s%@sim_reserved_bits@%$sim_reserved_bits%g
+s%@sim_smp@%$sim_smp%g
+s%@sim_stdcall@%$sim_stdcall%g
+s%@sim_xor_endian@%$sim_xor_endian%g
+s%@WARN_CFLAGS@%$WARN_CFLAGS%g
+s%@WERROR_CFLAGS@%$WERROR_CFLAGS%g
+s%@SHELL@%$SHELL%g
+s%@CFLAGS@%$CFLAGS%g
+s%@CPPFLAGS@%$CPPFLAGS%g
+s%@CXXFLAGS@%$CXXFLAGS%g
+s%@FFLAGS@%$FFLAGS%g
+s%@DEFS@%$DEFS%g
+s%@LDFLAGS@%$LDFLAGS%g
+s%@LIBS@%$LIBS%g
+s%@exec_prefix@%$exec_prefix%g
+s%@prefix@%$prefix%g
+s%@program_transform_name@%$program_transform_name%g
+s%@bindir@%$bindir%g
+s%@sbindir@%$sbindir%g
+s%@libexecdir@%$libexecdir%g
+s%@datadir@%$datadir%g
+s%@sysconfdir@%$sysconfdir%g
+s%@sharedstatedir@%$sharedstatedir%g
+s%@localstatedir@%$localstatedir%g
+s%@libdir@%$libdir%g
+s%@includedir@%$includedir%g
+s%@oldincludedir@%$oldincludedir%g
+s%@infodir@%$infodir%g
+s%@mandir@%$mandir%g
+s%@host@%$host%g
+s%@host_alias@%$host_alias%g
+s%@host_cpu@%$host_cpu%g
+s%@host_vendor@%$host_vendor%g
+s%@host_os@%$host_os%g
+s%@target@%$target%g
+s%@target_alias@%$target_alias%g
+s%@target_cpu@%$target_cpu%g
+s%@target_vendor@%$target_vendor%g
+s%@target_os@%$target_os%g
+s%@build@%$build%g
+s%@build_alias@%$build_alias%g
+s%@build_cpu@%$build_cpu%g
+s%@build_vendor@%$build_vendor%g
+s%@build_os@%$build_os%g
+s%@CC@%$CC%g
+s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
+s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g
+s%@INSTALL_DATA@%$INSTALL_DATA%g
+s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g
+s%@HDEFINES@%$HDEFINES%g
+s%@AR@%$AR%g
+s%@RANLIB@%$RANLIB%g
+s%@SET_MAKE@%$SET_MAKE%g
+s%@CPP@%$CPP%g
+s%@ALLOCA@%$ALLOCA%g
+s%@USE_NLS@%$USE_NLS%g
+s%@MSGFMT@%$MSGFMT%g
+s%@GMSGFMT@%$GMSGFMT%g
+s%@XGETTEXT@%$XGETTEXT%g
+s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g
+s%@CATALOGS@%$CATALOGS%g
+s%@CATOBJEXT@%$CATOBJEXT%g
+s%@DATADIRNAME@%$DATADIRNAME%g
+s%@GMOFILES@%$GMOFILES%g
+s%@INSTOBJEXT@%$INSTOBJEXT%g
+s%@INTLDEPS@%$INTLDEPS%g
+s%@INTLLIBS@%$INTLLIBS%g
+s%@INTLOBJS@%$INTLOBJS%g
+s%@POFILES@%$POFILES%g
+s%@POSUB@%$POSUB%g
+s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g
+s%@GT_NO@%$GT_NO%g
+s%@GT_YES@%$GT_YES%g
+s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g
+s%@l@%$l%g
+s%@MAINT@%$MAINT%g
+s%@sim_bswap@%$sim_bswap%g
+s%@sim_cflags@%$sim_cflags%g
+s%@sim_debug@%$sim_debug%g
+s%@sim_stdio@%$sim_stdio%g
+s%@sim_trace@%$sim_trace%g
+s%@sim_profile@%$sim_profile%g
+s%@EXEEXT@%$EXEEXT%g
+s%@CGEN_MAINT@%$CGEN_MAINT%g
+s%@cgendir@%$cgendir%g
+s%@cgen@%$cgen%g
+s%@sim_trapdump@%$sim_trapdump%g
+
+CEOF
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+  if test $ac_beg -gt 1; then
+    sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+  else
+    sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+  fi
+  if test ! -s conftest.s$ac_file; then
+    ac_more_lines=false
+    rm -f conftest.s$ac_file
+  else
+    if test -z "$ac_sed_cmds"; then
+      ac_sed_cmds="sed -f conftest.s$ac_file"
+    else
+      ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+    fi
+    ac_file=`expr $ac_file + 1`
+    ac_beg=$ac_end
+    ac_end=`expr $ac_end + $ac_max_sed_cmds`
+  fi
+done
+if test -z "$ac_sed_cmds"; then
+  ac_sed_cmds=cat
+fi
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+
+CONFIG_FILES=\${CONFIG_FILES-"Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in"}
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+  case "$ac_file" in
+  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+  *) ac_file_in="${ac_file}.in" ;;
+  esac
+
+  # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+  # Remove last slash and all that follows it.  Not all systems have dirname.
+  ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+  if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+    # The file is in a subdirectory.
+    test ! -d "$ac_dir" && mkdir "$ac_dir"
+    ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+    # A "../" for each directory in $ac_dir_suffix.
+    ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+  else
+    ac_dir_suffix= ac_dots=
+  fi
+
+  case "$ac_given_srcdir" in
+  .)  srcdir=.
+      if test -z "$ac_dots"; then top_srcdir=.
+      else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+  /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+  *) # Relative path.
+    srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+    top_srcdir="$ac_dots$ac_given_srcdir" ;;
+  esac
+
+  case "$ac_given_INSTALL" in
+  [/$]*) INSTALL="$ac_given_INSTALL" ;;
+  *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
+  esac
+
+  echo creating "$ac_file"
+  rm -f "$ac_file"
+  configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+  case "$ac_file" in
+  *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+  *) ac_comsub= ;;
+  esac
+
+  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+  sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+s%@INSTALL@%$INSTALL%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s%^\([ 	]*\)#\([ 	]*define[ 	][ 	]*\)'
+ac_dB='\([ 	][ 	]*\)[^ 	]*%\1#\2'
+ac_dC='\3'
+ac_dD='%g'
+# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
+ac_uA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
+ac_uB='\([ 	]\)%\1#\2define\3'
+ac_uC=' '
+ac_uD='\4%g'
+# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_eA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
+ac_eB='$%\1#\2define\3'
+ac_eC=' '
+ac_eD='%g'
+
+if test "${CONFIG_HEADERS+set}" != set; then
+EOF
+cat >> $CONFIG_STATUS <<EOF
+  CONFIG_HEADERS="config.h:config.in"
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+fi
+for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
+  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+  case "$ac_file" in
+  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+  *) ac_file_in="${ac_file}.in" ;;
+  esac
+
+  echo creating $ac_file
+
+  rm -f conftest.frag conftest.in conftest.out
+  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+  cat $ac_file_inputs > conftest.in
+
+EOF
+
+# Transform confdefs.h into a sed script conftest.vals that substitutes
+# the proper values into config.h.in to produce config.h.  And first:
+# Protect against being on the right side of a sed subst in config.status.
+# Protect against being in an unquoted here document in config.status.
+rm -f conftest.vals
+cat > conftest.hdr <<\EOF
+s/[\\&%]/\\&/g
+s%[\\$`]%\\&%g
+s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp
+s%ac_d%ac_u%gp
+s%ac_u%ac_e%gp
+EOF
+sed -n -f conftest.hdr confdefs.h > conftest.vals
+rm -f conftest.hdr
+
+# This sed command replaces #undef with comments.  This is necessary, for
+# example, in the case of _POSIX_SOURCE, which is predefined and required
+# on some systems where configure will not decide to define it.
+cat >> conftest.vals <<\EOF
+s%^[ 	]*#[ 	]*undef[ 	][ 	]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
+EOF
+
+# Break up conftest.vals because some shells have a limit on
+# the size of here documents, and old seds have small limits too.
+
+rm -f conftest.tail
+while :
+do
+  ac_lines=`grep -c . conftest.vals`
+  # grep -c gives empty output for an empty file on some AIX systems.
+  if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi
+  # Write a limited-size here document to conftest.frag.
+  echo '  cat > conftest.frag <<CEOF' >> $CONFIG_STATUS
+  sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS
+  echo 'CEOF
+  sed -f conftest.frag conftest.in > conftest.out
+  rm -f conftest.in
+  mv conftest.out conftest.in
+' >> $CONFIG_STATUS
+  sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail
+  rm -f conftest.vals
+  mv conftest.tail conftest.vals
+done
+rm -f conftest.vals
+
+cat >> $CONFIG_STATUS <<\EOF
+  rm -f conftest.frag conftest.h
+  echo "/* $ac_file.  Generated automatically by configure.  */" > conftest.h
+  cat conftest.in >> conftest.h
+  rm -f conftest.in
+  if cmp -s $ac_file conftest.h 2>/dev/null; then
+    echo "$ac_file is unchanged"
+    rm -f conftest.h
+  else
+    # Remove last slash and all that follows it.  Not all systems have dirname.
+      ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+      if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+      # The file is in a subdirectory.
+      test ! -d "$ac_dir" && mkdir "$ac_dir"
+    fi
+    rm -f $ac_file
+    mv conftest.h $ac_file
+  fi
+fi; done
+
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+srcdir=$ac_given_srcdir
+while test -n "$ac_sources"; do
+  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+  set $ac_sources; ac_source=$1; shift; ac_sources=$*
+
+  echo "linking $srcdir/$ac_source to $ac_dest"
+
+  if test ! -r $srcdir/$ac_source; then
+    { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; }
+  fi
+  rm -f $ac_dest
+
+  # Make relative symlinks.
+  # Remove last slash and all that follows it.  Not all systems have dirname.
+  ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'`
+  if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then
+    # The dest file is in a subdirectory.
+    test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir"
+    ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`"
+    # A "../" for each directory in $ac_dest_dir_suffix.
+    ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'`
+  else
+    ac_dest_dir_suffix= ac_dots=
+  fi
+
+  case "$srcdir" in
+  [/$]*) ac_rel_source="$srcdir/$ac_source" ;;
+  *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;;
+  esac
+
+  # Make a symlink if possible; otherwise try a hard link.
+  if ln -s $ac_rel_source $ac_dest 2>/dev/null ||
+    ln $srcdir/$ac_source $ac_dest; then :
+  else
+    { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; }
+  fi
+done
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+case "x$CONFIG_FILES" in
+ xMakefile*)
+   echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+   rm -f Makesim1.tmp Makesim2.tmp Makefile
+   sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
+   sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
+   sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
+	<Makefile.sim >Makefile
+   rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+   ;;
+ esac
+ case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac
+
+exit 0
+EOF
+chmod +x $CONFIG_STATUS
+rm -fr confdefs* $ac_clean_files
+test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
+
+
diff --git a/sim/frv/configure.in b/sim/frv/configure.in
new file mode 100644
index 00000000000..62ff5af4884
--- /dev/null
+++ b/sim/frv/configure.in
@@ -0,0 +1,31 @@
+dnl Process this file with autoconf to produce a configure script.
+sinclude(../common/aclocal.m4)
+AC_PREREQ(2.5)dnl
+AC_INIT(Makefile.in)
+
+SIM_AC_COMMON
+
+SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(16384)
+SIM_AC_OPTION_DEFAULT_MODEL(fr500)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_CGEN_MAINT
+
+#
+# Enable making unknown traps dump out registers
+#
+AC_ARG_ENABLE(sim-trapdump,
+[  --enable-sim-trapdump		Make unknown traps dump the registers],
+[case "${enableval}" in
+  yes) sim_trapdump="-DTRAPDUMP=1";;
+  no)  sim_trapdump="-DTRAPDUMP=0";;
+  *)   AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-trapdump"); sim_trapdump="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trapdump" != x""; then
+  echo "Setting sim_trapdump = $sim_trapdump" 6>&1
+fi],[sim_trapdump=""])dnl
+AC_SUBST(sim_trapdump)
+
+SIM_AC_OUTPUT
diff --git a/sim/frv/cpu.c b/sim/frv/cpu.c
new file mode 100644
index 00000000000..08e3a2c6503
--- /dev/null
+++ b/sim/frv/cpu.c
@@ -0,0 +1,677 @@
+/* Misc. support for CPU family frvbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-pc.  */
+
+USI
+frvbf_h_pc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pc);
+}
+
+/* Set a value for h-pc.  */
+
+void
+frvbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_pc) = newval;
+}
+
+/* Get the value of h-psr_imple.  */
+
+UQI
+frvbf_h_psr_imple_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_imple);
+}
+
+/* Set a value for h-psr_imple.  */
+
+void
+frvbf_h_psr_imple_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_psr_imple) = newval;
+}
+
+/* Get the value of h-psr_ver.  */
+
+UQI
+frvbf_h_psr_ver_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_ver);
+}
+
+/* Set a value for h-psr_ver.  */
+
+void
+frvbf_h_psr_ver_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_psr_ver) = newval;
+}
+
+/* Get the value of h-psr_ice.  */
+
+BI
+frvbf_h_psr_ice_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_ice);
+}
+
+/* Set a value for h-psr_ice.  */
+
+void
+frvbf_h_psr_ice_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_ice) = newval;
+}
+
+/* Get the value of h-psr_nem.  */
+
+BI
+frvbf_h_psr_nem_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_nem);
+}
+
+/* Set a value for h-psr_nem.  */
+
+void
+frvbf_h_psr_nem_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_nem) = newval;
+}
+
+/* Get the value of h-psr_cm.  */
+
+BI
+frvbf_h_psr_cm_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_cm);
+}
+
+/* Set a value for h-psr_cm.  */
+
+void
+frvbf_h_psr_cm_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_cm) = newval;
+}
+
+/* Get the value of h-psr_be.  */
+
+BI
+frvbf_h_psr_be_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_be);
+}
+
+/* Set a value for h-psr_be.  */
+
+void
+frvbf_h_psr_be_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_be) = newval;
+}
+
+/* Get the value of h-psr_esr.  */
+
+BI
+frvbf_h_psr_esr_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_esr);
+}
+
+/* Set a value for h-psr_esr.  */
+
+void
+frvbf_h_psr_esr_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_esr) = newval;
+}
+
+/* Get the value of h-psr_ef.  */
+
+BI
+frvbf_h_psr_ef_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_ef);
+}
+
+/* Set a value for h-psr_ef.  */
+
+void
+frvbf_h_psr_ef_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_ef) = newval;
+}
+
+/* Get the value of h-psr_em.  */
+
+BI
+frvbf_h_psr_em_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_em);
+}
+
+/* Set a value for h-psr_em.  */
+
+void
+frvbf_h_psr_em_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_em) = newval;
+}
+
+/* Get the value of h-psr_pil.  */
+
+UQI
+frvbf_h_psr_pil_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_pil);
+}
+
+/* Set a value for h-psr_pil.  */
+
+void
+frvbf_h_psr_pil_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_psr_pil) = newval;
+}
+
+/* Get the value of h-psr_ps.  */
+
+BI
+frvbf_h_psr_ps_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_ps);
+}
+
+/* Set a value for h-psr_ps.  */
+
+void
+frvbf_h_psr_ps_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_ps) = newval;
+}
+
+/* Get the value of h-psr_et.  */
+
+BI
+frvbf_h_psr_et_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_et);
+}
+
+/* Set a value for h-psr_et.  */
+
+void
+frvbf_h_psr_et_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_psr_et) = newval;
+}
+
+/* Get the value of h-psr_s.  */
+
+BI
+frvbf_h_psr_s_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_psr_s);
+}
+
+/* Set a value for h-psr_s.  */
+
+void
+frvbf_h_psr_s_set (SIM_CPU *current_cpu, BI newval)
+{
+  SET_H_PSR_S (newval);
+}
+
+/* Get the value of h-tbr_tba.  */
+
+USI
+frvbf_h_tbr_tba_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tbr_tba);
+}
+
+/* Set a value for h-tbr_tba.  */
+
+void
+frvbf_h_tbr_tba_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_tbr_tba) = newval;
+}
+
+/* Get the value of h-tbr_tt.  */
+
+UQI
+frvbf_h_tbr_tt_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tbr_tt);
+}
+
+/* Set a value for h-tbr_tt.  */
+
+void
+frvbf_h_tbr_tt_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_tbr_tt) = newval;
+}
+
+/* Get the value of h-bpsr_bs.  */
+
+BI
+frvbf_h_bpsr_bs_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_bpsr_bs);
+}
+
+/* Set a value for h-bpsr_bs.  */
+
+void
+frvbf_h_bpsr_bs_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_bpsr_bs) = newval;
+}
+
+/* Get the value of h-bpsr_bet.  */
+
+BI
+frvbf_h_bpsr_bet_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_bpsr_bet);
+}
+
+/* Set a value for h-bpsr_bet.  */
+
+void
+frvbf_h_bpsr_bet_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_bpsr_bet) = newval;
+}
+
+/* Get the value of h-gr.  */
+
+USI
+frvbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_GR (regno);
+}
+
+/* Set a value for h-gr.  */
+
+void
+frvbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+  SET_H_GR (regno, newval);
+}
+
+/* Get the value of h-gr_double.  */
+
+DI
+frvbf_h_gr_double_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_GR_DOUBLE (regno);
+}
+
+/* Set a value for h-gr_double.  */
+
+void
+frvbf_h_gr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+  SET_H_GR_DOUBLE (regno, newval);
+}
+
+/* Get the value of h-gr_hi.  */
+
+UHI
+frvbf_h_gr_hi_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_GR_HI (regno);
+}
+
+/* Set a value for h-gr_hi.  */
+
+void
+frvbf_h_gr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_GR_HI (regno, newval);
+}
+
+/* Get the value of h-gr_lo.  */
+
+UHI
+frvbf_h_gr_lo_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_GR_LO (regno);
+}
+
+/* Set a value for h-gr_lo.  */
+
+void
+frvbf_h_gr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_GR_LO (regno, newval);
+}
+
+/* Get the value of h-fr.  */
+
+SF
+frvbf_h_fr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR (regno);
+}
+
+/* Set a value for h-fr.  */
+
+void
+frvbf_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+  SET_H_FR (regno, newval);
+}
+
+/* Get the value of h-fr_double.  */
+
+DF
+frvbf_h_fr_double_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_DOUBLE (regno);
+}
+
+/* Set a value for h-fr_double.  */
+
+void
+frvbf_h_fr_double_set (SIM_CPU *current_cpu, UINT regno, DF newval)
+{
+  SET_H_FR_DOUBLE (regno, newval);
+}
+
+/* Get the value of h-fr_int.  */
+
+USI
+frvbf_h_fr_int_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_INT (regno);
+}
+
+/* Set a value for h-fr_int.  */
+
+void
+frvbf_h_fr_int_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+  SET_H_FR_INT (regno, newval);
+}
+
+/* Get the value of h-fr_hi.  */
+
+UHI
+frvbf_h_fr_hi_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_HI (regno);
+}
+
+/* Set a value for h-fr_hi.  */
+
+void
+frvbf_h_fr_hi_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_FR_HI (regno, newval);
+}
+
+/* Get the value of h-fr_lo.  */
+
+UHI
+frvbf_h_fr_lo_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_LO (regno);
+}
+
+/* Set a value for h-fr_lo.  */
+
+void
+frvbf_h_fr_lo_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_FR_LO (regno, newval);
+}
+
+/* Get the value of h-fr_0.  */
+
+UHI
+frvbf_h_fr_0_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_0 (regno);
+}
+
+/* Set a value for h-fr_0.  */
+
+void
+frvbf_h_fr_0_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_FR_0 (regno, newval);
+}
+
+/* Get the value of h-fr_1.  */
+
+UHI
+frvbf_h_fr_1_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_1 (regno);
+}
+
+/* Set a value for h-fr_1.  */
+
+void
+frvbf_h_fr_1_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_FR_1 (regno, newval);
+}
+
+/* Get the value of h-fr_2.  */
+
+UHI
+frvbf_h_fr_2_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_2 (regno);
+}
+
+/* Set a value for h-fr_2.  */
+
+void
+frvbf_h_fr_2_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_FR_2 (regno, newval);
+}
+
+/* Get the value of h-fr_3.  */
+
+UHI
+frvbf_h_fr_3_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_FR_3 (regno);
+}
+
+/* Set a value for h-fr_3.  */
+
+void
+frvbf_h_fr_3_set (SIM_CPU *current_cpu, UINT regno, UHI newval)
+{
+  SET_H_FR_3 (regno, newval);
+}
+
+/* Get the value of h-cpr.  */
+
+SI
+frvbf_h_cpr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_cpr[regno]);
+}
+
+/* Set a value for h-cpr.  */
+
+void
+frvbf_h_cpr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_cpr[regno]) = newval;
+}
+
+/* Get the value of h-cpr_double.  */
+
+DI
+frvbf_h_cpr_double_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_CPR_DOUBLE (regno);
+}
+
+/* Set a value for h-cpr_double.  */
+
+void
+frvbf_h_cpr_double_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+  SET_H_CPR_DOUBLE (regno, newval);
+}
+
+/* Get the value of h-spr.  */
+
+USI
+frvbf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_SPR (regno);
+}
+
+/* Set a value for h-spr.  */
+
+void
+frvbf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+  SET_H_SPR (regno, newval);
+}
+
+/* Get the value of h-accg.  */
+
+USI
+frvbf_h_accg_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_ACCG (regno);
+}
+
+/* Set a value for h-accg.  */
+
+void
+frvbf_h_accg_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+  SET_H_ACCG (regno, newval);
+}
+
+/* Get the value of h-acc40S.  */
+
+DI
+frvbf_h_acc40S_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_ACC40S (regno);
+}
+
+/* Set a value for h-acc40S.  */
+
+void
+frvbf_h_acc40S_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+  SET_H_ACC40S (regno, newval);
+}
+
+/* Get the value of h-acc40U.  */
+
+UDI
+frvbf_h_acc40U_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_ACC40U (regno);
+}
+
+/* Set a value for h-acc40U.  */
+
+void
+frvbf_h_acc40U_set (SIM_CPU *current_cpu, UINT regno, UDI newval)
+{
+  SET_H_ACC40U (regno, newval);
+}
+
+/* Get the value of h-iccr.  */
+
+UQI
+frvbf_h_iccr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_iccr[regno]);
+}
+
+/* Set a value for h-iccr.  */
+
+void
+frvbf_h_iccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval)
+{
+  CPU (h_iccr[regno]) = newval;
+}
+
+/* Get the value of h-fccr.  */
+
+UQI
+frvbf_h_fccr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_fccr[regno]);
+}
+
+/* Set a value for h-fccr.  */
+
+void
+frvbf_h_fccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval)
+{
+  CPU (h_fccr[regno]) = newval;
+}
+
+/* Get the value of h-cccr.  */
+
+UQI
+frvbf_h_cccr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_cccr[regno]);
+}
+
+/* Set a value for h-cccr.  */
+
+void
+frvbf_h_cccr_set (SIM_CPU *current_cpu, UINT regno, UQI newval)
+{
+  CPU (h_cccr[regno]) = newval;
+}
+
+/* Record trace results for INSN.  */
+
+void
+frvbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h
new file mode 100644
index 00000000000..354d4c02242
--- /dev/null
+++ b/sim/frv/cpu.h
@@ -0,0 +1,4310 @@
+/* CPU family header for frvbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_FRVBF_H
+#define CPU_FRVBF_H
+
+/* Maximum number of instructions that are fetched at a time.
+   This is for LIW type instructions sets (e.g. m32r).  */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel.  */
+#define MAX_PARALLEL_INSNS 4
+
+/* CPU state information.  */
+typedef struct {
+  /* Hardware elements.  */
+  struct {
+  /* program counter */
+  USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+  /* PSR.IMPLE */
+  UQI h_psr_imple;
+#define GET_H_PSR_IMPLE() CPU (h_psr_imple)
+#define SET_H_PSR_IMPLE(x) (CPU (h_psr_imple) = (x))
+  /* PSR.VER */
+  UQI h_psr_ver;
+#define GET_H_PSR_VER() CPU (h_psr_ver)
+#define SET_H_PSR_VER(x) (CPU (h_psr_ver) = (x))
+  /* PSR.ICE bit */
+  BI h_psr_ice;
+#define GET_H_PSR_ICE() CPU (h_psr_ice)
+#define SET_H_PSR_ICE(x) (CPU (h_psr_ice) = (x))
+  /* PSR.NEM bit */
+  BI h_psr_nem;
+#define GET_H_PSR_NEM() CPU (h_psr_nem)
+#define SET_H_PSR_NEM(x) (CPU (h_psr_nem) = (x))
+  /* PSR.CM  bit */
+  BI h_psr_cm;
+#define GET_H_PSR_CM() CPU (h_psr_cm)
+#define SET_H_PSR_CM(x) (CPU (h_psr_cm) = (x))
+  /* PSR.BE  bit */
+  BI h_psr_be;
+#define GET_H_PSR_BE() CPU (h_psr_be)
+#define SET_H_PSR_BE(x) (CPU (h_psr_be) = (x))
+  /* PSR.ESR bit */
+  BI h_psr_esr;
+#define GET_H_PSR_ESR() CPU (h_psr_esr)
+#define SET_H_PSR_ESR(x) (CPU (h_psr_esr) = (x))
+  /* PSR.EF  bit */
+  BI h_psr_ef;
+#define GET_H_PSR_EF() CPU (h_psr_ef)
+#define SET_H_PSR_EF(x) (CPU (h_psr_ef) = (x))
+  /* PSR.EM  bit */
+  BI h_psr_em;
+#define GET_H_PSR_EM() CPU (h_psr_em)
+#define SET_H_PSR_EM(x) (CPU (h_psr_em) = (x))
+  /* PSR.PIL     */
+  UQI h_psr_pil;
+#define GET_H_PSR_PIL() CPU (h_psr_pil)
+#define SET_H_PSR_PIL(x) (CPU (h_psr_pil) = (x))
+  /* PSR.PS  bit */
+  BI h_psr_ps;
+#define GET_H_PSR_PS() CPU (h_psr_ps)
+#define SET_H_PSR_PS(x) (CPU (h_psr_ps) = (x))
+  /* PSR.ET  bit */
+  BI h_psr_et;
+#define GET_H_PSR_ET() CPU (h_psr_et)
+#define SET_H_PSR_ET(x) (CPU (h_psr_et) = (x))
+  /* PSR.S bit */
+  BI h_psr_s;
+#define GET_H_PSR_S() CPU (h_psr_s)
+#define SET_H_PSR_S(x) \
+do { \
+frvbf_h_psr_s_set_handler (current_cpu, (x));\
+;} while (0)
+  /* TBR.TBA */
+  USI h_tbr_tba;
+#define GET_H_TBR_TBA() CPU (h_tbr_tba)
+#define SET_H_TBR_TBA(x) (CPU (h_tbr_tba) = (x))
+  /* TBR.TT */
+  UQI h_tbr_tt;
+#define GET_H_TBR_TT() CPU (h_tbr_tt)
+#define SET_H_TBR_TT(x) (CPU (h_tbr_tt) = (x))
+  /* PSR.S   bit */
+  BI h_bpsr_bs;
+#define GET_H_BPSR_BS() CPU (h_bpsr_bs)
+#define SET_H_BPSR_BS(x) (CPU (h_bpsr_bs) = (x))
+  /* PSR.ET  bit */
+  BI h_bpsr_bet;
+#define GET_H_BPSR_BET() CPU (h_bpsr_bet)
+#define SET_H_BPSR_BET(x) (CPU (h_bpsr_bet) = (x))
+  /* general registers */
+  USI h_gr[64];
+#define GET_H_GR(index) frvbf_h_gr_get_handler (current_cpu, index)
+#define SET_H_GR(index, x) \
+do { \
+frvbf_h_gr_set_handler (current_cpu, (index), (x));\
+;} while (0)
+  /* floating point registers */
+  SF h_fr[64];
+#define GET_H_FR(index) frvbf_h_fr_get_handler (current_cpu, index)
+#define SET_H_FR(index, x) \
+do { \
+frvbf_h_fr_set_handler (current_cpu, (index), (x));\
+;} while (0)
+  /* coprocessor registers */
+  SI h_cpr[64];
+#define GET_H_CPR(a1) CPU (h_cpr)[a1]
+#define SET_H_CPR(a1, x) (CPU (h_cpr)[a1] = (x))
+  /* special purpose registers */
+  USI h_spr[4096];
+#define GET_H_SPR(index) frvbf_h_spr_get_handler (current_cpu, index)
+#define SET_H_SPR(index, x) \
+do { \
+frvbf_h_spr_set_handler (current_cpu, (index), (x));\
+;} while (0)
+  /* Integer condition code registers */
+  UQI h_iccr[4];
+#define GET_H_ICCR(a1) CPU (h_iccr)[a1]
+#define SET_H_ICCR(a1, x) (CPU (h_iccr)[a1] = (x))
+  /* Integer condition code registers */
+  UQI h_fccr[4];
+#define GET_H_FCCR(a1) CPU (h_fccr)[a1]
+#define SET_H_FCCR(a1, x) (CPU (h_fccr)[a1] = (x))
+  /* Condition code registers */
+  UQI h_cccr[8];
+#define GET_H_CCCR(a1) CPU (h_cccr)[a1]
+#define SET_H_CCCR(a1, x) (CPU (h_cccr)[a1] = (x))
+  } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} FRVBF_CPU_DATA;
+
+/* Virtual regs.  */
+
+#define GET_H_GR_DOUBLE(index) frvbf_h_gr_double_get_handler (current_cpu, index)
+#define SET_H_GR_DOUBLE(index, x) \
+do { \
+frvbf_h_gr_double_set_handler (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_GR_HI(index) frvbf_h_gr_hi_get_handler (current_cpu, index)
+#define SET_H_GR_HI(index, x) \
+do { \
+frvbf_h_gr_hi_set_handler (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_GR_LO(index) frvbf_h_gr_lo_get_handler (current_cpu, index)
+#define SET_H_GR_LO(index, x) \
+do { \
+frvbf_h_gr_lo_set_handler (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_FR_DOUBLE(index) frvbf_h_fr_double_get_handler (current_cpu, index)
+#define SET_H_FR_DOUBLE(index, x) \
+do { \
+frvbf_h_fr_double_set_handler (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_FR_INT(index) frvbf_h_fr_int_get_handler (current_cpu, index)
+#define SET_H_FR_INT(index, x) \
+do { \
+frvbf_h_fr_int_set_handler (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_FR_HI(index) SRLSI (GET_H_FR_INT (index), 16)
+#define SET_H_FR_HI(index, x) \
+do { \
+SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 65535), SLLHI ((x), 16)));\
+;} while (0)
+#define GET_H_FR_LO(index) ANDSI (GET_H_FR_INT (index), 65535)
+#define SET_H_FR_LO(index, x) \
+do { \
+SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffff0000), ANDHI ((x), 65535)));\
+;} while (0)
+#define GET_H_FR_0(index) ANDSI (GET_H_FR_INT (index), 255)
+#define SET_H_FR_0(index, x) \
+do { \
+{\
+if (GTSI ((x), 255)) {\
+  (x) = 255;\
+}\
+SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffffff00), (x)));\
+}\
+;} while (0)
+#define GET_H_FR_1(index) ANDSI (SRLSI (GET_H_FR_INT (index), 8), 255)
+#define SET_H_FR_1(index, x) \
+do { \
+{\
+if (GTSI ((x), 255)) {\
+  (x) = 255;\
+}\
+SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xffff00ff), SLLHI ((x), 8)));\
+}\
+;} while (0)
+#define GET_H_FR_2(index) ANDSI (SRLSI (GET_H_FR_INT (index), 16), 255)
+#define SET_H_FR_2(index, x) \
+do { \
+{\
+if (GTSI ((x), 255)) {\
+  (x) = 255;\
+}\
+SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 0xff00ffff), SLLHI ((x), 16)));\
+}\
+;} while (0)
+#define GET_H_FR_3(index) ANDSI (SRLSI (GET_H_FR_INT (index), 24), 255)
+#define SET_H_FR_3(index, x) \
+do { \
+{\
+if (GTSI ((x), 255)) {\
+  (x) = 255;\
+}\
+SET_H_FR_INT ((index), ORSI (ANDSI (GET_H_FR_INT ((index)), 16777215), SLLHI ((x), 24)));\
+}\
+;} while (0)
+#define GET_H_CPR_DOUBLE(index) frvbf_h_cpr_double_get_handler (current_cpu, index)
+#define SET_H_CPR_DOUBLE(index, x) \
+do { \
+frvbf_h_cpr_double_set_handler (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_ACCG(index) ANDSI (GET_H_SPR (((index) + (1472))), 255)
+#define SET_H_ACCG(index, x) \
+do { \
+CPU (h_spr[(((index)) + (1472))]) = ANDSI ((x), 255);\
+;} while (0)
+#define GET_H_ACC40S(index) ORDI (SLLDI (EXTQIDI (TRUNCSIQI (GET_H_SPR (((index) + (1472))))), 32), ZEXTSIDI (GET_H_SPR (((index) + (1408)))))
+#define SET_H_ACC40S(index, x) \
+do { \
+{\
+frv_check_spr_write_access (current_cpu, (((index)) + (1408)));\
+CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\
+CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\
+}\
+;} while (0)
+#define GET_H_ACC40U(index) ORDI (SLLDI (ZEXTSIDI (GET_H_SPR (((index) + (1472)))), 32), ZEXTSIDI (GET_H_SPR (((index) + (1408)))))
+#define SET_H_ACC40U(index, x) \
+do { \
+{\
+frv_check_spr_write_access (current_cpu, (((index)) + (1408)));\
+CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\
+CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\
+}\
+;} while (0)
+
+/* Cover fns for register access.  */
+USI frvbf_h_pc_get (SIM_CPU *);
+void frvbf_h_pc_set (SIM_CPU *, USI);
+UQI frvbf_h_psr_imple_get (SIM_CPU *);
+void frvbf_h_psr_imple_set (SIM_CPU *, UQI);
+UQI frvbf_h_psr_ver_get (SIM_CPU *);
+void frvbf_h_psr_ver_set (SIM_CPU *, UQI);
+BI frvbf_h_psr_ice_get (SIM_CPU *);
+void frvbf_h_psr_ice_set (SIM_CPU *, BI);
+BI frvbf_h_psr_nem_get (SIM_CPU *);
+void frvbf_h_psr_nem_set (SIM_CPU *, BI);
+BI frvbf_h_psr_cm_get (SIM_CPU *);
+void frvbf_h_psr_cm_set (SIM_CPU *, BI);
+BI frvbf_h_psr_be_get (SIM_CPU *);
+void frvbf_h_psr_be_set (SIM_CPU *, BI);
+BI frvbf_h_psr_esr_get (SIM_CPU *);
+void frvbf_h_psr_esr_set (SIM_CPU *, BI);
+BI frvbf_h_psr_ef_get (SIM_CPU *);
+void frvbf_h_psr_ef_set (SIM_CPU *, BI);
+BI frvbf_h_psr_em_get (SIM_CPU *);
+void frvbf_h_psr_em_set (SIM_CPU *, BI);
+UQI frvbf_h_psr_pil_get (SIM_CPU *);
+void frvbf_h_psr_pil_set (SIM_CPU *, UQI);
+BI frvbf_h_psr_ps_get (SIM_CPU *);
+void frvbf_h_psr_ps_set (SIM_CPU *, BI);
+BI frvbf_h_psr_et_get (SIM_CPU *);
+void frvbf_h_psr_et_set (SIM_CPU *, BI);
+BI frvbf_h_psr_s_get (SIM_CPU *);
+void frvbf_h_psr_s_set (SIM_CPU *, BI);
+USI frvbf_h_tbr_tba_get (SIM_CPU *);
+void frvbf_h_tbr_tba_set (SIM_CPU *, USI);
+UQI frvbf_h_tbr_tt_get (SIM_CPU *);
+void frvbf_h_tbr_tt_set (SIM_CPU *, UQI);
+BI frvbf_h_bpsr_bs_get (SIM_CPU *);
+void frvbf_h_bpsr_bs_set (SIM_CPU *, BI);
+BI frvbf_h_bpsr_bet_get (SIM_CPU *);
+void frvbf_h_bpsr_bet_set (SIM_CPU *, BI);
+USI frvbf_h_gr_get (SIM_CPU *, UINT);
+void frvbf_h_gr_set (SIM_CPU *, UINT, USI);
+DI frvbf_h_gr_double_get (SIM_CPU *, UINT);
+void frvbf_h_gr_double_set (SIM_CPU *, UINT, DI);
+UHI frvbf_h_gr_hi_get (SIM_CPU *, UINT);
+void frvbf_h_gr_hi_set (SIM_CPU *, UINT, UHI);
+UHI frvbf_h_gr_lo_get (SIM_CPU *, UINT);
+void frvbf_h_gr_lo_set (SIM_CPU *, UINT, UHI);
+SF frvbf_h_fr_get (SIM_CPU *, UINT);
+void frvbf_h_fr_set (SIM_CPU *, UINT, SF);
+DF frvbf_h_fr_double_get (SIM_CPU *, UINT);
+void frvbf_h_fr_double_set (SIM_CPU *, UINT, DF);
+USI frvbf_h_fr_int_get (SIM_CPU *, UINT);
+void frvbf_h_fr_int_set (SIM_CPU *, UINT, USI);
+UHI frvbf_h_fr_hi_get (SIM_CPU *, UINT);
+void frvbf_h_fr_hi_set (SIM_CPU *, UINT, UHI);
+UHI frvbf_h_fr_lo_get (SIM_CPU *, UINT);
+void frvbf_h_fr_lo_set (SIM_CPU *, UINT, UHI);
+UHI frvbf_h_fr_0_get (SIM_CPU *, UINT);
+void frvbf_h_fr_0_set (SIM_CPU *, UINT, UHI);
+UHI frvbf_h_fr_1_get (SIM_CPU *, UINT);
+void frvbf_h_fr_1_set (SIM_CPU *, UINT, UHI);
+UHI frvbf_h_fr_2_get (SIM_CPU *, UINT);
+void frvbf_h_fr_2_set (SIM_CPU *, UINT, UHI);
+UHI frvbf_h_fr_3_get (SIM_CPU *, UINT);
+void frvbf_h_fr_3_set (SIM_CPU *, UINT, UHI);
+SI frvbf_h_cpr_get (SIM_CPU *, UINT);
+void frvbf_h_cpr_set (SIM_CPU *, UINT, SI);
+DI frvbf_h_cpr_double_get (SIM_CPU *, UINT);
+void frvbf_h_cpr_double_set (SIM_CPU *, UINT, DI);
+USI frvbf_h_spr_get (SIM_CPU *, UINT);
+void frvbf_h_spr_set (SIM_CPU *, UINT, USI);
+USI frvbf_h_accg_get (SIM_CPU *, UINT);
+void frvbf_h_accg_set (SIM_CPU *, UINT, USI);
+DI frvbf_h_acc40S_get (SIM_CPU *, UINT);
+void frvbf_h_acc40S_set (SIM_CPU *, UINT, DI);
+UDI frvbf_h_acc40U_get (SIM_CPU *, UINT);
+void frvbf_h_acc40U_set (SIM_CPU *, UINT, UDI);
+UQI frvbf_h_iccr_get (SIM_CPU *, UINT);
+void frvbf_h_iccr_set (SIM_CPU *, UINT, UQI);
+UQI frvbf_h_fccr_get (SIM_CPU *, UINT);
+void frvbf_h_fccr_set (SIM_CPU *, UINT, UQI);
+UQI frvbf_h_cccr_get (SIM_CPU *, UINT);
+void frvbf_h_cccr_set (SIM_CPU *, UINT, UQI);
+
+/* These must be hand-written.  */
+extern CPUREG_FETCH_FN frvbf_fetch_register;
+extern CPUREG_STORE_FN frvbf_store_register;
+
+typedef struct {
+  int empty;
+} MODEL_FRV_DATA;
+
+typedef struct {
+  DI prev_fpop;
+  DI prev_media;
+  DI prev_cc_complex;
+  DI cur_fpop;
+  DI cur_media;
+  DI cur_cc_complex;
+} MODEL_FR500_DATA;
+
+typedef struct {
+  int empty;
+} MODEL_TOMCAT_DATA;
+
+typedef struct {
+  DI prev_fp_load;
+  DI prev_fr_p4;
+  DI prev_fr_p6;
+  DI prev_acc_p2;
+  DI prev_acc_p4;
+  DI cur_fp_load;
+  DI cur_fr_p4;
+  DI cur_fr_p6;
+  DI cur_acc_p2;
+  DI cur_acc_p4;
+} MODEL_FR400_DATA;
+
+typedef struct {
+  int empty;
+} MODEL_SIMPLE_DATA;
+
+/* Instruction argument buffer.  */
+
+union sem_fields {
+  struct { /* no operands */
+    int empty;
+  } fmt_empty;
+  struct { /*  */
+    unsigned short out_h_spr_USI_2;
+  } sfmt_break;
+  struct { /*  */
+    UINT f_debug;
+  } sfmt_rett;
+  struct { /*  */
+    IADDR i_label24;
+  } sfmt_call;
+  struct { /*  */
+    UINT f_A;
+    UINT f_ACC40Sk;
+  } sfmt_mclracc;
+  struct { /*  */
+    INT f_u12;
+    UINT f_FRk;
+    unsigned char out_FRkhi;
+  } sfmt_mhsethis;
+  struct { /*  */
+    INT f_u12;
+    UINT f_FRk;
+    unsigned char out_FRklo;
+  } sfmt_mhsetlos;
+  struct { /*  */
+    INT f_s16;
+    UINT f_GRk;
+    unsigned char out_GRk;
+  } sfmt_setlos;
+  struct { /*  */
+    UINT f_GRk;
+    UINT f_u16;
+    unsigned char out_GRkhi;
+  } sfmt_sethi;
+  struct { /*  */
+    UINT f_GRk;
+    UINT f_u16;
+    unsigned char out_GRklo;
+  } sfmt_setlo;
+  struct { /*  */
+    UINT f_ACCGk;
+    UINT f_FRi;
+    unsigned char in_FRinti;
+    unsigned char out_ACCGk;
+  } sfmt_mwtaccg;
+  struct { /*  */
+    UINT f_ACCGi;
+    UINT f_FRk;
+    unsigned char in_ACCGi;
+    unsigned char out_FRintk;
+  } sfmt_mrdaccg;
+  struct { /*  */
+    INT f_s5;
+    UINT f_FRk;
+    unsigned char in_FRkhi;
+    unsigned char out_FRkhi;
+  } sfmt_mhsethih;
+  struct { /*  */
+    INT f_s5;
+    UINT f_FRk;
+    unsigned char in_FRklo;
+    unsigned char out_FRklo;
+  } sfmt_mhsetloh;
+  struct { /*  */
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRdoublej;
+    unsigned char out_FRintk;
+  } sfmt_fdtoi;
+  struct { /*  */
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRintj;
+    unsigned char out_FRdoublek;
+  } sfmt_fitod;
+  struct { /*  */
+    INT f_d12;
+    UINT f_GRi;
+    UINT f_LI;
+    unsigned char in_GRi;
+  } sfmt_jmpil;
+  struct { /*  */
+    IADDR i_label16;
+    UINT f_FCCi_2;
+    UINT f_hint;
+    unsigned char in_FCCi_2;
+  } sfmt_fbne;
+  struct { /*  */
+    IADDR i_label16;
+    UINT f_ICCi_2;
+    UINT f_hint;
+    unsigned char in_ICCi_2;
+  } sfmt_beq;
+  struct { /*  */
+    UINT f_GRj;
+    UINT f_spr;
+    unsigned short in_spr;
+    unsigned char out_GRj;
+  } sfmt_movsg;
+  struct { /*  */
+    UINT f_GRj;
+    UINT f_spr;
+    unsigned short out_spr;
+    unsigned char in_GRj;
+  } sfmt_movgs;
+  struct { /*  */
+    INT f_s6;
+    UINT f_ACC40Si;
+    UINT f_FRk;
+    unsigned char in_ACC40Si;
+    unsigned char out_FRintk;
+  } sfmt_mcuti;
+  struct { /*  */
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_lock;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+  } sfmt_icpl;
+  struct { /*  */
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_ae;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+  } sfmt_icei;
+  struct { /*  */
+    INT f_d12;
+    UINT f_FRk;
+    UINT f_GRi;
+    unsigned char in_FRdoublek;
+    unsigned char in_GRi;
+  } sfmt_stdfi;
+  struct { /*  */
+    INT f_d12;
+    UINT f_GRi;
+    UINT f_GRk;
+    unsigned char in_GRdoublek;
+    unsigned char in_GRi;
+  } sfmt_stdi;
+  struct { /*  */
+    INT f_d12;
+    UINT f_FRk;
+    UINT f_GRi;
+    unsigned char in_FRintk;
+    unsigned char in_GRi;
+  } sfmt_stbfi;
+  struct { /*  */
+    INT f_d12;
+    UINT f_FRk;
+    UINT f_GRi;
+    unsigned char in_GRi;
+    unsigned char out_FRdoublek;
+  } sfmt_lddfi;
+  struct { /*  */
+    INT f_d12;
+    UINT f_FRk;
+    UINT f_GRi;
+    unsigned char in_GRi;
+    unsigned char out_FRintk;
+  } sfmt_ldbfi;
+  struct { /*  */
+    INT f_d12;
+    UINT f_GRi;
+    UINT f_GRk;
+    unsigned char in_GRi;
+    unsigned char out_GRdoublek;
+  } sfmt_smuli;
+  struct { /*  */
+    UINT f_ACC40Si;
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_ACC40Si;
+    unsigned char in_FRintj;
+    unsigned char out_FRintk;
+  } sfmt_mcut;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRk;
+    UINT f_u6;
+    unsigned char in_FRinti;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1;
+    unsigned char out_FRintk;
+  } sfmt_mwcuti;
+  struct { /*  */
+    INT f_u12;
+    UINT f_FRk;
+    unsigned char in_FRintk;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_mhdsets;
+  struct { /*  */
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_FRj;
+    unsigned char in_FRdoublei;
+    unsigned char in_FRdoublej;
+    unsigned char out_FCCi_2;
+  } sfmt_fcmpd;
+  struct { /*  */
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRj;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1;
+  } sfmt_fdstoi;
+  struct { /*  */
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRintj;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintj_1;
+    unsigned char out_FRk;
+    unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1;
+  } sfmt_fditos;
+  struct { /*  */
+    UINT f_CRi;
+    UINT f_CRj;
+    UINT f_CRk;
+    unsigned char in_CRi;
+    unsigned char in_CRj;
+    unsigned char out_CRk;
+  } sfmt_andcr;
+  struct { /*  */
+    INT f_d12;
+    UINT f_GRi;
+    UINT f_GRk;
+    unsigned char in_GRi;
+    unsigned char in_GRk;
+    unsigned char out_GRk;
+  } sfmt_swapi;
+  struct { /*  */
+    INT f_s6;
+    UINT f_FRi;
+    UINT f_FRk;
+    unsigned char in_FRintieven;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char out_FRintkeven;
+    unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1;
+  } sfmt_mdrotli;
+  struct { /*  */
+    INT f_s6;
+    UINT f_ACC40Si;
+    UINT f_FRk;
+    unsigned char in_ACC40Si;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1;
+    unsigned char out_FRintkeven;
+    unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1;
+  } sfmt_mdcutssi;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRinti;
+    unsigned char in_FRintj;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1;
+    unsigned char out_FRintk;
+  } sfmt_mwcut;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRdoublei;
+    unsigned char in_FRdoublej;
+    unsigned char in_FRdoublek;
+    unsigned char out_FRdoublek;
+  } sfmt_fmaddd;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRj;
+    unsigned char out_FRintk;
+  } sfmt_cfstoi;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRintj;
+    unsigned char out_FRk;
+  } sfmt_cfitos;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_CRj_float;
+    UINT f_FCCi_3;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FCCi_3;
+    unsigned char out_CRj_float;
+  } sfmt_cfckne;
+  struct { /*  */
+    SI f_CRj_int;
+    UINT f_CCi;
+    UINT f_ICCi_3;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_ICCi_3;
+    unsigned char out_CRj_int;
+  } sfmt_cckeq;
+  struct { /*  */
+    UINT f_FCCi_2;
+    UINT f_ccond;
+    UINT f_hint;
+    unsigned short in_h_spr_USI_272;
+    unsigned short in_h_spr_USI_273;
+    unsigned short out_h_spr_USI_273;
+    unsigned char in_FCCi_2;
+  } sfmt_fcbeqlr;
+  struct { /*  */
+    UINT f_ICCi_2;
+    UINT f_ccond;
+    UINT f_hint;
+    unsigned short in_h_spr_USI_272;
+    unsigned short in_h_spr_USI_273;
+    unsigned short out_h_spr_USI_273;
+    unsigned char in_ICCi_2;
+  } sfmt_bceqlr;
+  struct { /*  */
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    unsigned char in_CPRdoublek;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_GRi;
+  } sfmt_stdcu;
+  struct { /*  */
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    unsigned char in_CPRk;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_GRi;
+  } sfmt_stcu;
+  struct { /*  */
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_CPRdoublek;
+    unsigned char out_GRi;
+  } sfmt_lddcu;
+  struct { /*  */
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_CPRk;
+    unsigned char out_GRi;
+  } sfmt_ldcu;
+  struct { /*  */
+    INT f_s5;
+    UINT f_FRk;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_mhdseth;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_LI;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+  } sfmt_cjmpl;
+  struct { /*  */
+    INT f_s10;
+    UINT f_GRi;
+    UINT f_GRk;
+    UINT f_ICCi_1;
+    unsigned char in_GRi;
+    unsigned char in_ICCi_1;
+    unsigned char out_GRdoublek;
+    unsigned char out_ICCi_1;
+  } sfmt_smulicc;
+  struct { /*  */
+    INT f_s10;
+    UINT f_GRi;
+    UINT f_GRk;
+    UINT f_ICCi_1;
+    unsigned char in_GRi;
+    unsigned char in_ICCi_1;
+    unsigned char out_GRk;
+    unsigned char out_ICCi_1;
+  } sfmt_addicc;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRinti;
+    unsigned char in_FRintj;
+    unsigned char out_FRintk;
+  } sfmt_cmand;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRi;
+    unsigned char in_FRj;
+    unsigned char out_FCCi_2;
+  } sfmt_cfcmps;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRk;
+    UINT f_GRj;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1;
+    unsigned char out_GRj;
+    unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1;
+  } sfmt_cmovfgd;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRk;
+    UINT f_GRj;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRj;
+    unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1;
+  } sfmt_cmovgfd;
+  struct { /*  */
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_ICCi_1;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char in_ICCi_1;
+    unsigned char out_GRdoublek;
+    unsigned char out_ICCi_1;
+  } sfmt_smulcc;
+  struct { /*  */
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_ICCi_1;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char in_ICCi_1;
+    unsigned char out_GRk;
+    unsigned char out_ICCi_1;
+  } sfmt_addcc;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRk;
+    UINT f_cond;
+    UINT f_u6;
+    unsigned char in_CCi;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_cmexpdhw;
+  struct { /*  */
+    UINT f_ACC40Si;
+    UINT f_ACC40Sk;
+    unsigned char in_ACC40Si;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_2;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_3;
+    unsigned char out_ACC40Sk;
+    unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1;
+    unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2;
+    unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3;
+  } sfmt_mdasaccs;
+  struct { /*  */
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRintj;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char out_FRintj;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_mabshs;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRk;
+    UINT f_u6;
+    unsigned char in_FRinti;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_1;
+    unsigned char out_FRinti;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_mcplhi;
+  struct { /*  */
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRi;
+    unsigned char in_FRj;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1;
+    unsigned char out_FCCi_2;
+    unsigned char out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCi_2_1;
+  } sfmt_nfdcmps;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRi;
+    unsigned char in_FRj;
+    unsigned char in_FRk;
+    unsigned char out_FRk;
+  } sfmt_cfmadds;
+  struct { /*  */
+    INT f_d12;
+    UINT f_FCCi_2;
+    UINT f_GRi;
+    unsigned short out_h_spr_USI_1;
+    unsigned short out_h_spr_USI_768;
+    unsigned short out_h_spr_USI_769;
+    unsigned short out_h_spr_USI_770;
+    unsigned short out_h_spr_USI_771;
+    unsigned char in_FCCi_2;
+    unsigned char in_GRi;
+  } sfmt_ftine;
+  struct { /*  */
+    INT f_d12;
+    UINT f_GRi;
+    UINT f_ICCi_2;
+    unsigned short out_h_spr_USI_1;
+    unsigned short out_h_spr_USI_768;
+    unsigned short out_h_spr_USI_769;
+    unsigned short out_h_spr_USI_770;
+    unsigned short out_h_spr_USI_771;
+    unsigned char in_GRi;
+    unsigned char in_ICCi_2;
+  } sfmt_tieq;
+  struct { /*  */
+    UINT f_FRk;
+    UINT f_GRj;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2;
+    unsigned char in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3;
+    unsigned char out_GRj;
+    unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1;
+    unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2;
+    unsigned char out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3;
+  } sfmt_movfgq;
+  struct { /*  */
+    UINT f_FRk;
+    UINT f_GRj;
+    unsigned char in_GRj;
+    unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1;
+    unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2;
+    unsigned char in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1;
+    unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2;
+    unsigned char out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3;
+  } sfmt_movgfq;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char in_GRk;
+    unsigned char out_GRk;
+  } sfmt_cswap;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRdoublek;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_GRi;
+  } sfmt_cstdfu;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRdoublek;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_GRi;
+  } sfmt_cstdu;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRintk;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_GRi;
+  } sfmt_cstbfu;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char in_GRk;
+    unsigned char out_GRi;
+  } sfmt_cstbu;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_FRdoublek;
+    unsigned char out_GRi;
+  } sfmt_clddfu;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_GRdoublek;
+    unsigned char out_GRi;
+  } sfmt_clddu;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_FRintk;
+    unsigned char out_GRi;
+  } sfmt_cldbfu;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char out_GRi;
+    unsigned char out_GRk;
+  } sfmt_cldsbu;
+  struct { /*  */
+    UINT f_FCCk;
+    UINT f_FRi;
+    UINT f_FRj;
+    unsigned char in_FRinti;
+    unsigned char in_FRintj;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char out_FCCk;
+    unsigned char out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCk_1;
+  } sfmt_mcmpsh;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRk;
+    UINT f_u6;
+    unsigned char in_FRinti;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char out_FRinti;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_msllhi;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRi;
+    unsigned char in_FRj;
+    unsigned char in_FRk;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1;
+    unsigned char out_FRk;
+    unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1;
+  } sfmt_fdmadds;
+  struct { /*  */
+    UINT f_FCCi_2;
+    UINT f_GRi;
+    UINT f_GRj;
+    unsigned short out_h_spr_USI_1;
+    unsigned short out_h_spr_USI_768;
+    unsigned short out_h_spr_USI_769;
+    unsigned short out_h_spr_USI_770;
+    unsigned short out_h_spr_USI_771;
+    unsigned char in_FCCi_2;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+  } sfmt_ftne;
+  struct { /*  */
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_ICCi_2;
+    unsigned short out_h_spr_USI_1;
+    unsigned short out_h_spr_USI_768;
+    unsigned short out_h_spr_USI_769;
+    unsigned short out_h_spr_USI_770;
+    unsigned short out_h_spr_USI_771;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char in_ICCi_2;
+  } sfmt_teq;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3;
+    unsigned char out_GRdoublek;
+    unsigned char out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3;
+  } sfmt_csmulcc;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_GRi;
+    UINT f_GRj;
+    UINT f_GRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_GRi;
+    unsigned char in_GRj;
+    unsigned char in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3;
+    unsigned char out_GRk;
+    unsigned char out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3;
+  } sfmt_caddcc;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRk;
+    unsigned char in_FRinti;
+    unsigned char in_FRintkeven;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char out_FRinti;
+    unsigned char out_FRintkeven;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1;
+  } sfmt_munpackh;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRi;
+    unsigned char in_FRj;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1;
+    unsigned char out_FRk;
+    unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1;
+  } sfmt_cfmas;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRk;
+    UINT f_cond;
+    UINT f_u6;
+    unsigned char in_CCi;
+    unsigned char in_FRintkeven;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char out_FRintkeven;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+  } sfmt_cmexpdhd;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRinti;
+    unsigned char in_FRintj;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_cmaddhss;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRi;
+    unsigned char in_FRj;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_2;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_3;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_2;
+    unsigned char in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_3;
+    unsigned char out_FRk;
+    unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1;
+    unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_2;
+    unsigned char out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_3;
+  } sfmt_fdmas;
+  struct { /*  */
+    UINT f_ACC40Uk;
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_cond;
+    unsigned char in_ACC40Uk;
+    unsigned char in_CCi;
+    unsigned char in_FRinti;
+    unsigned char in_FRintj;
+    unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char out_ACC40Uk;
+    unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1;
+  } sfmt_cmmachu;
+  struct { /*  */
+    UINT f_ACC40Sk;
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_cond;
+    unsigned char in_ACC40Sk;
+    unsigned char in_CCi;
+    unsigned char in_FRinti;
+    unsigned char in_FRintj;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char out_ACC40Sk;
+    unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1;
+  } sfmt_cmmachs;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRintjeven;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char out_FRintjeven;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+  } sfmt_cmhtob;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRintj;
+    unsigned char in_FRintkeven;
+    unsigned char in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char out_FRintj;
+    unsigned char out_FRintkeven;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+  } sfmt_cmbtoh;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    unsigned char in_FRintieven;
+    unsigned char in_FRintjeven;
+    unsigned char in_FRintkeven;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char out_FRintieven;
+    unsigned char out_FRintjeven;
+    unsigned char out_FRintkeven;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+  } sfmt_mdpackh;
+  struct { /*  */
+    UINT f_FRi;
+    UINT f_FRk;
+    unsigned char in_FRintieven;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char out_FRintieven;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1;
+  } sfmt_mdunpackh;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRintj;
+    unsigned char in_FRintk;
+    unsigned char in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0;
+    unsigned char out_FRintj;
+    unsigned char out_FRintk;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_1;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_3;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_3;
+  } sfmt_cmbtohe;
+  struct { /*  */
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_FRk;
+    UINT f_cond;
+    unsigned char in_CCi;
+    unsigned char in_FRintieven;
+    unsigned char in_FRintjeven;
+    unsigned char in_FRintkeven;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char out_FRintkeven;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+    unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+  } sfmt_cmqaddhss;
+  struct { /*  */
+    UINT f_ACC40Uk;
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_cond;
+    unsigned char in_ACC40Uk;
+    unsigned char in_CCi;
+    unsigned char in_FRintieven;
+    unsigned char in_FRintjeven;
+    unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1;
+    unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2;
+    unsigned char in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char out_ACC40Uk;
+    unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1;
+    unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2;
+    unsigned char out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3;
+  } sfmt_cmqmachu;
+  struct { /*  */
+    UINT f_ACC40Sk;
+    UINT f_CCi;
+    UINT f_FRi;
+    UINT f_FRj;
+    UINT f_cond;
+    unsigned char in_ACC40Sk;
+    unsigned char in_CCi;
+    unsigned char in_FRintieven;
+    unsigned char in_FRintjeven;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2;
+    unsigned char in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0;
+    unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1;
+    unsigned char out_ACC40Sk;
+    unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1;
+    unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2;
+    unsigned char out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3;
+  } sfmt_cmqmachs;
+#if WITH_SCACHE_PBB
+  /* Writeback handler.  */
+  struct {
+    /* Pointer to argbuf entry for insn whose results need writing back.  */
+    const struct argbuf *abuf;
+  } write;
+  /* x-before handler */
+  struct {
+    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+    int first_p;
+  } before;
+  /* x-after handler */
+  struct {
+    int empty;
+  } after;
+  /* This entry is used to terminate each pbb.  */
+  struct {
+    /* Number of insns in pbb.  */
+    int insn_count;
+    /* Next pbb to execute.  */
+    SCACHE *next;
+    SCACHE *branch_target;
+  } chain;
+#endif
+};
+
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
+  /* cpu specific data follows */
+  union sem semantic;
+  int written;
+  union sem_fields fields;
+};
+
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+  int first_insn_p;
+  int last_insn_p;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+   These define and assign the local vars that contain the insn's fields.  */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+  unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+  length = 0; \
+
+#define EXTRACT_IFMT_ADD_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ICCi_1_null; \
+  UINT f_ope2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1_null = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_NOT_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ICCi_1_null; \
+  UINT f_ope2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_NOT_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1_null = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SMUL_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ICCi_1_null; \
+  UINT f_ope2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_SMUL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1_null = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CADD_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CADD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CNOT_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CNOT_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CSMUL_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CSMUL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ADDCC_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ICCi_1; \
+  UINT f_ope2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDCC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SMULCC_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ICCi_1; \
+  UINT f_ope2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_SMULCC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ADDI_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_SMULI_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_SMULI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_ADDICC_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ICCi_1; \
+  INT f_s10; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDICC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); \
+
+#define EXTRACT_IFMT_SMULICC_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ICCi_1; \
+  INT f_s10; \
+  unsigned int length;
+#define EXTRACT_IFMT_SMULICC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10); \
+
+#define EXTRACT_IFMT_CMPB_VARS \
+  UINT f_pack; \
+  UINT f_GRk_null; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ICCi_1; \
+  UINT f_ope2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMPB_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2); \
+  f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SETLO_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_misc_null_4; \
+  UINT f_u16; \
+  unsigned int length;
+#define EXTRACT_IFMT_SETLO_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_SETHI_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_misc_null_4; \
+  UINT f_u16; \
+  unsigned int length;
+#define EXTRACT_IFMT_SETHI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_SETLOS_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_misc_null_4; \
+  INT f_s16; \
+  unsigned int length;
+#define EXTRACT_IFMT_SETLOS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_s16 = EXTRACT_LSB0_INT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_LDSB_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDSB_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LDBF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDBF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LDC_VARS \
+  UINT f_pack; \
+  UINT f_CPRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LDD_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LDDF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDDF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LDDC_VARS \
+  UINT f_pack; \
+  UINT f_CPRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDDC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LDSBI_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDSBI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_LDBFI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDBFI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_LDDI_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDDI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_LDDFI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDDFI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_STDF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_STDF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CLDBF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CLDBF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CLDDF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CLDDF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CSTDF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CSTDF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_STDFI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_STDFI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_MOVGF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MOVGF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMOVGF_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMOVGF_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MOVGS_VARS \
+  UINT f_pack; \
+  UINT f_op; \
+  UINT f_spr_h; \
+  UINT f_spr_l; \
+  UINT f_spr; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MOVGS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_spr_h = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_spr_l = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+{\
+  f_spr = ((((f_spr_h) << (6))) | (f_spr_l));\
+}\
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_BRA_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  SI f_label16; \
+  unsigned int length;
+#define EXTRACT_IFMT_BRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_BNO_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_label16_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BNO_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_label16_null = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_BEQ_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2; \
+  UINT f_op; \
+  UINT f_hint; \
+  SI f_label16; \
+  unsigned int length;
+#define EXTRACT_IFMT_BEQ_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_FBRA_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  SI f_label16; \
+  unsigned int length;
+#define EXTRACT_IFMT_FBRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_FBNO_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_label16_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FBNO_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_label16_null = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_FBNE_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_hint; \
+  SI f_label16; \
+  unsigned int length;
+#define EXTRACT_IFMT_FBNE_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_BCTRLR_VARS \
+  UINT f_pack; \
+  UINT f_cond_null; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BCTRLR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_BRALR_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BRALR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_BNOLR_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BNOLR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_BEQLR_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BEQLR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FBRALR_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FBRALR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FBNOLR_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FBNOLR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FBEQLR_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FBEQLR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond_null = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_BCRALR_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BCRALR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_BCEQLR_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BCEQLR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FCBRALR_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FCBRALR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FCBEQLR_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_hint; \
+  UINT f_ope3; \
+  UINT f_ccond; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FCBEQLR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
+  f_ope3 = EXTRACT_LSB0_UINT (insn, 32, 15, 3); \
+  f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_JMPL_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_LI_off; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_misc_null_2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_JMPL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_LI_off = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_2 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CALLL_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_LI_on; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_misc_null_2; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CALLL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_LI_on = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_2 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_JMPIL_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_LI_off; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_JMPIL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_LI_off = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_CALLIL_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_LI_on; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_CALLIL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_LI_on = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_CALL_VARS \
+  UINT f_pack; \
+  UINT f_op; \
+  INT f_labelH6; \
+  UINT f_labelL18; \
+  INT f_label24; \
+  unsigned int length;
+#define EXTRACT_IFMT_CALL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_labelH6 = EXTRACT_LSB0_INT (insn, 32, 30, 6); \
+  f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18); \
+{\
+  f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc));\
+}\
+
+#define EXTRACT_IFMT_RETT_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_debug; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_RETT_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_debug = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_REI_VARS \
+  UINT f_pack; \
+  UINT f_rd_null; \
+  UINT f_op; \
+  UINT f_eir; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_REI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_eir = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_TRA_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_misc_null_3; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_TRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_TNO_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi_null; \
+  UINT f_misc_null_3; \
+  UINT f_ope4; \
+  UINT f_GRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_TNO_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_TEQ_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_misc_null_3; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_TEQ_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FTRA_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_misc_null_3; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FTRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FTNO_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi_null; \
+  UINT f_misc_null_3; \
+  UINT f_ope4; \
+  UINT f_GRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FTNO_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FTNE_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_misc_null_3; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FTNE_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_TIRA_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_TIRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_TINO_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_TINO_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_TIEQ_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  UINT f_ICCi_2; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_TIEQ_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FTIRA_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_ICCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_FTIRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FTINO_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2_null; \
+  UINT f_op; \
+  UINT f_GRi_null; \
+  UINT f_s12_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FTINO_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_s12_null = EXTRACT_LSB0_UINT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_FTINE_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_GRi; \
+  INT f_d12; \
+  unsigned int length;
+#define EXTRACT_IFMT_FTINE_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); \
+
+#define EXTRACT_IFMT_BREAK_VARS \
+  UINT f_pack; \
+  UINT f_rd_null; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_misc_null_3; \
+  UINT f_ope4; \
+  UINT f_GRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BREAK_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_misc_null_3 = EXTRACT_LSB0_UINT (insn, 32, 11, 4); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ANDCR_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_6; \
+  UINT f_CRk; \
+  UINT f_op; \
+  UINT f_misc_null_7; \
+  UINT f_CRi; \
+  UINT f_ope1; \
+  UINT f_misc_null_8; \
+  UINT f_CRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_ANDCR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_6 = EXTRACT_LSB0_UINT (insn, 32, 30, 3); \
+  f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_misc_null_7 = EXTRACT_LSB0_UINT (insn, 32, 17, 3); \
+  f_CRi = EXTRACT_LSB0_UINT (insn, 32, 14, 3); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_misc_null_8 = EXTRACT_LSB0_UINT (insn, 32, 5, 3); \
+  f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \
+
+#define EXTRACT_IFMT_NOTCR_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_6; \
+  UINT f_CRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_misc_null_8; \
+  UINT f_CRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_NOTCR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_6 = EXTRACT_LSB0_UINT (insn, 32, 30, 3); \
+  f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_misc_null_8 = EXTRACT_LSB0_UINT (insn, 32, 5, 3); \
+  f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \
+
+#define EXTRACT_IFMT_CKRA_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  SI f_CRj_int; \
+  UINT f_op; \
+  UINT f_misc_null_5; \
+  UINT f_ICCi_3_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_CKRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_misc_null_5 = EXTRACT_LSB0_UINT (insn, 32, 17, 16); \
+  f_ICCi_3_null = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \
+
+#define EXTRACT_IFMT_CKEQ_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  SI f_CRj_int; \
+  UINT f_op; \
+  UINT f_misc_null_5; \
+  UINT f_ICCi_3; \
+  unsigned int length;
+#define EXTRACT_IFMT_CKEQ_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_misc_null_5 = EXTRACT_LSB0_UINT (insn, 32, 17, 16); \
+  f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \
+
+#define EXTRACT_IFMT_FCKRA_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_CRj_float; \
+  UINT f_op; \
+  UINT f_misc_null_5; \
+  UINT f_FCCi_3; \
+  unsigned int length;
+#define EXTRACT_IFMT_FCKRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_misc_null_5 = EXTRACT_LSB0_UINT (insn, 32, 17, 16); \
+  f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \
+
+#define EXTRACT_IFMT_CCKRA_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  SI f_CRj_int; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_misc_null_9; \
+  UINT f_ICCi_3_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_CCKRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \
+  f_ICCi_3_null = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \
+
+#define EXTRACT_IFMT_CCKEQ_VARS \
+  UINT f_pack; \
+  UINT f_int_cc; \
+  SI f_CRj_int; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_misc_null_9; \
+  UINT f_ICCi_3; \
+  unsigned int length;
+#define EXTRACT_IFMT_CCKEQ_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_int_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4)); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \
+  f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \
+
+#define EXTRACT_IFMT_CFCKRA_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_CRj_float; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_misc_null_9; \
+  UINT f_FCCi_3_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFCKRA_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \
+  f_FCCi_3_null = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \
+
+#define EXTRACT_IFMT_CFCKNE_VARS \
+  UINT f_pack; \
+  UINT f_flt_cc; \
+  UINT f_CRj_float; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_misc_null_9; \
+  UINT f_FCCi_3; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFCKNE_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_flt_cc = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_misc_null_9 = EXTRACT_LSB0_UINT (insn, 32, 5, 4); \
+  f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2); \
+
+#define EXTRACT_IFMT_CJMPL_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_LI_off; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CJMPL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_LI_off = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CCALLL_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_LI_on; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CCALLL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_LI_on = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ICI_VARS \
+  UINT f_pack; \
+  UINT f_rd_null; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_ICI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ICEI_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_ae; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_ICEI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_ae = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ICPL_VARS \
+  UINT f_pack; \
+  UINT f_misc_null_1; \
+  UINT f_lock; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_ICPL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_misc_null_1 = EXTRACT_LSB0_UINT (insn, 32, 30, 5); \
+  f_lock = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ICUL_VARS \
+  UINT f_pack; \
+  UINT f_rd_null; \
+  UINT f_op; \
+  UINT f_GRi; \
+  UINT f_ope1; \
+  UINT f_GRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_ICUL_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_BAR_VARS \
+  UINT f_pack; \
+  UINT f_rd_null; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_GRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_BAR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_COP1_VARS \
+  UINT f_pack; \
+  UINT f_CPRk; \
+  UINT f_op; \
+  UINT f_CPRi; \
+  INT f_s6_1; \
+  UINT f_CPRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_COP1_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_CPRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_s6_1 = EXTRACT_LSB0_INT (insn, 32, 11, 6); \
+  f_CPRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CLRGR_VARS \
+  UINT f_pack; \
+  UINT f_GRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_GRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_CLRGR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CLRFR_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_GRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_CLRFR_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FITOS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FITOS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FSTOI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FSTOI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FITOD_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FITOD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FDTOI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FDTOI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CFITOS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFITOS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CFSTOI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFSTOI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FMOVS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FMOVS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FMOVD_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FMOVD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CFMOVS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFMOVS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FADDS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FADDS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FADDD_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FADDD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CFADDS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFADDS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FCMPS_VARS \
+  UINT f_pack; \
+  UINT f_cond_null; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FCMPS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FCMPD_VARS \
+  UINT f_pack; \
+  UINT f_cond_null; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_FCMPD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CFCMPS_VARS \
+  UINT f_pack; \
+  UINT f_cond_null; \
+  UINT f_FCCi_2; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFCMPS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MHSETLOS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ope1; \
+  INT f_u12_h; \
+  UINT f_u12_l; \
+  INT f_u12; \
+  unsigned int length;
+#define EXTRACT_IFMT_MHSETLOS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); \
+  f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+{\
+  f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
+}\
+
+#define EXTRACT_IFMT_MHSETHIS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ope1; \
+  INT f_u12_h; \
+  UINT f_u12_l; \
+  INT f_u12; \
+  unsigned int length;
+#define EXTRACT_IFMT_MHSETHIS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); \
+  f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+{\
+  f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
+}\
+
+#define EXTRACT_IFMT_MHDSETS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ope1; \
+  INT f_u12_h; \
+  UINT f_u12_l; \
+  INT f_u12; \
+  unsigned int length;
+#define EXTRACT_IFMT_MHDSETS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6); \
+  f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+{\
+  f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
+}\
+
+#define EXTRACT_IFMT_MHSETLOH_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_ope1; \
+  UINT f_misc_null_11; \
+  INT f_s5; \
+  unsigned int length;
+#define EXTRACT_IFMT_MHSETLOH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_misc_null_11 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
+  f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); \
+
+#define EXTRACT_IFMT_MHSETHIH_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_ope1; \
+  UINT f_misc_null_11; \
+  INT f_s5; \
+  unsigned int length;
+#define EXTRACT_IFMT_MHSETHIH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_misc_null_11 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
+  f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); \
+
+#define EXTRACT_IFMT_MHDSETH_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_ope1; \
+  UINT f_misc_null_11; \
+  INT f_s5; \
+  unsigned int length;
+#define EXTRACT_IFMT_MHDSETH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_misc_null_11 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
+  f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5); \
+
+#define EXTRACT_IFMT_MAND_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MAND_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMAND_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMAND_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MNOT_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MNOT_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMNOT_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_rs_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMNOT_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MROTLI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_u6; \
+  unsigned int length;
+#define EXTRACT_IFMT_MROTLI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MCUT_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ACC40Si; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MCUT_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MCUTI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ACC40Si; \
+  UINT f_ope1; \
+  INT f_s6; \
+  unsigned int length;
+#define EXTRACT_IFMT_MCUTI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MDCUTSSI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ACC40Si; \
+  UINT f_ope1; \
+  INT f_s6; \
+  unsigned int length;
+#define EXTRACT_IFMT_MDCUTSSI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MDROTLI_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  INT f_s6; \
+  unsigned int length;
+#define EXTRACT_IFMT_MDROTLI_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MQSATHS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MQSATHS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MCMPSH_VARS \
+  UINT f_pack; \
+  UINT f_cond_null; \
+  UINT f_FCCk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MCMPSH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_cond_null = EXTRACT_LSB0_UINT (insn, 32, 30, 4); \
+  f_FCCk = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MABSHS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MABSHS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMQADDHSS_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMQADDHSS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MADDACCS_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Sk; \
+  UINT f_op; \
+  UINT f_ACC40Si; \
+  UINT f_ope1; \
+  UINT f_ACCj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MADDACCS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_ACCj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MMULHS_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Sk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MMULHS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMMULHS_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Sk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMMULHS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MQMULHS_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Sk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MQMULHS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMQMULHS_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Sk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMQMULHS_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MMACHU_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Uk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MMACHU_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMMACHU_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Uk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMMACHU_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MQMACHU_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Uk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MQMACHU_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMQMACHU_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Uk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMQMACHU_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMEXPDHW_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_u6; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMEXPDHW_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MEXPDHD_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_u6; \
+  unsigned int length;
+#define EXTRACT_IFMT_MEXPDHD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMEXPDHD_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_u6; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMEXPDHD_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MUNPACKH_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MUNPACKH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MDUNPACKH_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MDUNPACKH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MBTOH_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MBTOH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMBTOH_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMBTOH_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MHTOB_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_ope1; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_MHTOB_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMHTOB_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMHTOB_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_CMBTOHE_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_CCi; \
+  UINT f_cond; \
+  UINT f_ope4; \
+  UINT f_FRj; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMBTOHE_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3); \
+  f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1); \
+  f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+  f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MCLRACC_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Sk; \
+  UINT f_op; \
+  UINT f_A; \
+  UINT f_misc_null_10; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MCLRACC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_A = EXTRACT_LSB0_UINT (insn, 32, 17, 1); \
+  f_misc_null_10 = EXTRACT_LSB0_UINT (insn, 32, 16, 5); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MRDACC_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ACC40Si; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MRDACC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MRDACCG_VARS \
+  UINT f_pack; \
+  UINT f_FRk; \
+  UINT f_op; \
+  UINT f_ACCGi; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MRDACCG_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_ACCGi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MWTACC_VARS \
+  UINT f_pack; \
+  UINT f_ACC40Sk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MWTACC_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_MWTACCG_VARS \
+  UINT f_pack; \
+  UINT f_ACCGk; \
+  UINT f_op; \
+  UINT f_FRi; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_MWTACCG_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_ACCGk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_FNOP_VARS \
+  UINT f_pack; \
+  UINT f_rd_null; \
+  UINT f_op; \
+  UINT f_FRi_null; \
+  UINT f_ope1; \
+  UINT f_FRj_null; \
+  unsigned int length;
+#define EXTRACT_IFMT_FNOP_CODE \
+  length = 4; \
+  f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+  f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+  f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+  f_FRi_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+  f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+  f_FRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  IADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_FRVBF_H */
diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h
new file mode 100644
index 00000000000..94034399ba4
--- /dev/null
+++ b/sim/frv/cpuall.h
@@ -0,0 +1,70 @@
+/* Simulator CPU header for frv.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FRV_CPUALL_H
+#define FRV_CPUALL_H
+
+/* Include files for each cpu family.  */
+
+#ifdef WANT_CPU_FRVBF
+#include "eng.h"
+#include "cgen-engine.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const MACH frv_mach;
+extern const MACH fr500_mach;
+extern const MACH tomcat_mach;
+extern const MACH fr400_mach;
+extern const MACH simple_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
+  /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+#endif
+
+#endif /* FRV_CPUALL_H */
diff --git a/sim/frv/decode.c b/sim/frv/decode.c
new file mode 100644
index 00000000000..20cd67a37e0
--- /dev/null
+++ b/sim/frv/decode.c
@@ -0,0 +1,10891 @@
+/* Simulator instruction decoder for frvbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+   This is computed at runtime.  Space for it is not malloc'd to save a
+   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
+   but won't be done until necessary (we don't currently support the runtime
+   addition of instructions nor an SMP machine with different cpus).  */
+static IDESC frvbf_insn_data[FRVBF_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+   Some of these are conditionally compiled out.  */
+
+static const struct insn_sem frvbf_insn_sem[] =
+{
+  { VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_AFTER, FRVBF_INSN_X_AFTER, FRVBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_BEFORE, FRVBF_INSN_X_BEFORE, FRVBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_CTI_CHAIN, FRVBF_INSN_X_CTI_CHAIN, FRVBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_CHAIN, FRVBF_INSN_X_CHAIN, FRVBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_BEGIN, FRVBF_INSN_X_BEGIN, FRVBF_SFMT_EMPTY },
+  { FRV_INSN_ADD, FRVBF_INSN_ADD, FRVBF_SFMT_ADD },
+  { FRV_INSN_SUB, FRVBF_INSN_SUB, FRVBF_SFMT_ADD },
+  { FRV_INSN_AND, FRVBF_INSN_AND, FRVBF_SFMT_ADD },
+  { FRV_INSN_OR, FRVBF_INSN_OR, FRVBF_SFMT_ADD },
+  { FRV_INSN_XOR, FRVBF_INSN_XOR, FRVBF_SFMT_ADD },
+  { FRV_INSN_NOT, FRVBF_INSN_NOT, FRVBF_SFMT_NOT },
+  { FRV_INSN_SDIV, FRVBF_INSN_SDIV, FRVBF_SFMT_SDIV },
+  { FRV_INSN_NSDIV, FRVBF_INSN_NSDIV, FRVBF_SFMT_SDIV },
+  { FRV_INSN_UDIV, FRVBF_INSN_UDIV, FRVBF_SFMT_SDIV },
+  { FRV_INSN_NUDIV, FRVBF_INSN_NUDIV, FRVBF_SFMT_SDIV },
+  { FRV_INSN_SMUL, FRVBF_INSN_SMUL, FRVBF_SFMT_SMUL },
+  { FRV_INSN_UMUL, FRVBF_INSN_UMUL, FRVBF_SFMT_SMUL },
+  { FRV_INSN_SLL, FRVBF_INSN_SLL, FRVBF_SFMT_ADD },
+  { FRV_INSN_SRL, FRVBF_INSN_SRL, FRVBF_SFMT_ADD },
+  { FRV_INSN_SRA, FRVBF_INSN_SRA, FRVBF_SFMT_ADD },
+  { FRV_INSN_SCAN, FRVBF_INSN_SCAN, FRVBF_SFMT_ADD },
+  { FRV_INSN_CADD, FRVBF_INSN_CADD, FRVBF_SFMT_CADD },
+  { FRV_INSN_CSUB, FRVBF_INSN_CSUB, FRVBF_SFMT_CADD },
+  { FRV_INSN_CAND, FRVBF_INSN_CAND, FRVBF_SFMT_CADD },
+  { FRV_INSN_COR, FRVBF_INSN_COR, FRVBF_SFMT_CADD },
+  { FRV_INSN_CXOR, FRVBF_INSN_CXOR, FRVBF_SFMT_CADD },
+  { FRV_INSN_CNOT, FRVBF_INSN_CNOT, FRVBF_SFMT_CNOT },
+  { FRV_INSN_CSMUL, FRVBF_INSN_CSMUL, FRVBF_SFMT_CSMUL },
+  { FRV_INSN_CSDIV, FRVBF_INSN_CSDIV, FRVBF_SFMT_CSDIV },
+  { FRV_INSN_CUDIV, FRVBF_INSN_CUDIV, FRVBF_SFMT_CSDIV },
+  { FRV_INSN_CSLL, FRVBF_INSN_CSLL, FRVBF_SFMT_CADD },
+  { FRV_INSN_CSRL, FRVBF_INSN_CSRL, FRVBF_SFMT_CADD },
+  { FRV_INSN_CSRA, FRVBF_INSN_CSRA, FRVBF_SFMT_CADD },
+  { FRV_INSN_CSCAN, FRVBF_INSN_CSCAN, FRVBF_SFMT_CADD },
+  { FRV_INSN_ADDCC, FRVBF_INSN_ADDCC, FRVBF_SFMT_ADDCC },
+  { FRV_INSN_SUBCC, FRVBF_INSN_SUBCC, FRVBF_SFMT_ADDCC },
+  { FRV_INSN_ANDCC, FRVBF_INSN_ANDCC, FRVBF_SFMT_ANDCC },
+  { FRV_INSN_ORCC, FRVBF_INSN_ORCC, FRVBF_SFMT_ANDCC },
+  { FRV_INSN_XORCC, FRVBF_INSN_XORCC, FRVBF_SFMT_ANDCC },
+  { FRV_INSN_SLLCC, FRVBF_INSN_SLLCC, FRVBF_SFMT_ADDCC },
+  { FRV_INSN_SRLCC, FRVBF_INSN_SRLCC, FRVBF_SFMT_ADDCC },
+  { FRV_INSN_SRACC, FRVBF_INSN_SRACC, FRVBF_SFMT_ADDCC },
+  { FRV_INSN_SMULCC, FRVBF_INSN_SMULCC, FRVBF_SFMT_SMULCC },
+  { FRV_INSN_UMULCC, FRVBF_INSN_UMULCC, FRVBF_SFMT_SMULCC },
+  { FRV_INSN_CADDCC, FRVBF_INSN_CADDCC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_CSUBCC, FRVBF_INSN_CSUBCC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_CSMULCC, FRVBF_INSN_CSMULCC, FRVBF_SFMT_CSMULCC },
+  { FRV_INSN_CANDCC, FRVBF_INSN_CANDCC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_CORCC, FRVBF_INSN_CORCC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_CXORCC, FRVBF_INSN_CXORCC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_CSLLCC, FRVBF_INSN_CSLLCC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_CSRLCC, FRVBF_INSN_CSRLCC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_CSRACC, FRVBF_INSN_CSRACC, FRVBF_SFMT_CADDCC },
+  { FRV_INSN_ADDX, FRVBF_INSN_ADDX, FRVBF_SFMT_ADDX },
+  { FRV_INSN_SUBX, FRVBF_INSN_SUBX, FRVBF_SFMT_ADDX },
+  { FRV_INSN_ADDXCC, FRVBF_INSN_ADDXCC, FRVBF_SFMT_ADDCC },
+  { FRV_INSN_SUBXCC, FRVBF_INSN_SUBXCC, FRVBF_SFMT_ADDCC },
+  { FRV_INSN_ADDI, FRVBF_INSN_ADDI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_SUBI, FRVBF_INSN_SUBI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_ANDI, FRVBF_INSN_ANDI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_ORI, FRVBF_INSN_ORI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_XORI, FRVBF_INSN_XORI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_SDIVI, FRVBF_INSN_SDIVI, FRVBF_SFMT_SDIVI },
+  { FRV_INSN_NSDIVI, FRVBF_INSN_NSDIVI, FRVBF_SFMT_SDIVI },
+  { FRV_INSN_UDIVI, FRVBF_INSN_UDIVI, FRVBF_SFMT_SDIVI },
+  { FRV_INSN_NUDIVI, FRVBF_INSN_NUDIVI, FRVBF_SFMT_SDIVI },
+  { FRV_INSN_SMULI, FRVBF_INSN_SMULI, FRVBF_SFMT_SMULI },
+  { FRV_INSN_UMULI, FRVBF_INSN_UMULI, FRVBF_SFMT_SMULI },
+  { FRV_INSN_SLLI, FRVBF_INSN_SLLI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_SRLI, FRVBF_INSN_SRLI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_SRAI, FRVBF_INSN_SRAI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_SCANI, FRVBF_INSN_SCANI, FRVBF_SFMT_ADDI },
+  { FRV_INSN_ADDICC, FRVBF_INSN_ADDICC, FRVBF_SFMT_ADDICC },
+  { FRV_INSN_SUBICC, FRVBF_INSN_SUBICC, FRVBF_SFMT_ADDICC },
+  { FRV_INSN_ANDICC, FRVBF_INSN_ANDICC, FRVBF_SFMT_ANDICC },
+  { FRV_INSN_ORICC, FRVBF_INSN_ORICC, FRVBF_SFMT_ANDICC },
+  { FRV_INSN_XORICC, FRVBF_INSN_XORICC, FRVBF_SFMT_ANDICC },
+  { FRV_INSN_SMULICC, FRVBF_INSN_SMULICC, FRVBF_SFMT_SMULICC },
+  { FRV_INSN_UMULICC, FRVBF_INSN_UMULICC, FRVBF_SFMT_SMULICC },
+  { FRV_INSN_SLLICC, FRVBF_INSN_SLLICC, FRVBF_SFMT_ADDICC },
+  { FRV_INSN_SRLICC, FRVBF_INSN_SRLICC, FRVBF_SFMT_ADDICC },
+  { FRV_INSN_SRAICC, FRVBF_INSN_SRAICC, FRVBF_SFMT_ADDICC },
+  { FRV_INSN_ADDXI, FRVBF_INSN_ADDXI, FRVBF_SFMT_ADDXI },
+  { FRV_INSN_SUBXI, FRVBF_INSN_SUBXI, FRVBF_SFMT_ADDXI },
+  { FRV_INSN_ADDXICC, FRVBF_INSN_ADDXICC, FRVBF_SFMT_ADDICC },
+  { FRV_INSN_SUBXICC, FRVBF_INSN_SUBXICC, FRVBF_SFMT_ADDICC },
+  { FRV_INSN_CMPB, FRVBF_INSN_CMPB, FRVBF_SFMT_CMPB },
+  { FRV_INSN_CMPBA, FRVBF_INSN_CMPBA, FRVBF_SFMT_CMPB },
+  { FRV_INSN_SETLO, FRVBF_INSN_SETLO, FRVBF_SFMT_SETLO },
+  { FRV_INSN_SETHI, FRVBF_INSN_SETHI, FRVBF_SFMT_SETHI },
+  { FRV_INSN_SETLOS, FRVBF_INSN_SETLOS, FRVBF_SFMT_SETLOS },
+  { FRV_INSN_LDSB, FRVBF_INSN_LDSB, FRVBF_SFMT_LDSB },
+  { FRV_INSN_LDUB, FRVBF_INSN_LDUB, FRVBF_SFMT_LDSB },
+  { FRV_INSN_LDSH, FRVBF_INSN_LDSH, FRVBF_SFMT_LDSB },
+  { FRV_INSN_LDUH, FRVBF_INSN_LDUH, FRVBF_SFMT_LDSB },
+  { FRV_INSN_LD, FRVBF_INSN_LD, FRVBF_SFMT_LDSB },
+  { FRV_INSN_LDBF, FRVBF_INSN_LDBF, FRVBF_SFMT_LDBF },
+  { FRV_INSN_LDHF, FRVBF_INSN_LDHF, FRVBF_SFMT_LDBF },
+  { FRV_INSN_LDF, FRVBF_INSN_LDF, FRVBF_SFMT_LDBF },
+  { FRV_INSN_LDC, FRVBF_INSN_LDC, FRVBF_SFMT_LDC },
+  { FRV_INSN_NLDSB, FRVBF_INSN_NLDSB, FRVBF_SFMT_NLDSB },
+  { FRV_INSN_NLDUB, FRVBF_INSN_NLDUB, FRVBF_SFMT_NLDSB },
+  { FRV_INSN_NLDSH, FRVBF_INSN_NLDSH, FRVBF_SFMT_NLDSB },
+  { FRV_INSN_NLDUH, FRVBF_INSN_NLDUH, FRVBF_SFMT_NLDSB },
+  { FRV_INSN_NLD, FRVBF_INSN_NLD, FRVBF_SFMT_NLDSB },
+  { FRV_INSN_NLDBF, FRVBF_INSN_NLDBF, FRVBF_SFMT_NLDBF },
+  { FRV_INSN_NLDHF, FRVBF_INSN_NLDHF, FRVBF_SFMT_NLDBF },
+  { FRV_INSN_NLDF, FRVBF_INSN_NLDF, FRVBF_SFMT_NLDBF },
+  { FRV_INSN_LDD, FRVBF_INSN_LDD, FRVBF_SFMT_LDD },
+  { FRV_INSN_LDDF, FRVBF_INSN_LDDF, FRVBF_SFMT_LDDF },
+  { FRV_INSN_LDDC, FRVBF_INSN_LDDC, FRVBF_SFMT_LDDC },
+  { FRV_INSN_NLDD, FRVBF_INSN_NLDD, FRVBF_SFMT_NLDD },
+  { FRV_INSN_NLDDF, FRVBF_INSN_NLDDF, FRVBF_SFMT_NLDDF },
+  { FRV_INSN_LDQ, FRVBF_INSN_LDQ, FRVBF_SFMT_LDQ },
+  { FRV_INSN_LDQF, FRVBF_INSN_LDQF, FRVBF_SFMT_LDQF },
+  { FRV_INSN_LDQC, FRVBF_INSN_LDQC, FRVBF_SFMT_LDQC },
+  { FRV_INSN_NLDQ, FRVBF_INSN_NLDQ, FRVBF_SFMT_NLDQ },
+  { FRV_INSN_NLDQF, FRVBF_INSN_NLDQF, FRVBF_SFMT_NLDQF },
+  { FRV_INSN_LDSBU, FRVBF_INSN_LDSBU, FRVBF_SFMT_LDSBU },
+  { FRV_INSN_LDUBU, FRVBF_INSN_LDUBU, FRVBF_SFMT_LDSBU },
+  { FRV_INSN_LDSHU, FRVBF_INSN_LDSHU, FRVBF_SFMT_LDSBU },
+  { FRV_INSN_LDUHU, FRVBF_INSN_LDUHU, FRVBF_SFMT_LDSBU },
+  { FRV_INSN_LDU, FRVBF_INSN_LDU, FRVBF_SFMT_LDSBU },
+  { FRV_INSN_NLDSBU, FRVBF_INSN_NLDSBU, FRVBF_SFMT_NLDSBU },
+  { FRV_INSN_NLDUBU, FRVBF_INSN_NLDUBU, FRVBF_SFMT_NLDSBU },
+  { FRV_INSN_NLDSHU, FRVBF_INSN_NLDSHU, FRVBF_SFMT_NLDSBU },
+  { FRV_INSN_NLDUHU, FRVBF_INSN_NLDUHU, FRVBF_SFMT_NLDSBU },
+  { FRV_INSN_NLDU, FRVBF_INSN_NLDU, FRVBF_SFMT_NLDSBU },
+  { FRV_INSN_LDBFU, FRVBF_INSN_LDBFU, FRVBF_SFMT_LDBFU },
+  { FRV_INSN_LDHFU, FRVBF_INSN_LDHFU, FRVBF_SFMT_LDBFU },
+  { FRV_INSN_LDFU, FRVBF_INSN_LDFU, FRVBF_SFMT_LDBFU },
+  { FRV_INSN_LDCU, FRVBF_INSN_LDCU, FRVBF_SFMT_LDCU },
+  { FRV_INSN_NLDBFU, FRVBF_INSN_NLDBFU, FRVBF_SFMT_NLDBFU },
+  { FRV_INSN_NLDHFU, FRVBF_INSN_NLDHFU, FRVBF_SFMT_NLDBFU },
+  { FRV_INSN_NLDFU, FRVBF_INSN_NLDFU, FRVBF_SFMT_NLDBFU },
+  { FRV_INSN_LDDU, FRVBF_INSN_LDDU, FRVBF_SFMT_LDDU },
+  { FRV_INSN_NLDDU, FRVBF_INSN_NLDDU, FRVBF_SFMT_NLDDU },
+  { FRV_INSN_LDDFU, FRVBF_INSN_LDDFU, FRVBF_SFMT_LDDFU },
+  { FRV_INSN_LDDCU, FRVBF_INSN_LDDCU, FRVBF_SFMT_LDDCU },
+  { FRV_INSN_NLDDFU, FRVBF_INSN_NLDDFU, FRVBF_SFMT_NLDDFU },
+  { FRV_INSN_LDQU, FRVBF_INSN_LDQU, FRVBF_SFMT_LDQU },
+  { FRV_INSN_NLDQU, FRVBF_INSN_NLDQU, FRVBF_SFMT_NLDQU },
+  { FRV_INSN_LDQFU, FRVBF_INSN_LDQFU, FRVBF_SFMT_LDQFU },
+  { FRV_INSN_LDQCU, FRVBF_INSN_LDQCU, FRVBF_SFMT_LDQCU },
+  { FRV_INSN_NLDQFU, FRVBF_INSN_NLDQFU, FRVBF_SFMT_NLDQFU },
+  { FRV_INSN_LDSBI, FRVBF_INSN_LDSBI, FRVBF_SFMT_LDSBI },
+  { FRV_INSN_LDSHI, FRVBF_INSN_LDSHI, FRVBF_SFMT_LDSBI },
+  { FRV_INSN_LDI, FRVBF_INSN_LDI, FRVBF_SFMT_LDSBI },
+  { FRV_INSN_LDUBI, FRVBF_INSN_LDUBI, FRVBF_SFMT_LDSBI },
+  { FRV_INSN_LDUHI, FRVBF_INSN_LDUHI, FRVBF_SFMT_LDSBI },
+  { FRV_INSN_LDBFI, FRVBF_INSN_LDBFI, FRVBF_SFMT_LDBFI },
+  { FRV_INSN_LDHFI, FRVBF_INSN_LDHFI, FRVBF_SFMT_LDBFI },
+  { FRV_INSN_LDFI, FRVBF_INSN_LDFI, FRVBF_SFMT_LDBFI },
+  { FRV_INSN_NLDSBI, FRVBF_INSN_NLDSBI, FRVBF_SFMT_NLDSBI },
+  { FRV_INSN_NLDUBI, FRVBF_INSN_NLDUBI, FRVBF_SFMT_NLDSBI },
+  { FRV_INSN_NLDSHI, FRVBF_INSN_NLDSHI, FRVBF_SFMT_NLDSBI },
+  { FRV_INSN_NLDUHI, FRVBF_INSN_NLDUHI, FRVBF_SFMT_NLDSBI },
+  { FRV_INSN_NLDI, FRVBF_INSN_NLDI, FRVBF_SFMT_NLDSBI },
+  { FRV_INSN_NLDBFI, FRVBF_INSN_NLDBFI, FRVBF_SFMT_NLDBFI },
+  { FRV_INSN_NLDHFI, FRVBF_INSN_NLDHFI, FRVBF_SFMT_NLDBFI },
+  { FRV_INSN_NLDFI, FRVBF_INSN_NLDFI, FRVBF_SFMT_NLDBFI },
+  { FRV_INSN_LDDI, FRVBF_INSN_LDDI, FRVBF_SFMT_LDDI },
+  { FRV_INSN_LDDFI, FRVBF_INSN_LDDFI, FRVBF_SFMT_LDDFI },
+  { FRV_INSN_NLDDI, FRVBF_INSN_NLDDI, FRVBF_SFMT_NLDDI },
+  { FRV_INSN_NLDDFI, FRVBF_INSN_NLDDFI, FRVBF_SFMT_NLDDFI },
+  { FRV_INSN_LDQI, FRVBF_INSN_LDQI, FRVBF_SFMT_LDQI },
+  { FRV_INSN_LDQFI, FRVBF_INSN_LDQFI, FRVBF_SFMT_LDQFI },
+  { FRV_INSN_NLDQI, FRVBF_INSN_NLDQI, FRVBF_SFMT_NLDQI },
+  { FRV_INSN_NLDQFI, FRVBF_INSN_NLDQFI, FRVBF_SFMT_NLDQFI },
+  { FRV_INSN_STB, FRVBF_INSN_STB, FRVBF_SFMT_STB },
+  { FRV_INSN_STH, FRVBF_INSN_STH, FRVBF_SFMT_STB },
+  { FRV_INSN_ST, FRVBF_INSN_ST, FRVBF_SFMT_STB },
+  { FRV_INSN_STBF, FRVBF_INSN_STBF, FRVBF_SFMT_STBF },
+  { FRV_INSN_STHF, FRVBF_INSN_STHF, FRVBF_SFMT_STBF },
+  { FRV_INSN_STF, FRVBF_INSN_STF, FRVBF_SFMT_STBF },
+  { FRV_INSN_STC, FRVBF_INSN_STC, FRVBF_SFMT_STC },
+  { FRV_INSN_RSTB, FRVBF_INSN_RSTB, FRVBF_SFMT_RSTB },
+  { FRV_INSN_RSTH, FRVBF_INSN_RSTH, FRVBF_SFMT_RSTB },
+  { FRV_INSN_RST, FRVBF_INSN_RST, FRVBF_SFMT_RSTB },
+  { FRV_INSN_RSTBF, FRVBF_INSN_RSTBF, FRVBF_SFMT_RSTBF },
+  { FRV_INSN_RSTHF, FRVBF_INSN_RSTHF, FRVBF_SFMT_RSTBF },
+  { FRV_INSN_RSTF, FRVBF_INSN_RSTF, FRVBF_SFMT_RSTBF },
+  { FRV_INSN_STD, FRVBF_INSN_STD, FRVBF_SFMT_STD },
+  { FRV_INSN_STDF, FRVBF_INSN_STDF, FRVBF_SFMT_STDF },
+  { FRV_INSN_STDC, FRVBF_INSN_STDC, FRVBF_SFMT_STDC },
+  { FRV_INSN_RSTD, FRVBF_INSN_RSTD, FRVBF_SFMT_RSTD },
+  { FRV_INSN_RSTDF, FRVBF_INSN_RSTDF, FRVBF_SFMT_RSTDF },
+  { FRV_INSN_STQ, FRVBF_INSN_STQ, FRVBF_SFMT_LDQ },
+  { FRV_INSN_STQF, FRVBF_INSN_STQF, FRVBF_SFMT_LDQF },
+  { FRV_INSN_STQC, FRVBF_INSN_STQC, FRVBF_SFMT_LDQC },
+  { FRV_INSN_RSTQ, FRVBF_INSN_RSTQ, FRVBF_SFMT_LDQ },
+  { FRV_INSN_RSTQF, FRVBF_INSN_RSTQF, FRVBF_SFMT_LDQF },
+  { FRV_INSN_STBU, FRVBF_INSN_STBU, FRVBF_SFMT_STBU },
+  { FRV_INSN_STHU, FRVBF_INSN_STHU, FRVBF_SFMT_STBU },
+  { FRV_INSN_STU, FRVBF_INSN_STU, FRVBF_SFMT_STBU },
+  { FRV_INSN_STBFU, FRVBF_INSN_STBFU, FRVBF_SFMT_STBFU },
+  { FRV_INSN_STHFU, FRVBF_INSN_STHFU, FRVBF_SFMT_STBFU },
+  { FRV_INSN_STFU, FRVBF_INSN_STFU, FRVBF_SFMT_STBFU },
+  { FRV_INSN_STCU, FRVBF_INSN_STCU, FRVBF_SFMT_STCU },
+  { FRV_INSN_STDU, FRVBF_INSN_STDU, FRVBF_SFMT_STDU },
+  { FRV_INSN_STDFU, FRVBF_INSN_STDFU, FRVBF_SFMT_STDFU },
+  { FRV_INSN_STDCU, FRVBF_INSN_STDCU, FRVBF_SFMT_STDCU },
+  { FRV_INSN_STQU, FRVBF_INSN_STQU, FRVBF_SFMT_STQU },
+  { FRV_INSN_STQFU, FRVBF_INSN_STQFU, FRVBF_SFMT_LDQFU },
+  { FRV_INSN_STQCU, FRVBF_INSN_STQCU, FRVBF_SFMT_LDQCU },
+  { FRV_INSN_CLDSB, FRVBF_INSN_CLDSB, FRVBF_SFMT_CLDSB },
+  { FRV_INSN_CLDUB, FRVBF_INSN_CLDUB, FRVBF_SFMT_CLDSB },
+  { FRV_INSN_CLDSH, FRVBF_INSN_CLDSH, FRVBF_SFMT_CLDSB },
+  { FRV_INSN_CLDUH, FRVBF_INSN_CLDUH, FRVBF_SFMT_CLDSB },
+  { FRV_INSN_CLD, FRVBF_INSN_CLD, FRVBF_SFMT_CLDSB },
+  { FRV_INSN_CLDBF, FRVBF_INSN_CLDBF, FRVBF_SFMT_CLDBF },
+  { FRV_INSN_CLDHF, FRVBF_INSN_CLDHF, FRVBF_SFMT_CLDBF },
+  { FRV_INSN_CLDF, FRVBF_INSN_CLDF, FRVBF_SFMT_CLDBF },
+  { FRV_INSN_CLDD, FRVBF_INSN_CLDD, FRVBF_SFMT_CLDD },
+  { FRV_INSN_CLDDF, FRVBF_INSN_CLDDF, FRVBF_SFMT_CLDDF },
+  { FRV_INSN_CLDQ, FRVBF_INSN_CLDQ, FRVBF_SFMT_CLDQ },
+  { FRV_INSN_CLDSBU, FRVBF_INSN_CLDSBU, FRVBF_SFMT_CLDSBU },
+  { FRV_INSN_CLDUBU, FRVBF_INSN_CLDUBU, FRVBF_SFMT_CLDSBU },
+  { FRV_INSN_CLDSHU, FRVBF_INSN_CLDSHU, FRVBF_SFMT_CLDSBU },
+  { FRV_INSN_CLDUHU, FRVBF_INSN_CLDUHU, FRVBF_SFMT_CLDSBU },
+  { FRV_INSN_CLDU, FRVBF_INSN_CLDU, FRVBF_SFMT_CLDSBU },
+  { FRV_INSN_CLDBFU, FRVBF_INSN_CLDBFU, FRVBF_SFMT_CLDBFU },
+  { FRV_INSN_CLDHFU, FRVBF_INSN_CLDHFU, FRVBF_SFMT_CLDBFU },
+  { FRV_INSN_CLDFU, FRVBF_INSN_CLDFU, FRVBF_SFMT_CLDBFU },
+  { FRV_INSN_CLDDU, FRVBF_INSN_CLDDU, FRVBF_SFMT_CLDDU },
+  { FRV_INSN_CLDDFU, FRVBF_INSN_CLDDFU, FRVBF_SFMT_CLDDFU },
+  { FRV_INSN_CLDQU, FRVBF_INSN_CLDQU, FRVBF_SFMT_CLDQU },
+  { FRV_INSN_CSTB, FRVBF_INSN_CSTB, FRVBF_SFMT_CSTB },
+  { FRV_INSN_CSTH, FRVBF_INSN_CSTH, FRVBF_SFMT_CSTB },
+  { FRV_INSN_CST, FRVBF_INSN_CST, FRVBF_SFMT_CSTB },
+  { FRV_INSN_CSTBF, FRVBF_INSN_CSTBF, FRVBF_SFMT_CSTBF },
+  { FRV_INSN_CSTHF, FRVBF_INSN_CSTHF, FRVBF_SFMT_CSTBF },
+  { FRV_INSN_CSTF, FRVBF_INSN_CSTF, FRVBF_SFMT_CSTBF },
+  { FRV_INSN_CSTD, FRVBF_INSN_CSTD, FRVBF_SFMT_CSTD },
+  { FRV_INSN_CSTDF, FRVBF_INSN_CSTDF, FRVBF_SFMT_CSTDF },
+  { FRV_INSN_CSTQ, FRVBF_INSN_CSTQ, FRVBF_SFMT_CLDQ },
+  { FRV_INSN_CSTBU, FRVBF_INSN_CSTBU, FRVBF_SFMT_CSTBU },
+  { FRV_INSN_CSTHU, FRVBF_INSN_CSTHU, FRVBF_SFMT_CSTBU },
+  { FRV_INSN_CSTU, FRVBF_INSN_CSTU, FRVBF_SFMT_CSTBU },
+  { FRV_INSN_CSTBFU, FRVBF_INSN_CSTBFU, FRVBF_SFMT_CSTBFU },
+  { FRV_INSN_CSTHFU, FRVBF_INSN_CSTHFU, FRVBF_SFMT_CSTBFU },
+  { FRV_INSN_CSTFU, FRVBF_INSN_CSTFU, FRVBF_SFMT_CSTBFU },
+  { FRV_INSN_CSTDU, FRVBF_INSN_CSTDU, FRVBF_SFMT_CSTDU },
+  { FRV_INSN_CSTDFU, FRVBF_INSN_CSTDFU, FRVBF_SFMT_CSTDFU },
+  { FRV_INSN_STBI, FRVBF_INSN_STBI, FRVBF_SFMT_STBI },
+  { FRV_INSN_STHI, FRVBF_INSN_STHI, FRVBF_SFMT_STBI },
+  { FRV_INSN_STI, FRVBF_INSN_STI, FRVBF_SFMT_STBI },
+  { FRV_INSN_STBFI, FRVBF_INSN_STBFI, FRVBF_SFMT_STBFI },
+  { FRV_INSN_STHFI, FRVBF_INSN_STHFI, FRVBF_SFMT_STBFI },
+  { FRV_INSN_STFI, FRVBF_INSN_STFI, FRVBF_SFMT_STBFI },
+  { FRV_INSN_STDI, FRVBF_INSN_STDI, FRVBF_SFMT_STDI },
+  { FRV_INSN_STDFI, FRVBF_INSN_STDFI, FRVBF_SFMT_STDFI },
+  { FRV_INSN_STQI, FRVBF_INSN_STQI, FRVBF_SFMT_LDQI },
+  { FRV_INSN_STQFI, FRVBF_INSN_STQFI, FRVBF_SFMT_LDQFI },
+  { FRV_INSN_SWAP, FRVBF_INSN_SWAP, FRVBF_SFMT_SWAP },
+  { FRV_INSN_SWAPI, FRVBF_INSN_SWAPI, FRVBF_SFMT_SWAPI },
+  { FRV_INSN_CSWAP, FRVBF_INSN_CSWAP, FRVBF_SFMT_CSWAP },
+  { FRV_INSN_MOVGF, FRVBF_INSN_MOVGF, FRVBF_SFMT_MOVGF },
+  { FRV_INSN_MOVFG, FRVBF_INSN_MOVFG, FRVBF_SFMT_MOVFG },
+  { FRV_INSN_MOVGFD, FRVBF_INSN_MOVGFD, FRVBF_SFMT_MOVGFD },
+  { FRV_INSN_MOVFGD, FRVBF_INSN_MOVFGD, FRVBF_SFMT_MOVFGD },
+  { FRV_INSN_MOVGFQ, FRVBF_INSN_MOVGFQ, FRVBF_SFMT_MOVGFQ },
+  { FRV_INSN_MOVFGQ, FRVBF_INSN_MOVFGQ, FRVBF_SFMT_MOVFGQ },
+  { FRV_INSN_CMOVGF, FRVBF_INSN_CMOVGF, FRVBF_SFMT_CMOVGF },
+  { FRV_INSN_CMOVFG, FRVBF_INSN_CMOVFG, FRVBF_SFMT_CMOVFG },
+  { FRV_INSN_CMOVGFD, FRVBF_INSN_CMOVGFD, FRVBF_SFMT_CMOVGFD },
+  { FRV_INSN_CMOVFGD, FRVBF_INSN_CMOVFGD, FRVBF_SFMT_CMOVFGD },
+  { FRV_INSN_MOVGS, FRVBF_INSN_MOVGS, FRVBF_SFMT_MOVGS },
+  { FRV_INSN_MOVSG, FRVBF_INSN_MOVSG, FRVBF_SFMT_MOVSG },
+  { FRV_INSN_BRA, FRVBF_INSN_BRA, FRVBF_SFMT_BRA },
+  { FRV_INSN_BNO, FRVBF_INSN_BNO, FRVBF_SFMT_BNO },
+  { FRV_INSN_BEQ, FRVBF_INSN_BEQ, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BNE, FRVBF_INSN_BNE, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BLE, FRVBF_INSN_BLE, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BGT, FRVBF_INSN_BGT, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BLT, FRVBF_INSN_BLT, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BGE, FRVBF_INSN_BGE, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BLS, FRVBF_INSN_BLS, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BHI, FRVBF_INSN_BHI, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BC, FRVBF_INSN_BC, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BNC, FRVBF_INSN_BNC, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BN, FRVBF_INSN_BN, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BP, FRVBF_INSN_BP, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BV, FRVBF_INSN_BV, FRVBF_SFMT_BEQ },
+  { FRV_INSN_BNV, FRVBF_INSN_BNV, FRVBF_SFMT_BEQ },
+  { FRV_INSN_FBRA, FRVBF_INSN_FBRA, FRVBF_SFMT_BRA },
+  { FRV_INSN_FBNO, FRVBF_INSN_FBNO, FRVBF_SFMT_BNO },
+  { FRV_INSN_FBNE, FRVBF_INSN_FBNE, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBEQ, FRVBF_INSN_FBEQ, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBLG, FRVBF_INSN_FBLG, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBUE, FRVBF_INSN_FBUE, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBUL, FRVBF_INSN_FBUL, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBGE, FRVBF_INSN_FBGE, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBLT, FRVBF_INSN_FBLT, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBUGE, FRVBF_INSN_FBUGE, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBUG, FRVBF_INSN_FBUG, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBLE, FRVBF_INSN_FBLE, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBGT, FRVBF_INSN_FBGT, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBULE, FRVBF_INSN_FBULE, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBU, FRVBF_INSN_FBU, FRVBF_SFMT_FBNE },
+  { FRV_INSN_FBO, FRVBF_INSN_FBO, FRVBF_SFMT_FBNE },
+  { FRV_INSN_BCTRLR, FRVBF_INSN_BCTRLR, FRVBF_SFMT_BCTRLR },
+  { FRV_INSN_BRALR, FRVBF_INSN_BRALR, FRVBF_SFMT_BRALR },
+  { FRV_INSN_BNOLR, FRVBF_INSN_BNOLR, FRVBF_SFMT_BNOLR },
+  { FRV_INSN_BEQLR, FRVBF_INSN_BEQLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BNELR, FRVBF_INSN_BNELR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BLELR, FRVBF_INSN_BLELR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BGTLR, FRVBF_INSN_BGTLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BLTLR, FRVBF_INSN_BLTLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BGELR, FRVBF_INSN_BGELR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BLSLR, FRVBF_INSN_BLSLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BHILR, FRVBF_INSN_BHILR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BCLR, FRVBF_INSN_BCLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BNCLR, FRVBF_INSN_BNCLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BNLR, FRVBF_INSN_BNLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BPLR, FRVBF_INSN_BPLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BVLR, FRVBF_INSN_BVLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_BNVLR, FRVBF_INSN_BNVLR, FRVBF_SFMT_BEQLR },
+  { FRV_INSN_FBRALR, FRVBF_INSN_FBRALR, FRVBF_SFMT_BRALR },
+  { FRV_INSN_FBNOLR, FRVBF_INSN_FBNOLR, FRVBF_SFMT_BNOLR },
+  { FRV_INSN_FBEQLR, FRVBF_INSN_FBEQLR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBNELR, FRVBF_INSN_FBNELR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBLGLR, FRVBF_INSN_FBLGLR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBUELR, FRVBF_INSN_FBUELR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBULLR, FRVBF_INSN_FBULLR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBGELR, FRVBF_INSN_FBGELR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBLTLR, FRVBF_INSN_FBLTLR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBUGELR, FRVBF_INSN_FBUGELR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBUGLR, FRVBF_INSN_FBUGLR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBLELR, FRVBF_INSN_FBLELR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBGTLR, FRVBF_INSN_FBGTLR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBULELR, FRVBF_INSN_FBULELR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBULR, FRVBF_INSN_FBULR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_FBOLR, FRVBF_INSN_FBOLR, FRVBF_SFMT_FBEQLR },
+  { FRV_INSN_BCRALR, FRVBF_INSN_BCRALR, FRVBF_SFMT_BCRALR },
+  { FRV_INSN_BCNOLR, FRVBF_INSN_BCNOLR, FRVBF_SFMT_BCNOLR },
+  { FRV_INSN_BCEQLR, FRVBF_INSN_BCEQLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCNELR, FRVBF_INSN_BCNELR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCLELR, FRVBF_INSN_BCLELR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCGTLR, FRVBF_INSN_BCGTLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCLTLR, FRVBF_INSN_BCLTLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCGELR, FRVBF_INSN_BCGELR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCLSLR, FRVBF_INSN_BCLSLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCHILR, FRVBF_INSN_BCHILR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCCLR, FRVBF_INSN_BCCLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCNCLR, FRVBF_INSN_BCNCLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCNLR, FRVBF_INSN_BCNLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCPLR, FRVBF_INSN_BCPLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCVLR, FRVBF_INSN_BCVLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_BCNVLR, FRVBF_INSN_BCNVLR, FRVBF_SFMT_BCEQLR },
+  { FRV_INSN_FCBRALR, FRVBF_INSN_FCBRALR, FRVBF_SFMT_BCRALR },
+  { FRV_INSN_FCBNOLR, FRVBF_INSN_FCBNOLR, FRVBF_SFMT_BCNOLR },
+  { FRV_INSN_FCBEQLR, FRVBF_INSN_FCBEQLR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBNELR, FRVBF_INSN_FCBNELR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBLGLR, FRVBF_INSN_FCBLGLR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBUELR, FRVBF_INSN_FCBUELR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBULLR, FRVBF_INSN_FCBULLR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBGELR, FRVBF_INSN_FCBGELR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBLTLR, FRVBF_INSN_FCBLTLR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBUGELR, FRVBF_INSN_FCBUGELR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBUGLR, FRVBF_INSN_FCBUGLR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBLELR, FRVBF_INSN_FCBLELR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBGTLR, FRVBF_INSN_FCBGTLR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBULELR, FRVBF_INSN_FCBULELR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBULR, FRVBF_INSN_FCBULR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_FCBOLR, FRVBF_INSN_FCBOLR, FRVBF_SFMT_FCBEQLR },
+  { FRV_INSN_JMPL, FRVBF_INSN_JMPL, FRVBF_SFMT_JMPL },
+  { FRV_INSN_CALLL, FRVBF_INSN_CALLL, FRVBF_SFMT_JMPL },
+  { FRV_INSN_JMPIL, FRVBF_INSN_JMPIL, FRVBF_SFMT_JMPIL },
+  { FRV_INSN_CALLIL, FRVBF_INSN_CALLIL, FRVBF_SFMT_JMPIL },
+  { FRV_INSN_CALL, FRVBF_INSN_CALL, FRVBF_SFMT_CALL },
+  { FRV_INSN_RETT, FRVBF_INSN_RETT, FRVBF_SFMT_RETT },
+  { FRV_INSN_REI, FRVBF_INSN_REI, FRVBF_SFMT_REI },
+  { FRV_INSN_TRA, FRVBF_INSN_TRA, FRVBF_SFMT_TRA },
+  { FRV_INSN_TNO, FRVBF_INSN_TNO, FRVBF_SFMT_REI },
+  { FRV_INSN_TEQ, FRVBF_INSN_TEQ, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TNE, FRVBF_INSN_TNE, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TLE, FRVBF_INSN_TLE, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TGT, FRVBF_INSN_TGT, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TLT, FRVBF_INSN_TLT, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TGE, FRVBF_INSN_TGE, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TLS, FRVBF_INSN_TLS, FRVBF_SFMT_TEQ },
+  { FRV_INSN_THI, FRVBF_INSN_THI, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TC, FRVBF_INSN_TC, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TNC, FRVBF_INSN_TNC, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TN, FRVBF_INSN_TN, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TP, FRVBF_INSN_TP, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TV, FRVBF_INSN_TV, FRVBF_SFMT_TEQ },
+  { FRV_INSN_TNV, FRVBF_INSN_TNV, FRVBF_SFMT_TEQ },
+  { FRV_INSN_FTRA, FRVBF_INSN_FTRA, FRVBF_SFMT_TRA },
+  { FRV_INSN_FTNO, FRVBF_INSN_FTNO, FRVBF_SFMT_REI },
+  { FRV_INSN_FTNE, FRVBF_INSN_FTNE, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTEQ, FRVBF_INSN_FTEQ, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTLG, FRVBF_INSN_FTLG, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTUE, FRVBF_INSN_FTUE, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTUL, FRVBF_INSN_FTUL, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTGE, FRVBF_INSN_FTGE, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTLT, FRVBF_INSN_FTLT, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTUGE, FRVBF_INSN_FTUGE, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTUG, FRVBF_INSN_FTUG, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTLE, FRVBF_INSN_FTLE, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTGT, FRVBF_INSN_FTGT, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTULE, FRVBF_INSN_FTULE, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTU, FRVBF_INSN_FTU, FRVBF_SFMT_FTNE },
+  { FRV_INSN_FTO, FRVBF_INSN_FTO, FRVBF_SFMT_FTNE },
+  { FRV_INSN_TIRA, FRVBF_INSN_TIRA, FRVBF_SFMT_TIRA },
+  { FRV_INSN_TINO, FRVBF_INSN_TINO, FRVBF_SFMT_REI },
+  { FRV_INSN_TIEQ, FRVBF_INSN_TIEQ, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TINE, FRVBF_INSN_TINE, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TILE, FRVBF_INSN_TILE, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TIGT, FRVBF_INSN_TIGT, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TILT, FRVBF_INSN_TILT, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TIGE, FRVBF_INSN_TIGE, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TILS, FRVBF_INSN_TILS, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TIHI, FRVBF_INSN_TIHI, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TIC, FRVBF_INSN_TIC, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TINC, FRVBF_INSN_TINC, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TIN, FRVBF_INSN_TIN, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TIP, FRVBF_INSN_TIP, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TIV, FRVBF_INSN_TIV, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_TINV, FRVBF_INSN_TINV, FRVBF_SFMT_TIEQ },
+  { FRV_INSN_FTIRA, FRVBF_INSN_FTIRA, FRVBF_SFMT_TIRA },
+  { FRV_INSN_FTINO, FRVBF_INSN_FTINO, FRVBF_SFMT_REI },
+  { FRV_INSN_FTINE, FRVBF_INSN_FTINE, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIEQ, FRVBF_INSN_FTIEQ, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTILG, FRVBF_INSN_FTILG, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIUE, FRVBF_INSN_FTIUE, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIUL, FRVBF_INSN_FTIUL, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIGE, FRVBF_INSN_FTIGE, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTILT, FRVBF_INSN_FTILT, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIUGE, FRVBF_INSN_FTIUGE, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIUG, FRVBF_INSN_FTIUG, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTILE, FRVBF_INSN_FTILE, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIGT, FRVBF_INSN_FTIGT, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIULE, FRVBF_INSN_FTIULE, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIU, FRVBF_INSN_FTIU, FRVBF_SFMT_FTINE },
+  { FRV_INSN_FTIO, FRVBF_INSN_FTIO, FRVBF_SFMT_FTINE },
+  { FRV_INSN_BREAK, FRVBF_INSN_BREAK, FRVBF_SFMT_BREAK },
+  { FRV_INSN_MTRAP, FRVBF_INSN_MTRAP, FRVBF_SFMT_REI },
+  { FRV_INSN_ANDCR, FRVBF_INSN_ANDCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_ORCR, FRVBF_INSN_ORCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_XORCR, FRVBF_INSN_XORCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_NANDCR, FRVBF_INSN_NANDCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_NORCR, FRVBF_INSN_NORCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_ANDNCR, FRVBF_INSN_ANDNCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_ORNCR, FRVBF_INSN_ORNCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_NANDNCR, FRVBF_INSN_NANDNCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_NORNCR, FRVBF_INSN_NORNCR, FRVBF_SFMT_ANDCR },
+  { FRV_INSN_NOTCR, FRVBF_INSN_NOTCR, FRVBF_SFMT_NOTCR },
+  { FRV_INSN_CKRA, FRVBF_INSN_CKRA, FRVBF_SFMT_CKRA },
+  { FRV_INSN_CKNO, FRVBF_INSN_CKNO, FRVBF_SFMT_CKRA },
+  { FRV_INSN_CKEQ, FRVBF_INSN_CKEQ, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKNE, FRVBF_INSN_CKNE, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKLE, FRVBF_INSN_CKLE, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKGT, FRVBF_INSN_CKGT, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKLT, FRVBF_INSN_CKLT, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKGE, FRVBF_INSN_CKGE, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKLS, FRVBF_INSN_CKLS, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKHI, FRVBF_INSN_CKHI, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKC, FRVBF_INSN_CKC, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKNC, FRVBF_INSN_CKNC, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKN, FRVBF_INSN_CKN, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKP, FRVBF_INSN_CKP, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKV, FRVBF_INSN_CKV, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_CKNV, FRVBF_INSN_CKNV, FRVBF_SFMT_CKEQ },
+  { FRV_INSN_FCKRA, FRVBF_INSN_FCKRA, FRVBF_SFMT_FCKRA },
+  { FRV_INSN_FCKNO, FRVBF_INSN_FCKNO, FRVBF_SFMT_FCKRA },
+  { FRV_INSN_FCKNE, FRVBF_INSN_FCKNE, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKEQ, FRVBF_INSN_FCKEQ, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKLG, FRVBF_INSN_FCKLG, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKUE, FRVBF_INSN_FCKUE, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKUL, FRVBF_INSN_FCKUL, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKGE, FRVBF_INSN_FCKGE, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKLT, FRVBF_INSN_FCKLT, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKUGE, FRVBF_INSN_FCKUGE, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKUG, FRVBF_INSN_FCKUG, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKLE, FRVBF_INSN_FCKLE, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKGT, FRVBF_INSN_FCKGT, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKULE, FRVBF_INSN_FCKULE, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKU, FRVBF_INSN_FCKU, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_FCKO, FRVBF_INSN_FCKO, FRVBF_SFMT_FCKNE },
+  { FRV_INSN_CCKRA, FRVBF_INSN_CCKRA, FRVBF_SFMT_CCKRA },
+  { FRV_INSN_CCKNO, FRVBF_INSN_CCKNO, FRVBF_SFMT_CCKRA },
+  { FRV_INSN_CCKEQ, FRVBF_INSN_CCKEQ, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKNE, FRVBF_INSN_CCKNE, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKLE, FRVBF_INSN_CCKLE, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKGT, FRVBF_INSN_CCKGT, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKLT, FRVBF_INSN_CCKLT, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKGE, FRVBF_INSN_CCKGE, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKLS, FRVBF_INSN_CCKLS, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKHI, FRVBF_INSN_CCKHI, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKC, FRVBF_INSN_CCKC, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKNC, FRVBF_INSN_CCKNC, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKN, FRVBF_INSN_CCKN, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKP, FRVBF_INSN_CCKP, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKV, FRVBF_INSN_CCKV, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CCKNV, FRVBF_INSN_CCKNV, FRVBF_SFMT_CCKEQ },
+  { FRV_INSN_CFCKRA, FRVBF_INSN_CFCKRA, FRVBF_SFMT_CFCKRA },
+  { FRV_INSN_CFCKNO, FRVBF_INSN_CFCKNO, FRVBF_SFMT_CFCKRA },
+  { FRV_INSN_CFCKNE, FRVBF_INSN_CFCKNE, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKEQ, FRVBF_INSN_CFCKEQ, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKLG, FRVBF_INSN_CFCKLG, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKUE, FRVBF_INSN_CFCKUE, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKUL, FRVBF_INSN_CFCKUL, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKGE, FRVBF_INSN_CFCKGE, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKLT, FRVBF_INSN_CFCKLT, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKUGE, FRVBF_INSN_CFCKUGE, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKUG, FRVBF_INSN_CFCKUG, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKLE, FRVBF_INSN_CFCKLE, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKGT, FRVBF_INSN_CFCKGT, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKULE, FRVBF_INSN_CFCKULE, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKU, FRVBF_INSN_CFCKU, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CFCKO, FRVBF_INSN_CFCKO, FRVBF_SFMT_CFCKNE },
+  { FRV_INSN_CJMPL, FRVBF_INSN_CJMPL, FRVBF_SFMT_CJMPL },
+  { FRV_INSN_CCALLL, FRVBF_INSN_CCALLL, FRVBF_SFMT_CJMPL },
+  { FRV_INSN_ICI, FRVBF_INSN_ICI, FRVBF_SFMT_ICI },
+  { FRV_INSN_DCI, FRVBF_INSN_DCI, FRVBF_SFMT_ICI },
+  { FRV_INSN_ICEI, FRVBF_INSN_ICEI, FRVBF_SFMT_ICEI },
+  { FRV_INSN_DCEI, FRVBF_INSN_DCEI, FRVBF_SFMT_ICEI },
+  { FRV_INSN_DCF, FRVBF_INSN_DCF, FRVBF_SFMT_ICI },
+  { FRV_INSN_DCEF, FRVBF_INSN_DCEF, FRVBF_SFMT_ICEI },
+  { FRV_INSN_WITLB, FRVBF_INSN_WITLB, FRVBF_SFMT_REI },
+  { FRV_INSN_WDTLB, FRVBF_INSN_WDTLB, FRVBF_SFMT_REI },
+  { FRV_INSN_ITLBI, FRVBF_INSN_ITLBI, FRVBF_SFMT_REI },
+  { FRV_INSN_DTLBI, FRVBF_INSN_DTLBI, FRVBF_SFMT_REI },
+  { FRV_INSN_ICPL, FRVBF_INSN_ICPL, FRVBF_SFMT_ICPL },
+  { FRV_INSN_DCPL, FRVBF_INSN_DCPL, FRVBF_SFMT_ICPL },
+  { FRV_INSN_ICUL, FRVBF_INSN_ICUL, FRVBF_SFMT_ICUL },
+  { FRV_INSN_DCUL, FRVBF_INSN_DCUL, FRVBF_SFMT_ICUL },
+  { FRV_INSN_BAR, FRVBF_INSN_BAR, FRVBF_SFMT_REI },
+  { FRV_INSN_MEMBAR, FRVBF_INSN_MEMBAR, FRVBF_SFMT_REI },
+  { FRV_INSN_COP1, FRVBF_INSN_COP1, FRVBF_SFMT_REI },
+  { FRV_INSN_COP2, FRVBF_INSN_COP2, FRVBF_SFMT_REI },
+  { FRV_INSN_CLRGR, FRVBF_INSN_CLRGR, FRVBF_SFMT_CLRGR },
+  { FRV_INSN_CLRFR, FRVBF_INSN_CLRFR, FRVBF_SFMT_CLRFR },
+  { FRV_INSN_CLRGA, FRVBF_INSN_CLRGA, FRVBF_SFMT_REI },
+  { FRV_INSN_CLRFA, FRVBF_INSN_CLRFA, FRVBF_SFMT_REI },
+  { FRV_INSN_COMMITGR, FRVBF_INSN_COMMITGR, FRVBF_SFMT_CLRGR },
+  { FRV_INSN_COMMITFR, FRVBF_INSN_COMMITFR, FRVBF_SFMT_CLRFR },
+  { FRV_INSN_COMMITGA, FRVBF_INSN_COMMITGA, FRVBF_SFMT_REI },
+  { FRV_INSN_COMMITFA, FRVBF_INSN_COMMITFA, FRVBF_SFMT_REI },
+  { FRV_INSN_FITOS, FRVBF_INSN_FITOS, FRVBF_SFMT_FITOS },
+  { FRV_INSN_FSTOI, FRVBF_INSN_FSTOI, FRVBF_SFMT_FSTOI },
+  { FRV_INSN_FITOD, FRVBF_INSN_FITOD, FRVBF_SFMT_FITOD },
+  { FRV_INSN_FDTOI, FRVBF_INSN_FDTOI, FRVBF_SFMT_FDTOI },
+  { FRV_INSN_FDITOS, FRVBF_INSN_FDITOS, FRVBF_SFMT_FDITOS },
+  { FRV_INSN_FDSTOI, FRVBF_INSN_FDSTOI, FRVBF_SFMT_FDSTOI },
+  { FRV_INSN_NFDITOS, FRVBF_INSN_NFDITOS, FRVBF_SFMT_FDITOS },
+  { FRV_INSN_NFDSTOI, FRVBF_INSN_NFDSTOI, FRVBF_SFMT_FDSTOI },
+  { FRV_INSN_CFITOS, FRVBF_INSN_CFITOS, FRVBF_SFMT_CFITOS },
+  { FRV_INSN_CFSTOI, FRVBF_INSN_CFSTOI, FRVBF_SFMT_CFSTOI },
+  { FRV_INSN_NFITOS, FRVBF_INSN_NFITOS, FRVBF_SFMT_NFITOS },
+  { FRV_INSN_NFSTOI, FRVBF_INSN_NFSTOI, FRVBF_SFMT_NFSTOI },
+  { FRV_INSN_FMOVS, FRVBF_INSN_FMOVS, FRVBF_SFMT_FMOVS },
+  { FRV_INSN_FMOVD, FRVBF_INSN_FMOVD, FRVBF_SFMT_FMOVD },
+  { FRV_INSN_FDMOVS, FRVBF_INSN_FDMOVS, FRVBF_SFMT_FDMOVS },
+  { FRV_INSN_CFMOVS, FRVBF_INSN_CFMOVS, FRVBF_SFMT_CFMOVS },
+  { FRV_INSN_FNEGS, FRVBF_INSN_FNEGS, FRVBF_SFMT_FMOVS },
+  { FRV_INSN_FNEGD, FRVBF_INSN_FNEGD, FRVBF_SFMT_FMOVD },
+  { FRV_INSN_FDNEGS, FRVBF_INSN_FDNEGS, FRVBF_SFMT_FDMOVS },
+  { FRV_INSN_CFNEGS, FRVBF_INSN_CFNEGS, FRVBF_SFMT_CFMOVS },
+  { FRV_INSN_FABSS, FRVBF_INSN_FABSS, FRVBF_SFMT_FMOVS },
+  { FRV_INSN_FABSD, FRVBF_INSN_FABSD, FRVBF_SFMT_FMOVD },
+  { FRV_INSN_FDABSS, FRVBF_INSN_FDABSS, FRVBF_SFMT_FDMOVS },
+  { FRV_INSN_CFABSS, FRVBF_INSN_CFABSS, FRVBF_SFMT_CFMOVS },
+  { FRV_INSN_FSQRTS, FRVBF_INSN_FSQRTS, FRVBF_SFMT_FMOVS },
+  { FRV_INSN_FDSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_SFMT_FDMOVS },
+  { FRV_INSN_NFDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_SFMT_FDMOVS },
+  { FRV_INSN_FSQRTD, FRVBF_INSN_FSQRTD, FRVBF_SFMT_FMOVD },
+  { FRV_INSN_CFSQRTS, FRVBF_INSN_CFSQRTS, FRVBF_SFMT_CFMOVS },
+  { FRV_INSN_NFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_SFMT_NFSQRTS },
+  { FRV_INSN_FADDS, FRVBF_INSN_FADDS, FRVBF_SFMT_FADDS },
+  { FRV_INSN_FSUBS, FRVBF_INSN_FSUBS, FRVBF_SFMT_FADDS },
+  { FRV_INSN_FMULS, FRVBF_INSN_FMULS, FRVBF_SFMT_FADDS },
+  { FRV_INSN_FDIVS, FRVBF_INSN_FDIVS, FRVBF_SFMT_FADDS },
+  { FRV_INSN_FADDD, FRVBF_INSN_FADDD, FRVBF_SFMT_FADDD },
+  { FRV_INSN_FSUBD, FRVBF_INSN_FSUBD, FRVBF_SFMT_FADDD },
+  { FRV_INSN_FMULD, FRVBF_INSN_FMULD, FRVBF_SFMT_FADDD },
+  { FRV_INSN_FDIVD, FRVBF_INSN_FDIVD, FRVBF_SFMT_FADDD },
+  { FRV_INSN_CFADDS, FRVBF_INSN_CFADDS, FRVBF_SFMT_CFADDS },
+  { FRV_INSN_CFSUBS, FRVBF_INSN_CFSUBS, FRVBF_SFMT_CFADDS },
+  { FRV_INSN_CFMULS, FRVBF_INSN_CFMULS, FRVBF_SFMT_CFADDS },
+  { FRV_INSN_CFDIVS, FRVBF_INSN_CFDIVS, FRVBF_SFMT_CFADDS },
+  { FRV_INSN_NFADDS, FRVBF_INSN_NFADDS, FRVBF_SFMT_NFADDS },
+  { FRV_INSN_NFSUBS, FRVBF_INSN_NFSUBS, FRVBF_SFMT_NFADDS },
+  { FRV_INSN_NFMULS, FRVBF_INSN_NFMULS, FRVBF_SFMT_NFADDS },
+  { FRV_INSN_NFDIVS, FRVBF_INSN_NFDIVS, FRVBF_SFMT_NFADDS },
+  { FRV_INSN_FCMPS, FRVBF_INSN_FCMPS, FRVBF_SFMT_FCMPS },
+  { FRV_INSN_FCMPD, FRVBF_INSN_FCMPD, FRVBF_SFMT_FCMPD },
+  { FRV_INSN_CFCMPS, FRVBF_INSN_CFCMPS, FRVBF_SFMT_CFCMPS },
+  { FRV_INSN_FDCMPS, FRVBF_INSN_FDCMPS, FRVBF_SFMT_FDCMPS },
+  { FRV_INSN_FMADDS, FRVBF_INSN_FMADDS, FRVBF_SFMT_FMADDS },
+  { FRV_INSN_FMSUBS, FRVBF_INSN_FMSUBS, FRVBF_SFMT_FMADDS },
+  { FRV_INSN_FMADDD, FRVBF_INSN_FMADDD, FRVBF_SFMT_FMADDD },
+  { FRV_INSN_FMSUBD, FRVBF_INSN_FMSUBD, FRVBF_SFMT_FMADDD },
+  { FRV_INSN_FDMADDS, FRVBF_INSN_FDMADDS, FRVBF_SFMT_FDMADDS },
+  { FRV_INSN_NFDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_SFMT_FDMADDS },
+  { FRV_INSN_CFMADDS, FRVBF_INSN_CFMADDS, FRVBF_SFMT_CFMADDS },
+  { FRV_INSN_CFMSUBS, FRVBF_INSN_CFMSUBS, FRVBF_SFMT_CFMADDS },
+  { FRV_INSN_NFMADDS, FRVBF_INSN_NFMADDS, FRVBF_SFMT_NFMADDS },
+  { FRV_INSN_NFMSUBS, FRVBF_INSN_NFMSUBS, FRVBF_SFMT_NFMADDS },
+  { FRV_INSN_FMAS, FRVBF_INSN_FMAS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FMSS, FRVBF_INSN_FMSS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FDMAS, FRVBF_INSN_FDMAS, FRVBF_SFMT_FDMAS },
+  { FRV_INSN_FDMSS, FRVBF_INSN_FDMSS, FRVBF_SFMT_FDMAS },
+  { FRV_INSN_NFDMAS, FRVBF_INSN_NFDMAS, FRVBF_SFMT_FDMAS },
+  { FRV_INSN_NFDMSS, FRVBF_INSN_NFDMSS, FRVBF_SFMT_FDMAS },
+  { FRV_INSN_CFMAS, FRVBF_INSN_CFMAS, FRVBF_SFMT_CFMAS },
+  { FRV_INSN_CFMSS, FRVBF_INSN_CFMSS, FRVBF_SFMT_CFMAS },
+  { FRV_INSN_FMAD, FRVBF_INSN_FMAD, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FMSD, FRVBF_INSN_FMSD, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFMAS, FRVBF_INSN_NFMAS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFMSS, FRVBF_INSN_NFMSS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FDADDS, FRVBF_INSN_FDADDS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FDSUBS, FRVBF_INSN_FDSUBS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FDMULS, FRVBF_INSN_FDMULS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FDDIVS, FRVBF_INSN_FDDIVS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FDSADS, FRVBF_INSN_FDSADS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_FDMULCS, FRVBF_INSN_FDMULCS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFDADDS, FRVBF_INSN_NFDADDS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFDSUBS, FRVBF_INSN_NFDSUBS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFDMULS, FRVBF_INSN_NFDMULS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFDDIVS, FRVBF_INSN_NFDDIVS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFDSADS, FRVBF_INSN_NFDSADS, FRVBF_SFMT_FMAS },
+  { FRV_INSN_NFDCMPS, FRVBF_INSN_NFDCMPS, FRVBF_SFMT_NFDCMPS },
+  { FRV_INSN_MHSETLOS, FRVBF_INSN_MHSETLOS, FRVBF_SFMT_MHSETLOS },
+  { FRV_INSN_MHSETHIS, FRVBF_INSN_MHSETHIS, FRVBF_SFMT_MHSETHIS },
+  { FRV_INSN_MHDSETS, FRVBF_INSN_MHDSETS, FRVBF_SFMT_MHDSETS },
+  { FRV_INSN_MHSETLOH, FRVBF_INSN_MHSETLOH, FRVBF_SFMT_MHSETLOH },
+  { FRV_INSN_MHSETHIH, FRVBF_INSN_MHSETHIH, FRVBF_SFMT_MHSETHIH },
+  { FRV_INSN_MHDSETH, FRVBF_INSN_MHDSETH, FRVBF_SFMT_MHDSETH },
+  { FRV_INSN_MAND, FRVBF_INSN_MAND, FRVBF_SFMT_MAND },
+  { FRV_INSN_MOR, FRVBF_INSN_MOR, FRVBF_SFMT_MAND },
+  { FRV_INSN_MXOR, FRVBF_INSN_MXOR, FRVBF_SFMT_MAND },
+  { FRV_INSN_CMAND, FRVBF_INSN_CMAND, FRVBF_SFMT_CMAND },
+  { FRV_INSN_CMOR, FRVBF_INSN_CMOR, FRVBF_SFMT_CMAND },
+  { FRV_INSN_CMXOR, FRVBF_INSN_CMXOR, FRVBF_SFMT_CMAND },
+  { FRV_INSN_MNOT, FRVBF_INSN_MNOT, FRVBF_SFMT_MNOT },
+  { FRV_INSN_CMNOT, FRVBF_INSN_CMNOT, FRVBF_SFMT_CMNOT },
+  { FRV_INSN_MROTLI, FRVBF_INSN_MROTLI, FRVBF_SFMT_MROTLI },
+  { FRV_INSN_MROTRI, FRVBF_INSN_MROTRI, FRVBF_SFMT_MROTLI },
+  { FRV_INSN_MWCUT, FRVBF_INSN_MWCUT, FRVBF_SFMT_MWCUT },
+  { FRV_INSN_MWCUTI, FRVBF_INSN_MWCUTI, FRVBF_SFMT_MWCUTI },
+  { FRV_INSN_MCUT, FRVBF_INSN_MCUT, FRVBF_SFMT_MCUT },
+  { FRV_INSN_MCUTI, FRVBF_INSN_MCUTI, FRVBF_SFMT_MCUTI },
+  { FRV_INSN_MCUTSS, FRVBF_INSN_MCUTSS, FRVBF_SFMT_MCUT },
+  { FRV_INSN_MCUTSSI, FRVBF_INSN_MCUTSSI, FRVBF_SFMT_MCUTI },
+  { FRV_INSN_MDCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_SFMT_MDCUTSSI },
+  { FRV_INSN_MAVEH, FRVBF_INSN_MAVEH, FRVBF_SFMT_MAND },
+  { FRV_INSN_MSLLHI, FRVBF_INSN_MSLLHI, FRVBF_SFMT_MSLLHI },
+  { FRV_INSN_MSRLHI, FRVBF_INSN_MSRLHI, FRVBF_SFMT_MSLLHI },
+  { FRV_INSN_MSRAHI, FRVBF_INSN_MSRAHI, FRVBF_SFMT_MSLLHI },
+  { FRV_INSN_MDROTLI, FRVBF_INSN_MDROTLI, FRVBF_SFMT_MDROTLI },
+  { FRV_INSN_MCPLHI, FRVBF_INSN_MCPLHI, FRVBF_SFMT_MCPLHI },
+  { FRV_INSN_MCPLI, FRVBF_INSN_MCPLI, FRVBF_SFMT_MCPLI },
+  { FRV_INSN_MSATHS, FRVBF_INSN_MSATHS, FRVBF_SFMT_MSATHS },
+  { FRV_INSN_MQSATHS, FRVBF_INSN_MQSATHS, FRVBF_SFMT_MQSATHS },
+  { FRV_INSN_MSATHU, FRVBF_INSN_MSATHU, FRVBF_SFMT_MSATHS },
+  { FRV_INSN_MCMPSH, FRVBF_INSN_MCMPSH, FRVBF_SFMT_MCMPSH },
+  { FRV_INSN_MCMPUH, FRVBF_INSN_MCMPUH, FRVBF_SFMT_MCMPSH },
+  { FRV_INSN_MABSHS, FRVBF_INSN_MABSHS, FRVBF_SFMT_MABSHS },
+  { FRV_INSN_MADDHSS, FRVBF_INSN_MADDHSS, FRVBF_SFMT_MSATHS },
+  { FRV_INSN_MADDHUS, FRVBF_INSN_MADDHUS, FRVBF_SFMT_MSATHS },
+  { FRV_INSN_MSUBHSS, FRVBF_INSN_MSUBHSS, FRVBF_SFMT_MSATHS },
+  { FRV_INSN_MSUBHUS, FRVBF_INSN_MSUBHUS, FRVBF_SFMT_MSATHS },
+  { FRV_INSN_CMADDHSS, FRVBF_INSN_CMADDHSS, FRVBF_SFMT_CMADDHSS },
+  { FRV_INSN_CMADDHUS, FRVBF_INSN_CMADDHUS, FRVBF_SFMT_CMADDHSS },
+  { FRV_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHSS, FRVBF_SFMT_CMADDHSS },
+  { FRV_INSN_CMSUBHUS, FRVBF_INSN_CMSUBHUS, FRVBF_SFMT_CMADDHSS },
+  { FRV_INSN_MQADDHSS, FRVBF_INSN_MQADDHSS, FRVBF_SFMT_MQSATHS },
+  { FRV_INSN_MQADDHUS, FRVBF_INSN_MQADDHUS, FRVBF_SFMT_MQSATHS },
+  { FRV_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHSS, FRVBF_SFMT_MQSATHS },
+  { FRV_INSN_MQSUBHUS, FRVBF_INSN_MQSUBHUS, FRVBF_SFMT_MQSATHS },
+  { FRV_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHSS, FRVBF_SFMT_CMQADDHSS },
+  { FRV_INSN_CMQADDHUS, FRVBF_INSN_CMQADDHUS, FRVBF_SFMT_CMQADDHSS },
+  { FRV_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHSS, FRVBF_SFMT_CMQADDHSS },
+  { FRV_INSN_CMQSUBHUS, FRVBF_INSN_CMQSUBHUS, FRVBF_SFMT_CMQADDHSS },
+  { FRV_INSN_MADDACCS, FRVBF_INSN_MADDACCS, FRVBF_SFMT_MADDACCS },
+  { FRV_INSN_MSUBACCS, FRVBF_INSN_MSUBACCS, FRVBF_SFMT_MADDACCS },
+  { FRV_INSN_MDADDACCS, FRVBF_INSN_MDADDACCS, FRVBF_SFMT_MDADDACCS },
+  { FRV_INSN_MDSUBACCS, FRVBF_INSN_MDSUBACCS, FRVBF_SFMT_MDADDACCS },
+  { FRV_INSN_MASACCS, FRVBF_INSN_MASACCS, FRVBF_SFMT_MASACCS },
+  { FRV_INSN_MDASACCS, FRVBF_INSN_MDASACCS, FRVBF_SFMT_MDASACCS },
+  { FRV_INSN_MMULHS, FRVBF_INSN_MMULHS, FRVBF_SFMT_MMULHS },
+  { FRV_INSN_MMULHU, FRVBF_INSN_MMULHU, FRVBF_SFMT_MMULHS },
+  { FRV_INSN_MMULXHS, FRVBF_INSN_MMULXHS, FRVBF_SFMT_MMULHS },
+  { FRV_INSN_MMULXHU, FRVBF_INSN_MMULXHU, FRVBF_SFMT_MMULHS },
+  { FRV_INSN_CMMULHS, FRVBF_INSN_CMMULHS, FRVBF_SFMT_CMMULHS },
+  { FRV_INSN_CMMULHU, FRVBF_INSN_CMMULHU, FRVBF_SFMT_CMMULHS },
+  { FRV_INSN_MQMULHS, FRVBF_INSN_MQMULHS, FRVBF_SFMT_MQMULHS },
+  { FRV_INSN_MQMULHU, FRVBF_INSN_MQMULHU, FRVBF_SFMT_MQMULHS },
+  { FRV_INSN_MQMULXHS, FRVBF_INSN_MQMULXHS, FRVBF_SFMT_MQMULHS },
+  { FRV_INSN_MQMULXHU, FRVBF_INSN_MQMULXHU, FRVBF_SFMT_MQMULHS },
+  { FRV_INSN_CMQMULHS, FRVBF_INSN_CMQMULHS, FRVBF_SFMT_CMQMULHS },
+  { FRV_INSN_CMQMULHU, FRVBF_INSN_CMQMULHU, FRVBF_SFMT_CMQMULHS },
+  { FRV_INSN_MMACHS, FRVBF_INSN_MMACHS, FRVBF_SFMT_MMACHS },
+  { FRV_INSN_MMACHU, FRVBF_INSN_MMACHU, FRVBF_SFMT_MMACHU },
+  { FRV_INSN_MMRDHS, FRVBF_INSN_MMRDHS, FRVBF_SFMT_MMACHS },
+  { FRV_INSN_MMRDHU, FRVBF_INSN_MMRDHU, FRVBF_SFMT_MMACHU },
+  { FRV_INSN_CMMACHS, FRVBF_INSN_CMMACHS, FRVBF_SFMT_CMMACHS },
+  { FRV_INSN_CMMACHU, FRVBF_INSN_CMMACHU, FRVBF_SFMT_CMMACHU },
+  { FRV_INSN_MQMACHS, FRVBF_INSN_MQMACHS, FRVBF_SFMT_MQMACHS },
+  { FRV_INSN_MQMACHU, FRVBF_INSN_MQMACHU, FRVBF_SFMT_MQMACHU },
+  { FRV_INSN_CMQMACHS, FRVBF_INSN_CMQMACHS, FRVBF_SFMT_CMQMACHS },
+  { FRV_INSN_CMQMACHU, FRVBF_INSN_CMQMACHU, FRVBF_SFMT_CMQMACHU },
+  { FRV_INSN_MQXMACHS, FRVBF_INSN_MQXMACHS, FRVBF_SFMT_MQMACHS },
+  { FRV_INSN_MQXMACXHS, FRVBF_INSN_MQXMACXHS, FRVBF_SFMT_MQMACHS },
+  { FRV_INSN_MQMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_SFMT_MQMACHS },
+  { FRV_INSN_MCPXRS, FRVBF_INSN_MCPXRS, FRVBF_SFMT_MCPXRS },
+  { FRV_INSN_MCPXRU, FRVBF_INSN_MCPXRU, FRVBF_SFMT_MCPXRS },
+  { FRV_INSN_MCPXIS, FRVBF_INSN_MCPXIS, FRVBF_SFMT_MCPXRS },
+  { FRV_INSN_MCPXIU, FRVBF_INSN_MCPXIU, FRVBF_SFMT_MCPXRS },
+  { FRV_INSN_CMCPXRS, FRVBF_INSN_CMCPXRS, FRVBF_SFMT_CMCPXRS },
+  { FRV_INSN_CMCPXRU, FRVBF_INSN_CMCPXRU, FRVBF_SFMT_CMCPXRS },
+  { FRV_INSN_CMCPXIS, FRVBF_INSN_CMCPXIS, FRVBF_SFMT_CMCPXRS },
+  { FRV_INSN_CMCPXIU, FRVBF_INSN_CMCPXIU, FRVBF_SFMT_CMCPXRS },
+  { FRV_INSN_MQCPXRS, FRVBF_INSN_MQCPXRS, FRVBF_SFMT_MQCPXRS },
+  { FRV_INSN_MQCPXRU, FRVBF_INSN_MQCPXRU, FRVBF_SFMT_MQCPXRS },
+  { FRV_INSN_MQCPXIS, FRVBF_INSN_MQCPXIS, FRVBF_SFMT_MQCPXRS },
+  { FRV_INSN_MQCPXIU, FRVBF_INSN_MQCPXIU, FRVBF_SFMT_MQCPXRS },
+  { FRV_INSN_MEXPDHW, FRVBF_INSN_MEXPDHW, FRVBF_SFMT_MEXPDHW },
+  { FRV_INSN_CMEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_SFMT_CMEXPDHW },
+  { FRV_INSN_MEXPDHD, FRVBF_INSN_MEXPDHD, FRVBF_SFMT_MEXPDHD },
+  { FRV_INSN_CMEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_SFMT_CMEXPDHD },
+  { FRV_INSN_MPACKH, FRVBF_INSN_MPACKH, FRVBF_SFMT_MPACKH },
+  { FRV_INSN_MDPACKH, FRVBF_INSN_MDPACKH, FRVBF_SFMT_MDPACKH },
+  { FRV_INSN_MUNPACKH, FRVBF_INSN_MUNPACKH, FRVBF_SFMT_MUNPACKH },
+  { FRV_INSN_MDUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_SFMT_MDUNPACKH },
+  { FRV_INSN_MBTOH, FRVBF_INSN_MBTOH, FRVBF_SFMT_MBTOH },
+  { FRV_INSN_CMBTOH, FRVBF_INSN_CMBTOH, FRVBF_SFMT_CMBTOH },
+  { FRV_INSN_MHTOB, FRVBF_INSN_MHTOB, FRVBF_SFMT_MHTOB },
+  { FRV_INSN_CMHTOB, FRVBF_INSN_CMHTOB, FRVBF_SFMT_CMHTOB },
+  { FRV_INSN_MBTOHE, FRVBF_INSN_MBTOHE, FRVBF_SFMT_MBTOHE },
+  { FRV_INSN_CMBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_SFMT_CMBTOHE },
+  { FRV_INSN_MCLRACC, FRVBF_INSN_MCLRACC, FRVBF_SFMT_MCLRACC },
+  { FRV_INSN_MRDACC, FRVBF_INSN_MRDACC, FRVBF_SFMT_MRDACC },
+  { FRV_INSN_MRDACCG, FRVBF_INSN_MRDACCG, FRVBF_SFMT_MRDACCG },
+  { FRV_INSN_MWTACC, FRVBF_INSN_MWTACC, FRVBF_SFMT_MWTACC },
+  { FRV_INSN_MWTACCG, FRVBF_INSN_MWTACCG, FRVBF_SFMT_MWTACCG },
+  { FRV_INSN_MCOP1, FRVBF_INSN_MCOP1, FRVBF_SFMT_REI },
+  { FRV_INSN_MCOP2, FRVBF_INSN_MCOP2, FRVBF_SFMT_REI },
+  { FRV_INSN_FNOP, FRVBF_INSN_FNOP, FRVBF_SFMT_REI },
+};
+
+static const struct insn_sem frvbf_insn_sem_invalid = {
+  VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts.  */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+  id->num = t->index;
+  id->sfmt = t->sfmt;
+  if ((int) t->type <= 0)
+    id->idata = & cgen_virtual_insn_table[- (int) t->type];
+  else
+    id->idata = & insn_table[t->type];
+  id->attrs = CGEN_INSN_ATTRS (id->idata);
+  /* Oh my god, a magic number.  */
+  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+  {
+    SIM_DESC sd = CPU_STATE (cpu);
+    SIM_ASSERT (t->index == id->timing->num);
+  }
+#endif
+
+  /* Semantic pointers are initialized elsewhere.  */
+}
+
+/* Initialize the instruction descriptor table.  */
+
+void
+frvbf_init_idesc_table (SIM_CPU *cpu)
+{
+  IDESC *id,*tabend;
+  const struct insn_sem *t,*tend;
+  int tabsize = FRVBF_INSN__MAX;
+  IDESC *table = frvbf_insn_data;
+
+  memset (table, 0, tabsize * sizeof (IDESC));
+
+  /* First set all entries to the `invalid insn'.  */
+  t = & frvbf_insn_sem_invalid;
+  for (id = table, tabend = table + tabsize; id < tabend; ++id)
+    init_idesc (cpu, id, t);
+
+  /* Now fill in the values for the chosen cpu.  */
+  for (t = frvbf_insn_sem, tend = t + sizeof (frvbf_insn_sem) / sizeof (*t);
+       t != tend; ++t)
+    {
+      init_idesc (cpu, & table[t->index], t);
+    }
+
+  /* Link the IDESC table into the cpu.  */
+  CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry.  */
+
+const IDESC *
+frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
+              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+              ARGBUF *abuf)
+{
+  /* Result of decoder.  */
+  FRVBF_INSN_TYPE itype;
+
+  {
+    CGEN_INSN_INT insn = base_insn;
+
+    {
+      unsigned int val = (((insn >> 18) & (127 << 0)));
+      switch (val)
+      {
+      case 0 :
+        {
+          unsigned int val = (((insn >> 6) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_ADD; goto extract_sfmt_add;
+          case 1 : itype = FRVBF_INSN_ADDCC; goto extract_sfmt_addcc;
+          case 2 : itype = FRVBF_INSN_ADDX; goto extract_sfmt_addx;
+          case 3 : itype = FRVBF_INSN_ADDXCC; goto extract_sfmt_addcc;
+          case 4 : itype = FRVBF_INSN_SUB; goto extract_sfmt_add;
+          case 5 : itype = FRVBF_INSN_SUBCC; goto extract_sfmt_addcc;
+          case 6 : itype = FRVBF_INSN_SUBX; goto extract_sfmt_addx;
+          case 7 : itype = FRVBF_INSN_SUBXCC; goto extract_sfmt_addcc;
+          case 8 : itype = FRVBF_INSN_SMUL; goto extract_sfmt_smul;
+          case 9 : itype = FRVBF_INSN_SMULCC; goto extract_sfmt_smulcc;
+          case 10 : itype = FRVBF_INSN_UMUL; goto extract_sfmt_smul;
+          case 11 : itype = FRVBF_INSN_UMULCC; goto extract_sfmt_smulcc;
+          case 12 : itype = FRVBF_INSN_CMPB; goto extract_sfmt_cmpb;
+          case 13 : itype = FRVBF_INSN_CMPBA; goto extract_sfmt_cmpb;
+          case 14 : itype = FRVBF_INSN_SDIV; goto extract_sfmt_sdiv;
+          case 15 : itype = FRVBF_INSN_UDIV; goto extract_sfmt_sdiv;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 1 :
+        {
+          unsigned int val = (((insn >> 6) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_AND; goto extract_sfmt_add;
+          case 1 : itype = FRVBF_INSN_ANDCC; goto extract_sfmt_andcc;
+          case 2 : itype = FRVBF_INSN_OR; goto extract_sfmt_add;
+          case 3 : itype = FRVBF_INSN_ORCC; goto extract_sfmt_andcc;
+          case 4 : itype = FRVBF_INSN_XOR; goto extract_sfmt_add;
+          case 5 : itype = FRVBF_INSN_XORCC; goto extract_sfmt_andcc;
+          case 6 : itype = FRVBF_INSN_NOT; goto extract_sfmt_not;
+          case 8 : itype = FRVBF_INSN_SLL; goto extract_sfmt_add;
+          case 9 : itype = FRVBF_INSN_SLLCC; goto extract_sfmt_addcc;
+          case 10 : itype = FRVBF_INSN_SRL; goto extract_sfmt_add;
+          case 11 : itype = FRVBF_INSN_SRLCC; goto extract_sfmt_addcc;
+          case 12 : itype = FRVBF_INSN_SRA; goto extract_sfmt_add;
+          case 13 : itype = FRVBF_INSN_SRACC; goto extract_sfmt_addcc;
+          case 14 : itype = FRVBF_INSN_NSDIV; goto extract_sfmt_sdiv;
+          case 15 : itype = FRVBF_INSN_NUDIV; goto extract_sfmt_sdiv;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 2 :
+        {
+          unsigned int val = (((insn >> 6) & (63 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_LDSB; goto extract_sfmt_ldsb;
+          case 1 : itype = FRVBF_INSN_LDUB; goto extract_sfmt_ldsb;
+          case 2 : itype = FRVBF_INSN_LDSH; goto extract_sfmt_ldsb;
+          case 3 : itype = FRVBF_INSN_LDUH; goto extract_sfmt_ldsb;
+          case 4 : itype = FRVBF_INSN_LD; goto extract_sfmt_ldsb;
+          case 5 : itype = FRVBF_INSN_LDD; goto extract_sfmt_ldd;
+          case 6 : itype = FRVBF_INSN_LDQ; goto extract_sfmt_ldq;
+          case 8 : itype = FRVBF_INSN_LDBF; goto extract_sfmt_ldbf;
+          case 9 : itype = FRVBF_INSN_LDHF; goto extract_sfmt_ldbf;
+          case 10 : itype = FRVBF_INSN_LDF; goto extract_sfmt_ldbf;
+          case 11 : itype = FRVBF_INSN_LDDF; goto extract_sfmt_lddf;
+          case 12 : itype = FRVBF_INSN_LDQF; goto extract_sfmt_ldqf;
+          case 13 : itype = FRVBF_INSN_LDC; goto extract_sfmt_ldc;
+          case 14 : itype = FRVBF_INSN_LDDC; goto extract_sfmt_lddc;
+          case 15 : itype = FRVBF_INSN_LDQC; goto extract_sfmt_ldqc;
+          case 16 : itype = FRVBF_INSN_LDSBU; goto extract_sfmt_ldsbu;
+          case 17 : itype = FRVBF_INSN_LDUBU; goto extract_sfmt_ldsbu;
+          case 18 : itype = FRVBF_INSN_LDSHU; goto extract_sfmt_ldsbu;
+          case 19 : itype = FRVBF_INSN_LDUHU; goto extract_sfmt_ldsbu;
+          case 20 : itype = FRVBF_INSN_LDU; goto extract_sfmt_ldsbu;
+          case 21 : itype = FRVBF_INSN_LDDU; goto extract_sfmt_lddu;
+          case 22 : itype = FRVBF_INSN_LDQU; goto extract_sfmt_ldqu;
+          case 24 : itype = FRVBF_INSN_LDBFU; goto extract_sfmt_ldbfu;
+          case 25 : itype = FRVBF_INSN_LDHFU; goto extract_sfmt_ldbfu;
+          case 26 : itype = FRVBF_INSN_LDFU; goto extract_sfmt_ldbfu;
+          case 27 : itype = FRVBF_INSN_LDDFU; goto extract_sfmt_lddfu;
+          case 28 : itype = FRVBF_INSN_LDQFU; goto extract_sfmt_ldqfu;
+          case 29 : itype = FRVBF_INSN_LDCU; goto extract_sfmt_ldcu;
+          case 30 : itype = FRVBF_INSN_LDDCU; goto extract_sfmt_lddcu;
+          case 31 : itype = FRVBF_INSN_LDQCU; goto extract_sfmt_ldqcu;
+          case 32 : itype = FRVBF_INSN_NLDSB; goto extract_sfmt_nldsb;
+          case 33 : itype = FRVBF_INSN_NLDUB; goto extract_sfmt_nldsb;
+          case 34 : itype = FRVBF_INSN_NLDSH; goto extract_sfmt_nldsb;
+          case 35 : itype = FRVBF_INSN_NLDUH; goto extract_sfmt_nldsb;
+          case 36 : itype = FRVBF_INSN_NLD; goto extract_sfmt_nldsb;
+          case 37 : itype = FRVBF_INSN_NLDD; goto extract_sfmt_nldd;
+          case 38 : itype = FRVBF_INSN_NLDQ; goto extract_sfmt_nldq;
+          case 40 : itype = FRVBF_INSN_NLDBF; goto extract_sfmt_nldbf;
+          case 41 : itype = FRVBF_INSN_NLDHF; goto extract_sfmt_nldbf;
+          case 42 : itype = FRVBF_INSN_NLDF; goto extract_sfmt_nldbf;
+          case 43 : itype = FRVBF_INSN_NLDDF; goto extract_sfmt_nlddf;
+          case 44 : itype = FRVBF_INSN_NLDQF; goto extract_sfmt_nldqf;
+          case 48 : itype = FRVBF_INSN_NLDSBU; goto extract_sfmt_nldsbu;
+          case 49 : itype = FRVBF_INSN_NLDUBU; goto extract_sfmt_nldsbu;
+          case 50 : itype = FRVBF_INSN_NLDSHU; goto extract_sfmt_nldsbu;
+          case 51 : itype = FRVBF_INSN_NLDUHU; goto extract_sfmt_nldsbu;
+          case 52 : itype = FRVBF_INSN_NLDU; goto extract_sfmt_nldsbu;
+          case 53 : itype = FRVBF_INSN_NLDDU; goto extract_sfmt_nlddu;
+          case 54 : itype = FRVBF_INSN_NLDQU; goto extract_sfmt_nldqu;
+          case 56 : itype = FRVBF_INSN_NLDBFU; goto extract_sfmt_nldbfu;
+          case 57 : itype = FRVBF_INSN_NLDHFU; goto extract_sfmt_nldbfu;
+          case 58 : itype = FRVBF_INSN_NLDFU; goto extract_sfmt_nldbfu;
+          case 59 : itype = FRVBF_INSN_NLDDFU; goto extract_sfmt_nlddfu;
+          case 60 : itype = FRVBF_INSN_NLDQFU; goto extract_sfmt_nldqfu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 3 :
+        {
+          unsigned int val = (((insn >> 6) & (63 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_STB; goto extract_sfmt_stb;
+          case 1 : itype = FRVBF_INSN_STH; goto extract_sfmt_stb;
+          case 2 : itype = FRVBF_INSN_ST; goto extract_sfmt_stb;
+          case 3 : itype = FRVBF_INSN_STD; goto extract_sfmt_std;
+          case 4 : itype = FRVBF_INSN_STQ; goto extract_sfmt_ldq;
+          case 5 : itype = FRVBF_INSN_SWAP; goto extract_sfmt_swap;
+          case 6 : itype = FRVBF_INSN_MOVGS; goto extract_sfmt_movgs;
+          case 7 : itype = FRVBF_INSN_MOVSG; goto extract_sfmt_movsg;
+          case 8 : itype = FRVBF_INSN_STBF; goto extract_sfmt_stbf;
+          case 9 : itype = FRVBF_INSN_STHF; goto extract_sfmt_stbf;
+          case 10 : itype = FRVBF_INSN_STF; goto extract_sfmt_stbf;
+          case 11 : itype = FRVBF_INSN_STDF; goto extract_sfmt_stdf;
+          case 12 : itype = FRVBF_INSN_STQF; goto extract_sfmt_ldqf;
+          case 13 : itype = FRVBF_INSN_MOVFG; goto extract_sfmt_movfg;
+          case 14 : itype = FRVBF_INSN_MOVFGD; goto extract_sfmt_movfgd;
+          case 15 : itype = FRVBF_INSN_MOVFGQ; goto extract_sfmt_movfgq;
+          case 16 : itype = FRVBF_INSN_STBU; goto extract_sfmt_stbu;
+          case 17 : itype = FRVBF_INSN_STHU; goto extract_sfmt_stbu;
+          case 18 : itype = FRVBF_INSN_STU; goto extract_sfmt_stbu;
+          case 19 : itype = FRVBF_INSN_STDU; goto extract_sfmt_stdu;
+          case 20 : itype = FRVBF_INSN_STQU; goto extract_sfmt_stqu;
+          case 21 : itype = FRVBF_INSN_MOVGF; goto extract_sfmt_movgf;
+          case 22 : itype = FRVBF_INSN_MOVGFD; goto extract_sfmt_movgfd;
+          case 23 : itype = FRVBF_INSN_MOVGFQ; goto extract_sfmt_movgfq;
+          case 24 : itype = FRVBF_INSN_STBFU; goto extract_sfmt_stbfu;
+          case 25 : itype = FRVBF_INSN_STHFU; goto extract_sfmt_stbfu;
+          case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu;
+          case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu;
+          case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu;
+          case 32 : itype = FRVBF_INSN_RSTB; goto extract_sfmt_rstb;
+          case 33 : itype = FRVBF_INSN_RSTH; goto extract_sfmt_rstb;
+          case 34 : itype = FRVBF_INSN_RST; goto extract_sfmt_rstb;
+          case 35 : itype = FRVBF_INSN_RSTD; goto extract_sfmt_rstd;
+          case 36 : itype = FRVBF_INSN_RSTQ; goto extract_sfmt_ldq;
+          case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc;
+          case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc;
+          case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc;
+          case 40 : itype = FRVBF_INSN_RSTBF; goto extract_sfmt_rstbf;
+          case 41 : itype = FRVBF_INSN_RSTHF; goto extract_sfmt_rstbf;
+          case 42 : itype = FRVBF_INSN_RSTF; goto extract_sfmt_rstbf;
+          case 43 : itype = FRVBF_INSN_RSTDF; goto extract_sfmt_rstdf;
+          case 44 : itype = FRVBF_INSN_RSTQF; goto extract_sfmt_ldqf;
+          case 45 : itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu;
+          case 46 : itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu;
+          case 47 : itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu;
+          case 48 : itype = FRVBF_INSN_ICPL; goto extract_sfmt_icpl;
+          case 49 : itype = FRVBF_INSN_ICUL; goto extract_sfmt_icul;
+          case 50 : itype = FRVBF_INSN_WITLB; goto extract_sfmt_rei;
+          case 51 : itype = FRVBF_INSN_ITLBI; goto extract_sfmt_rei;
+          case 52 : itype = FRVBF_INSN_DCPL; goto extract_sfmt_icpl;
+          case 53 : itype = FRVBF_INSN_DCUL; goto extract_sfmt_icul;
+          case 54 : itype = FRVBF_INSN_WDTLB; goto extract_sfmt_rei;
+          case 55 : itype = FRVBF_INSN_DTLBI; goto extract_sfmt_rei;
+          case 56 : itype = FRVBF_INSN_ICI; goto extract_sfmt_ici;
+          case 57 : itype = FRVBF_INSN_ICEI; goto extract_sfmt_icei;
+          case 58 : itype = FRVBF_INSN_DCEI; goto extract_sfmt_icei;
+          case 59 : itype = FRVBF_INSN_DCEF; goto extract_sfmt_icei;
+          case 60 : itype = FRVBF_INSN_DCI; goto extract_sfmt_ici;
+          case 61 : itype = FRVBF_INSN_DCF; goto extract_sfmt_ici;
+          case 62 : itype = FRVBF_INSN_BAR; goto extract_sfmt_rei;
+          case 63 : itype = FRVBF_INSN_MEMBAR; goto extract_sfmt_rei;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 4 :
+        {
+          unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_TNO; goto extract_sfmt_rei;
+          case 1 : itype = FRVBF_INSN_FTNO; goto extract_sfmt_rei;
+          case 2 : itype = FRVBF_INSN_MTRAP; goto extract_sfmt_rei;
+          case 3 : itype = FRVBF_INSN_BREAK; goto extract_sfmt_break;
+          case 4 : itype = FRVBF_INSN_TC; goto extract_sfmt_teq;
+          case 5 : itype = FRVBF_INSN_FTU; goto extract_sfmt_ftne;
+          case 8 : itype = FRVBF_INSN_TV; goto extract_sfmt_teq;
+          case 9 : itype = FRVBF_INSN_FTGT; goto extract_sfmt_ftne;
+          case 12 : itype = FRVBF_INSN_TLT; goto extract_sfmt_teq;
+          case 13 : itype = FRVBF_INSN_FTUG; goto extract_sfmt_ftne;
+          case 16 : itype = FRVBF_INSN_TEQ; goto extract_sfmt_teq;
+          case 17 : itype = FRVBF_INSN_FTLT; goto extract_sfmt_ftne;
+          case 20 : itype = FRVBF_INSN_TLS; goto extract_sfmt_teq;
+          case 21 : itype = FRVBF_INSN_FTUL; goto extract_sfmt_ftne;
+          case 24 : itype = FRVBF_INSN_TN; goto extract_sfmt_teq;
+          case 25 : itype = FRVBF_INSN_FTLG; goto extract_sfmt_ftne;
+          case 28 : itype = FRVBF_INSN_TLE; goto extract_sfmt_teq;
+          case 29 : itype = FRVBF_INSN_FTNE; goto extract_sfmt_ftne;
+          case 32 : itype = FRVBF_INSN_TRA; goto extract_sfmt_tra;
+          case 33 : itype = FRVBF_INSN_FTEQ; goto extract_sfmt_ftne;
+          case 36 : itype = FRVBF_INSN_TNC; goto extract_sfmt_teq;
+          case 37 : itype = FRVBF_INSN_FTUE; goto extract_sfmt_ftne;
+          case 40 : itype = FRVBF_INSN_TNV; goto extract_sfmt_teq;
+          case 41 : itype = FRVBF_INSN_FTGE; goto extract_sfmt_ftne;
+          case 44 : itype = FRVBF_INSN_TGE; goto extract_sfmt_teq;
+          case 45 : itype = FRVBF_INSN_FTUGE; goto extract_sfmt_ftne;
+          case 48 : itype = FRVBF_INSN_TNE; goto extract_sfmt_teq;
+          case 49 : itype = FRVBF_INSN_FTLE; goto extract_sfmt_ftne;
+          case 52 : itype = FRVBF_INSN_THI; goto extract_sfmt_teq;
+          case 53 : itype = FRVBF_INSN_FTULE; goto extract_sfmt_ftne;
+          case 56 : itype = FRVBF_INSN_TP; goto extract_sfmt_teq;
+          case 57 : itype = FRVBF_INSN_FTO; goto extract_sfmt_ftne;
+          case 60 : itype = FRVBF_INSN_TGT; goto extract_sfmt_teq;
+          case 61 : itype = FRVBF_INSN_FTRA; goto extract_sfmt_tra;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 5 : itype = FRVBF_INSN_RETT; goto extract_sfmt_rett;
+      case 6 :
+        {
+          unsigned int val = (((insn >> 27) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_BNO; goto extract_sfmt_bno;
+          case 1 : itype = FRVBF_INSN_BC; goto extract_sfmt_beq;
+          case 2 : itype = FRVBF_INSN_BV; goto extract_sfmt_beq;
+          case 3 : itype = FRVBF_INSN_BLT; goto extract_sfmt_beq;
+          case 4 : itype = FRVBF_INSN_BEQ; goto extract_sfmt_beq;
+          case 5 : itype = FRVBF_INSN_BLS; goto extract_sfmt_beq;
+          case 6 : itype = FRVBF_INSN_BN; goto extract_sfmt_beq;
+          case 7 : itype = FRVBF_INSN_BLE; goto extract_sfmt_beq;
+          case 8 : itype = FRVBF_INSN_BRA; goto extract_sfmt_bra;
+          case 9 : itype = FRVBF_INSN_BNC; goto extract_sfmt_beq;
+          case 10 : itype = FRVBF_INSN_BNV; goto extract_sfmt_beq;
+          case 11 : itype = FRVBF_INSN_BGE; goto extract_sfmt_beq;
+          case 12 : itype = FRVBF_INSN_BNE; goto extract_sfmt_beq;
+          case 13 : itype = FRVBF_INSN_BHI; goto extract_sfmt_beq;
+          case 14 : itype = FRVBF_INSN_BP; goto extract_sfmt_beq;
+          case 15 : itype = FRVBF_INSN_BGT; goto extract_sfmt_beq;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 7 :
+        {
+          unsigned int val = (((insn >> 27) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_FBNO; goto extract_sfmt_bno;
+          case 1 : itype = FRVBF_INSN_FBU; goto extract_sfmt_fbne;
+          case 2 : itype = FRVBF_INSN_FBGT; goto extract_sfmt_fbne;
+          case 3 : itype = FRVBF_INSN_FBUG; goto extract_sfmt_fbne;
+          case 4 : itype = FRVBF_INSN_FBLT; goto extract_sfmt_fbne;
+          case 5 : itype = FRVBF_INSN_FBUL; goto extract_sfmt_fbne;
+          case 6 : itype = FRVBF_INSN_FBLG; goto extract_sfmt_fbne;
+          case 7 : itype = FRVBF_INSN_FBNE; goto extract_sfmt_fbne;
+          case 8 : itype = FRVBF_INSN_FBEQ; goto extract_sfmt_fbne;
+          case 9 : itype = FRVBF_INSN_FBUE; goto extract_sfmt_fbne;
+          case 10 : itype = FRVBF_INSN_FBGE; goto extract_sfmt_fbne;
+          case 11 : itype = FRVBF_INSN_FBUGE; goto extract_sfmt_fbne;
+          case 12 : itype = FRVBF_INSN_FBLE; goto extract_sfmt_fbne;
+          case 13 : itype = FRVBF_INSN_FBULE; goto extract_sfmt_fbne;
+          case 14 : itype = FRVBF_INSN_FBO; goto extract_sfmt_fbne;
+          case 15 : itype = FRVBF_INSN_FBRA; goto extract_sfmt_bra;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 8 :
+        {
+          unsigned int val = (((insn >> 27) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CKNO; goto extract_sfmt_ckra;
+          case 1 : itype = FRVBF_INSN_CKC; goto extract_sfmt_ckeq;
+          case 2 : itype = FRVBF_INSN_CKV; goto extract_sfmt_ckeq;
+          case 3 : itype = FRVBF_INSN_CKLT; goto extract_sfmt_ckeq;
+          case 4 : itype = FRVBF_INSN_CKEQ; goto extract_sfmt_ckeq;
+          case 5 : itype = FRVBF_INSN_CKLS; goto extract_sfmt_ckeq;
+          case 6 : itype = FRVBF_INSN_CKN; goto extract_sfmt_ckeq;
+          case 7 : itype = FRVBF_INSN_CKLE; goto extract_sfmt_ckeq;
+          case 8 : itype = FRVBF_INSN_CKRA; goto extract_sfmt_ckra;
+          case 9 : itype = FRVBF_INSN_CKNC; goto extract_sfmt_ckeq;
+          case 10 : itype = FRVBF_INSN_CKNV; goto extract_sfmt_ckeq;
+          case 11 : itype = FRVBF_INSN_CKGE; goto extract_sfmt_ckeq;
+          case 12 : itype = FRVBF_INSN_CKNE; goto extract_sfmt_ckeq;
+          case 13 : itype = FRVBF_INSN_CKHI; goto extract_sfmt_ckeq;
+          case 14 : itype = FRVBF_INSN_CKP; goto extract_sfmt_ckeq;
+          case 15 : itype = FRVBF_INSN_CKGT; goto extract_sfmt_ckeq;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 9 :
+        {
+          unsigned int val = (((insn >> 27) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_FCKNO; goto extract_sfmt_fckra;
+          case 1 : itype = FRVBF_INSN_FCKU; goto extract_sfmt_fckne;
+          case 2 : itype = FRVBF_INSN_FCKGT; goto extract_sfmt_fckne;
+          case 3 : itype = FRVBF_INSN_FCKUG; goto extract_sfmt_fckne;
+          case 4 : itype = FRVBF_INSN_FCKLT; goto extract_sfmt_fckne;
+          case 5 : itype = FRVBF_INSN_FCKUL; goto extract_sfmt_fckne;
+          case 6 : itype = FRVBF_INSN_FCKLG; goto extract_sfmt_fckne;
+          case 7 : itype = FRVBF_INSN_FCKNE; goto extract_sfmt_fckne;
+          case 8 : itype = FRVBF_INSN_FCKEQ; goto extract_sfmt_fckne;
+          case 9 : itype = FRVBF_INSN_FCKUE; goto extract_sfmt_fckne;
+          case 10 : itype = FRVBF_INSN_FCKGE; goto extract_sfmt_fckne;
+          case 11 : itype = FRVBF_INSN_FCKUGE; goto extract_sfmt_fckne;
+          case 12 : itype = FRVBF_INSN_FCKLE; goto extract_sfmt_fckne;
+          case 13 : itype = FRVBF_INSN_FCKULE; goto extract_sfmt_fckne;
+          case 14 : itype = FRVBF_INSN_FCKO; goto extract_sfmt_fckne;
+          case 15 : itype = FRVBF_INSN_FCKRA; goto extract_sfmt_fckra;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 10 :
+        {
+          unsigned int val = (((insn >> 6) & (31 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CLRGR; goto extract_sfmt_clrgr;
+          case 1 : itype = FRVBF_INSN_CLRGA; goto extract_sfmt_rei;
+          case 2 : itype = FRVBF_INSN_CLRFR; goto extract_sfmt_clrfr;
+          case 3 : itype = FRVBF_INSN_CLRFA; goto extract_sfmt_rei;
+          case 4 : itype = FRVBF_INSN_COMMITGR; goto extract_sfmt_clrgr;
+          case 5 : itype = FRVBF_INSN_COMMITGA; goto extract_sfmt_rei;
+          case 6 : itype = FRVBF_INSN_COMMITFR; goto extract_sfmt_clrfr;
+          case 7 : itype = FRVBF_INSN_COMMITFA; goto extract_sfmt_rei;
+          case 8 : itype = FRVBF_INSN_ANDCR; goto extract_sfmt_andcr;
+          case 9 : itype = FRVBF_INSN_ORCR; goto extract_sfmt_andcr;
+          case 10 : itype = FRVBF_INSN_XORCR; goto extract_sfmt_andcr;
+          case 11 : itype = FRVBF_INSN_NOTCR; goto extract_sfmt_notcr;
+          case 12 : itype = FRVBF_INSN_NANDCR; goto extract_sfmt_andcr;
+          case 13 : itype = FRVBF_INSN_NORCR; goto extract_sfmt_andcr;
+          case 16 : itype = FRVBF_INSN_ANDNCR; goto extract_sfmt_andcr;
+          case 17 : itype = FRVBF_INSN_ORNCR; goto extract_sfmt_andcr;
+          case 20 : itype = FRVBF_INSN_NANDNCR; goto extract_sfmt_andcr;
+          case 21 : itype = FRVBF_INSN_NORNCR; goto extract_sfmt_andcr;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 11 : itype = FRVBF_INSN_SCAN; goto extract_sfmt_add;
+      case 12 :
+        {
+          unsigned int val = (((insn >> 25) & (1 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_JMPL; goto extract_sfmt_jmpl;
+          case 1 : itype = FRVBF_INSN_CALLL; goto extract_sfmt_jmpl;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 13 :
+        {
+          unsigned int val = (((insn >> 25) & (1 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_JMPIL; goto extract_sfmt_jmpil;
+          case 1 : itype = FRVBF_INSN_CALLIL; goto extract_sfmt_jmpil;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 14 :
+        {
+          unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 14) & (1 << 1)) | ((insn >> 13) & (1 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_BNOLR; goto extract_sfmt_bnolr;
+          case 1 :
+            {
+              unsigned int val = (((insn >> 14) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_BCTRLR; goto extract_sfmt_bctrlr;
+              case 1 : itype = FRVBF_INSN_BCNOLR; goto extract_sfmt_bcnolr;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 2 : itype = FRVBF_INSN_FBNOLR; goto extract_sfmt_bnolr;
+          case 3 : itype = FRVBF_INSN_FCBNOLR; goto extract_sfmt_bcnolr;
+          case 4 : itype = FRVBF_INSN_BCLR; goto extract_sfmt_beqlr;
+          case 5 : itype = FRVBF_INSN_BCCLR; goto extract_sfmt_bceqlr;
+          case 6 : itype = FRVBF_INSN_FBULR; goto extract_sfmt_fbeqlr;
+          case 7 : itype = FRVBF_INSN_FCBULR; goto extract_sfmt_fcbeqlr;
+          case 8 : itype = FRVBF_INSN_BVLR; goto extract_sfmt_beqlr;
+          case 9 : itype = FRVBF_INSN_BCVLR; goto extract_sfmt_bceqlr;
+          case 10 : itype = FRVBF_INSN_FBGTLR; goto extract_sfmt_fbeqlr;
+          case 11 : itype = FRVBF_INSN_FCBGTLR; goto extract_sfmt_fcbeqlr;
+          case 12 : itype = FRVBF_INSN_BLTLR; goto extract_sfmt_beqlr;
+          case 13 : itype = FRVBF_INSN_BCLTLR; goto extract_sfmt_bceqlr;
+          case 14 : itype = FRVBF_INSN_FBUGLR; goto extract_sfmt_fbeqlr;
+          case 15 : itype = FRVBF_INSN_FCBUGLR; goto extract_sfmt_fcbeqlr;
+          case 16 : itype = FRVBF_INSN_BEQLR; goto extract_sfmt_beqlr;
+          case 17 : itype = FRVBF_INSN_BCEQLR; goto extract_sfmt_bceqlr;
+          case 18 : itype = FRVBF_INSN_FBLTLR; goto extract_sfmt_fbeqlr;
+          case 19 : itype = FRVBF_INSN_FCBLTLR; goto extract_sfmt_fcbeqlr;
+          case 20 : itype = FRVBF_INSN_BLSLR; goto extract_sfmt_beqlr;
+          case 21 : itype = FRVBF_INSN_BCLSLR; goto extract_sfmt_bceqlr;
+          case 22 : itype = FRVBF_INSN_FBULLR; goto extract_sfmt_fbeqlr;
+          case 23 : itype = FRVBF_INSN_FCBULLR; goto extract_sfmt_fcbeqlr;
+          case 24 : itype = FRVBF_INSN_BNLR; goto extract_sfmt_beqlr;
+          case 25 : itype = FRVBF_INSN_BCNLR; goto extract_sfmt_bceqlr;
+          case 26 : itype = FRVBF_INSN_FBLGLR; goto extract_sfmt_fbeqlr;
+          case 27 : itype = FRVBF_INSN_FCBLGLR; goto extract_sfmt_fcbeqlr;
+          case 28 : itype = FRVBF_INSN_BLELR; goto extract_sfmt_beqlr;
+          case 29 : itype = FRVBF_INSN_BCLELR; goto extract_sfmt_bceqlr;
+          case 30 : itype = FRVBF_INSN_FBNELR; goto extract_sfmt_fbeqlr;
+          case 31 : itype = FRVBF_INSN_FCBNELR; goto extract_sfmt_fcbeqlr;
+          case 32 : itype = FRVBF_INSN_BRALR; goto extract_sfmt_bralr;
+          case 33 : itype = FRVBF_INSN_BCRALR; goto extract_sfmt_bcralr;
+          case 34 : itype = FRVBF_INSN_FBEQLR; goto extract_sfmt_fbeqlr;
+          case 35 : itype = FRVBF_INSN_FCBEQLR; goto extract_sfmt_fcbeqlr;
+          case 36 : itype = FRVBF_INSN_BNCLR; goto extract_sfmt_beqlr;
+          case 37 : itype = FRVBF_INSN_BCNCLR; goto extract_sfmt_bceqlr;
+          case 38 : itype = FRVBF_INSN_FBUELR; goto extract_sfmt_fbeqlr;
+          case 39 : itype = FRVBF_INSN_FCBUELR; goto extract_sfmt_fcbeqlr;
+          case 40 : itype = FRVBF_INSN_BNVLR; goto extract_sfmt_beqlr;
+          case 41 : itype = FRVBF_INSN_BCNVLR; goto extract_sfmt_bceqlr;
+          case 42 : itype = FRVBF_INSN_FBGELR; goto extract_sfmt_fbeqlr;
+          case 43 : itype = FRVBF_INSN_FCBGELR; goto extract_sfmt_fcbeqlr;
+          case 44 : itype = FRVBF_INSN_BGELR; goto extract_sfmt_beqlr;
+          case 45 : itype = FRVBF_INSN_BCGELR; goto extract_sfmt_bceqlr;
+          case 46 : itype = FRVBF_INSN_FBUGELR; goto extract_sfmt_fbeqlr;
+          case 47 : itype = FRVBF_INSN_FCBUGELR; goto extract_sfmt_fcbeqlr;
+          case 48 : itype = FRVBF_INSN_BNELR; goto extract_sfmt_beqlr;
+          case 49 : itype = FRVBF_INSN_BCNELR; goto extract_sfmt_bceqlr;
+          case 50 : itype = FRVBF_INSN_FBLELR; goto extract_sfmt_fbeqlr;
+          case 51 : itype = FRVBF_INSN_FCBLELR; goto extract_sfmt_fcbeqlr;
+          case 52 : itype = FRVBF_INSN_BHILR; goto extract_sfmt_beqlr;
+          case 53 : itype = FRVBF_INSN_BCHILR; goto extract_sfmt_bceqlr;
+          case 54 : itype = FRVBF_INSN_FBULELR; goto extract_sfmt_fbeqlr;
+          case 55 : itype = FRVBF_INSN_FCBULELR; goto extract_sfmt_fcbeqlr;
+          case 56 : itype = FRVBF_INSN_BPLR; goto extract_sfmt_beqlr;
+          case 57 : itype = FRVBF_INSN_BCPLR; goto extract_sfmt_bceqlr;
+          case 58 : itype = FRVBF_INSN_FBOLR; goto extract_sfmt_fbeqlr;
+          case 59 : itype = FRVBF_INSN_FCBOLR; goto extract_sfmt_fcbeqlr;
+          case 60 : itype = FRVBF_INSN_BGTLR; goto extract_sfmt_beqlr;
+          case 61 : itype = FRVBF_INSN_BCGTLR; goto extract_sfmt_bceqlr;
+          case 62 : itype = FRVBF_INSN_FBRALR; goto extract_sfmt_bralr;
+          case 63 : itype = FRVBF_INSN_FCBRALR; goto extract_sfmt_bcralr;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 15 : itype = FRVBF_INSN_CALL; goto extract_sfmt_call;
+      case 16 : itype = FRVBF_INSN_ADDI; goto extract_sfmt_addi;
+      case 17 : itype = FRVBF_INSN_ADDICC; goto extract_sfmt_addicc;
+      case 18 : itype = FRVBF_INSN_ADDXI; goto extract_sfmt_addxi;
+      case 19 : itype = FRVBF_INSN_ADDXICC; goto extract_sfmt_addicc;
+      case 20 : itype = FRVBF_INSN_SUBI; goto extract_sfmt_addi;
+      case 21 : itype = FRVBF_INSN_SUBICC; goto extract_sfmt_addicc;
+      case 22 : itype = FRVBF_INSN_SUBXI; goto extract_sfmt_addxi;
+      case 23 : itype = FRVBF_INSN_SUBXICC; goto extract_sfmt_addicc;
+      case 24 : itype = FRVBF_INSN_SMULI; goto extract_sfmt_smuli;
+      case 25 : itype = FRVBF_INSN_SMULICC; goto extract_sfmt_smulicc;
+      case 26 : itype = FRVBF_INSN_UMULI; goto extract_sfmt_smuli;
+      case 27 : itype = FRVBF_INSN_UMULICC; goto extract_sfmt_smulicc;
+      case 28 :
+        {
+          unsigned int val = (((insn >> 27) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_TINO; goto extract_sfmt_rei;
+          case 1 : itype = FRVBF_INSN_TIC; goto extract_sfmt_tieq;
+          case 2 : itype = FRVBF_INSN_TIV; goto extract_sfmt_tieq;
+          case 3 : itype = FRVBF_INSN_TILT; goto extract_sfmt_tieq;
+          case 4 : itype = FRVBF_INSN_TIEQ; goto extract_sfmt_tieq;
+          case 5 : itype = FRVBF_INSN_TILS; goto extract_sfmt_tieq;
+          case 6 : itype = FRVBF_INSN_TIN; goto extract_sfmt_tieq;
+          case 7 : itype = FRVBF_INSN_TILE; goto extract_sfmt_tieq;
+          case 8 : itype = FRVBF_INSN_TIRA; goto extract_sfmt_tira;
+          case 9 : itype = FRVBF_INSN_TINC; goto extract_sfmt_tieq;
+          case 10 : itype = FRVBF_INSN_TINV; goto extract_sfmt_tieq;
+          case 11 : itype = FRVBF_INSN_TIGE; goto extract_sfmt_tieq;
+          case 12 : itype = FRVBF_INSN_TINE; goto extract_sfmt_tieq;
+          case 13 : itype = FRVBF_INSN_TIHI; goto extract_sfmt_tieq;
+          case 14 : itype = FRVBF_INSN_TIP; goto extract_sfmt_tieq;
+          case 15 : itype = FRVBF_INSN_TIGT; goto extract_sfmt_tieq;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 29 :
+        {
+          unsigned int val = (((insn >> 27) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_FTINO; goto extract_sfmt_rei;
+          case 1 : itype = FRVBF_INSN_FTIU; goto extract_sfmt_ftine;
+          case 2 : itype = FRVBF_INSN_FTIGT; goto extract_sfmt_ftine;
+          case 3 : itype = FRVBF_INSN_FTIUG; goto extract_sfmt_ftine;
+          case 4 : itype = FRVBF_INSN_FTILT; goto extract_sfmt_ftine;
+          case 5 : itype = FRVBF_INSN_FTIUL; goto extract_sfmt_ftine;
+          case 6 : itype = FRVBF_INSN_FTILG; goto extract_sfmt_ftine;
+          case 7 : itype = FRVBF_INSN_FTINE; goto extract_sfmt_ftine;
+          case 8 : itype = FRVBF_INSN_FTIEQ; goto extract_sfmt_ftine;
+          case 9 : itype = FRVBF_INSN_FTIUE; goto extract_sfmt_ftine;
+          case 10 : itype = FRVBF_INSN_FTIGE; goto extract_sfmt_ftine;
+          case 11 : itype = FRVBF_INSN_FTIUGE; goto extract_sfmt_ftine;
+          case 12 : itype = FRVBF_INSN_FTILE; goto extract_sfmt_ftine;
+          case 13 : itype = FRVBF_INSN_FTIULE; goto extract_sfmt_ftine;
+          case 14 : itype = FRVBF_INSN_FTIO; goto extract_sfmt_ftine;
+          case 15 : itype = FRVBF_INSN_FTIRA; goto extract_sfmt_tira;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 30 : itype = FRVBF_INSN_SDIVI; goto extract_sfmt_sdivi;
+      case 31 : itype = FRVBF_INSN_UDIVI; goto extract_sfmt_sdivi;
+      case 32 : itype = FRVBF_INSN_ANDI; goto extract_sfmt_addi;
+      case 33 : itype = FRVBF_INSN_ANDICC; goto extract_sfmt_andicc;
+      case 34 : itype = FRVBF_INSN_ORI; goto extract_sfmt_addi;
+      case 35 : itype = FRVBF_INSN_ORICC; goto extract_sfmt_andicc;
+      case 36 : itype = FRVBF_INSN_XORI; goto extract_sfmt_addi;
+      case 37 : itype = FRVBF_INSN_XORICC; goto extract_sfmt_andicc;
+      case 40 : itype = FRVBF_INSN_SLLI; goto extract_sfmt_addi;
+      case 41 : itype = FRVBF_INSN_SLLICC; goto extract_sfmt_addicc;
+      case 42 : itype = FRVBF_INSN_SRLI; goto extract_sfmt_addi;
+      case 43 : itype = FRVBF_INSN_SRLICC; goto extract_sfmt_addicc;
+      case 44 : itype = FRVBF_INSN_SRAI; goto extract_sfmt_addi;
+      case 45 : itype = FRVBF_INSN_SRAICC; goto extract_sfmt_addicc;
+      case 46 : itype = FRVBF_INSN_NSDIVI; goto extract_sfmt_sdivi;
+      case 47 : itype = FRVBF_INSN_NUDIVI; goto extract_sfmt_sdivi;
+      case 48 : itype = FRVBF_INSN_LDSBI; goto extract_sfmt_ldsbi;
+      case 49 : itype = FRVBF_INSN_LDSHI; goto extract_sfmt_ldsbi;
+      case 50 : itype = FRVBF_INSN_LDI; goto extract_sfmt_ldsbi;
+      case 51 : itype = FRVBF_INSN_LDDI; goto extract_sfmt_lddi;
+      case 52 : itype = FRVBF_INSN_LDQI; goto extract_sfmt_ldqi;
+      case 53 : itype = FRVBF_INSN_LDUBI; goto extract_sfmt_ldsbi;
+      case 54 : itype = FRVBF_INSN_LDUHI; goto extract_sfmt_ldsbi;
+      case 55 : itype = FRVBF_INSN_REI; goto extract_sfmt_rei;
+      case 56 : itype = FRVBF_INSN_LDBFI; goto extract_sfmt_ldbfi;
+      case 57 : itype = FRVBF_INSN_LDHFI; goto extract_sfmt_ldbfi;
+      case 58 : itype = FRVBF_INSN_LDFI; goto extract_sfmt_ldbfi;
+      case 59 : itype = FRVBF_INSN_LDDFI; goto extract_sfmt_lddfi;
+      case 60 : itype = FRVBF_INSN_LDQFI; goto extract_sfmt_ldqfi;
+      case 61 : itype = FRVBF_INSN_SETLO; goto extract_sfmt_setlo;
+      case 62 : itype = FRVBF_INSN_SETHI; goto extract_sfmt_sethi;
+      case 63 : itype = FRVBF_INSN_SETLOS; goto extract_sfmt_setlos;
+      case 64 : itype = FRVBF_INSN_NLDSBI; goto extract_sfmt_nldsbi;
+      case 65 : itype = FRVBF_INSN_NLDUBI; goto extract_sfmt_nldsbi;
+      case 66 : itype = FRVBF_INSN_NLDSHI; goto extract_sfmt_nldsbi;
+      case 67 : itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi;
+      case 68 : itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi;
+      case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi;
+      case 70 : itype = FRVBF_INSN_NLDQI; goto extract_sfmt_nldqi;
+      case 71 : itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi;
+      case 72 : itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi;
+      case 73 : itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi;
+      case 74 : itype = FRVBF_INSN_NLDFI; goto extract_sfmt_nldbfi;
+      case 75 : itype = FRVBF_INSN_NLDDFI; goto extract_sfmt_nlddfi;
+      case 76 : itype = FRVBF_INSN_NLDQFI; goto extract_sfmt_nldqfi;
+      case 77 : itype = FRVBF_INSN_SWAPI; goto extract_sfmt_swapi;
+      case 78 : itype = FRVBF_INSN_STBFI; goto extract_sfmt_stbfi;
+      case 79 : itype = FRVBF_INSN_STHFI; goto extract_sfmt_stbfi;
+      case 80 : itype = FRVBF_INSN_STBI; goto extract_sfmt_stbi;
+      case 81 : itype = FRVBF_INSN_STHI; goto extract_sfmt_stbi;
+      case 82 : itype = FRVBF_INSN_STI; goto extract_sfmt_stbi;
+      case 83 : itype = FRVBF_INSN_STDI; goto extract_sfmt_stdi;
+      case 84 : itype = FRVBF_INSN_STQI; goto extract_sfmt_ldqi;
+      case 85 : itype = FRVBF_INSN_STFI; goto extract_sfmt_stbfi;
+      case 86 : itype = FRVBF_INSN_STDFI; goto extract_sfmt_stdfi;
+      case 87 : itype = FRVBF_INSN_STQFI; goto extract_sfmt_ldqfi;
+      case 88 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CADD; goto extract_sfmt_cadd;
+          case 1 : itype = FRVBF_INSN_CSUB; goto extract_sfmt_cadd;
+          case 2 : itype = FRVBF_INSN_CSMUL; goto extract_sfmt_csmul;
+          case 3 : itype = FRVBF_INSN_CSDIV; goto extract_sfmt_csdiv;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 89 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CADDCC; goto extract_sfmt_caddcc;
+          case 1 : itype = FRVBF_INSN_CSUBCC; goto extract_sfmt_caddcc;
+          case 2 : itype = FRVBF_INSN_CSMULCC; goto extract_sfmt_csmulcc;
+          case 3 : itype = FRVBF_INSN_CUDIV; goto extract_sfmt_csdiv;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 90 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CAND; goto extract_sfmt_cadd;
+          case 1 : itype = FRVBF_INSN_COR; goto extract_sfmt_cadd;
+          case 2 : itype = FRVBF_INSN_CXOR; goto extract_sfmt_cadd;
+          case 3 : itype = FRVBF_INSN_CNOT; goto extract_sfmt_cnot;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 91 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CANDCC; goto extract_sfmt_caddcc;
+          case 1 : itype = FRVBF_INSN_CORCC; goto extract_sfmt_caddcc;
+          case 2 : itype = FRVBF_INSN_CXORCC; goto extract_sfmt_caddcc;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 92 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CSLL; goto extract_sfmt_cadd;
+          case 1 : itype = FRVBF_INSN_CSRL; goto extract_sfmt_cadd;
+          case 2 : itype = FRVBF_INSN_CSRA; goto extract_sfmt_cadd;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 93 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CSLLCC; goto extract_sfmt_caddcc;
+          case 1 : itype = FRVBF_INSN_CSRLCC; goto extract_sfmt_caddcc;
+          case 2 : itype = FRVBF_INSN_CSRACC; goto extract_sfmt_caddcc;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 94 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CLDSB; goto extract_sfmt_cldsb;
+          case 1 : itype = FRVBF_INSN_CLDUB; goto extract_sfmt_cldsb;
+          case 2 : itype = FRVBF_INSN_CLDSH; goto extract_sfmt_cldsb;
+          case 3 : itype = FRVBF_INSN_CLDUH; goto extract_sfmt_cldsb;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 95 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CLD; goto extract_sfmt_cldsb;
+          case 1 : itype = FRVBF_INSN_CLDD; goto extract_sfmt_cldd;
+          case 2 : itype = FRVBF_INSN_CLDQ; goto extract_sfmt_cldq;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 96 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CLDBF; goto extract_sfmt_cldbf;
+          case 1 : itype = FRVBF_INSN_CLDHF; goto extract_sfmt_cldbf;
+          case 2 : itype = FRVBF_INSN_CLDF; goto extract_sfmt_cldbf;
+          case 3 : itype = FRVBF_INSN_CLDDF; goto extract_sfmt_clddf;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 97 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CLDSBU; goto extract_sfmt_cldsbu;
+          case 1 : itype = FRVBF_INSN_CLDUBU; goto extract_sfmt_cldsbu;
+          case 2 : itype = FRVBF_INSN_CLDSHU; goto extract_sfmt_cldsbu;
+          case 3 : itype = FRVBF_INSN_CLDUHU; goto extract_sfmt_cldsbu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 98 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CLDU; goto extract_sfmt_cldsbu;
+          case 1 : itype = FRVBF_INSN_CLDDU; goto extract_sfmt_clddu;
+          case 2 : itype = FRVBF_INSN_CLDQU; goto extract_sfmt_cldqu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 99 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CLDBFU; goto extract_sfmt_cldbfu;
+          case 1 : itype = FRVBF_INSN_CLDHFU; goto extract_sfmt_cldbfu;
+          case 2 : itype = FRVBF_INSN_CLDFU; goto extract_sfmt_cldbfu;
+          case 3 : itype = FRVBF_INSN_CLDDFU; goto extract_sfmt_clddfu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 100 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CSTB; goto extract_sfmt_cstb;
+          case 1 : itype = FRVBF_INSN_CSTH; goto extract_sfmt_cstb;
+          case 2 : itype = FRVBF_INSN_CST; goto extract_sfmt_cstb;
+          case 3 : itype = FRVBF_INSN_CSTD; goto extract_sfmt_cstd;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 101 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CSTQ; goto extract_sfmt_cldq;
+          case 2 : itype = FRVBF_INSN_CSWAP; goto extract_sfmt_cswap;
+          case 3 : itype = FRVBF_INSN_CSCAN; goto extract_sfmt_cadd;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 102 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CSTBF; goto extract_sfmt_cstbf;
+          case 1 : itype = FRVBF_INSN_CSTHF; goto extract_sfmt_cstbf;
+          case 2 : itype = FRVBF_INSN_CSTF; goto extract_sfmt_cstbf;
+          case 3 : itype = FRVBF_INSN_CSTDF; goto extract_sfmt_cstdf;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 103 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CSTBU; goto extract_sfmt_cstbu;
+          case 1 : itype = FRVBF_INSN_CSTHU; goto extract_sfmt_cstbu;
+          case 2 : itype = FRVBF_INSN_CSTU; goto extract_sfmt_cstbu;
+          case 3 : itype = FRVBF_INSN_CSTDU; goto extract_sfmt_cstdu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 104 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CSTBFU; goto extract_sfmt_cstbfu;
+          case 1 : itype = FRVBF_INSN_CSTHFU; goto extract_sfmt_cstbfu;
+          case 2 : itype = FRVBF_INSN_CSTFU; goto extract_sfmt_cstbfu;
+          case 3 : itype = FRVBF_INSN_CSTDFU; goto extract_sfmt_cstdfu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 105 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMOVGF; goto extract_sfmt_cmovgf;
+          case 1 : itype = FRVBF_INSN_CMOVGFD; goto extract_sfmt_cmovgfd;
+          case 2 : itype = FRVBF_INSN_CMOVFG; goto extract_sfmt_cmovfg;
+          case 3 : itype = FRVBF_INSN_CMOVFGD; goto extract_sfmt_cmovfgd;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 106 :
+        {
+          unsigned int val = (((insn >> 26) & (15 << 1)) | ((insn >> 6) & (1 << 0)));
+          switch (val)
+          {
+          case 0 :
+            {
+              unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 7) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : /* fall through */
+              case 2 : itype = FRVBF_INSN_CCKNO; goto extract_sfmt_cckra;
+              case 1 : itype = FRVBF_INSN_CJMPL; goto extract_sfmt_cjmpl;
+              case 3 : itype = FRVBF_INSN_CCALLL; goto extract_sfmt_cjmpl;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 1 : itype = FRVBF_INSN_CFCKNO; goto extract_sfmt_cfckra;
+          case 2 : itype = FRVBF_INSN_CCKC; goto extract_sfmt_cckeq;
+          case 3 : itype = FRVBF_INSN_CFCKU; goto extract_sfmt_cfckne;
+          case 4 : itype = FRVBF_INSN_CCKV; goto extract_sfmt_cckeq;
+          case 5 : itype = FRVBF_INSN_CFCKGT; goto extract_sfmt_cfckne;
+          case 6 : itype = FRVBF_INSN_CCKLT; goto extract_sfmt_cckeq;
+          case 7 : itype = FRVBF_INSN_CFCKUG; goto extract_sfmt_cfckne;
+          case 8 : itype = FRVBF_INSN_CCKEQ; goto extract_sfmt_cckeq;
+          case 9 : itype = FRVBF_INSN_CFCKLT; goto extract_sfmt_cfckne;
+          case 10 : itype = FRVBF_INSN_CCKLS; goto extract_sfmt_cckeq;
+          case 11 : itype = FRVBF_INSN_CFCKUL; goto extract_sfmt_cfckne;
+          case 12 : itype = FRVBF_INSN_CCKN; goto extract_sfmt_cckeq;
+          case 13 : itype = FRVBF_INSN_CFCKLG; goto extract_sfmt_cfckne;
+          case 14 : itype = FRVBF_INSN_CCKLE; goto extract_sfmt_cckeq;
+          case 15 : itype = FRVBF_INSN_CFCKNE; goto extract_sfmt_cfckne;
+          case 16 : itype = FRVBF_INSN_CCKRA; goto extract_sfmt_cckra;
+          case 17 : itype = FRVBF_INSN_CFCKEQ; goto extract_sfmt_cfckne;
+          case 18 : itype = FRVBF_INSN_CCKNC; goto extract_sfmt_cckeq;
+          case 19 : itype = FRVBF_INSN_CFCKUE; goto extract_sfmt_cfckne;
+          case 20 : itype = FRVBF_INSN_CCKNV; goto extract_sfmt_cckeq;
+          case 21 : itype = FRVBF_INSN_CFCKGE; goto extract_sfmt_cfckne;
+          case 22 : itype = FRVBF_INSN_CCKGE; goto extract_sfmt_cckeq;
+          case 23 : itype = FRVBF_INSN_CFCKUGE; goto extract_sfmt_cfckne;
+          case 24 : itype = FRVBF_INSN_CCKNE; goto extract_sfmt_cckeq;
+          case 25 : itype = FRVBF_INSN_CFCKLE; goto extract_sfmt_cfckne;
+          case 26 : itype = FRVBF_INSN_CCKHI; goto extract_sfmt_cckeq;
+          case 27 : itype = FRVBF_INSN_CFCKULE; goto extract_sfmt_cfckne;
+          case 28 : itype = FRVBF_INSN_CCKP; goto extract_sfmt_cckeq;
+          case 29 : itype = FRVBF_INSN_CFCKO; goto extract_sfmt_cfckne;
+          case 30 : itype = FRVBF_INSN_CCKGT; goto extract_sfmt_cckeq;
+          case 31 : itype = FRVBF_INSN_CFCKRA; goto extract_sfmt_cfckra;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 107 :
+        {
+          unsigned int val = (((insn >> 6) & (1 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CFITOS; goto extract_sfmt_cfitos;
+          case 1 : itype = FRVBF_INSN_CFSTOI; goto extract_sfmt_cfstoi;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 108 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CFMOVS; goto extract_sfmt_cfmovs;
+          case 1 : itype = FRVBF_INSN_CFNEGS; goto extract_sfmt_cfmovs;
+          case 2 : itype = FRVBF_INSN_CFABSS; goto extract_sfmt_cfmovs;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 109 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CFADDS; goto extract_sfmt_cfadds;
+          case 1 : itype = FRVBF_INSN_CFSUBS; goto extract_sfmt_cfadds;
+          case 2 : itype = FRVBF_INSN_CFCMPS; goto extract_sfmt_cfcmps;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 110 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CFMULS; goto extract_sfmt_cfadds;
+          case 1 : itype = FRVBF_INSN_CFDIVS; goto extract_sfmt_cfadds;
+          case 2 : itype = FRVBF_INSN_CFSQRTS; goto extract_sfmt_cfmovs;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 111 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CFMADDS; goto extract_sfmt_cfmadds;
+          case 1 : itype = FRVBF_INSN_CFMSUBS; goto extract_sfmt_cfmadds;
+          case 2 : itype = FRVBF_INSN_CFMAS; goto extract_sfmt_cfmas;
+          case 3 : itype = FRVBF_INSN_CFMSS; goto extract_sfmt_cfmas;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 112 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMAND; goto extract_sfmt_cmand;
+          case 1 : itype = FRVBF_INSN_CMOR; goto extract_sfmt_cmand;
+          case 2 : itype = FRVBF_INSN_CMXOR; goto extract_sfmt_cmand;
+          case 3 : itype = FRVBF_INSN_CMNOT; goto extract_sfmt_cmnot;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 113 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMADDHSS; goto extract_sfmt_cmaddhss;
+          case 1 : itype = FRVBF_INSN_CMADDHUS; goto extract_sfmt_cmaddhss;
+          case 2 : itype = FRVBF_INSN_CMSUBHSS; goto extract_sfmt_cmaddhss;
+          case 3 : itype = FRVBF_INSN_CMSUBHUS; goto extract_sfmt_cmaddhss;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 114 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMMULHS; goto extract_sfmt_cmmulhs;
+          case 1 : itype = FRVBF_INSN_CMMULHU; goto extract_sfmt_cmmulhs;
+          case 2 : itype = FRVBF_INSN_CMMACHS; goto extract_sfmt_cmmachs;
+          case 3 : itype = FRVBF_INSN_CMMACHU; goto extract_sfmt_cmmachu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 115 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMQADDHSS; goto extract_sfmt_cmqaddhss;
+          case 1 : itype = FRVBF_INSN_CMQADDHUS; goto extract_sfmt_cmqaddhss;
+          case 2 : itype = FRVBF_INSN_CMQSUBHSS; goto extract_sfmt_cmqaddhss;
+          case 3 : itype = FRVBF_INSN_CMQSUBHUS; goto extract_sfmt_cmqaddhss;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 116 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMQMULHS; goto extract_sfmt_cmqmulhs;
+          case 1 : itype = FRVBF_INSN_CMQMULHU; goto extract_sfmt_cmqmulhs;
+          case 2 : itype = FRVBF_INSN_CMQMACHS; goto extract_sfmt_cmqmachs;
+          case 3 : itype = FRVBF_INSN_CMQMACHU; goto extract_sfmt_cmqmachu;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 117 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMCPXRS; goto extract_sfmt_cmcpxrs;
+          case 1 : itype = FRVBF_INSN_CMCPXRU; goto extract_sfmt_cmcpxrs;
+          case 2 : itype = FRVBF_INSN_CMCPXIS; goto extract_sfmt_cmcpxrs;
+          case 3 : itype = FRVBF_INSN_CMCPXIU; goto extract_sfmt_cmcpxrs;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 118 :
+        {
+          unsigned int val = (((insn >> 6) & (1 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMEXPDHW; goto extract_sfmt_cmexpdhw;
+          case 1 : itype = FRVBF_INSN_CMEXPDHD; goto extract_sfmt_cmexpdhd;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 119 :
+        {
+          unsigned int val = (((insn >> 6) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_CMBTOH; goto extract_sfmt_cmbtoh;
+          case 1 : itype = FRVBF_INSN_CMHTOB; goto extract_sfmt_cmhtob;
+          case 2 : itype = FRVBF_INSN_CMBTOHE; goto extract_sfmt_cmbtohe;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 120 :
+        {
+          unsigned int val = (((insn >> 7) & (1 << 4)) | ((insn >> 6) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs;
+          case 1 : itype = FRVBF_INSN_MQXMACXHS; goto extract_sfmt_mqmachs;
+          case 2 : itype = FRVBF_INSN_MQMACXHS; goto extract_sfmt_mqmachs;
+          case 4 : itype = FRVBF_INSN_MADDACCS; goto extract_sfmt_maddaccs;
+          case 5 : itype = FRVBF_INSN_MSUBACCS; goto extract_sfmt_maddaccs;
+          case 6 : itype = FRVBF_INSN_MDADDACCS; goto extract_sfmt_mdaddaccs;
+          case 7 : itype = FRVBF_INSN_MDSUBACCS; goto extract_sfmt_mdaddaccs;
+          case 8 : itype = FRVBF_INSN_MASACCS; goto extract_sfmt_masaccs;
+          case 9 : itype = FRVBF_INSN_MDASACCS; goto extract_sfmt_mdasaccs;
+          case 10 : itype = FRVBF_INSN_MABSHS; goto extract_sfmt_mabshs;
+          case 11 : itype = FRVBF_INSN_MDROTLI; goto extract_sfmt_mdrotli;
+          case 12 : itype = FRVBF_INSN_MCPLHI; goto extract_sfmt_mcplhi;
+          case 13 : itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli;
+          case 14 : itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi;
+          case 15 : itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths;
+          case 16 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos;
+          case 17 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh;
+          case 18 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis;
+          case 19 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih;
+          case 20 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets;
+          case 21 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 121 :
+        {
+          unsigned int val = (((insn >> 7) & (1 << 3)) | ((insn >> 6) & (7 << 0)));
+          switch (val)
+          {
+          case 0 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FITOS; goto extract_sfmt_fitos;
+              case 1 : itype = FRVBF_INSN_FMULS; goto extract_sfmt_fadds;
+              case 2 : itype = FRVBF_INSN_NFITOS; goto extract_sfmt_nfitos;
+              case 3 : itype = FRVBF_INSN_NFMULS; goto extract_sfmt_nfadds;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 1 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FSTOI; goto extract_sfmt_fstoi;
+              case 1 : itype = FRVBF_INSN_FDIVS; goto extract_sfmt_fadds;
+              case 2 : itype = FRVBF_INSN_NFSTOI; goto extract_sfmt_nfstoi;
+              case 3 : itype = FRVBF_INSN_NFDIVS; goto extract_sfmt_nfadds;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 2 :
+            {
+              unsigned int val = (((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FMOVS; goto extract_sfmt_fmovs;
+              case 1 : itype = FRVBF_INSN_FCMPS; goto extract_sfmt_fcmps;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 3 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FNEGS; goto extract_sfmt_fmovs;
+              case 1 : itype = FRVBF_INSN_FMADDS; goto extract_sfmt_fmadds;
+              case 3 : itype = FRVBF_INSN_NFMADDS; goto extract_sfmt_nfmadds;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 4 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FABSS; goto extract_sfmt_fmovs;
+              case 1 : itype = FRVBF_INSN_FMSUBS; goto extract_sfmt_fmadds;
+              case 3 : itype = FRVBF_INSN_NFMSUBS; goto extract_sfmt_nfmadds;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 5 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FSQRTS; goto extract_sfmt_fmovs;
+              case 1 : itype = FRVBF_INSN_FNOP; goto extract_sfmt_rei;
+              case 2 : itype = FRVBF_INSN_NFSQRTS; goto extract_sfmt_nfsqrts;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 6 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FADDS; goto extract_sfmt_fadds;
+              case 1 : itype = FRVBF_INSN_FMAS; goto extract_sfmt_fmas;
+              case 2 : itype = FRVBF_INSN_NFADDS; goto extract_sfmt_nfadds;
+              case 3 : itype = FRVBF_INSN_NFMAS; goto extract_sfmt_fmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 7 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FSUBS; goto extract_sfmt_fadds;
+              case 1 : itype = FRVBF_INSN_FMSS; goto extract_sfmt_fmas;
+              case 2 : itype = FRVBF_INSN_NFSUBS; goto extract_sfmt_nfadds;
+              case 3 : itype = FRVBF_INSN_NFMSS; goto extract_sfmt_fmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 8 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDITOS; goto extract_sfmt_fditos;
+              case 1 : itype = FRVBF_INSN_FDMULS; goto extract_sfmt_fmas;
+              case 2 : itype = FRVBF_INSN_NFDITOS; goto extract_sfmt_fditos;
+              case 3 : itype = FRVBF_INSN_NFDMULS; goto extract_sfmt_fmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 9 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDSTOI; goto extract_sfmt_fdstoi;
+              case 1 : itype = FRVBF_INSN_FDDIVS; goto extract_sfmt_fmas;
+              case 2 : itype = FRVBF_INSN_NFDSTOI; goto extract_sfmt_fdstoi;
+              case 3 : itype = FRVBF_INSN_NFDDIVS; goto extract_sfmt_fmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 10 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDMOVS; goto extract_sfmt_fdmovs;
+              case 1 : itype = FRVBF_INSN_FDCMPS; goto extract_sfmt_fdcmps;
+              case 3 : itype = FRVBF_INSN_NFDCMPS; goto extract_sfmt_nfdcmps;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 11 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDNEGS; goto extract_sfmt_fdmovs;
+              case 1 : itype = FRVBF_INSN_FDMADDS; goto extract_sfmt_fdmadds;
+              case 3 : itype = FRVBF_INSN_NFDMADDS; goto extract_sfmt_fdmadds;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 12 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDABSS; goto extract_sfmt_fdmovs;
+              case 1 : itype = FRVBF_INSN_FDMAS; goto extract_sfmt_fdmas;
+              case 3 : itype = FRVBF_INSN_NFDMAS; goto extract_sfmt_fdmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 13 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDSQRTS; goto extract_sfmt_fdmovs;
+              case 1 : itype = FRVBF_INSN_FDMSS; goto extract_sfmt_fdmas;
+              case 2 : itype = FRVBF_INSN_NFDSQRTS; goto extract_sfmt_fdmovs;
+              case 3 : itype = FRVBF_INSN_NFDMSS; goto extract_sfmt_fdmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 14 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDADDS; goto extract_sfmt_fmas;
+              case 1 : itype = FRVBF_INSN_FDSADS; goto extract_sfmt_fmas;
+              case 2 : itype = FRVBF_INSN_NFDADDS; goto extract_sfmt_fmas;
+              case 3 : itype = FRVBF_INSN_NFDSADS; goto extract_sfmt_fmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          case 15 :
+            {
+              unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
+              switch (val)
+              {
+              case 0 : itype = FRVBF_INSN_FDSUBS; goto extract_sfmt_fmas;
+              case 1 : itype = FRVBF_INSN_FDMULCS; goto extract_sfmt_fmas;
+              case 2 : itype = FRVBF_INSN_NFDSUBS; goto extract_sfmt_fmas;
+              case 3 : itype = FRVBF_INSN_NFDMULCS; goto extract_sfmt_fmas;
+              default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              }
+            }
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 122 :
+        {
+          unsigned int val = (((insn >> 6) & (15 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_FITOD; goto extract_sfmt_fitod;
+          case 1 : itype = FRVBF_INSN_FDTOI; goto extract_sfmt_fdtoi;
+          case 2 : itype = FRVBF_INSN_FMOVD; goto extract_sfmt_fmovd;
+          case 3 : itype = FRVBF_INSN_FNEGD; goto extract_sfmt_fmovd;
+          case 4 : itype = FRVBF_INSN_FABSD; goto extract_sfmt_fmovd;
+          case 5 : itype = FRVBF_INSN_FSQRTD; goto extract_sfmt_fmovd;
+          case 6 : itype = FRVBF_INSN_FADDD; goto extract_sfmt_faddd;
+          case 7 : itype = FRVBF_INSN_FSUBD; goto extract_sfmt_faddd;
+          case 8 : itype = FRVBF_INSN_FMULD; goto extract_sfmt_faddd;
+          case 9 : itype = FRVBF_INSN_FDIVD; goto extract_sfmt_faddd;
+          case 10 : itype = FRVBF_INSN_FCMPD; goto extract_sfmt_fcmpd;
+          case 11 : itype = FRVBF_INSN_FMADDD; goto extract_sfmt_fmaddd;
+          case 12 : itype = FRVBF_INSN_FMSUBD; goto extract_sfmt_fmaddd;
+          case 14 : itype = FRVBF_INSN_FMAD; goto extract_sfmt_fmas;
+          case 15 : itype = FRVBF_INSN_FMSD; goto extract_sfmt_fmas;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 123 :
+        {
+          unsigned int val = (((insn >> 6) & (63 << 0)));
+          switch (val)
+          {
+          case 0 : itype = FRVBF_INSN_MAND; goto extract_sfmt_mand;
+          case 1 : itype = FRVBF_INSN_MOR; goto extract_sfmt_mand;
+          case 2 : itype = FRVBF_INSN_MXOR; goto extract_sfmt_mand;
+          case 3 : itype = FRVBF_INSN_MNOT; goto extract_sfmt_mnot;
+          case 4 : itype = FRVBF_INSN_MROTLI; goto extract_sfmt_mrotli;
+          case 5 : itype = FRVBF_INSN_MROTRI; goto extract_sfmt_mrotli;
+          case 6 : itype = FRVBF_INSN_MWCUT; goto extract_sfmt_mwcut;
+          case 7 : itype = FRVBF_INSN_MWCUTI; goto extract_sfmt_mwcuti;
+          case 8 : itype = FRVBF_INSN_MAVEH; goto extract_sfmt_mand;
+          case 9 : itype = FRVBF_INSN_MSLLHI; goto extract_sfmt_msllhi;
+          case 10 : itype = FRVBF_INSN_MSRLHI; goto extract_sfmt_msllhi;
+          case 11 : itype = FRVBF_INSN_MSRAHI; goto extract_sfmt_msllhi;
+          case 12 : itype = FRVBF_INSN_MSATHS; goto extract_sfmt_msaths;
+          case 13 : itype = FRVBF_INSN_MSATHU; goto extract_sfmt_msaths;
+          case 14 : itype = FRVBF_INSN_MCMPSH; goto extract_sfmt_mcmpsh;
+          case 15 : itype = FRVBF_INSN_MCMPUH; goto extract_sfmt_mcmpsh;
+          case 16 : itype = FRVBF_INSN_MADDHSS; goto extract_sfmt_msaths;
+          case 17 : itype = FRVBF_INSN_MADDHUS; goto extract_sfmt_msaths;
+          case 18 : itype = FRVBF_INSN_MSUBHSS; goto extract_sfmt_msaths;
+          case 19 : itype = FRVBF_INSN_MSUBHUS; goto extract_sfmt_msaths;
+          case 20 : itype = FRVBF_INSN_MMULHS; goto extract_sfmt_mmulhs;
+          case 21 : itype = FRVBF_INSN_MMULHU; goto extract_sfmt_mmulhs;
+          case 22 : itype = FRVBF_INSN_MMACHS; goto extract_sfmt_mmachs;
+          case 23 : itype = FRVBF_INSN_MMACHU; goto extract_sfmt_mmachu;
+          case 24 : itype = FRVBF_INSN_MQADDHSS; goto extract_sfmt_mqsaths;
+          case 25 : itype = FRVBF_INSN_MQADDHUS; goto extract_sfmt_mqsaths;
+          case 26 : itype = FRVBF_INSN_MQSUBHSS; goto extract_sfmt_mqsaths;
+          case 27 : itype = FRVBF_INSN_MQSUBHUS; goto extract_sfmt_mqsaths;
+          case 28 : itype = FRVBF_INSN_MQMULHS; goto extract_sfmt_mqmulhs;
+          case 29 : itype = FRVBF_INSN_MQMULHU; goto extract_sfmt_mqmulhs;
+          case 30 : itype = FRVBF_INSN_MQMACHS; goto extract_sfmt_mqmachs;
+          case 31 : itype = FRVBF_INSN_MQMACHU; goto extract_sfmt_mqmachu;
+          case 32 : itype = FRVBF_INSN_MCPXRS; goto extract_sfmt_mcpxrs;
+          case 33 : itype = FRVBF_INSN_MCPXRU; goto extract_sfmt_mcpxrs;
+          case 34 : itype = FRVBF_INSN_MCPXIS; goto extract_sfmt_mcpxrs;
+          case 35 : itype = FRVBF_INSN_MCPXIU; goto extract_sfmt_mcpxrs;
+          case 36 : itype = FRVBF_INSN_MQCPXRS; goto extract_sfmt_mqcpxrs;
+          case 37 : itype = FRVBF_INSN_MQCPXRU; goto extract_sfmt_mqcpxrs;
+          case 38 : itype = FRVBF_INSN_MQCPXIS; goto extract_sfmt_mqcpxrs;
+          case 39 : itype = FRVBF_INSN_MQCPXIU; goto extract_sfmt_mqcpxrs;
+          case 40 : itype = FRVBF_INSN_MMULXHS; goto extract_sfmt_mmulhs;
+          case 41 : itype = FRVBF_INSN_MMULXHU; goto extract_sfmt_mmulhs;
+          case 42 : itype = FRVBF_INSN_MQMULXHS; goto extract_sfmt_mqmulhs;
+          case 43 : itype = FRVBF_INSN_MQMULXHU; goto extract_sfmt_mqmulhs;
+          case 44 : itype = FRVBF_INSN_MCUT; goto extract_sfmt_mcut;
+          case 45 : itype = FRVBF_INSN_MCUTSS; goto extract_sfmt_mcut;
+          case 46 : itype = FRVBF_INSN_MCUTI; goto extract_sfmt_mcuti;
+          case 47 : itype = FRVBF_INSN_MCUTSSI; goto extract_sfmt_mcuti;
+          case 48 : itype = FRVBF_INSN_MMRDHS; goto extract_sfmt_mmachs;
+          case 49 : itype = FRVBF_INSN_MMRDHU; goto extract_sfmt_mmachu;
+          case 50 : itype = FRVBF_INSN_MEXPDHW; goto extract_sfmt_mexpdhw;
+          case 51 : itype = FRVBF_INSN_MEXPDHD; goto extract_sfmt_mexpdhd;
+          case 52 : itype = FRVBF_INSN_MPACKH; goto extract_sfmt_mpackh;
+          case 53 : itype = FRVBF_INSN_MUNPACKH; goto extract_sfmt_munpackh;
+          case 54 : itype = FRVBF_INSN_MDPACKH; goto extract_sfmt_mdpackh;
+          case 55 : itype = FRVBF_INSN_MDUNPACKH; goto extract_sfmt_mdunpackh;
+          case 56 : itype = FRVBF_INSN_MBTOH; goto extract_sfmt_mbtoh;
+          case 57 : itype = FRVBF_INSN_MHTOB; goto extract_sfmt_mhtob;
+          case 58 : itype = FRVBF_INSN_MBTOHE; goto extract_sfmt_mbtohe;
+          case 59 : itype = FRVBF_INSN_MCLRACC; goto extract_sfmt_mclracc;
+          case 60 : itype = FRVBF_INSN_MRDACC; goto extract_sfmt_mrdacc;
+          case 61 : itype = FRVBF_INSN_MWTACC; goto extract_sfmt_mwtacc;
+          case 62 : itype = FRVBF_INSN_MRDACCG; goto extract_sfmt_mrdaccg;
+          case 63 : itype = FRVBF_INSN_MWTACCG; goto extract_sfmt_mwtaccg;
+          default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 124 : itype = FRVBF_INSN_MCOP1; goto extract_sfmt_rei;
+      case 125 : itype = FRVBF_INSN_MCOP2; goto extract_sfmt_rei;
+      case 126 : itype = FRVBF_INSN_COP1; goto extract_sfmt_rei;
+      case 127 : itype = FRVBF_INSN_COP2; goto extract_sfmt_rei;
+      default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      }
+    }
+  }
+
+  /* The instruction has been decoded, now extract the fields.  */
+
+ extract_sfmt_empty:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_add:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_not:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not", "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sdiv:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sdiv", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_smul:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smul", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cadd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cadd", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cnot:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cnot", "f_CCi 0x%x", 'x', f_CCi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_csmul:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_csmul", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_csdiv:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_csdiv", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addcc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRk) = f_GRk;
+      FLD (out_ICCi_1) = f_ICCi_1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_andcc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRk) = f_GRk;
+      FLD (out_ICCi_1) = f_ICCi_1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_smulcc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smulcc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRdoublek) = f_GRk;
+      FLD (out_ICCi_1) = f_ICCi_1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_caddcc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_caddcc", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3));
+      FLD (out_GRk) = f_GRk;
+      FLD (out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_csmulcc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_csmulcc", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3));
+      FLD (out_GRdoublek) = f_GRk;
+      FLD (out_h_iccr_UQI_and__DFLT_index_of__DFLT_CCi_3) = ((FLD (f_CCi)) & (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addx:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_swapi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sdivi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_swapi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sdivi", "f_GRi 0x%x", 'x', f_GRi, "f_GRk 0x%x", 'x', f_GRk, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_smuli:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smuli.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smuli", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addicc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addicc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    INT f_s10;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_s10) = f_s10;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addicc", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRk) = f_GRk;
+      FLD (out_ICCi_1) = f_ICCi_1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_andicc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addicc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    INT f_s10;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_s10) = f_s10;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andicc", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRk) = f_GRk;
+      FLD (out_ICCi_1) = f_ICCi_1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_smulicc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    INT f_s10;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_s10) = f_s10;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smulicc", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRdoublek) = f_GRk;
+      FLD (out_ICCi_1) = f_ICCi_1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addxi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addicc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    INT f_s10;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_s10 = EXTRACT_LSB0_INT (insn, 32, 9, 10);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  FLD (f_s10) = f_s10;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addxi", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_1 0x%x", 'x', f_ICCi_1, "f_s10 0x%x", 'x', f_s10, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_ICCi_1) = f_ICCi_1;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmpb:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+    UINT f_GRi;
+    UINT f_ICCi_1;
+    UINT f_GRj;
+
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_ICCi_1 = EXTRACT_LSB0_UINT (insn, 32, 11, 2);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_ICCi_1) = f_ICCi_1;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_1 0x%x", 'x', f_ICCi_1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_ICCi_1) = f_ICCi_1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_setlo:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_setlo.f
+    UINT f_GRk;
+    UINT f_u16;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u16) = f_u16;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setlo", "f_u16 0x%x", 'x', f_u16, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_GRklo) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sethi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sethi.f
+    UINT f_GRk;
+    UINT f_u16;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_u16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u16) = f_u16;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sethi", "f_u16 0x%x", 'x', f_u16, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_GRkhi) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_setlos:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_setlos.f
+    UINT f_GRk;
+    INT f_s16;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_s16 = EXTRACT_LSB0_INT (insn, 32, 15, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_s16) = f_s16;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setlos", "f_s16 0x%x", 'x', f_s16, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldsb:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldbf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldbf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_CPRk) = f_CPRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_CPRk) = f_CPRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldsb:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldsb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldbf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldbf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldd", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lddf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lddc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_CPRk) = f_CPRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_CPRdoublek) = f_CPRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldd", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nlddf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldqf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldqc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_CPRk) = f_CPRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqc", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldq", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldqf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqf", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldsbu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsbu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldsbu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldsbu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldbfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldbfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldcu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_CPRk) = f_CPRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldcu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_CPRk) = f_CPRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldbfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldbfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lddu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nlddu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lddfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRdoublek) = f_FRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lddcu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_CPRk) = f_CPRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddcu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_CPRdoublek) = f_CPRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nlddfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRdoublek) = f_FRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldqu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldqu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldqfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldqcu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_CPRk) = f_CPRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqcu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_CPRk 0x%x", 'x', f_CPRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldqfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqfu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldsbi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_swapi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsbi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldbfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldbfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldsbi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_swapi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldsbi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldbfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldbfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lddi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smuli.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lddfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nlddi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smuli.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nlddfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nlddfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldqi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldqfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldqfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldqi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nldqfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqfi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stb:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stbf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CPRk) = f_CPRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stc", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CPRk) = f_CPRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rstb:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rstbf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_std:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRk) = f_GRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_std", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRdoublek) = f_GRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stdf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublek) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stdc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CPRk) = f_CPRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdc", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CPRdoublek) = f_CPRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rstd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRk) = f_GRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstd", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRdoublek) = f_GRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rstdf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublek) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stbu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_GRk) = f_GRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stbfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbfu", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stcu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CPRk) = f_CPRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stcu", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CPRk) = f_CPRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stdu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRk) = f_GRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdu", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRdoublek) = f_GRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stdfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdfu", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublek) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stdcu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+    UINT f_CPRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_CPRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CPRk) = f_CPRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdcu", "f_CPRk 0x%x", 'x', f_CPRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CPRdoublek) = f_CPRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stqu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stqu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cldsb:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldsb", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cldbf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldbf", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cldd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldd", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_clddf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clddf", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cldq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldq", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cldsbu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldsbu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cldbfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldbfu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_clddu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clddu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRdoublek) = f_GRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_clddfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clddfu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRdoublek) = f_FRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cldqu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cldqu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstb:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstb", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstbf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstbf", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstd", "f_CCi 0x%x", 'x', f_CCi, "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRdoublek) = f_GRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstdf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstdf", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRdoublek) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstbu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstbu", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_GRk) = f_GRk;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstbfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstbfu", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstdu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstdu", "f_CCi 0x%x", 'x', f_CCi, "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRdoublek) = f_GRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cstdfu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+    UINT f_FRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cstdfu", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRdoublek) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stbi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_swapi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbi", "f_GRi 0x%x", 'x', f_GRi, "f_GRk 0x%x", 'x', f_GRk, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stbfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbfi", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stdi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRk) = f_GRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdi", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRdoublek) = f_GRk;
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stdfi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+    UINT f_FRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdfi", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublek) = f_FRk;
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_swap:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_GRk) = f_GRk;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_swapi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_swapi.f
+    UINT f_GRk;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swapi", "f_GRi 0x%x", 'x', f_GRi, "f_GRk 0x%x", 'x', f_GRk, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRk) = f_GRk;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cswap:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cswap.f
+    UINT f_GRk;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_GRk) = f_GRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cswap", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_GRk) = f_GRk;
+      FLD (out_GRk) = f_GRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movgf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+    UINT f_FRk;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgf", "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movfg:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+    UINT f_FRk;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movfg", "f_FRk 0x%x", 'x', f_FRk, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (out_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movgfd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+    UINT f_FRk;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgfd", "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRj) = f_GRj;
+      FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1));
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movfgd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+    UINT f_FRk;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movfgd", "f_FRk 0x%x", 'x', f_FRk, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_GRj) = f_GRj;
+      FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movgfq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+    UINT f_FRk;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRj) = f_GRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgfq", "f_GRj 0x%x", 'x', f_GRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRj) = f_GRj;
+      FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1));
+      FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2) = ((FLD (f_GRj)) + (2));
+      FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3) = ((FLD (f_GRj)) + (3));
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movfgq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+    UINT f_FRk;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movfgq", "f_FRk 0x%x", 'x', f_FRk, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3));
+      FLD (out_GRj) = f_GRj;
+      FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1));
+      FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_2) = ((FLD (f_GRj)) + (2));
+      FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_3) = ((FLD (f_GRj)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmovgf:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovgf", "f_CCi 0x%x", 'x', f_CCi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmovfg:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovfg", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintk) = f_FRk;
+      FLD (out_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmovgfd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovgfd", "f_CCi 0x%x", 'x', f_CCi, "f_GRj 0x%x", 'x', f_GRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1));
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmovfgd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmovfgd", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_GRj) = f_GRj;
+      FLD (out_h_gr_USI_add__DFLT_index_of__DFLT_GRj_1) = ((FLD (f_GRj)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movgs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movgs.f
+    UINT f_spr_h;
+    UINT f_spr_l;
+    UINT f_GRj;
+    UINT f_spr;
+
+    f_spr_h = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_spr_l = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+{
+  f_spr = ((((f_spr_h) << (6))) | (f_spr_l));
+}
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRj) = f_GRj;
+  FLD (f_spr) = f_spr;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movgs", "f_GRj 0x%x", 'x', f_GRj, "f_spr 0x%x", 'x', f_spr, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRj) = f_GRj;
+      FLD (out_spr) = f_spr;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_movsg:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movsg.f
+    UINT f_spr_h;
+    UINT f_spr_l;
+    UINT f_GRj;
+    UINT f_spr;
+
+    f_spr_h = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_spr_l = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+{
+  f_spr = ((((f_spr_h) << (6))) | (f_spr_l));
+}
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_spr) = f_spr;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movsg", "f_spr 0x%x", 'x', f_spr, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_spr) = f_spr;
+      FLD (out_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bra:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fbne.f
+    UINT f_hint;
+    SI f_label16;
+
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hint) = f_hint;
+  FLD (i_label16) = f_label16;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra", "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bno:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fbne.f
+    UINT f_hint;
+    SI f_label16;
+
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hint) = f_hint;
+  FLD (i_label16) = f_label16;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bno", "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_beq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+    UINT f_ICCi_2;
+    UINT f_hint;
+    SI f_label16;
+
+    f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ICCi_2) = f_ICCi_2;
+  FLD (f_hint) = f_hint;
+  FLD (i_label16) = f_label16;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ICCi_2) = f_ICCi_2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fbne:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fbne.f
+    UINT f_FCCi_2;
+    UINT f_hint;
+    SI f_label16;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_label16 = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FCCi_2) = f_FCCi_2;
+  FLD (f_hint) = f_hint;
+  FLD (i_label16) = f_label16;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fbne", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_hint 0x%x", 'x', f_hint, "label16 0x%x", 'x', f_label16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FCCi_2) = f_FCCi_2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bctrlr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+    UINT f_hint;
+    UINT f_ccond;
+
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ccond) = f_ccond;
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bctrlr", "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_spr_USI_272) = 272;
+      FLD (in_h_spr_USI_273) = 273;
+      FLD (out_h_spr_USI_273) = 273;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bralr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+    UINT f_hint;
+
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bralr", "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_spr_USI_272) = 272;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bnolr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+    UINT f_hint;
+
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bnolr", "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_spr_USI_272) = 272;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_beqlr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+    UINT f_ICCi_2;
+    UINT f_hint;
+
+    f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ICCi_2) = f_ICCi_2;
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqlr", "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ICCi_2) = f_ICCi_2;
+      FLD (in_h_spr_USI_272) = 272;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fbeqlr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+    UINT f_FCCi_2;
+    UINT f_hint;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FCCi_2) = f_FCCi_2;
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fbeqlr", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FCCi_2) = f_FCCi_2;
+      FLD (in_h_spr_USI_272) = 272;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bcralr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+    UINT f_hint;
+    UINT f_ccond;
+
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ccond) = f_ccond;
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcralr", "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_spr_USI_272) = 272;
+      FLD (in_h_spr_USI_273) = 273;
+      FLD (out_h_spr_USI_273) = 273;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bcnolr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+    UINT f_hint;
+
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcnolr", "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_spr_USI_272) = 272;
+      FLD (in_h_spr_USI_273) = 273;
+      FLD (out_h_spr_USI_273) = 273;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bceqlr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+    UINT f_ICCi_2;
+    UINT f_hint;
+    UINT f_ccond;
+
+    f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ICCi_2) = f_ICCi_2;
+  FLD (f_ccond) = f_ccond;
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bceqlr", "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ICCi_2) = f_ICCi_2;
+      FLD (in_h_spr_USI_272) = 272;
+      FLD (in_h_spr_USI_273) = 273;
+      FLD (out_h_spr_USI_273) = 273;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fcbeqlr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+    UINT f_FCCi_2;
+    UINT f_hint;
+    UINT f_ccond;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
+    f_ccond = EXTRACT_LSB0_UINT (insn, 32, 12, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FCCi_2) = f_FCCi_2;
+  FLD (f_ccond) = f_ccond;
+  FLD (f_hint) = f_hint;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcbeqlr", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_ccond 0x%x", 'x', f_ccond, "f_hint 0x%x", 'x', f_hint, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FCCi_2) = f_FCCi_2;
+      FLD (in_h_spr_USI_272) = 272;
+      FLD (in_h_spr_USI_273) = 273;
+      FLD (out_h_spr_USI_273) = 273;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_jmpl:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+    UINT f_LI;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_LI = EXTRACT_LSB0_UINT (insn, 32, 25, 1);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_LI) = f_LI;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmpl", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_LI 0x%x", 'x', f_LI, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_jmpil:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+    UINT f_LI;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_LI = EXTRACT_LSB0_UINT (insn, 32, 25, 1);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_LI) = f_LI;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmpil", "f_GRi 0x%x", 'x', f_GRi, "f_LI 0x%x", 'x', f_LI, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_call:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_call.f
+    INT f_labelH6;
+    UINT f_labelL18;
+    INT f_label24;
+
+    f_labelH6 = EXTRACT_LSB0_INT (insn, 32, 30, 6);
+    f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18);
+{
+  f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc));
+}
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_label24) = f_label24;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_call", "label24 0x%x", 'x', f_label24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rett:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_rett.f
+    UINT f_debug;
+
+    f_debug = EXTRACT_LSB0_UINT (insn, 32, 25, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_debug) = f_debug;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rett", "f_debug 0x%x", 'x', f_debug, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rei:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rei", (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_tra:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ftne.f
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tra", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_h_spr_USI_1) = 1;
+      FLD (out_h_spr_USI_768) = 768;
+      FLD (out_h_spr_USI_769) = 769;
+      FLD (out_h_spr_USI_770) = 770;
+      FLD (out_h_spr_USI_771) = 771;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_teq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_teq.f
+    UINT f_ICCi_2;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_ICCi_2) = f_ICCi_2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_teq", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ICCi_2 0x%x", 'x', f_ICCi_2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (in_ICCi_2) = f_ICCi_2;
+      FLD (out_h_spr_USI_1) = 1;
+      FLD (out_h_spr_USI_768) = 768;
+      FLD (out_h_spr_USI_769) = 769;
+      FLD (out_h_spr_USI_770) = 770;
+      FLD (out_h_spr_USI_771) = 771;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ftne:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ftne.f
+    UINT f_FCCi_2;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FCCi_2) = f_FCCi_2;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftne", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FCCi_2) = f_FCCi_2;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+      FLD (out_h_spr_USI_1) = 1;
+      FLD (out_h_spr_USI_768) = 768;
+      FLD (out_h_spr_USI_769) = 769;
+      FLD (out_h_spr_USI_770) = 770;
+      FLD (out_h_spr_USI_771) = 771;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_tira:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ftine.f
+    UINT f_GRi;
+    INT f_d12;
+
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tira", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (out_h_spr_USI_1) = 1;
+      FLD (out_h_spr_USI_768) = 768;
+      FLD (out_h_spr_USI_769) = 769;
+      FLD (out_h_spr_USI_770) = 770;
+      FLD (out_h_spr_USI_771) = 771;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_tieq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_tieq.f
+    UINT f_ICCi_2;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_ICCi_2) = f_ICCi_2;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tieq", "f_GRi 0x%x", 'x', f_GRi, "f_ICCi_2 0x%x", 'x', f_ICCi_2, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_ICCi_2) = f_ICCi_2;
+      FLD (out_h_spr_USI_1) = 1;
+      FLD (out_h_spr_USI_768) = 768;
+      FLD (out_h_spr_USI_769) = 769;
+      FLD (out_h_spr_USI_770) = 770;
+      FLD (out_h_spr_USI_771) = 771;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ftine:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ftine.f
+    UINT f_FCCi_2;
+    UINT f_GRi;
+    INT f_d12;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FCCi_2) = f_FCCi_2;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_d12) = f_d12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftine", "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FCCi_2) = f_FCCi_2;
+      FLD (in_GRi) = f_GRi;
+      FLD (out_h_spr_USI_1) = 1;
+      FLD (out_h_spr_USI_768) = 768;
+      FLD (out_h_spr_USI_769) = 769;
+      FLD (out_h_spr_USI_770) = 770;
+      FLD (out_h_spr_USI_771) = 771;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_break:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_break.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_spr_USI_2) = 2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_andcr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_andcr.f
+    UINT f_CRk;
+    UINT f_CRi;
+    UINT f_CRj;
+
+    f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3);
+    f_CRi = EXTRACT_LSB0_UINT (insn, 32, 14, 3);
+    f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CRi) = f_CRi;
+  FLD (f_CRj) = f_CRj;
+  FLD (f_CRk) = f_CRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcr", "f_CRi 0x%x", 'x', f_CRi, "f_CRj 0x%x", 'x', f_CRj, "f_CRk 0x%x", 'x', f_CRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CRi) = f_CRi;
+      FLD (in_CRj) = f_CRj;
+      FLD (out_CRk) = f_CRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_notcr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_andcr.f
+    UINT f_CRk;
+    UINT f_CRj;
+
+    f_CRk = EXTRACT_LSB0_UINT (insn, 32, 27, 3);
+    f_CRj = EXTRACT_LSB0_UINT (insn, 32, 2, 3);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CRj) = f_CRj;
+  FLD (f_CRk) = f_CRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_notcr", "f_CRj 0x%x", 'x', f_CRj, "f_CRk 0x%x", 'x', f_CRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CRj) = f_CRj;
+      FLD (out_CRk) = f_CRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ckra:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+    SI f_CRj_int;
+
+    f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CRj_int) = f_CRj_int;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ckra", "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_CRj_int) = f_CRj_int;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ckeq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+    SI f_CRj_int;
+    UINT f_ICCi_3;
+
+    f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4));
+    f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ICCi_3) = f_ICCi_3;
+  FLD (f_CRj_int) = f_CRj_int;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ckeq", "f_ICCi_3 0x%x", 'x', f_ICCi_3, "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ICCi_3) = f_ICCi_3;
+      FLD (out_CRj_int) = f_CRj_int;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fckra:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+    UINT f_CRj_float;
+
+    f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CRj_float) = f_CRj_float;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fckra", "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_CRj_float) = f_CRj_float;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fckne:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+    UINT f_CRj_float;
+    UINT f_FCCi_3;
+
+    f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FCCi_3) = f_FCCi_3;
+  FLD (f_CRj_float) = f_CRj_float;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fckne", "f_FCCi_3 0x%x", 'x', f_FCCi_3, "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FCCi_3) = f_FCCi_3;
+      FLD (out_CRj_float) = f_CRj_float;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cckra:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+    SI f_CRj_int;
+    UINT f_CCi;
+    UINT f_cond;
+
+    f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4));
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_cond) = f_cond;
+  FLD (f_CRj_int) = f_CRj_int;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cckra", "f_CCi 0x%x", 'x', f_CCi, "f_cond 0x%x", 'x', f_cond, "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (out_CRj_int) = f_CRj_int;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cckeq:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+    SI f_CRj_int;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_ICCi_3;
+
+    f_CRj_int = ((EXTRACT_LSB0_UINT (insn, 32, 26, 2)) + (4));
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_ICCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_ICCi_3) = f_ICCi_3;
+  FLD (f_cond) = f_cond;
+  FLD (f_CRj_int) = f_CRj_int;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cckeq", "f_CCi 0x%x", 'x', f_CCi, "f_ICCi_3 0x%x", 'x', f_ICCi_3, "f_cond 0x%x", 'x', f_cond, "f_CRj_int 0x%x", 'x', f_CRj_int, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_ICCi_3) = f_ICCi_3;
+      FLD (out_CRj_int) = f_CRj_int;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfckra:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+    UINT f_CRj_float;
+    UINT f_CCi;
+    UINT f_cond;
+
+    f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_cond) = f_cond;
+  FLD (f_CRj_float) = f_CRj_float;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfckra", "f_CCi 0x%x", 'x', f_CCi, "f_cond 0x%x", 'x', f_cond, "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (out_CRj_float) = f_CRj_float;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfckne:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+    UINT f_CRj_float;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FCCi_3;
+
+    f_CRj_float = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FCCi_3 = EXTRACT_LSB0_UINT (insn, 32, 1, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FCCi_3) = f_FCCi_3;
+  FLD (f_cond) = f_cond;
+  FLD (f_CRj_float) = f_CRj_float;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfckne", "f_CCi 0x%x", 'x', f_CCi, "f_FCCi_3 0x%x", 'x', f_FCCi_3, "f_cond 0x%x", 'x', f_cond, "f_CRj_float 0x%x", 'x', f_CRj_float, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FCCi_3) = f_FCCi_3;
+      FLD (out_CRj_float) = f_CRj_float;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cjmpl:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+    UINT f_LI;
+    UINT f_GRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_GRj;
+
+    f_LI = EXTRACT_LSB0_UINT (insn, 32, 25, 1);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_LI) = f_LI;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cjmpl", "f_CCi 0x%x", 'x', f_CCi, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_LI 0x%x", 'x', f_LI, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ici:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_icpl.f
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ici", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_icei:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_icei.f
+    UINT f_ae;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_ae = EXTRACT_LSB0_UINT (insn, 32, 25, 1);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_ae) = f_ae;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_icei", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_ae 0x%x", 'x', f_ae, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_icpl:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_icpl.f
+    UINT f_lock;
+    UINT f_GRi;
+    UINT f_GRj;
+
+    f_lock = EXTRACT_LSB0_UINT (insn, 32, 25, 1);
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  FLD (f_GRj) = f_GRj;
+  FLD (f_lock) = f_lock;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_icpl", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_lock 0x%x", 'x', f_lock, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+      FLD (in_GRj) = f_GRj;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_icul:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+    UINT f_GRi;
+
+    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRi) = f_GRi;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_icul", "f_GRi 0x%x", 'x', f_GRi, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_GRi) = f_GRi;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_clrgr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_setlos.f
+    UINT f_GRk;
+
+    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_GRk) = f_GRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrgr", "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_clrfr:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+    UINT f_FRk;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrfr", "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fitos:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fditos.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fitos", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fstoi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fitod:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fitod.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fitod", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fdtoi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdtoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublej) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fditos:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fditos.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fditos", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintj_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRk) = f_FRk;
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fdstoi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdstoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRj) = f_FRj;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfitos:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfitos", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfstoi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfstoi", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nfitos:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fditos.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfitos", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nfstoi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfstoi", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fmovs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovs", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fmovd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovd", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublej) = f_FRj;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fdmovs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdmovs", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRj) = f_FRj;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRk) = f_FRk;
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfmovs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfmovs", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nfsqrts:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfsqrts", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fadds:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_faddd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_faddd", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublei) = f_FRi;
+      FLD (in_FRdoublej) = f_FRj;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfadds:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfadds", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nfadds:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fcmps:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FCCi_2) = f_FCCi_2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmps", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FCCi_2) = f_FCCi_2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fcmpd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FCCi_2) = f_FCCi_2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpd", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublei) = f_FRi;
+      FLD (in_FRdoublej) = f_FRj;
+      FLD (out_FCCi_2) = f_FCCi_2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfcmps:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FCCi_2) = f_FCCi_2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfcmps", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (out_FCCi_2) = f_FCCi_2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fdcmps:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FCCi_2) = f_FCCi_2;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdcmps", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FCCi_2) = f_FCCi_2;
+      FLD (out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCi_2_1) = ((FLD (f_FCCi_2)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fmadds:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_FRk) = f_FRk;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fmaddd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmaddd", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRdoublei) = f_FRi;
+      FLD (in_FRdoublej) = f_FRj;
+      FLD (in_FRdoublek) = f_FRk;
+      FLD (out_FRdoublek) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fdmadds:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdmadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_FRk) = f_FRk;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_FRk) = f_FRk;
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfmadds:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfmadds", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_FRk) = f_FRk;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nfmadds:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfmadds", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_FRk) = f_FRk;
+      FLD (out_FRk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fmas:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmas", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRk) = f_FRk;
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_fdmas:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fdmas", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_2) = ((FLD (f_FRi)) + (2));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_3) = ((FLD (f_FRi)) + (3));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_2) = ((FLD (f_FRj)) + (2));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_3) = ((FLD (f_FRj)) + (3));
+      FLD (out_FRk) = f_FRk;
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_3) = ((FLD (f_FRk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cfmas:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfmas", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRk) = f_FRk;
+      FLD (out_h_fr_SF_add__DFLT_index_of__DFLT_FRk_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nfdcmps:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+    UINT f_FRk;
+    UINT f_FCCi_2;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FCCi_2) = f_FCCi_2;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nfdcmps", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCi_2 0x%x", 'x', f_FCCi_2, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRi) = f_FRi;
+      FLD (in_FRj) = f_FRj;
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRi_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_SF_add__DFLT_index_of__DFLT_FRj_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FCCi_2) = f_FCCi_2;
+      FLD (out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCi_2_1) = ((FLD (f_FCCi_2)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mhsetlos:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+    UINT f_FRk;
+    INT f_u12_h;
+    UINT f_u12_l;
+    INT f_u12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6);
+    f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+{
+  f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
+}
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u12) = f_u12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsetlos", "f_u12 0x%x", 'x', f_u12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_FRklo) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mhsethis:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+    UINT f_FRk;
+    INT f_u12_h;
+    UINT f_u12_l;
+    INT f_u12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6);
+    f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+{
+  f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
+}
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_u12) = f_u12;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsethis", "f_u12 0x%x", 'x', f_u12, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_FRkhi) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mhdsets:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+    UINT f_FRk;
+    INT f_u12_h;
+    UINT f_u12_l;
+    INT f_u12;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_u12_h = EXTRACT_LSB0_INT (insn, 32, 17, 6);
+    f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+{
+  f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
+}
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_u12) = f_u12;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhdsets", "f_FRk 0x%x", 'x', f_FRk, "f_u12 0x%x", 'x', f_u12, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mhsetloh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+    UINT f_FRk;
+    INT f_s5;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_s5) = f_s5;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsetloh", "f_FRk 0x%x", 'x', f_FRk, "f_s5 0x%x", 'x', f_s5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRklo) = f_FRk;
+      FLD (out_FRklo) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mhsethih:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+    UINT f_FRk;
+    INT f_s5;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_s5) = f_s5;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhsethih", "f_FRk 0x%x", 'x', f_FRk, "f_s5 0x%x", 'x', f_s5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRkhi) = f_FRk;
+      FLD (out_FRkhi) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mhdseth:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+    UINT f_FRk;
+    INT f_s5;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_s5 = EXTRACT_LSB0_INT (insn, 32, 4, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_s5) = f_s5;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhdseth", "f_FRk 0x%x", 'x', f_FRk, "f_s5 0x%x", 'x', f_s5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mand:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mand", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmand:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmand.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmand", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mnot:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mcut.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mnot", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmnot:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmand.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmnot", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mrotli:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_u6) = f_u6;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mrotli", "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mwcut:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwcut", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1));
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mwcuti:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_u6) = f_u6;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwcuti", "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1));
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mcut:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mcut.f
+    UINT f_FRk;
+    UINT f_ACC40Si;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcut", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (in_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mcuti:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+    UINT f_FRk;
+    UINT f_ACC40Si;
+    INT f_s6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_s6) = f_s6;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcuti", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_s6 0x%x", 'x', f_s6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mdcutssi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+    UINT f_FRk;
+    UINT f_ACC40Si;
+    INT f_s6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_s6) = f_s6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdcutssi", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_FRk 0x%x", 'x', f_FRk, "f_s6 0x%x", 'x', f_s6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1));
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_msllhi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_u6) = f_u6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msllhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (out_FRinti) = f_FRi;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mdrotli:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+    UINT f_FRk;
+    UINT f_FRi;
+    INT f_s6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_s6 = EXTRACT_LSB0_INT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_s6) = f_s6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdrotli", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_s6 0x%x", 'x', f_s6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_int_USI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mcplhi:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_u6) = f_u6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcplhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1));
+      FLD (out_FRinti) = f_FRi;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mcpli:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_u6) = f_u6;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcpli", "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_h_fr_int_USI_add__DFLT_index_of__DFLT_FRinti_1) = ((FLD (f_FRi)) + (1));
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_msaths:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msaths", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mqsaths:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqsaths", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mcmpsh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+    UINT f_FCCk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FCCk = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FCCk) = f_FCCk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcmpsh", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FCCk 0x%x", 'x', f_FCCk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_FCCk) = f_FCCk;
+      FLD (out_h_fccr_UQI_add__DFLT_index_of__DFLT_FCCk_1) = ((FLD (f_FCCk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mabshs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mabshs", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmaddhss:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmaddhss", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmqaddhss:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqaddhss", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_maddaccs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+    UINT f_ACC40Sk;
+    UINT f_ACC40Si;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_maddaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mdaddaccs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+    UINT f_ACC40Sk;
+    UINT f_ACC40Si;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdaddaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_2) = ((FLD (f_ACC40Si)) + (2));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_3) = ((FLD (f_ACC40Si)) + (3));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_masaccs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+    UINT f_ACC40Sk;
+    UINT f_ACC40Si;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_masaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mdasaccs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+    UINT f_ACC40Sk;
+    UINT f_ACC40Si;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdasaccs", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_1) = ((FLD (f_ACC40Si)) + (1));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_2) = ((FLD (f_ACC40Si)) + (2));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Si_3) = ((FLD (f_ACC40Si)) + (3));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mmulhs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mmulhs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmmulhs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmmulhs", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mqmulhs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqmulhs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmqmulhs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqmulhs", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mmachs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Sk) = f_ACC40Sk;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mmachu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+    UINT f_ACC40Uk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Uk) = f_ACC40Uk;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Uk) = f_ACC40Uk;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Uk) = f_ACC40Uk;
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmmachs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Sk) = f_ACC40Sk;
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmmachu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+    UINT f_ACC40Uk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Uk) = f_ACC40Uk;
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Uk) = f_ACC40Uk;
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Uk) = f_ACC40Uk;
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mqmachs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Sk) = f_ACC40Sk;
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mqmachu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+    UINT f_ACC40Uk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Uk) = f_ACC40Uk;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Uk) = f_ACC40Uk;
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2));
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_ACC40Uk) = f_ACC40Uk;
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2));
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmqmachs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqmachs", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Sk) = f_ACC40Sk;
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2));
+      FLD (in_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_2) = ((FLD (f_ACC40Sk)) + (2));
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_3) = ((FLD (f_ACC40Sk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmqmachu:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+    UINT f_ACC40Uk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_ACC40Uk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Uk) = f_ACC40Uk;
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmqmachu", "f_ACC40Uk 0x%x", 'x', f_ACC40Uk, "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Uk) = f_ACC40Uk;
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2));
+      FLD (in_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_ACC40Uk) = f_ACC40Uk;
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_1) = ((FLD (f_ACC40Uk)) + (1));
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_2) = ((FLD (f_ACC40Uk)) + (2));
+      FLD (out_h_acc40U_UDI_add__DFLT_index_of__DFLT_ACC40Uk_3) = ((FLD (f_ACC40Uk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mcpxrs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcpxrs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmcpxrs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_cond) = f_cond;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmcpxrs", "f_CCi 0x%x", 'x', f_CCi, "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_cond 0x%x", 'x', f_cond, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mqcpxrs:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqcpxrs", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+      FLD (out_h_acc40S_DI_add__DFLT_index_of__DFLT_ACC40Sk_1) = ((FLD (f_ACC40Sk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mexpdhw:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_u6) = f_u6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mexpdhw", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmexpdhw:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_u6) = f_u6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmexpdhw", "f_CCi 0x%x", 'x', f_CCi, "f_cond 0x%x", 'x', f_cond, "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mexpdhd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRk) = f_FRk;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_u6) = f_u6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mexpdhd", "f_FRk 0x%x", 'x', f_FRk, "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmexpdhd:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_u6;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  FLD (f_FRi) = f_FRi;
+  FLD (f_u6) = f_u6;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmexpdhd", "f_CCi 0x%x", 'x', f_CCi, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, "f_FRi 0x%x", 'x', f_FRi, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mpackh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mdpackh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+    UINT f_FRk;
+    UINT f_FRi;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRintieven) = f_FRi;
+      FLD (out_FRintjeven) = f_FRj;
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_munpackh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+    UINT f_FRk;
+    UINT f_FRi;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_munpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRinti_0) = ((FLD (f_FRi)) + (0));
+      FLD (out_FRinti) = f_FRi;
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1))));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1))));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mdunpackh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+    UINT f_FRk;
+    UINT f_FRi;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mdunpackh", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintieven) = f_FRi;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+      FLD (out_FRintieven) = f_FRi;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1))));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1) = ((FLD (f_FRk)) + (((2) + (1))));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_0_1) = ((FLD (f_FRk)) + (((0) + (1))));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_add__DFLT_2_1) = ((FLD (f_FRk)) + (((2) + (1))));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mbtoh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mbtoh", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_FRintj) = f_FRj;
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmbtoh:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmbtoh", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_FRintkeven) = f_FRk;
+      FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_FRintj) = f_FRj;
+      FLD (out_FRintkeven) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mhtob:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mhtob", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRintjeven) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmhtob:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmhtob", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintjeven) = f_FRj;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintjeven_1) = ((FLD (f_FRj)) + (1));
+      FLD (out_FRintjeven) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mbtohe:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+    UINT f_FRk;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mbtohe", "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmbtohe:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+    UINT f_FRk;
+    UINT f_CCi;
+    UINT f_cond;
+    UINT f_FRj;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_CCi = EXTRACT_LSB0_UINT (insn, 32, 11, 3);
+    f_cond = EXTRACT_LSB0_UINT (insn, 32, 8, 1);
+    f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_CCi) = f_CCi;
+  FLD (f_FRj) = f_FRj;
+  FLD (f_FRk) = f_FRk;
+  FLD (f_cond) = f_cond;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmbtohe", "f_CCi 0x%x", 'x', f_CCi, "f_FRj 0x%x", 'x', f_FRj, "f_FRk 0x%x", 'x', f_FRk, "f_cond 0x%x", 'x', f_cond, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_CCi) = f_CCi;
+      FLD (in_FRintj) = f_FRj;
+      FLD (in_FRintk) = f_FRk;
+      FLD (in_h_fr_0_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_1_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_2_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (in_h_fr_3_UHI_add__DFLT_index_of__DFLT_FRintj_0) = ((FLD (f_FRj)) + (0));
+      FLD (out_FRintj) = f_FRj;
+      FLD (out_FRintk) = f_FRk;
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0) = ((FLD (f_FRk)) + (0));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_1) = ((FLD (f_FRk)) + (1));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_2) = ((FLD (f_FRk)) + (2));
+      FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_3) = ((FLD (f_FRk)) + (3));
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mclracc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mclracc.f
+    UINT f_ACC40Sk;
+    UINT f_A;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_A = EXTRACT_LSB0_UINT (insn, 32, 17, 1);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_A) = f_A;
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mclracc", "f_A 0x%x", 'x', f_A, "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mrdacc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+    UINT f_FRk;
+    UINT f_ACC40Si;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACC40Si = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Si) = f_ACC40Si;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mrdacc", "f_ACC40Si 0x%x", 'x', f_ACC40Si, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Si) = f_ACC40Si;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mrdaccg:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+    UINT f_FRk;
+    UINT f_ACCGi;
+
+    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_ACCGi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACCGi) = f_ACCGi;
+  FLD (f_FRk) = f_FRk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mrdaccg", "f_ACCGi 0x%x", 'x', f_ACCGi, "f_FRk 0x%x", 'x', f_FRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACCGi) = f_ACCGi;
+      FLD (out_FRintk) = f_FRk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mwtacc:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+    UINT f_ACC40Sk;
+    UINT f_FRi;
+
+    f_ACC40Sk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_ACC40Sk) = f_ACC40Sk;
+  FLD (f_FRi) = f_FRi;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtacc", "f_ACC40Sk 0x%x", 'x', f_ACC40Sk, "f_FRi 0x%x", 'x', f_FRi, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_ACC40Sk) = f_ACC40Sk;
+      FLD (in_FRinti) = f_FRi;
+      FLD (out_ACC40Sk) = f_ACC40Sk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mwtaccg:
+  {
+    const IDESC *idesc = &frvbf_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+    UINT f_ACCGk;
+    UINT f_FRi;
+
+    f_ACCGk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+    f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_FRi) = f_FRi;
+  FLD (f_ACCGk) = f_ACCGk;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtaccg", "f_FRi 0x%x", 'x', f_FRi, "f_ACCGk 0x%x", 'x', f_ACCGk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_FRinti) = f_FRi;
+      FLD (out_ACCGk) = f_ACCGk;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+}
diff --git a/sim/frv/decode.h b/sim/frv/decode.h
new file mode 100644
index 00000000000..190e19b66af
--- /dev/null
+++ b/sim/frv/decode.h
@@ -0,0 +1,399 @@
+/* Decode header for frvbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FRVBF_DECODE_H
+#define FRVBF_DECODE_H
+
+extern const IDESC *frvbf_decode (SIM_CPU *, IADDR,
+                                  CGEN_INSN_INT, CGEN_INSN_INT,
+                                  ARGBUF *);
+extern void frvbf_init_idesc_table (SIM_CPU *);
+extern void frvbf_sem_init_idesc_table (SIM_CPU *);
+extern void frvbf_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family frvbf.  */
+typedef enum frvbf_insn_type {
+  FRVBF_INSN_X_INVALID, FRVBF_INSN_X_AFTER, FRVBF_INSN_X_BEFORE, FRVBF_INSN_X_CTI_CHAIN
+ , FRVBF_INSN_X_CHAIN, FRVBF_INSN_X_BEGIN, FRVBF_INSN_ADD, FRVBF_INSN_SUB
+ , FRVBF_INSN_AND, FRVBF_INSN_OR, FRVBF_INSN_XOR, FRVBF_INSN_NOT
+ , FRVBF_INSN_SDIV, FRVBF_INSN_NSDIV, FRVBF_INSN_UDIV, FRVBF_INSN_NUDIV
+ , FRVBF_INSN_SMUL, FRVBF_INSN_UMUL, FRVBF_INSN_SLL, FRVBF_INSN_SRL
+ , FRVBF_INSN_SRA, FRVBF_INSN_SCAN, FRVBF_INSN_CADD, FRVBF_INSN_CSUB
+ , FRVBF_INSN_CAND, FRVBF_INSN_COR, FRVBF_INSN_CXOR, FRVBF_INSN_CNOT
+ , FRVBF_INSN_CSMUL, FRVBF_INSN_CSDIV, FRVBF_INSN_CUDIV, FRVBF_INSN_CSLL
+ , FRVBF_INSN_CSRL, FRVBF_INSN_CSRA, FRVBF_INSN_CSCAN, FRVBF_INSN_ADDCC
+ , FRVBF_INSN_SUBCC, FRVBF_INSN_ANDCC, FRVBF_INSN_ORCC, FRVBF_INSN_XORCC
+ , FRVBF_INSN_SLLCC, FRVBF_INSN_SRLCC, FRVBF_INSN_SRACC, FRVBF_INSN_SMULCC
+ , FRVBF_INSN_UMULCC, FRVBF_INSN_CADDCC, FRVBF_INSN_CSUBCC, FRVBF_INSN_CSMULCC
+ , FRVBF_INSN_CANDCC, FRVBF_INSN_CORCC, FRVBF_INSN_CXORCC, FRVBF_INSN_CSLLCC
+ , FRVBF_INSN_CSRLCC, FRVBF_INSN_CSRACC, FRVBF_INSN_ADDX, FRVBF_INSN_SUBX
+ , FRVBF_INSN_ADDXCC, FRVBF_INSN_SUBXCC, FRVBF_INSN_ADDI, FRVBF_INSN_SUBI
+ , FRVBF_INSN_ANDI, FRVBF_INSN_ORI, FRVBF_INSN_XORI, FRVBF_INSN_SDIVI
+ , FRVBF_INSN_NSDIVI, FRVBF_INSN_UDIVI, FRVBF_INSN_NUDIVI, FRVBF_INSN_SMULI
+ , FRVBF_INSN_UMULI, FRVBF_INSN_SLLI, FRVBF_INSN_SRLI, FRVBF_INSN_SRAI
+ , FRVBF_INSN_SCANI, FRVBF_INSN_ADDICC, FRVBF_INSN_SUBICC, FRVBF_INSN_ANDICC
+ , FRVBF_INSN_ORICC, FRVBF_INSN_XORICC, FRVBF_INSN_SMULICC, FRVBF_INSN_UMULICC
+ , FRVBF_INSN_SLLICC, FRVBF_INSN_SRLICC, FRVBF_INSN_SRAICC, FRVBF_INSN_ADDXI
+ , FRVBF_INSN_SUBXI, FRVBF_INSN_ADDXICC, FRVBF_INSN_SUBXICC, FRVBF_INSN_CMPB
+ , FRVBF_INSN_CMPBA, FRVBF_INSN_SETLO, FRVBF_INSN_SETHI, FRVBF_INSN_SETLOS
+ , FRVBF_INSN_LDSB, FRVBF_INSN_LDUB, FRVBF_INSN_LDSH, FRVBF_INSN_LDUH
+ , FRVBF_INSN_LD, FRVBF_INSN_LDBF, FRVBF_INSN_LDHF, FRVBF_INSN_LDF
+ , FRVBF_INSN_LDC, FRVBF_INSN_NLDSB, FRVBF_INSN_NLDUB, FRVBF_INSN_NLDSH
+ , FRVBF_INSN_NLDUH, FRVBF_INSN_NLD, FRVBF_INSN_NLDBF, FRVBF_INSN_NLDHF
+ , FRVBF_INSN_NLDF, FRVBF_INSN_LDD, FRVBF_INSN_LDDF, FRVBF_INSN_LDDC
+ , FRVBF_INSN_NLDD, FRVBF_INSN_NLDDF, FRVBF_INSN_LDQ, FRVBF_INSN_LDQF
+ , FRVBF_INSN_LDQC, FRVBF_INSN_NLDQ, FRVBF_INSN_NLDQF, FRVBF_INSN_LDSBU
+ , FRVBF_INSN_LDUBU, FRVBF_INSN_LDSHU, FRVBF_INSN_LDUHU, FRVBF_INSN_LDU
+ , FRVBF_INSN_NLDSBU, FRVBF_INSN_NLDUBU, FRVBF_INSN_NLDSHU, FRVBF_INSN_NLDUHU
+ , FRVBF_INSN_NLDU, FRVBF_INSN_LDBFU, FRVBF_INSN_LDHFU, FRVBF_INSN_LDFU
+ , FRVBF_INSN_LDCU, FRVBF_INSN_NLDBFU, FRVBF_INSN_NLDHFU, FRVBF_INSN_NLDFU
+ , FRVBF_INSN_LDDU, FRVBF_INSN_NLDDU, FRVBF_INSN_LDDFU, FRVBF_INSN_LDDCU
+ , FRVBF_INSN_NLDDFU, FRVBF_INSN_LDQU, FRVBF_INSN_NLDQU, FRVBF_INSN_LDQFU
+ , FRVBF_INSN_LDQCU, FRVBF_INSN_NLDQFU, FRVBF_INSN_LDSBI, FRVBF_INSN_LDSHI
+ , FRVBF_INSN_LDI, FRVBF_INSN_LDUBI, FRVBF_INSN_LDUHI, FRVBF_INSN_LDBFI
+ , FRVBF_INSN_LDHFI, FRVBF_INSN_LDFI, FRVBF_INSN_NLDSBI, FRVBF_INSN_NLDUBI
+ , FRVBF_INSN_NLDSHI, FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI
+ , FRVBF_INSN_NLDHFI, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI
+ , FRVBF_INSN_NLDDI, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI
+ , FRVBF_INSN_NLDQI, FRVBF_INSN_NLDQFI, FRVBF_INSN_STB, FRVBF_INSN_STH
+ , FRVBF_INSN_ST, FRVBF_INSN_STBF, FRVBF_INSN_STHF, FRVBF_INSN_STF
+ , FRVBF_INSN_STC, FRVBF_INSN_RSTB, FRVBF_INSN_RSTH, FRVBF_INSN_RST
+ , FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF, FRVBF_INSN_RSTF, FRVBF_INSN_STD
+ , FRVBF_INSN_STDF, FRVBF_INSN_STDC, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF
+ , FRVBF_INSN_STQ, FRVBF_INSN_STQF, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ
+ , FRVBF_INSN_RSTQF, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU
+ , FRVBF_INSN_STBFU, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU
+ , FRVBF_INSN_STDU, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU
+ , FRVBF_INSN_STQFU, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB
+ , FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF
+ , FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF
+ , FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU
+ , FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU
+ , FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU
+ , FRVBF_INSN_CSTB, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF
+ , FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF
+ , FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU
+ , FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU
+ , FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI
+ , FRVBF_INSN_STBFI, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI
+ , FRVBF_INSN_STDFI, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP
+ , FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG
+ , FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ
+ , FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD
+ , FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO
+ , FRVBF_INSN_BEQ, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT
+ , FRVBF_INSN_BLT, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI
+ , FRVBF_INSN_BC, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP
+ , FRVBF_INSN_BV, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO
+ , FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE
+ , FRVBF_INSN_FBUL, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE
+ , FRVBF_INSN_FBUG, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE
+ , FRVBF_INSN_FBU, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR
+ , FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR
+ , FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR
+ , FRVBF_INSN_BHILR, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR
+ , FRVBF_INSN_BPLR, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR
+ , FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR
+ , FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR
+ , FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR
+ , FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR
+ , FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR
+ , FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR
+ , FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR
+ , FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR
+ , FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR
+ , FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR
+ , FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR
+ , FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL
+ , FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL
+ , FRVBF_INSN_RETT, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO
+ , FRVBF_INSN_TEQ, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT
+ , FRVBF_INSN_TLT, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI
+ , FRVBF_INSN_TC, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP
+ , FRVBF_INSN_TV, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO
+ , FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE
+ , FRVBF_INSN_FTUL, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE
+ , FRVBF_INSN_FTUG, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE
+ , FRVBF_INSN_FTU, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO
+ , FRVBF_INSN_TIEQ, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT
+ , FRVBF_INSN_TILT, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI
+ , FRVBF_INSN_TIC, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP
+ , FRVBF_INSN_TIV, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO
+ , FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE
+ , FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE
+ , FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE
+ , FRVBF_INSN_FTIU, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP
+ , FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR
+ , FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR
+ , FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO
+ , FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT
+ , FRVBF_INSN_CKLT, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI
+ , FRVBF_INSN_CKC, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP
+ , FRVBF_INSN_CKV, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO
+ , FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE
+ , FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE
+ , FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE
+ , FRVBF_INSN_FCKU, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO
+ , FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT
+ , FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI
+ , FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP
+ , FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO
+ , FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE
+ , FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE
+ , FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE
+ , FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL
+ , FRVBF_INSN_ICI, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI
+ , FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB
+ , FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL
+ , FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR
+ , FRVBF_INSN_COP1, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR
+ , FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR
+ , FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI
+ , FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI
+ , FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI
+ , FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD
+ , FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD
+ , FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD
+ , FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS
+ , FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS
+ , FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS
+ , FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD
+ , FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS
+ , FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS
+ , FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS
+ , FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD
+ , FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS
+ , FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS
+ , FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS
+ , FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD
+ , FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS
+ , FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS
+ , FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS
+ , FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS
+ , FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH
+ , FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR
+ , FRVBF_INSN_CMAND, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT
+ , FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT
+ , FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS
+ , FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI
+ , FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI
+ , FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU
+ , FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS
+ , FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS
+ , FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS
+ , FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS
+ , FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS
+ , FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS
+ , FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS
+ , FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS
+ , FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS
+ , FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS
+ , FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS
+ , FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS
+ , FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU
+ , FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU
+ , FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU
+ , FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW
+ , FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH
+ , FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH
+ , FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE
+ , FRVBF_INSN_MCLRACC, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC
+ , FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP
+ , FRVBF_INSN__MAX
+} FRVBF_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family frvbf.  */
+typedef enum frvbf_sfmt_type {
+  FRVBF_SFMT_EMPTY, FRVBF_SFMT_ADD, FRVBF_SFMT_NOT, FRVBF_SFMT_SDIV
+ , FRVBF_SFMT_SMUL, FRVBF_SFMT_CADD, FRVBF_SFMT_CNOT, FRVBF_SFMT_CSMUL
+ , FRVBF_SFMT_CSDIV, FRVBF_SFMT_ADDCC, FRVBF_SFMT_ANDCC, FRVBF_SFMT_SMULCC
+ , FRVBF_SFMT_CADDCC, FRVBF_SFMT_CSMULCC, FRVBF_SFMT_ADDX, FRVBF_SFMT_ADDI
+ , FRVBF_SFMT_SDIVI, FRVBF_SFMT_SMULI, FRVBF_SFMT_ADDICC, FRVBF_SFMT_ANDICC
+ , FRVBF_SFMT_SMULICC, FRVBF_SFMT_ADDXI, FRVBF_SFMT_CMPB, FRVBF_SFMT_SETLO
+ , FRVBF_SFMT_SETHI, FRVBF_SFMT_SETLOS, FRVBF_SFMT_LDSB, FRVBF_SFMT_LDBF
+ , FRVBF_SFMT_LDC, FRVBF_SFMT_NLDSB, FRVBF_SFMT_NLDBF, FRVBF_SFMT_LDD
+ , FRVBF_SFMT_LDDF, FRVBF_SFMT_LDDC, FRVBF_SFMT_NLDD, FRVBF_SFMT_NLDDF
+ , FRVBF_SFMT_LDQ, FRVBF_SFMT_LDQF, FRVBF_SFMT_LDQC, FRVBF_SFMT_NLDQ
+ , FRVBF_SFMT_NLDQF, FRVBF_SFMT_LDSBU, FRVBF_SFMT_NLDSBU, FRVBF_SFMT_LDBFU
+ , FRVBF_SFMT_LDCU, FRVBF_SFMT_NLDBFU, FRVBF_SFMT_LDDU, FRVBF_SFMT_NLDDU
+ , FRVBF_SFMT_LDDFU, FRVBF_SFMT_LDDCU, FRVBF_SFMT_NLDDFU, FRVBF_SFMT_LDQU
+ , FRVBF_SFMT_NLDQU, FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU
+ , FRVBF_SFMT_LDSBI, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI
+ , FRVBF_SFMT_LDDI, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI
+ , FRVBF_SFMT_LDQI, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQI, FRVBF_SFMT_NLDQFI
+ , FRVBF_SFMT_STB, FRVBF_SFMT_STBF, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB
+ , FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC
+ , FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU
+ , FRVBF_SFMT_STCU, FRVBF_SFMT_STDU, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU
+ , FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD
+ , FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU
+ , FRVBF_SFMT_CLDDU, FRVBF_SFMT_CLDDFU, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB
+ , FRVBF_SFMT_CSTBF, FRVBF_SFMT_CSTD, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU
+ , FRVBF_SFMT_CSTBFU, FRVBF_SFMT_CSTDU, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI
+ , FRVBF_SFMT_STBFI, FRVBF_SFMT_STDI, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP
+ , FRVBF_SFMT_SWAPI, FRVBF_SFMT_CSWAP, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG
+ , FRVBF_SFMT_MOVGFD, FRVBF_SFMT_MOVFGD, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ
+ , FRVBF_SFMT_CMOVGF, FRVBF_SFMT_CMOVFG, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD
+ , FRVBF_SFMT_MOVGS, FRVBF_SFMT_MOVSG, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO
+ , FRVBF_SFMT_BEQ, FRVBF_SFMT_FBNE, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR
+ , FRVBF_SFMT_BNOLR, FRVBF_SFMT_BEQLR, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR
+ , FRVBF_SFMT_BCNOLR, FRVBF_SFMT_BCEQLR, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL
+ , FRVBF_SFMT_JMPIL, FRVBF_SFMT_CALL, FRVBF_SFMT_RETT, FRVBF_SFMT_REI
+ , FRVBF_SFMT_TRA, FRVBF_SFMT_TEQ, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA
+ , FRVBF_SFMT_TIEQ, FRVBF_SFMT_FTINE, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR
+ , FRVBF_SFMT_NOTCR, FRVBF_SFMT_CKRA, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA
+ , FRVBF_SFMT_FCKNE, FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA
+ , FRVBF_SFMT_CFCKNE, FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI
+ , FRVBF_SFMT_ICPL, FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR
+ , FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI
+ , FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI
+ , FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD
+ , FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS
+ , FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS
+ , FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS
+ , FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS
+ , FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS
+ , FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH
+ , FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND
+ , FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT
+ , FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI
+ , FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI
+ , FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS
+ , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS
+ , FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS
+ , FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU
+ , FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU
+ , FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS
+ , FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD
+ , FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH
+ , FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB
+ , FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC
+ , FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
+} FRVBF_SFMT_TYPE;
+
+/* Function unit handlers (user written).  */
+
+extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr500_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr500_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_media_quad_complex (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr500_u_media_quad_mul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr500_u_media_dual_mul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr500_u_media_quad_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_media (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Si*/, INT /*ACCGi*/, INT /*FRintk*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/, INT /*ACCGk*/);
+extern int frvbf_model_fr500_u_float_dual_convert (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRintj*/, INT /*FRk*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_float_convert (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRintj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr500_u_float_dual_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr500_u_float_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRk*/);
+extern int frvbf_model_fr500_u_float_sqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr500_u_float_div (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRk*/);
+extern int frvbf_model_fr500_u_float_dual_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr500_u_float_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr500_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/);
+extern int frvbf_model_fr500_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/);
+extern int frvbf_model_fr500_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/);
+extern int frvbf_model_fr500_u_fr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRk*/);
+extern int frvbf_model_fr500_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/);
+extern int frvbf_model_fr500_u_fr_r_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr500_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr500_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr500_u_gr_r_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr500_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr500_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr500_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/);
+extern int frvbf_model_fr500_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/);
+extern int frvbf_model_fr500_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr500_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr500_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr500_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr500_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr500_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_tomcat_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr400_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr400_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr400_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_7 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FCCk*/);
+extern int frvbf_model_fr400_u_media_6 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_4_accg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACCGi*/, INT /*FRinti*/, INT /*ACCGk*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_3_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_3 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr400_u_media_2_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr400_u_media_2_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr400_u_media_2 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr400_u_media_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRkhi*/, INT /*FRklo*/);
+extern int frvbf_model_fr400_u_media_1_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_media_1 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/);
+extern int frvbf_model_fr400_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/);
+extern int frvbf_model_fr400_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/);
+extern int frvbf_model_fr400_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/);
+extern int frvbf_model_fr400_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr400_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr400_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr400_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr400_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/);
+extern int frvbf_model_fr400_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/);
+extern int frvbf_model_fr400_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr400_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr400_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr400_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr400_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr400_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_simple_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void frvbf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void frvbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* FRVBF_DECODE_H */
diff --git a/sim/frv/devices.c b/sim/frv/devices.c
new file mode 100644
index 00000000000..3c1dedbc700
--- /dev/null
+++ b/sim/frv/devices.c
@@ -0,0 +1,96 @@
+/* frv device support
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* ??? All of this is just to get something going.  wip!  */
+
+#include "sim-main.h"
+
+#ifdef HAVE_DV_SOCKSER
+#include "dv-sockser.h"
+#endif
+
+device frv_devices;
+
+int
+device_io_read_buffer (device *me, void *source, int space,
+		       address_word addr, unsigned nr_bytes,
+		       SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
+{
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#ifdef HAVE_DV_SOCKSER
+  if (addr == UART_INCHAR_ADDR)
+    {
+      int c = dv_sockser_read (sd);
+      if (c == -1)
+	return 0;
+      *(char *) source = c;
+      return 1;
+    }
+  if (addr == UART_STATUS_ADDR)
+    {
+      int status = dv_sockser_status (sd);
+      unsigned char *p = source;
+      p[0] = 0;
+      p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
+#ifdef UART_INPUT_READY0
+	       ? UART_INPUT_READY : 0)
+#else
+	       ? 0 : UART_INPUT_READY)
+#endif
+	      + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
+      return 2;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+int
+device_io_write_buffer (device *me, const void *source, int space,
+			address_word addr, unsigned nr_bytes,
+                        SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
+{
+
+#if WITH_SCACHE
+  if (addr == MCCR_ADDR)
+    {
+      if ((*(const char *) source & MCCR_CP) != 0)
+	scache_flush (sd);
+      return nr_bytes;
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#if HAVE_DV_SOCKSER
+  if (addr == UART_OUTCHAR_ADDR)
+    {
+      int rc = dv_sockser_write (sd, *(char *) source);
+      return rc == 1;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+void device_error (device *me, char* message, ...) {}
diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h
new file mode 100644
index 00000000000..f8dafccfb60
--- /dev/null
+++ b/sim/frv/frv-sim.h
@@ -0,0 +1,916 @@
+/* collection of junk waiting time to sort out
+   Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef FRV_SIM_H
+#define FRV_SIM_H
+
+#include "sim-options.h"
+
+/* Not defined in the cgen cpu file for access restriction purposes.  */
+#define H_SPR_ACC0   1408
+#define H_SPR_ACC63  1471
+#define H_SPR_ACCG0  1472
+#define H_SPR_ACCG63 1535
+
+/* gdb register numbers.  */
+#define GR_REGNUM_MAX	63
+#define FR_REGNUM_MAX  127
+#define PC_REGNUM      128
+#define LR_REGNUM      145
+
+/* Initialization of the frv cpu.  */
+void frv_initialize (SIM_CPU *, SIM_DESC);
+void frv_term (SIM_DESC);
+void frv_power_on_reset (SIM_CPU *);
+void frv_hardware_reset (SIM_CPU *);
+void frv_software_reset (SIM_CPU *);
+
+/* The reset register.  See FRV LSI section 10.3.1  */
+#define RSTR_ADDRESS        0xfeff0500
+#define RSTR_INITIAL_VALUE  0x00000400
+#define RSTR_HARDWARE_RESET 0x00000200
+#define RSTR_SOFTWARE_RESET 0x00000100
+
+#define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
+#define GET_RSTR_SR(rstr) (((rstr)     ) & 1)
+
+#define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
+#define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
+
+#define CLEAR_RSTR_P(rstr)  ((rstr) &= ~(1 << 10))
+#define CLEAR_RSTR_H(rstr)  ((rstr) &= ~(1 <<  9))
+#define CLEAR_RSTR_S(rstr)  ((rstr) &= ~(1 <<  8))
+#define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 <<  1))
+#define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
+
+/* Cutomized hardware get/set functions.  */
+extern USI  frvbf_h_spr_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI);
+extern USI  frvbf_h_gr_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI);
+extern UHI  frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI);
+extern UHI  frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI);
+extern DI   frvbf_h_gr_double_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI);
+extern SF   frvbf_h_fr_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF);
+extern DF   frvbf_h_fr_double_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF);
+extern USI  frvbf_h_fr_int_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI);
+extern DI   frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT);
+extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI);
+extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *);
+extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *);
+extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *);
+extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
+
+extern USI  spr_psr_get_handler (SIM_CPU *);
+extern void spr_psr_set_handler (SIM_CPU *, USI);
+extern USI  spr_tbr_get_handler (SIM_CPU *);
+extern void spr_tbr_set_handler (SIM_CPU *, USI);
+extern USI  spr_bpsr_get_handler (SIM_CPU *);
+extern void spr_bpsr_set_handler (SIM_CPU *, USI);
+extern USI  spr_ccr_get_handler (SIM_CPU *);
+extern void spr_ccr_set_handler (SIM_CPU *, USI);
+extern void spr_cccr_set_handler (SIM_CPU *, USI);
+extern USI  spr_cccr_get_handler (SIM_CPU *);
+extern USI  spr_isr_get_handler (SIM_CPU *);
+extern void spr_isr_set_handler (SIM_CPU *, USI);
+extern USI  spr_sr_get_handler (SIM_CPU *, UINT);
+extern void spr_sr_set_handler (SIM_CPU *, UINT, USI);
+
+extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
+
+extern QI frvbf_set_icc_for_shift_left  (SIM_CPU *, SI, SI, QI);
+extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
+
+extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
+extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
+
+extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
+
+extern SI   frvbf_scan_result (SIM_CPU *, SI);
+extern SI   frvbf_cut (SIM_CPU *, SI, SI, SI);
+extern SI   frvbf_media_cut (SIM_CPU *, DI, SI);
+extern SI   frvbf_media_cut_ss (SIM_CPU *, DI, SI);
+extern void frvbf_media_cop (SIM_CPU *, int);
+extern UQI  frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI);
+
+extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int);
+extern int  frvbf_write_next_vliw_addr_to_LR;
+
+extern void frvbf_set_ne_index (SIM_CPU *, int);
+extern void frvbf_force_update (SIM_CPU *);
+
+#define GETTWI GETTSI
+#define SETTWI SETTSI
+#define LEUINT LEUSI
+
+/* Hardware/device support.
+   ??? Will eventually want to move device stuff to config files.  */
+
+/* Support for the MCCR register (Cache Control Register) is needed in order
+   for overlays to work correctly with the scache: cached instructions need
+   to be flushed when the instruction space is changed at runtime.  */
+
+/* These were just copied from another port and are necessary to build, but
+   but don't appear to be used.  */
+#define MCCR_ADDR 0xffffffff
+#define MCCR_CP 0x80
+/* not supported */
+#define MCCR_CM0 2
+#define MCCR_CM1 1
+
+/* sim_core_attach device argument.  */
+extern device frv_devices;
+
+/* FIXME: Temporary, until device support ready.  */
+struct _device { int foo; };
+
+/* maintain the address of the start of the previous VLIW insn sequence.  */
+extern IADDR previous_vliw_pc;
+
+/* Hardware status.  */
+#define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
+#define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
+
+#define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
+#define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
+#define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
+
+#define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
+#define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
+#define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
+
+#define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
+#define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
+#define GET_HSR0_SA(hsr0)  (((hsr0) >> 12) & 1)
+#define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
+#define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
+#define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
+#define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
+#define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
+#define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
+
+#define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
+#define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
+
+void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
+void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
+void frvbf_insn_cache_unlock (SIM_CPU *, SI);
+void frvbf_data_cache_unlock (SIM_CPU *, SI);
+void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int);
+void frvbf_data_cache_invalidate (SIM_CPU *, SI, int);
+void frvbf_data_cache_flush (SIM_CPU *, SI, int);
+
+/* FR-V Interrupt classes.
+   These are declared in order of increasing priority.  */
+enum frv_interrupt_class
+{
+  FRV_EXTERNAL_INTERRUPT,
+  FRV_SOFTWARE_INTERRUPT,
+  FRV_PROGRAM_INTERRUPT,
+  FRV_BREAK_INTERRUPT,
+  FRV_RESET_INTERRUPT,
+  NUM_FRV_INTERRUPT_CLASSES
+};
+
+/* FR-V Interrupt kinds.
+   These are declared in order of increasing priority.  */
+enum frv_interrupt_kind
+{
+  /* External interrupts */
+  FRV_INTERRUPT_LEVEL_1,
+  FRV_INTERRUPT_LEVEL_2,
+  FRV_INTERRUPT_LEVEL_3,
+  FRV_INTERRUPT_LEVEL_4,
+  FRV_INTERRUPT_LEVEL_5,
+  FRV_INTERRUPT_LEVEL_6,
+  FRV_INTERRUPT_LEVEL_7,
+  FRV_INTERRUPT_LEVEL_8,
+  FRV_INTERRUPT_LEVEL_9,
+  FRV_INTERRUPT_LEVEL_10,
+  FRV_INTERRUPT_LEVEL_11,
+  FRV_INTERRUPT_LEVEL_12,
+  FRV_INTERRUPT_LEVEL_13,
+  FRV_INTERRUPT_LEVEL_14,
+  FRV_INTERRUPT_LEVEL_15,
+  /* Software interrupt */
+  FRV_TRAP_INSTRUCTION,
+  /* Program interrupts */
+  FRV_COMMIT_EXCEPTION,
+  FRV_DIVISION_EXCEPTION,
+  FRV_DATA_STORE_ERROR,
+  FRV_DATA_ACCESS_EXCEPTION,
+  FRV_DATA_ACCESS_MMU_MISS,
+  FRV_DATA_ACCESS_ERROR,
+  FRV_MP_EXCEPTION,
+  FRV_FP_EXCEPTION,
+  FRV_MEM_ADDRESS_NOT_ALIGNED,
+  FRV_REGISTER_EXCEPTION,
+  FRV_MP_DISABLED,
+  FRV_FP_DISABLED,
+  FRV_PRIVILEGED_INSTRUCTION,
+  FRV_ILLEGAL_INSTRUCTION,
+  FRV_INSTRUCTION_ACCESS_EXCEPTION,
+  FRV_INSTRUCTION_ACCESS_ERROR,
+  FRV_INSTRUCTION_ACCESS_MMU_MISS,
+  FRV_COMPOUND_EXCEPTION,
+  /* Break interrupt */
+  FRV_BREAK_EXCEPTION,
+  /* Reset interrupt */
+  FRV_RESET,
+  NUM_FRV_INTERRUPT_KINDS
+};
+
+/* FRV interrupt exception codes */
+enum frv_ec
+{
+  FRV_EC_DATA_STORE_ERROR             = 0x00,
+  FRV_EC_INSTRUCTION_ACCESS_MMU_MISS  = 0x01,
+  FRV_EC_INSTRUCTION_ACCESS_ERROR     = 0x02,
+  FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03,
+  FRV_EC_PRIVILEGED_INSTRUCTION       = 0x04,
+  FRV_EC_ILLEGAL_INSTRUCTION          = 0x05,
+  FRV_EC_FP_DISABLED                  = 0x06,
+  FRV_EC_MP_DISABLED                  = 0x07,
+  FRV_EC_MEM_ADDRESS_NOT_ALIGNED      = 0x0b,
+  FRV_EC_REGISTER_EXCEPTION           = 0x0c,
+  FRV_EC_FP_EXCEPTION                 = 0x0d,
+  FRV_EC_MP_EXCEPTION                 = 0x0e,
+  FRV_EC_DATA_ACCESS_ERROR            = 0x10,
+  FRV_EC_DATA_ACCESS_MMU_MISS         = 0x11,
+  FRV_EC_DATA_ACCESS_EXCEPTION        = 0x12,
+  FRV_EC_DIVISION_EXCEPTION           = 0x13,
+  FRV_EC_COMMIT_EXCEPTION             = 0x14,
+  FRV_EC_NOT_EXECUTED                 = 0x1f,
+  FRV_EC_INTERRUPT_LEVEL_1            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_2            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_3            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_4            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_5            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_6            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_7            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_8            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_9            = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_10           = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_11           = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_12           = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_13           = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_14           = FRV_EC_NOT_EXECUTED,
+  FRV_EC_INTERRUPT_LEVEL_15           = FRV_EC_NOT_EXECUTED,
+  FRV_EC_TRAP_INSTRUCTION             = FRV_EC_NOT_EXECUTED,
+  FRV_EC_COMPOUND_EXCEPTION           = FRV_EC_NOT_EXECUTED,
+  FRV_EC_BREAK_EXCEPTION              = FRV_EC_NOT_EXECUTED,
+  FRV_EC_RESET                        = FRV_EC_NOT_EXECUTED
+};
+
+/* FR-V Interrupt.
+   This struct contains enough information to describe a particular interrupt
+   occurance.  */
+struct frv_interrupt
+{
+  enum frv_interrupt_kind  kind;
+  enum frv_ec              ec;
+  enum frv_interrupt_class iclass;
+  unsigned char deferred;
+  unsigned char precise;
+  unsigned char handler_offset;
+};
+
+/* FR-V Interrupt table.
+   Describes the interrupts supported by the FR-V.  */
+extern struct frv_interrupt frv_interrupt_table[];
+
+/* FR-V Interrupt State.
+   Interrupts are queued during execution of parallel insns and the interupt(s)
+   to be handled determined by analysing the queue after each VLIW insn.  */
+#define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now.  */
+
+/* register_exception codes */
+enum frv_rec
+{
+  FRV_REC_UNIMPLEMENTED = 0,
+  FRV_REC_UNALIGNED     = 1
+};
+
+/* instruction_access_exception codes */
+enum frv_iaec
+{
+  FRV_IAEC_PROTECT_VIOLATION = 1
+};
+
+/* data_access_exception codes */
+enum frv_daec
+{
+  FRV_DAEC_PROTECT_VIOLATION = 1
+};
+
+/* division_exception ISR codes */
+enum frv_dtt
+{
+  FRV_DTT_NO_EXCEPTION     = 0,
+  FRV_DTT_DIVISION_BY_ZERO = 1,
+  FRV_DTT_OVERFLOW         = 2,
+  FRV_DTT_BOTH             = 3
+};
+
+/* data written during an insn causing an interrupt */
+struct frv_data_written
+{
+  USI words[4]; /* Actual data in words */
+  int length;   /* length of data written */
+};
+
+/* fp_exception info */
+/* Trap codes for FSR0 and FQ registers.  */
+enum frv_fsr_traps
+{
+  FSR_INVALID_OPERATION = 0x20,
+  FSR_OVERFLOW          = 0x10,
+  FSR_UNDERFLOW         = 0x08,
+  FSR_DIVISION_BY_ZERO  = 0x04,
+  FSR_INEXACT           = 0x02,
+  FSR_DENORMAL_INPUT    = 0x01,
+  FSR_NO_EXCEPTION      = 0
+};
+
+/* Floating point trap types for FSR.  */
+enum frv_fsr_ftt
+{
+  FTT_NONE               = 0,
+  FTT_IEEE_754_EXCEPTION = 1,
+  FTT_UNIMPLEMENTED_FPOP = 3,
+  FTT_SEQUENCE_ERROR     = 4,
+  FTT_INVALID_FR         = 6,
+  FTT_DENORMAL_INPUT     = 7
+};
+
+struct frv_fp_exception_info
+{
+  enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
+  enum frv_fsr_ftt   ftt;      /* floating point trap type */
+};
+
+struct frv_interrupt_queue_element
+{
+  enum frv_interrupt_kind kind;      /* kind of interrupt */
+  IADDR                   vpc;       /* address of insn causing interrupt */
+  int                     slot;      /* VLIW slot containing the insn.  */
+  USI                     eaddress;  /* address of data access */
+  union {
+    enum frv_rec  rec;               /* register exception code */
+    enum frv_iaec iaec;              /* insn access exception code */
+    enum frv_daec daec;              /* data access exception code */
+    enum frv_dtt  dtt;               /* division exception code */
+    struct frv_fp_exception_info fp_info;
+    struct frv_data_written data_written;
+  } u;
+};
+
+struct frv_interrupt_timer
+{
+  int enabled;
+  unsigned value;
+  unsigned current;
+  enum frv_interrupt_kind interrupt;
+};
+
+struct frv_interrupt_state
+{
+  /* The interrupt queue */
+  struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE];
+  int queue_index;
+
+  /* interrupt queue element causing imprecise interrupt.  */
+  struct frv_interrupt_queue_element *imprecise_interrupt;
+
+  /* interrupt timer.  */
+  struct frv_interrupt_timer timer;
+
+  /* The last data written stored as an array of words.  */
+  struct frv_data_written data_written;
+
+  /* The vliw slot of the insn causing the interrupt.  */
+  int slot;
+
+  /* target register index for non excepting insns.  */
+#define NE_NOFLAG (-1)
+  int ne_index;
+
+  /* Accumulated NE flags for non excepting floating point insns.  */
+  SI f_ne_flags[2];
+};
+
+extern struct frv_interrupt_state frv_interrupt_state;
+
+/* Macros to manipulate the PSR.  */
+#define GET_PSR() GET_H_SPR (H_SPR_PSR)
+
+#define SET_PSR_ET(psr, et) (           \
+  (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
+)
+
+#define GET_PSR_PS(psr) (((psr) >> 1) & 1)
+
+#define SET_PSR_S(psr, s) (                          \
+  (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
+)
+
+/* Macros to handle the ISR register.  */
+#define GET_ISR() GET_H_SPR (H_SPR_ISR)
+#define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
+
+#define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
+
+#define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
+#define SET_ISR_DTT(isr, dtt) (                        \
+  (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
+)
+
+#define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
+
+#define GET_ISR_EMAM(isr) ((isr) & 1)
+
+/* Macros to handle exception status registers.
+   Get and set the hardware directly, since we may be getting/setting fields
+   which are not accessible to the user.  */
+#define GET_ESR(index) \
+  (CPU (h_spr[H_SPR_ESR0 + (index)]))
+#define SET_ESR(index, esr) \
+  (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
+
+#define SET_ESR_VALID(esr) ((esr) |= 1)
+#define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
+
+#define SET_ESR_EC(esr, ec) (                           \
+  (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
+)
+
+#define SET_ESR_REC(esr, rec) (                        \
+  (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
+)
+
+#define SET_ESR_IAEC(esr, iaec) (                       \
+  (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
+)
+
+#define SET_ESR_DAEC(esr, daec) (                       \
+  (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
+)
+
+#define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
+#define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
+
+#define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
+#define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
+#define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
+
+#define GET_ESR_EDN(esr) ( \
+  ((esr) >> 13) & 0xf      \
+)
+#define SET_ESR_EDN(esr, edn) (                       \
+  (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
+)
+
+#define SET_EPCR(index, address) \
+  (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
+
+#define SET_EAR(index, address) \
+  (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
+
+#define SET_EDR(index, edr) \
+  (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
+
+#define GET_ESFR(index) \
+  (CPU (h_spr[H_SPR_ESFR0 + (index)]))
+#define SET_ESFR(index, esfr) \
+  (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
+
+#define GET_ESFR_FLAG(findex) ( \
+  (findex) > 31 ? \
+    ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
+    : \
+    ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
+)
+#define SET_ESFR_FLAG(findex) ( \
+  (findex) > 31 ? \
+    (CPU (h_spr[H_SPR_ESFR0]) = \
+      (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
+    ) : \
+    (CPU (h_spr[H_SPR_ESFR1]) = \
+      (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
+    ) \
+)
+
+/* The FSR registers.
+   Get and set the hardware directly, since we may be getting/setting fields
+   which are not accessible to the user.  */
+#define GET_FSR(index) \
+  (CPU (h_spr[H_SPR_FSR0 + (index)]))
+#define SET_FSR(index, fsr) \
+  (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
+
+#define GET_FSR_TEM(fsr) ( \
+  ((fsr) >> 24) & 0x3f     \
+)
+
+#define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
+#define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
+
+#define SET_FSR_FTT(fsr, ftt) (                          \
+  (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
+)
+
+#define GET_FSR_AEXC(fsr) ( \
+  ((fsr) >> 10) & 0x3f      \
+)
+#define SET_FSR_AEXC(fsr, aexc) (                          \
+  (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
+)
+
+/* SIMD instruction exception codes for FQ.  */
+enum frv_sie
+{
+  SIE_NIL   = 0,
+  SIE_FRi   = 1,
+  SIE_FRi_1 = 2
+};
+
+/* MIV field of FQ.  */
+enum frv_miv
+{
+  MIV_FLOAT = 0,
+  MIV_MEDIA = 1
+};
+
+/* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
+   index here refers to the low order 32 bit element.
+   Get and set the hardware directly, since we may be getting/setting fields
+   which are not accessible to the user.  */
+#define GET_FQ(index) \
+  (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
+#define SET_FQ(index, fq) \
+  (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
+
+#define SET_FQ_MIV(fq, miv) (                          \
+  (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
+)
+
+#define SET_FQ_SIE(fq, sie) (                          \
+  (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
+)
+
+#define SET_FQ_FTT(fq, ftt) (                        \
+  (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
+)
+
+#define SET_FQ_CEXC(fq, cexc) (                         \
+  (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
+)
+
+#define GET_FQ_VALID(fq) ((fq) & 1)
+#define SET_FQ_VALID(fq) ((fq) |= 1)
+
+#define SET_FQ_OPC(index, insn) \
+  (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
+
+/* mp_exception support.  */
+/* Media trap types for MSR.  */
+enum frv_msr_mtt
+{
+  MTT_NONE                = 0,
+  MTT_OVERFLOW            = 1,
+  MTT_ACC_NOT_ALIGNED     = 2,
+  MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED.  */
+  MTT_CR_NOT_ALIGNED      = 3,
+  MTT_UNIMPLEMENTED_MPOP  = 5,
+  MTT_INVALID_FR          = 6
+};
+
+/* Media status registers.
+   Get and set the hardware directly, since we may be getting/setting fields
+   which are not accessible to the user.  */
+#define GET_MSR(index) \
+  (CPU (h_spr[H_SPR_MSR0 + (index)]))
+#define SET_MSR(index, msr) \
+  (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
+
+#define GET_MSR_AOVF(msr) ((msr) & 1)
+#define SET_MSR_AOVF(msr) ((msr) |=  1)
+
+#define GET_MSR_OVF(msr) ( \
+  ((msr) >> 1) & 0x1       \
+)
+#define SET_MSR_OVF(msr) ( \
+  (msr) |= (1 << 1)        \
+)
+#define CLEAR_MSR_OVF(msr) ( \
+  (msr) &= ~(1 << 1)         \
+)
+
+#define OR_MSR_SIE(msr, sie) (  \
+  (msr) |= (((sie) & 0xf) << 2) \
+)
+#define CLEAR_MSR_SIE(msr) ( \
+  (msr) &= ~(0xf << 2)       \
+)
+
+#define GET_MSR_MTT(msr) ( \
+  ((msr) >> 12) & 0x7      \
+)
+#define SET_MSR_MTT(msr, mtt) (                          \
+  (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
+)
+#define GET_MSR_EMCI(msr) ( \
+  ((msr) >> 24) & 0x1       \
+)
+#define GET_MSR_SRDAV(msr) ( \
+  ((msr) >> 28) & 0x1        \
+)
+#define GET_MSR_RDAV(msr) ( \
+  ((msr) >> 29) & 0x1       \
+)
+#define GET_MSR_RD(msr) ( \
+  ((msr) >> 30) & 0x3     \
+)
+
+void frvbf_media_register_not_aligned (SIM_CPU *);
+void frvbf_media_acc_not_aligned (SIM_CPU *);
+void frvbf_media_cr_not_aligned (SIM_CPU *);
+void frvbf_media_overflow (SIM_CPU *, int);
+
+/* Functions for queuing and processing interrupts.  */
+struct frv_interrupt_queue_element *
+frv_queue_break_interrupt (SIM_CPU *);
+
+struct frv_interrupt_queue_element *
+frv_queue_software_interrupt (SIM_CPU *, SI);
+
+struct frv_interrupt_queue_element *
+frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);
+
+struct frv_interrupt_queue_element *
+frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
+
+struct frv_interrupt_queue_element *
+frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
+
+struct frv_interrupt_queue_element *
+frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
+
+struct frv_interrupt_queue_element *
+frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);
+
+struct frv_interrupt_queue_element *
+frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
+
+struct frv_interrupt_queue_element *
+frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
+
+struct frv_interrupt_queue_element *
+frv_queue_instruction_access_error_interrupt (SIM_CPU *);
+
+struct frv_interrupt_queue_element *
+frv_queue_instruction_access_exception_interrupt (SIM_CPU *);
+
+struct frv_interrupt_queue_element *
+frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
+
+enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
+
+struct frv_interrupt_queue_element *
+frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
+
+void
+frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);
+
+void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
+void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);
+
+void frv_process_interrupts (SIM_CPU *);
+
+void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
+void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
+void frv_program_interrupt (
+  SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
+);
+void frv_software_interrupt (
+  SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
+);
+void frv_external_interrupt (
+  SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
+);
+void frv_program_or_software_interrupt (
+  SIM_CPU *, struct frv_interrupt *, IADDR
+);
+void frv_clear_interrupt_classes (
+  enum frv_interrupt_class, enum frv_interrupt_class
+);
+
+void
+frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);
+
+/* Special purpose traps.  */
+#define TRAP_SYSCALL	0x80
+#define TRAP_BREAKPOINT	0x81
+#define TRAP_REGDUMP1	0x82
+#define TRAP_REGDUMP2	0x83
+
+/* Handle the trap insns  */
+void frv_itrap (SIM_CPU *, PCADDR, USI, int);
+void frv_mtrap (SIM_CPU *);
+/* Handle the break insn.  */
+void frv_break (SIM_CPU *);
+/* Handle the rett insn.  */
+USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
+
+/* Parallel write queue flags.  */
+#define FRV_WRITE_QUEUE_FORCE_WRITE 1
+
+#define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
+
+/* Functions and macros for handling non-excepting instruction side effects.
+   Get and set the hardware directly, since we may be getting/setting fields
+   which are not accessible to the user.  */
+#define GET_NECR()           (GET_H_SPR (H_SPR_NECR))
+#define GET_NECR_ELOS(necr)  (((necr) >> 6) & 1)
+#define GET_NECR_NEN(necr)   (((necr) >> 1) & 0x1f)
+#define GET_NECR_VALID(necr) (((necr)     ) & 1)
+
+#define NO_NESR    (-1)
+/* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
+   Architecture volume 1.  */
+#define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
+#define NESR_REGISTER_NOT_ALIGNED    0x1
+#define NESR_UQI_SIZE 0
+#define NESR_QI_SIZE  1
+#define NESR_UHI_SIZE 2
+#define NESR_HI_SIZE  3
+#define NESR_SI_SIZE  4
+#define NESR_DI_SIZE  5
+#define NESR_XI_SIZE  6
+
+#define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
+#define SET_NESR(index, value) (                          \
+  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,    \
+			 H_SPR_NESR0 + (index), (value)), \
+  frvbf_force_update (current_cpu)                        \
+)
+#define GET_NESR_VALID(nesr) ((nesr) & 1)
+#define SET_NESR_VALID(nesr) ((nesr) |= 1)
+
+#define SET_NESR_EAV(nesr)   ((nesr) |= (1 << 31))
+
+#define GET_NESR_FR(nesr)    (((nesr) >> 30) & 1)
+#define SET_NESR_FR(nesr)    ((nesr) |= (1 << 30))
+#define CLEAR_NESR_FR(nesr)  ((nesr) &= ~(1 << 30))
+
+#define GET_NESR_DRN(nesr)   (((nesr) >> 24) & 0x3f)
+#define SET_NESR_DRN(nesr, drn) (                            \
+  (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
+)
+
+#define SET_NESR_SIZE(nesr, data_size) (                         \
+  (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
+)
+
+#define SET_NESR_NEAN(nesr, index) (                           \
+  (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
+)
+
+#define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
+#define SET_NESR_DAEC(nesr, daec) (                   \
+  (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
+)
+
+#define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
+#define SET_NESR_REC(nesr, rec) (                    \
+  (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
+)
+
+#define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
+#define SET_NESR_EC(nesr, ec) (                       \
+  (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
+)
+
+#define SET_NEEAR(index, address) ( \
+  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,       \
+			 H_SPR_NEEAR0 + (index), (address)), \
+  frvbf_force_update (current_cpu)                           \
+)
+
+#define GET_NE_FLAGS(flags, NE_base) (   \
+  (flags)[0] = GET_H_SPR ((NE_base)),    \
+  (flags)[1] = GET_H_SPR ((NE_base) + 1) \
+)
+#define SET_NE_FLAGS(NE_base, flags) ( \
+  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base),      \
+                         (flags)[0]),                                  \
+  frvbf_force_update (current_cpu),                                    \
+  sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1,  \
+                         (flags)[1]),                                  \
+  frvbf_force_update (current_cpu)                                     \
+)
+
+#define GET_NE_FLAG(flags, index) (    \
+  (index) > 31 ?                       \
+    ((flags[0] >> ((index) - 32)) & 1) \
+  :                                    \
+    ((flags[1] >> (index)) & 1)        \
+)
+#define SET_NE_FLAG(flags, index) (       \
+  (index) > 31 ?                          \
+    ((flags)[0] |= (1 << ((index) - 32))) \
+  :                                       \
+    ((flags)[1] |= (1 << (index)))        \
+)
+#define CLEAR_NE_FLAG(flags, index) (      \
+  (index) > 31 ?                           \
+    ((flags)[0] &= ~(1 << ((index) - 32))) \
+  :                                        \
+    ((flags)[1] &= ~(1 << (index)))        \
+)
+
+BI   frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
+void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
+
+void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
+void frvbf_commit (SIM_CPU *, SI, BI);
+
+void frvbf_fpu_error (CGEN_FPU *, int);
+
+void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);
+
+extern int insns_in_slot[];
+
+#define COUNT_INSNS_IN_SLOT(slot) \
+{                                 \
+  if (WITH_PROFILE_MODEL_P)       \
+    ++insns_in_slot[slot];        \
+}
+    
+#define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
+    
+/* Multiple loads and stores.  */
+void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
+void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
+void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
+void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
+void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
+void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
+
+/* Memory and cache support.  */
+QI  frvbf_read_mem_QI  (SIM_CPU *, IADDR, SI);
+UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
+HI  frvbf_read_mem_HI  (SIM_CPU *, IADDR, SI);
+UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
+SI  frvbf_read_mem_SI  (SIM_CPU *, IADDR, SI);
+SI  frvbf_read_mem_WI  (SIM_CPU *, IADDR, SI);
+DI  frvbf_read_mem_DI  (SIM_CPU *, IADDR, SI);
+DF  frvbf_read_mem_DF  (SIM_CPU *, IADDR, SI);
+
+USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
+
+void frvbf_write_mem_QI  (SIM_CPU *, IADDR, SI, QI);
+void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
+void frvbf_write_mem_HI  (SIM_CPU *, IADDR, SI, HI);
+void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
+void frvbf_write_mem_SI  (SIM_CPU *, IADDR, SI, SI);
+void frvbf_write_mem_WI  (SIM_CPU *, IADDR, SI, SI);
+void frvbf_write_mem_DI  (SIM_CPU *, IADDR, SI, DI);
+void frvbf_write_mem_DF  (SIM_CPU *, IADDR, SI, DF);
+
+void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
+void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
+void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
+void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
+void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
+void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
+
+void frv_set_write_queue_slot (SIM_CPU *current_cpu);
+
+/* FRV specific options.  */
+extern const OPTION frv_options[];
+
+#endif /* FRV_SIM_H */
diff --git a/sim/frv/frv.c b/sim/frv/frv.c
new file mode 100644
index 00000000000..a13af6b5ecd
--- /dev/null
+++ b/sim/frv/frv.c
@@ -0,0 +1,1419 @@
+/* frv simulator support code
+   Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+#include "cgen-engine.h"
+#include "cgen-par.h"
+#include "bfd.h"
+#include <math.h>
+
+/* Maintain a flag in order to know when to write the address of the next
+   VLIW instruction into the LR register.  Used by JMPL. JMPIL, and CALL
+   insns.  */
+int frvbf_write_next_vliw_addr_to_LR;
+
+/* The contents of BUF are in target byte order.  */
+int
+frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  if (rn <= GR_REGNUM_MAX)
+    SETTSI (buf, GET_H_GR (rn));
+  else if (rn <= FR_REGNUM_MAX)
+    SETTSI (buf, GET_H_FR (rn - GR_REGNUM_MAX - 1));
+  else if (rn == PC_REGNUM)
+    SETTSI (buf, GET_H_PC ());
+  else if (rn == LR_REGNUM)
+    SETTSI (buf, GET_H_SPR (H_SPR_LR));
+  else
+    SETTSI (buf, 0xdeadbeef);
+
+  return -1;
+}
+
+/* The contents of BUF are in target byte order.  */
+
+int
+frvbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  if (rn <= GR_REGNUM_MAX)
+    SET_H_GR (rn, GETTSI (buf));
+  else if (rn <= FR_REGNUM_MAX)
+    SET_H_FR (rn - GR_REGNUM_MAX - 1, GETTSI (buf));
+  else if (rn == PC_REGNUM)
+    SET_H_PC (GETTSI (buf));
+  else if (rn == LR_REGNUM)
+    SET_H_SPR (H_SPR_LR, GETTSI (buf));
+
+  return -1;
+}
+
+/* Cover fns to access the general registers.  */
+USI
+frvbf_h_gr_get_handler (SIM_CPU *current_cpu, UINT gr)
+{
+  frv_check_gr_access (current_cpu, gr);
+  return CPU (h_gr[gr]);
+}
+
+void
+frvbf_h_gr_set_handler (SIM_CPU *current_cpu, UINT gr, USI newval)
+{
+  frv_check_gr_access (current_cpu, gr);
+
+  if (gr == 0)
+    return; /* Storing into gr0 has no effect.  */
+
+  CPU (h_gr[gr]) = newval;
+}
+
+/* Cover fns to access the floating point registers.  */
+SF
+frvbf_h_fr_get_handler (SIM_CPU *current_cpu, UINT fr)
+{
+  frv_check_fr_access (current_cpu, fr);
+  return CPU (h_fr[fr]);
+}
+
+void
+frvbf_h_fr_set_handler (SIM_CPU *current_cpu, UINT fr, SF newval)
+{
+  frv_check_fr_access (current_cpu, fr);
+  CPU (h_fr[fr]) = newval;
+}
+
+/* Cover fns to access the general registers as double words.  */
+static UINT
+check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
+{
+  if (reg & align_mask)
+    {
+      SIM_DESC sd = CPU_STATE (current_cpu);
+      switch (STATE_ARCHITECTURE (sd)->mach)
+	{
+	case bfd_mach_fr400:
+	  frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+	  break;
+	case bfd_mach_frvtomcat:
+	case bfd_mach_fr500:
+	case bfd_mach_frv:
+	  frv_queue_register_exception_interrupt (current_cpu,
+						  FRV_REC_UNALIGNED);
+	  break;
+	default:
+	  break;
+	}
+
+      reg &= ~align_mask;
+    }
+
+  return reg;
+}
+
+static UINT
+check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
+{
+  if (reg & align_mask)
+    {
+      SIM_DESC sd = CPU_STATE (current_cpu);
+      switch (STATE_ARCHITECTURE (sd)->mach)
+	{
+	case bfd_mach_fr400:
+	  frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+	  break;
+	case bfd_mach_frvtomcat:
+	case bfd_mach_fr500:
+	case bfd_mach_frv:
+	  {
+	    struct frv_fp_exception_info fp_info = {
+	      FSR_NO_EXCEPTION, FTT_INVALID_FR
+	    };
+	    frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
+	  }
+	  break;
+	default:
+	  break;
+	}
+
+      reg &= ~align_mask;
+    }
+
+  return reg;
+}
+
+static UINT
+check_memory_alignment (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  if (address & align_mask)
+    {
+      SIM_DESC sd = CPU_STATE (current_cpu);
+      switch (STATE_ARCHITECTURE (sd)->mach)
+	{
+	case bfd_mach_fr400:
+	  frv_queue_data_access_error_interrupt (current_cpu, address);
+	  break;
+	case bfd_mach_frvtomcat:
+	case bfd_mach_fr500:
+	case bfd_mach_frv:
+	  frv_queue_mem_address_not_aligned_interrupt (current_cpu, address);
+	  break;
+	default:
+	  break;
+	}
+
+      address &= ~align_mask;
+    }
+
+  return address;
+}
+
+DI
+frvbf_h_gr_double_get_handler (SIM_CPU *current_cpu, UINT gr)
+{
+  DI value;
+
+  if (gr == 0)
+    return 0; /* gr0 is always 0.  */
+
+  /* Check the register alignment.  */
+  gr = check_register_alignment (current_cpu, gr, 1);
+
+  value = GET_H_GR (gr);
+  value <<= 32;
+  value |=  (USI) GET_H_GR (gr + 1);
+  return value;
+}
+
+void
+frvbf_h_gr_double_set_handler (SIM_CPU *current_cpu, UINT gr, DI newval)
+{
+  if (gr == 0)
+    return; /* Storing into gr0 has no effect.  */
+
+  /* Check the register alignment.  */
+  gr = check_register_alignment (current_cpu, gr, 1);
+
+  SET_H_GR (gr    , (newval >> 32) & 0xffffffff);
+  SET_H_GR (gr + 1, (newval      ) & 0xffffffff);
+}
+
+/* Cover fns to access the floating point register as double words.  */
+DF
+frvbf_h_fr_double_get_handler (SIM_CPU *current_cpu, UINT fr)
+{
+  union {
+    SF as_sf[2];
+    DF as_df;
+  } value;
+
+  /* Check the register alignment.  */
+  fr = check_fr_register_alignment (current_cpu, fr, 1);
+
+  if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
+    {
+      value.as_sf[1] = GET_H_FR (fr);
+      value.as_sf[0] = GET_H_FR (fr + 1);
+    }
+  else
+    {
+      value.as_sf[0] = GET_H_FR (fr);
+      value.as_sf[1] = GET_H_FR (fr + 1);
+    }
+
+  return value.as_df;
+}
+
+void
+frvbf_h_fr_double_set_handler (SIM_CPU *current_cpu, UINT fr, DF newval)
+{
+  union {
+    SF as_sf[2];
+    DF as_df;
+  } value;
+
+  /* Check the register alignment.  */
+  fr = check_fr_register_alignment (current_cpu, fr, 1);
+
+  value.as_df = newval;
+  if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
+    {
+      SET_H_FR (fr    , value.as_sf[1]);
+      SET_H_FR (fr + 1, value.as_sf[0]);
+    }
+  else
+    {
+      SET_H_FR (fr    , value.as_sf[0]);
+      SET_H_FR (fr + 1, value.as_sf[1]);
+    }
+}
+
+/* Cover fns to access the floating point register as integer words.  */
+USI
+frvbf_h_fr_int_get_handler (SIM_CPU *current_cpu, UINT fr)
+{
+  union {
+    SF  as_sf;
+    USI as_usi;
+  } value;
+
+  value.as_sf = GET_H_FR (fr);
+  return value.as_usi;
+}
+
+void
+frvbf_h_fr_int_set_handler (SIM_CPU *current_cpu, UINT fr, USI newval)
+{
+  union {
+    SF  as_sf;
+    USI as_usi;
+  } value;
+
+  value.as_usi = newval;
+  SET_H_FR (fr, value.as_sf);
+}
+
+/* Cover fns to access the coprocessor registers as double words.  */
+DI
+frvbf_h_cpr_double_get_handler (SIM_CPU *current_cpu, UINT cpr)
+{
+  DI value;
+
+  /* Check the register alignment.  */
+  cpr = check_register_alignment (current_cpu, cpr, 1);
+
+  value = GET_H_CPR (cpr);
+  value <<= 32;
+  value |=  (USI) GET_H_CPR (cpr + 1);
+  return value;
+}
+
+void
+frvbf_h_cpr_double_set_handler (SIM_CPU *current_cpu, UINT cpr, DI newval)
+{
+  /* Check the register alignment.  */
+  cpr = check_register_alignment (current_cpu, cpr, 1);
+
+  SET_H_CPR (cpr    , (newval >> 32) & 0xffffffff);
+  SET_H_CPR (cpr + 1, (newval      ) & 0xffffffff);
+}
+
+/* Cover fns to write registers as quad words.  */
+void
+frvbf_h_gr_quad_set_handler (SIM_CPU *current_cpu, UINT gr, SI *newval)
+{
+  if (gr == 0)
+    return; /* Storing into gr0 has no effect.  */
+
+  /* Check the register alignment.  */
+  gr = check_register_alignment (current_cpu, gr, 3);
+
+  SET_H_GR (gr    , newval[0]);
+  SET_H_GR (gr + 1, newval[1]);
+  SET_H_GR (gr + 2, newval[2]);
+  SET_H_GR (gr + 3, newval[3]);
+}
+
+void
+frvbf_h_fr_quad_set_handler (SIM_CPU *current_cpu, UINT fr, SI *newval)
+{
+  /* Check the register alignment.  */
+  fr = check_fr_register_alignment (current_cpu, fr, 3);
+
+  SET_H_FR (fr    , newval[0]);
+  SET_H_FR (fr + 1, newval[1]);
+  SET_H_FR (fr + 2, newval[2]);
+  SET_H_FR (fr + 3, newval[3]);
+}
+
+void
+frvbf_h_cpr_quad_set_handler (SIM_CPU *current_cpu, UINT cpr, SI *newval)
+{
+  /* Check the register alignment.  */
+  cpr = check_register_alignment (current_cpu, cpr, 3);
+
+  SET_H_CPR (cpr    , newval[0]);
+  SET_H_CPR (cpr + 1, newval[1]);
+  SET_H_CPR (cpr + 2, newval[2]);
+  SET_H_CPR (cpr + 3, newval[3]);
+}
+
+/* Cover fns to access the special purpose registers.  */
+USI
+frvbf_h_spr_get_handler (SIM_CPU *current_cpu, UINT spr)
+{
+  /* Check access restrictions.  */
+  frv_check_spr_read_access (current_cpu, spr);
+
+  switch (spr)
+    {
+    case H_SPR_PSR:
+      return spr_psr_get_handler (current_cpu);
+    case H_SPR_TBR:
+      return spr_tbr_get_handler (current_cpu);
+    case H_SPR_BPSR:
+      return spr_bpsr_get_handler (current_cpu);
+    case H_SPR_CCR:
+      return spr_ccr_get_handler (current_cpu);
+    case H_SPR_CCCR:
+      return spr_cccr_get_handler (current_cpu);
+    case H_SPR_SR0:
+    case H_SPR_SR1:
+    case H_SPR_SR2:
+    case H_SPR_SR3:
+      return spr_sr_get_handler (current_cpu, spr);
+      break;
+    default:
+      return CPU (h_spr[spr]);
+    }
+  return 0;
+}
+
+void
+frvbf_h_spr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval)
+{
+  FRV_REGISTER_CONTROL *control;
+  USI mask;
+  USI oldval;
+
+  /* Check access restrictions.  */
+  frv_check_spr_write_access (current_cpu, spr);
+
+  /* Only set those fields which are writeable.  */
+  control = CPU_REGISTER_CONTROL (current_cpu);
+  mask = control->spr[spr].read_only_mask;
+  oldval = GET_H_SPR (spr);
+
+  newval = (newval & ~mask) | (oldval & mask);
+
+  /* Some registers are represented by individual components which are
+     referenced more often than the register itself.  */
+  switch (spr)
+    {
+    case H_SPR_PSR:
+      spr_psr_set_handler (current_cpu, newval);
+      break;
+    case H_SPR_TBR:
+      spr_tbr_set_handler (current_cpu, newval);
+      break;
+    case H_SPR_BPSR:
+      spr_bpsr_set_handler (current_cpu, newval);
+      break;
+    case H_SPR_CCR:
+      spr_ccr_set_handler (current_cpu, newval);
+      break;
+    case H_SPR_CCCR:
+      spr_cccr_set_handler (current_cpu, newval);
+      break;
+    case H_SPR_SR0:
+    case H_SPR_SR1:
+    case H_SPR_SR2:
+    case H_SPR_SR3:
+      spr_sr_set_handler (current_cpu, spr, newval);
+      break;
+    default:
+      CPU (h_spr[spr]) = newval;
+      break;
+    }
+}
+
+/* Cover fns to access the gr_hi and gr_lo registers.  */
+UHI
+frvbf_h_gr_hi_get_handler (SIM_CPU *current_cpu, UINT gr)
+{
+  return (GET_H_GR(gr) >> 16) & 0xffff;
+}
+
+void
+frvbf_h_gr_hi_set_handler (SIM_CPU *current_cpu, UINT gr, UHI newval)
+{
+  USI value = (GET_H_GR (gr) & 0xffff) | (newval << 16);
+  SET_H_GR (gr, value);
+}
+
+UHI
+frvbf_h_gr_lo_get_handler (SIM_CPU *current_cpu, UINT gr)
+{
+  return GET_H_GR(gr) & 0xffff;
+}
+
+void
+frvbf_h_gr_lo_set_handler (SIM_CPU *current_cpu, UINT gr, UHI newval)
+{
+  USI value = (GET_H_GR (gr) & 0xffff0000) | (newval & 0xffff);
+  SET_H_GR (gr, value);
+}
+
+/* Cover fns to access the tbr bits.  */
+USI
+spr_tbr_get_handler (SIM_CPU *current_cpu)
+{
+  int tbr = ((GET_H_TBR_TBA () & 0xfffff) << 12) |
+            ((GET_H_TBR_TT  () &  0xff) <<  4);
+
+  return tbr;
+}
+
+void
+spr_tbr_set_handler (SIM_CPU *current_cpu, USI newval)
+{
+  int tbr = newval;
+
+  SET_H_TBR_TBA ((tbr >> 12) & 0xfffff) ;
+  SET_H_TBR_TT  ((tbr >>  4) & 0xff) ;
+}
+
+/* Cover fns to access the bpsr bits.  */
+USI
+spr_bpsr_get_handler (SIM_CPU *current_cpu)
+{
+  int bpsr = ((GET_H_BPSR_BS  () & 0x1) << 12) |
+             ((GET_H_BPSR_BET () & 0x1)      );
+
+  return bpsr;
+}
+
+void
+spr_bpsr_set_handler (SIM_CPU *current_cpu, USI newval)
+{
+  int bpsr = newval;
+
+  SET_H_BPSR_BS  ((bpsr >> 12) & 1);
+  SET_H_BPSR_BET ((bpsr      ) & 1);
+}
+
+/* Cover fns to access the psr bits.  */
+USI
+spr_psr_get_handler (SIM_CPU *current_cpu)
+{
+  int psr = ((GET_H_PSR_IMPLE () & 0xf) << 28) |
+            ((GET_H_PSR_VER   () & 0xf) << 24) |
+            ((GET_H_PSR_ICE   () & 0x1) << 16) |
+            ((GET_H_PSR_NEM   () & 0x1) << 14) |
+            ((GET_H_PSR_CM    () & 0x1) << 13) |
+            ((GET_H_PSR_BE    () & 0x1) << 12) |
+            ((GET_H_PSR_ESR   () & 0x1) << 11) |
+            ((GET_H_PSR_EF    () & 0x1) <<  8) |
+            ((GET_H_PSR_EM    () & 0x1) <<  7) |
+            ((GET_H_PSR_PIL   () & 0xf) <<  3) |
+            ((GET_H_PSR_S     () & 0x1) <<  2) |
+            ((GET_H_PSR_PS    () & 0x1) <<  1) |
+            ((GET_H_PSR_ET    () & 0x1)      );
+
+  return psr;
+}
+
+void
+spr_psr_set_handler (SIM_CPU *current_cpu, USI newval)
+{
+  /* The handler for PSR.S references the value of PSR.ESR, so set PSR.S
+     first.  */
+  SET_H_PSR_S ((newval >>  2) & 1);
+
+  SET_H_PSR_IMPLE ((newval >> 28) & 0xf);
+  SET_H_PSR_VER   ((newval >> 24) & 0xf);
+  SET_H_PSR_ICE   ((newval >> 16) & 1);
+  SET_H_PSR_NEM   ((newval >> 14) & 1);
+  SET_H_PSR_CM    ((newval >> 13) & 1);
+  SET_H_PSR_BE    ((newval >> 12) & 1);
+  SET_H_PSR_ESR   ((newval >> 11) & 1);
+  SET_H_PSR_EF    ((newval >>  8) & 1);
+  SET_H_PSR_EM    ((newval >>  7) & 1);
+  SET_H_PSR_PIL   ((newval >>  3) & 0xf);
+  SET_H_PSR_PS    ((newval >>  1) & 1);
+  SET_H_PSR_ET    ((newval      ) & 1);
+}
+
+void
+frvbf_h_psr_s_set_handler (SIM_CPU *current_cpu, BI newval)
+{
+  /* If switching from user to supervisor mode, or vice-versa, then switch
+     the supervisor/user context.  */
+  int psr_s = GET_H_PSR_S ();
+  if (psr_s != (newval & 1))
+    {
+      frvbf_switch_supervisor_user_context (current_cpu);
+      CPU (h_psr_s) = newval & 1;
+    }
+}
+
+/* Cover fns to access the ccr bits.  */
+USI
+spr_ccr_get_handler (SIM_CPU *current_cpu)
+{
+  int ccr = ((GET_H_ICCR (H_ICCR_ICC3) & 0xf) << 28) |
+            ((GET_H_ICCR (H_ICCR_ICC2) & 0xf) << 24) |
+            ((GET_H_ICCR (H_ICCR_ICC1) & 0xf) << 20) |
+            ((GET_H_ICCR (H_ICCR_ICC0) & 0xf) << 16) |
+            ((GET_H_FCCR (H_FCCR_FCC3) & 0xf) << 12) |
+            ((GET_H_FCCR (H_FCCR_FCC2) & 0xf) <<  8) |
+            ((GET_H_FCCR (H_FCCR_FCC1) & 0xf) <<  4) |
+            ((GET_H_FCCR (H_FCCR_FCC0) & 0xf)      );
+
+  return ccr;
+}
+
+void
+spr_ccr_set_handler (SIM_CPU *current_cpu, USI newval)
+{
+  int ccr = newval;
+
+  SET_H_ICCR (H_ICCR_ICC3, (newval >> 28) & 0xf);
+  SET_H_ICCR (H_ICCR_ICC2, (newval >> 24) & 0xf);
+  SET_H_ICCR (H_ICCR_ICC1, (newval >> 20) & 0xf);
+  SET_H_ICCR (H_ICCR_ICC0, (newval >> 16) & 0xf);
+  SET_H_FCCR (H_FCCR_FCC3, (newval >> 12) & 0xf);
+  SET_H_FCCR (H_FCCR_FCC2, (newval >>  8) & 0xf);
+  SET_H_FCCR (H_FCCR_FCC1, (newval >>  4) & 0xf);
+  SET_H_FCCR (H_FCCR_FCC0, (newval      ) & 0xf);
+}
+
+QI
+frvbf_set_icc_for_shift_right (
+  SIM_CPU *current_cpu, SI value, SI shift, QI icc
+)
+{
+  /* Set the C flag of the given icc to the logical OR of the bits shifted
+     out.  */
+  int mask = (1 << shift) - 1;
+  if ((value & mask) != 0)
+    return icc | 0x1;
+
+  return icc & 0xe;
+}
+
+QI
+frvbf_set_icc_for_shift_left (
+  SIM_CPU *current_cpu, SI value, SI shift, QI icc
+)
+{
+  /* Set the V flag of the given icc to the logical OR of the bits shifted
+     out.  */
+  int mask = ((1 << shift) - 1) << (32 - shift);
+  if ((value & mask) != 0)
+    return icc | 0x2;
+
+  return icc & 0xd;
+}
+
+/* Cover fns to access the cccr bits.  */
+USI
+spr_cccr_get_handler (SIM_CPU *current_cpu)
+{
+  int cccr = ((GET_H_CCCR (H_CCCR_CC7) & 0x3) << 14) |
+             ((GET_H_CCCR (H_CCCR_CC6) & 0x3) << 12) |
+             ((GET_H_CCCR (H_CCCR_CC5) & 0x3) << 10) |
+             ((GET_H_CCCR (H_CCCR_CC4) & 0x3) <<  8) |
+             ((GET_H_CCCR (H_CCCR_CC3) & 0x3) <<  6) |
+             ((GET_H_CCCR (H_CCCR_CC2) & 0x3) <<  4) |
+             ((GET_H_CCCR (H_CCCR_CC1) & 0x3) <<  2) |
+             ((GET_H_CCCR (H_CCCR_CC0) & 0x3)      );
+
+  return cccr;
+}
+
+void
+spr_cccr_set_handler (SIM_CPU *current_cpu, USI newval)
+{
+  int cccr = newval;
+
+  SET_H_CCCR (H_CCCR_CC7, (newval >> 14) & 0x3);
+  SET_H_CCCR (H_CCCR_CC6, (newval >> 12) & 0x3);
+  SET_H_CCCR (H_CCCR_CC5, (newval >> 10) & 0x3);
+  SET_H_CCCR (H_CCCR_CC4, (newval >>  8) & 0x3);
+  SET_H_CCCR (H_CCCR_CC3, (newval >>  6) & 0x3);
+  SET_H_CCCR (H_CCCR_CC2, (newval >>  4) & 0x3);
+  SET_H_CCCR (H_CCCR_CC1, (newval >>  2) & 0x3);
+  SET_H_CCCR (H_CCCR_CC0, (newval      ) & 0x3);
+}
+
+/* Cover fns to access the sr bits.  */
+USI
+spr_sr_get_handler (SIM_CPU *current_cpu, UINT spr)
+{
+  /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
+     otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3.  */
+  int psr_esr = GET_H_PSR_ESR ();
+  if (! psr_esr)
+    return GET_H_GR (4 + (spr - H_SPR_SR0));
+
+  return CPU (h_spr[spr]);
+}
+
+void
+spr_sr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval)
+{
+  /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
+     otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3.  */
+  int psr_esr = GET_H_PSR_ESR ();
+  if (! psr_esr)
+    SET_H_GR (4 + (spr - H_SPR_SR0), newval);
+  else
+    CPU (h_spr[spr]) = newval;
+}
+
+/* Switch SR0-SR4 with GR4-GR7 if PSR.ESR is set.  */
+void
+frvbf_switch_supervisor_user_context (SIM_CPU *current_cpu)
+{
+  if (GET_H_PSR_ESR ())
+    {
+      /* We need to be in supervisor mode to swap the registers. Access the
+	 PSR.S directly in order to avoid recursive context switches.  */
+      int i;
+      int save_psr_s = CPU (h_psr_s);
+      CPU (h_psr_s) = 1;
+      for (i = 0; i < 4; ++i)
+	{
+	  int gr = i + 4;
+	  int spr = i + H_SPR_SR0;
+	  SI tmp = GET_H_SPR (spr);
+	  SET_H_SPR (spr, GET_H_GR (gr));
+	  SET_H_GR (gr, tmp);
+	}
+      CPU (h_psr_s) = save_psr_s;
+    }
+}
+
+/* Handle load/store of quad registers.  */
+void
+frvbf_load_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix)
+{
+  int i;
+  SI value[4];
+
+  /* Check memory alignment */
+  address = check_memory_alignment (current_cpu, address, 0xf);
+
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 16;
+    }
+  else
+    {
+      for (i = 0; i < 4; ++i)
+	{
+	  value[i] = frvbf_read_mem_SI (current_cpu, pc, address);
+	  address += 4;
+	}
+      sim_queue_fn_xi_write (current_cpu, frvbf_h_gr_quad_set_handler, targ_ix,
+			     value);
+    }
+}
+
+void
+frvbf_store_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix)
+{
+  int i;
+  SI value[4];
+  USI hsr0;
+
+  /* Check register and memory alignment.  */
+  src_ix = check_register_alignment (current_cpu, src_ix, 3);
+  address = check_memory_alignment (current_cpu, address, 0xf);
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* GR0 is always 0.  */
+      if (src_ix == 0)
+	value[i] = 0;
+      else
+	value[i] = GET_H_GR (src_ix + i);
+    }
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value);
+  else
+    sim_queue_mem_xi_write (current_cpu, address, value);
+}
+
+void
+frvbf_load_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix)
+{
+  int i;
+  SI value[4];
+
+  /* Check memory alignment */
+  address = check_memory_alignment (current_cpu, address, 0xf);
+
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 16;
+    }
+  else
+    {
+      for (i = 0; i < 4; ++i)
+	{
+	  value[i] = frvbf_read_mem_SI (current_cpu, pc, address);
+	  address += 4;
+	}
+      sim_queue_fn_xi_write (current_cpu, frvbf_h_fr_quad_set_handler, targ_ix,
+			     value);
+    }
+}
+
+void
+frvbf_store_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix)
+{
+  int i;
+  SI value[4];
+  USI hsr0;
+
+  /* Check register and memory alignment.  */
+  src_ix = check_fr_register_alignment (current_cpu, src_ix, 3);
+  address = check_memory_alignment (current_cpu, address, 0xf);
+
+  for (i = 0; i < 4; ++i)
+    value[i] = GET_H_FR (src_ix + i);
+
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value);
+  else
+    sim_queue_mem_xi_write (current_cpu, address, value);
+}
+
+void
+frvbf_load_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix)
+{
+  int i;
+  SI value[4];
+
+  /* Check memory alignment */
+  address = check_memory_alignment (current_cpu, address, 0xf);
+
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 16;
+    }
+  else
+    {
+      for (i = 0; i < 4; ++i)
+	{
+	  value[i] = frvbf_read_mem_SI (current_cpu, pc, address);
+	  address += 4;
+	}
+      sim_queue_fn_xi_write (current_cpu, frvbf_h_cpr_quad_set_handler, targ_ix,
+			     value);
+    }
+}
+
+void
+frvbf_store_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix)
+{
+  int i;
+  SI value[4];
+  USI hsr0;
+
+  /* Check register and memory alignment.  */
+  src_ix = check_register_alignment (current_cpu, src_ix, 3);
+  address = check_memory_alignment (current_cpu, address, 0xf);
+
+  for (i = 0; i < 4; ++i)
+    value[i] = GET_H_CPR (src_ix + i);
+
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value);
+  else
+    sim_queue_mem_xi_write (current_cpu, address, value);
+}
+
+void
+frvbf_signed_integer_divide (
+  SIM_CPU *current_cpu, SI arg1, SI arg2, int target_index, int non_excepting
+)
+{
+  enum frv_dtt dtt = FRV_DTT_NO_EXCEPTION;
+  if (arg1 == 0x80000000 && arg2 == -1)
+    {
+      /* 0x80000000/(-1) must result in 0x7fffffff when ISR.EDE is set
+	 otherwise it may result in 0x7fffffff (sparc compatibility) or
+	 0x80000000 (C language compatibility). */
+      USI isr;
+      dtt = FRV_DTT_OVERFLOW;
+
+      isr = GET_ISR ();
+      if (GET_ISR_EDE (isr))
+	sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
+			       0x7fffffff);
+      else
+	sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
+			       0x80000000);
+      frvbf_force_update (current_cpu); /* Force update of target register.  */
+    }
+  else if (arg2 == 0)
+    dtt = FRV_DTT_DIVISION_BY_ZERO;
+  else
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
+			   arg1 / arg2);
+
+  /* Check for exceptions.  */
+  if (dtt != FRV_DTT_NO_EXCEPTION)
+    dtt = frvbf_division_exception (current_cpu, dtt, target_index,
+				    non_excepting);
+  if (non_excepting && dtt == FRV_DTT_NO_EXCEPTION)
+    {
+      /* Non excepting instruction. Clear the NE flag for the target
+	 register.  */
+      SI NE_flags[2];
+      GET_NE_FLAGS (NE_flags, H_SPR_GNER0);
+      CLEAR_NE_FLAG (NE_flags, target_index);
+      SET_NE_FLAGS (H_SPR_GNER0, NE_flags);
+    }
+}
+
+void
+frvbf_unsigned_integer_divide (
+  SIM_CPU *current_cpu, USI arg1, USI arg2, int target_index, int non_excepting
+)
+{
+  if (arg2 == 0)
+    frvbf_division_exception (current_cpu, FRV_DTT_DIVISION_BY_ZERO,
+			      target_index, non_excepting);
+  else
+    {
+      sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
+			     arg1 / arg2);
+      if (non_excepting)
+	{
+	  /* Non excepting instruction. Clear the NE flag for the target
+	     register.  */
+	  SI NE_flags[2];
+	  GET_NE_FLAGS (NE_flags, H_SPR_GNER0);
+	  CLEAR_NE_FLAG (NE_flags, target_index);
+	  SET_NE_FLAGS (H_SPR_GNER0, NE_flags);
+	}
+    }
+}
+
+/* Clear accumulators.  */
+void
+frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  int acc_num = 
+    (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 :
+    (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 :
+    63;
+
+  if (A == 0 || acc_ix != 0) /* Clear 1 accumuator?  */
+    {
+      /* This instruction is a nop if the referenced accumulator is not
+	 implemented. */
+      if (acc_ix < acc_num)
+	sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, acc_ix, 0);
+    }
+  else
+    {
+      /* Clear all implemented accumulators.  */
+      int i;
+      for (i = 0; i < acc_num; ++i)
+	sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0);
+    }
+}
+
+/* Functions to aid insn semantics.  */
+
+/* Compute the result of the SCAN and SCANI insns after the shift and xor.  */
+SI
+frvbf_scan_result (SIM_CPU *current_cpu, SI value)
+{
+  SI i;
+  SI mask;
+
+  if (value == 0)
+    return 63;
+
+  /* Find the position of the first non-zero bit.
+     The loop will terminate since there is guaranteed to be at least one
+     non-zero bit.  */
+  mask = 1 << (sizeof (mask) * 8 - 1);
+  for (i = 0; (value & mask) == 0; ++i)
+    value <<= 1;
+
+  return i;
+}
+
+/* Compute the result of the cut insns.  */
+SI
+frvbf_cut (SIM_CPU *current_cpu, SI reg1, SI reg2, SI cut_point)
+{
+  SI result;
+  if (cut_point < 32)
+    {
+      result = reg1 << cut_point;
+      result |= (reg2 >> (32 - cut_point)) & ((1 << cut_point) - 1);
+    }
+  else
+    result = reg2 << (cut_point - 32);
+
+  return result;
+}
+
+/* Compute the result of the cut insns.  */
+SI
+frvbf_media_cut (SIM_CPU *current_cpu, DI acc, SI cut_point)
+{
+  /* The cut point is the lower 6 bits (signed) of what we are passed.  */
+  cut_point = cut_point << 26 >> 26;
+
+  /* The cut_point is relative to bit 40 of 64 bits.  */
+  if (cut_point >= 0)
+    return (acc << (cut_point + 24)) >> 32;
+
+  /* Extend the sign bit (bit 40) for negative cuts.  */
+  if (cut_point == -32)
+    return (acc << 24) >> 63; /* Special case for full shiftout.  */
+
+  return (acc << 24) >> (32 + -cut_point);
+}
+
+/* Compute the result of the cut insns.  */
+SI
+frvbf_media_cut_ss (SIM_CPU *current_cpu, DI acc, SI cut_point)
+{
+  /* The cut point is the lower 6 bits (signed) of what we are passed.  */
+  cut_point = cut_point << 26 >> 26;
+
+  if (cut_point >= 0)
+    {
+      /* The cut_point is relative to bit 40 of 64 bits.  */
+      DI shifted = acc << (cut_point + 24);
+      DI unshifted = shifted >> (cut_point + 24);
+
+      /* The result will be saturated if significant bits are shifted out.  */
+      if (unshifted != acc)
+	{
+	  if (acc < 0)
+	    return 0x80000000;
+	  return 0x7fffffff;
+	}
+    }
+
+  /* The result will not be saturated, so use the code for the normal cut.  */
+  return frvbf_media_cut (current_cpu, acc, cut_point);
+}
+
+/* Simulate the media custom insns.  */
+void
+frvbf_media_cop (SIM_CPU *current_cpu, int cop_num)
+{
+  /* The semantics of the insn are a nop, since it is implementation defined.
+     We do need to check whether it's implemented and set up for MTRAP
+     if it's not.  */
+  USI msr0 = GET_MSR (0);
+  if (GET_MSR_EMCI (msr0) == 0)
+    {
+      /* no interrupt queued at this time.  */
+      frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP, 0);
+    }
+}
+
+/* Simulate the media average (MAVEH) insn.  */
+static HI
+do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  SI sum = (arg1 + arg2);
+  HI result = sum >> 1;
+
+  /* On fr400, check the rounding mode.  On other machines rounding is always
+     toward negative infinity and the result is already correctly rounded.  */
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    {
+      /* Check whether rounding will be required.  Rounding will be required
+	 if the sum is an odd number.  */
+      int rounding_value = sum & 1;
+      if (rounding_value)
+	{
+	  USI msr0 = GET_MSR (0);
+	  /* Check MSR0.SRDAV to determine which bits control the rounding.  */
+	  if (GET_MSR_SRDAV (msr0))
+	    {
+	      /* MSR0.RD controls rounding.  */
+	      switch (GET_MSR_RD (msr0))
+		{
+		case 0:
+		  /* Round to nearest.  */
+		  if (result >= 0)
+		    ++result;
+		  break;
+		case 1:
+		  /* Round toward 0. */
+		  if (result < 0)
+		    ++result;
+		  break;
+		case 2:
+		  /* Round toward positive infinity.  */
+		  ++result;
+		  break;
+		case 3:
+		  /* Round toward negative infinity.  The result is already
+		     correctly rounded.  */
+		  break;
+		default:
+		  abort ();
+		  break;
+		}
+	    }
+	  else
+	    {
+	      /* MSR0.RDAV controls rounding.  If set, round toward positive
+		 infinity.  Otherwise the result is already rounded correctly
+		 toward negative infinity.  */
+	      if (GET_MSR_RDAV (msr0))
+		++result;
+	    }
+	}
+    }
+
+  return result;
+}
+
+SI
+frvbf_media_average (SIM_CPU *current_cpu, SI reg1, SI reg2)
+{
+  SI result;
+  result  = do_media_average (current_cpu, reg1 & 0xffff, reg2 & 0xffff);
+  result &= 0xffff;
+  result |= do_media_average (current_cpu, (reg1 >> 16) & 0xffff,
+			      (reg2 >> 16) & 0xffff) << 16;
+  return result;
+}
+
+/* Maintain a flag in order to know when to write the address of the next
+   VLIW instruction into the LR register.  Used by JMPL. JMPIL, and CALL.  */
+void
+frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *current_cpu, int value)
+{
+  frvbf_write_next_vliw_addr_to_LR = value;
+}
+
+void
+frvbf_set_ne_index (SIM_CPU *current_cpu, int index)
+{
+  USI NE_flags[2];
+
+  /* Save the target register so interrupt processing can set its NE flag
+     in the event of an exception.  */
+  frv_interrupt_state.ne_index = index;
+
+  /* Clear the NE flag of the target register. It will be reset if necessary
+     in the event of an exception.  */
+  GET_NE_FLAGS (NE_flags, H_SPR_FNER0);
+  CLEAR_NE_FLAG (NE_flags, index);
+  SET_NE_FLAGS (H_SPR_FNER0, NE_flags);
+}
+
+void
+frvbf_force_update (SIM_CPU *current_cpu)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
+  int ix = CGEN_WRITE_QUEUE_INDEX (q);
+  if (ix > 0)
+    {
+      CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, ix - 1);
+      item->flags |= FRV_WRITE_QUEUE_FORCE_WRITE;
+    }
+}
+
+/* Condition code logic.  */
+enum cr_ops {
+  andcr, orcr, xorcr, nandcr, norcr, andncr, orncr, nandncr, norncr,
+  num_cr_ops
+};
+
+enum cr_result {cr_undefined, cr_undefined1, cr_false, cr_true};
+
+static enum cr_result
+cr_logic[num_cr_ops][4][4] = {
+  /* andcr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* false     */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* true      */ {cr_undefined, cr_undefined, cr_false,     cr_true     }
+  },
+  /* orcr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_false,     cr_true     },
+    /* undefined */ {cr_undefined, cr_undefined, cr_false,     cr_true     },
+    /* false     */ {cr_false,     cr_false,     cr_false,     cr_true     },
+    /* true      */ {cr_true,      cr_true,      cr_true,      cr_true     }
+  },
+  /* xorcr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* false     */ {cr_undefined, cr_undefined, cr_false,     cr_true     },
+    /* true      */ {cr_true,      cr_true,      cr_true,      cr_false    }
+  },
+  /* nandcr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* false     */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* true      */ {cr_undefined, cr_undefined, cr_true,      cr_false    }
+  },
+  /* norcr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_true,      cr_false    },
+    /* undefined */ {cr_undefined, cr_undefined, cr_true,      cr_false    },
+    /* false     */ {cr_true,      cr_true,      cr_true,      cr_false    },
+    /* true      */ {cr_false,     cr_false,     cr_false,     cr_false    }
+  },
+  /* andncr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* false     */ {cr_undefined, cr_undefined, cr_false,     cr_true     },
+    /* true      */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}
+  },
+  /* orncr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_false,     cr_true     },
+    /* undefined */ {cr_undefined, cr_undefined, cr_false,     cr_true     },
+    /* false     */ {cr_true,      cr_true,      cr_true,      cr_true     },
+    /* true      */ {cr_false,     cr_false,     cr_false,     cr_true     }
+  },
+  /* nandncr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
+    /* false     */ {cr_undefined, cr_undefined, cr_true,      cr_false    },
+    /* true      */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}
+  },
+  /* norncr */
+  {
+    /*                undefined     undefined       false         true */
+    /* undefined */ {cr_undefined, cr_undefined, cr_true,      cr_false    },
+    /* undefined */ {cr_undefined, cr_undefined, cr_true,      cr_false    },
+    /* false     */ {cr_false,     cr_false,     cr_false,     cr_false    },
+    /* true      */ {cr_true,      cr_true,      cr_true,      cr_false    }
+  }
+};
+
+UQI
+frvbf_cr_logic (SIM_CPU *current_cpu, SI operation, UQI arg1, UQI arg2)
+{
+  return cr_logic[operation][arg1][arg2];
+}
+
+/* Cache Manipulation.  */
+void
+frvbf_insn_cache_preload (SIM_CPU *current_cpu, SI address, USI length, int lock)
+{
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  int hsr0 = GET_HSR0 ();
+  if (GET_HSR0_ICE (hsr0))
+    {
+      if (model_insn)
+	{
+	  CPU_LOAD_ADDRESS (current_cpu) = address;
+	  CPU_LOAD_LENGTH (current_cpu) = length;
+	  CPU_LOAD_LOCK (current_cpu) = lock;
+	}
+      else
+	{
+	  FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu);
+	  frv_cache_preload (cache, address, length, lock);
+	}
+    }
+}
+
+void
+frvbf_data_cache_preload (SIM_CPU *current_cpu, SI address, USI length, int lock)
+{
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  int hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    {
+      if (model_insn)
+	{
+	  CPU_LOAD_ADDRESS (current_cpu) = address;
+	  CPU_LOAD_LENGTH (current_cpu) = length;
+	  CPU_LOAD_LOCK (current_cpu) = lock;
+	}
+      else
+	{
+	  FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+	  frv_cache_preload (cache, address, length, lock);
+	}
+    }
+}
+
+void
+frvbf_insn_cache_unlock (SIM_CPU *current_cpu, SI address)
+{
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  int hsr0 = GET_HSR0 ();
+  if (GET_HSR0_ICE (hsr0))
+    {
+      if (model_insn)
+	CPU_LOAD_ADDRESS (current_cpu) = address;
+      else
+	{
+	  FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu);
+	  frv_cache_unlock (cache, address);
+	}
+    }
+}
+
+void
+frvbf_data_cache_unlock (SIM_CPU *current_cpu, SI address)
+{
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  int hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    {
+      if (model_insn)
+	CPU_LOAD_ADDRESS (current_cpu) = address;
+      else
+	{
+	  FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+	  frv_cache_unlock (cache, address);
+	}
+    }
+}
+
+void
+frvbf_insn_cache_invalidate (SIM_CPU *current_cpu, SI address, int all)
+{
+  /* Make sure the insn was specified properly.  -1 will be passed for ALL
+     for a icei with A=0.  */
+  if (all == -1)
+    {
+      frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+      return;
+    }
+
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      /* Record the all-entries flag for use in profiling.  */
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+      ps->all_cache_entries = all;
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+    }
+  else
+    {
+      FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu);
+      if (all)
+	frv_cache_invalidate_all (cache, 0/* flush? */);
+      else
+	frv_cache_invalidate (cache, address, 0/* flush? */);
+    }
+}
+
+void
+frvbf_data_cache_invalidate (SIM_CPU *current_cpu, SI address, int all)
+{
+  /* Make sure the insn was specified properly.  -1 will be passed for ALL
+     for a dcei with A=0.  */
+  if (all == -1)
+    {
+      frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+      return;
+    }
+
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      /* Record the all-entries flag for use in profiling.  */
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+      ps->all_cache_entries = all;
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+    }
+  else
+    {
+      FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+      if (all)
+	frv_cache_invalidate_all (cache, 0/* flush? */);
+      else
+	frv_cache_invalidate (cache, address, 0/* flush? */);
+    }
+}
+
+void
+frvbf_data_cache_flush (SIM_CPU *current_cpu, SI address, int all)
+{
+  /* Make sure the insn was specified properly.  -1 will be passed for ALL
+     for a dcef with A=0.  */
+  if (all == -1)
+    {
+      frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+      return;
+    }
+
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      /* Record the all-entries flag for use in profiling.  */
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+      ps->all_cache_entries = all;
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+    }
+  else
+    {
+      FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+      if (all)
+	frv_cache_invalidate_all (cache, 1/* flush? */);
+      else
+	frv_cache_invalidate (cache, address, 1/* flush? */);
+    }
+}
diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c
new file mode 100644
index 00000000000..1f5547e09e5
--- /dev/null
+++ b/sim/frv/interrupts.c
@@ -0,0 +1,1329 @@
+/* frv exception and interrupt support
+   Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+/* FR-V Interrupt table.
+   Describes the interrupts supported by the FR-V.
+   This table *must* be maintained in order of interrupt priority as defined by
+   frv_interrupt_kind.  */
+#define DEFERRED 1
+#define PRECISE  1
+#define ITABLE_ENTRY(name, class, deferral, precision, offset) \
+  {FRV_##name, FRV_EC_##name, class, deferral, precision, offset}
+
+struct frv_interrupt frv_interrupt_table[NUM_FRV_INTERRUPT_KINDS] =
+{
+  /* External interrupts */
+  ITABLE_ENTRY(INTERRUPT_LEVEL_1,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x21),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_2,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x22),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_3,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x23),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_4,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x24),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_5,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x25),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_6,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x26),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_7,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x27),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_8,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x28),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_9,            FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x29),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_10,           FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2a),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_11,           FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2b),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_12,           FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2c),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_13,           FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2d),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_14,           FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2e),
+  ITABLE_ENTRY(INTERRUPT_LEVEL_15,           FRV_EXTERNAL_INTERRUPT, !DEFERRED, !PRECISE, 0x2f),
+  /* Software interrupt */
+  ITABLE_ENTRY(TRAP_INSTRUCTION,             FRV_SOFTWARE_INTERRUPT, !DEFERRED, !PRECISE, 0x80),
+  /* Program interrupts */
+  ITABLE_ENTRY(COMMIT_EXCEPTION,             FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x19),
+  ITABLE_ENTRY(DIVISION_EXCEPTION,           FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x17),
+  ITABLE_ENTRY(DATA_STORE_ERROR,             FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x14),
+  ITABLE_ENTRY(DATA_ACCESS_EXCEPTION,        FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x13),
+  ITABLE_ENTRY(DATA_ACCESS_MMU_MISS,         FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x12),
+  ITABLE_ENTRY(DATA_ACCESS_ERROR,            FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x11),
+  ITABLE_ENTRY(MP_EXCEPTION,                 FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x0e),
+  ITABLE_ENTRY(FP_EXCEPTION,                 FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x0d),
+  ITABLE_ENTRY(MEM_ADDRESS_NOT_ALIGNED,      FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x10),
+  ITABLE_ENTRY(REGISTER_EXCEPTION,           FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x08),
+  ITABLE_ENTRY(MP_DISABLED,                  FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x0b),
+  ITABLE_ENTRY(FP_DISABLED,                  FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x0a),
+  ITABLE_ENTRY(PRIVILEGED_INSTRUCTION,       FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x06),
+  ITABLE_ENTRY(ILLEGAL_INSTRUCTION,          FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x07),
+  ITABLE_ENTRY(INSTRUCTION_ACCESS_EXCEPTION, FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x03),
+  ITABLE_ENTRY(INSTRUCTION_ACCESS_ERROR,     FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x02),
+  ITABLE_ENTRY(INSTRUCTION_ACCESS_MMU_MISS,  FRV_PROGRAM_INTERRUPT,  !DEFERRED,  PRECISE, 0x01),
+  ITABLE_ENTRY(COMPOUND_EXCEPTION,           FRV_PROGRAM_INTERRUPT,  !DEFERRED, !PRECISE, 0x20),
+  /* Break interrupt */
+  ITABLE_ENTRY(BREAK_EXCEPTION,              FRV_BREAK_INTERRUPT,    !DEFERRED, !PRECISE, 0xff),
+  /* Reset interrupt */
+  ITABLE_ENTRY(RESET,                        FRV_RESET_INTERRUPT,    !DEFERRED, !PRECISE, 0x00)
+};
+
+/* The current interrupt state.  */
+struct frv_interrupt_state frv_interrupt_state;
+
+/* maintain the address of the start of the previous VLIW insn sequence.  */
+IADDR previous_vliw_pc;
+
+/* Add a break interrupt to the interrupt queue.  */
+struct frv_interrupt_queue_element *
+frv_queue_break_interrupt (SIM_CPU *current_cpu)
+{
+  return frv_queue_interrupt (current_cpu, FRV_BREAK_EXCEPTION);
+}
+
+/* Add a software interrupt to the interrupt queue.  */
+struct frv_interrupt_queue_element *
+frv_queue_software_interrupt (SIM_CPU *current_cpu, SI offset)
+{
+  struct frv_interrupt_queue_element *new_element
+    = frv_queue_interrupt (current_cpu, FRV_TRAP_INSTRUCTION);
+
+  struct frv_interrupt *interrupt = & frv_interrupt_table[new_element->kind];
+  interrupt->handler_offset = offset;
+
+  return new_element;
+}
+
+/* Add a program interrupt to the interrupt queue.  */
+struct frv_interrupt_queue_element *
+frv_queue_program_interrupt (
+  SIM_CPU *current_cpu, enum frv_interrupt_kind kind
+)
+{
+  return frv_queue_interrupt (current_cpu, kind);
+}
+
+/* Add an external interrupt to the interrupt queue.  */
+struct frv_interrupt_queue_element *
+frv_queue_external_interrupt (
+  SIM_CPU *current_cpu, enum frv_interrupt_kind kind
+)
+{
+  if (! GET_H_PSR_ET ()
+      || (kind != FRV_INTERRUPT_LEVEL_15 && kind < GET_H_PSR_PIL ()))
+    return NULL; /* Leave it for later.  */
+
+  return frv_queue_interrupt (current_cpu, kind);
+}
+
+/* Add any interrupt to the interrupt queue. It will be added in reverse
+   priority order.  This makes it easy to find the highest priority interrupt
+   at the end of the queue and to remove it after processing.  */
+struct frv_interrupt_queue_element *
+frv_queue_interrupt (SIM_CPU *current_cpu, enum frv_interrupt_kind kind)
+{
+  int i;
+  int j;
+  int limit = frv_interrupt_state.queue_index;
+  struct frv_interrupt_queue_element *new_element;
+  enum frv_interrupt_class iclass;
+
+  if (limit >= FRV_INTERRUPT_QUEUE_SIZE)
+    abort (); /* TODO: Make the queue dynamic */
+
+  /* Find the right place in the queue.  */
+  for (i = 0; i < limit; ++i)
+    {
+      if (frv_interrupt_state.queue[i].kind >= kind)
+	break;
+    }
+
+  /* Don't queue two external interrupts of the same priority.  */
+  iclass = frv_interrupt_table[kind].iclass;
+  if (i < limit && iclass == FRV_EXTERNAL_INTERRUPT)
+    {
+      if (frv_interrupt_state.queue[i].kind == kind)
+	return & frv_interrupt_state.queue[i];
+    }
+
+  /* Make room for the new interrupt in this spot.  */
+  for (j = limit - 1; j >= i; --j)
+    frv_interrupt_state.queue[j + 1] = frv_interrupt_state.queue[j];
+
+  /* Add the new interrupt.  */
+  frv_interrupt_state.queue_index++;
+  new_element = & frv_interrupt_state.queue[i];
+  new_element->kind = kind;
+  new_element->vpc = CPU_PC_GET (current_cpu);
+  new_element->u.data_written.length = 0;
+  frv_set_interrupt_queue_slot (current_cpu, new_element);
+
+  return new_element;
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_register_exception_interrupt (SIM_CPU *current_cpu, enum frv_rec rec)
+{
+  struct frv_interrupt_queue_element *new_element =
+    frv_queue_program_interrupt (current_cpu, FRV_REGISTER_EXCEPTION);
+
+  new_element->u.rec = rec;
+
+  return new_element;
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *current_cpu, USI addr)
+{
+  struct frv_interrupt_queue_element *new_element;
+  USI isr = GET_ISR ();
+
+  /* Make sure that this exception is not masked.  */
+  if (GET_ISR_EMAM (isr))
+    return NULL;
+
+  /* Queue the interrupt.  */
+  new_element = frv_queue_program_interrupt (current_cpu,
+					     FRV_MEM_ADDRESS_NOT_ALIGNED);
+  new_element->eaddress = addr;
+  new_element->u.data_written = frv_interrupt_state.data_written;
+  frv_interrupt_state.data_written.length = 0;
+
+  return new_element;
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_data_access_error_interrupt (SIM_CPU *current_cpu, USI addr)
+{
+  struct frv_interrupt_queue_element *new_element;
+  new_element = frv_queue_program_interrupt (current_cpu,
+					     FRV_DATA_ACCESS_ERROR);
+  new_element->eaddress = addr;
+  return new_element;
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_data_access_exception_interrupt (SIM_CPU *current_cpu)
+{
+  return frv_queue_program_interrupt (current_cpu, FRV_DATA_ACCESS_EXCEPTION);
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_instruction_access_error_interrupt (SIM_CPU *current_cpu)
+{
+  return frv_queue_program_interrupt (current_cpu, FRV_INSTRUCTION_ACCESS_ERROR);
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_instruction_access_exception_interrupt (SIM_CPU *current_cpu)
+{
+  return frv_queue_program_interrupt (current_cpu, FRV_INSTRUCTION_ACCESS_EXCEPTION);
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_illegal_instruction_interrupt (
+  SIM_CPU *current_cpu, const CGEN_INSN *insn
+)
+{
+  /* The fr400 does not have the fp_exception.  */
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
+    {
+      if (frv_is_float_insn (insn) || frv_is_media_insn (insn))
+	{
+	  struct frv_fp_exception_info fp_info = {
+	    FSR_NO_EXCEPTION, FTT_SEQUENCE_ERROR
+	  };
+	  return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
+	}
+    }
+
+  return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_non_implemented_instruction_interrupt (
+  SIM_CPU *current_cpu, const CGEN_INSN *insn
+)
+{
+  /* The fr400 does not have the fp_exception, nor does it generate mp_exception
+     for this case.  */
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
+    {
+      if (frv_is_float_insn (insn))
+	{
+	  struct frv_fp_exception_info fp_info = {
+	    FSR_NO_EXCEPTION, FTT_UNIMPLEMENTED_FPOP
+	  };
+	  return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
+	}
+
+      if (frv_is_media_insn (insn))
+	{
+	  frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP,
+					  0);
+	  return NULL; /* no interrupt queued at this time.  */
+	}
+
+    }
+
+  return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+}
+
+/* Queue the given fp_exception interrupt. Also update fp_info by removing
+   masked interrupts and updating the 'slot' flield.  */
+struct frv_interrupt_queue_element *
+frv_queue_fp_exception_interrupt (
+  SIM_CPU *current_cpu, struct frv_fp_exception_info *fp_info
+)
+{
+  SI fsr0 = GET_FSR (0);
+  int tem = GET_FSR_TEM (fsr0);
+  int aexc = GET_FSR_AEXC (fsr0);
+  struct frv_interrupt_queue_element *new_element = NULL;
+
+  /* Update AEXC with the interrupts that are masked.  */
+  aexc |= fp_info->fsr_mask & ~tem;
+  SET_FSR_AEXC (fsr0, aexc);
+  SET_FSR (0, fsr0);
+
+  /* update fsr_mask with the exceptions that are enabled.  */
+  fp_info->fsr_mask &= tem;
+
+  /* If there is an unmasked interrupt then queue it, unless
+     this was a non-excepting insn, in which case simply set the NE
+     status registers.  */
+  if (frv_interrupt_state.ne_index != NE_NOFLAG
+      && fp_info->fsr_mask != FSR_NO_EXCEPTION)
+    {
+      SET_NE_FLAG (frv_interrupt_state.f_ne_flags, 
+		   frv_interrupt_state.ne_index);
+      /* TODO -- Set NESR for chips which support it.  */
+      new_element = NULL;
+    }
+  else if (fp_info->fsr_mask != FSR_NO_EXCEPTION
+	   || fp_info->ftt == FTT_UNIMPLEMENTED_FPOP
+	   || fp_info->ftt == FTT_SEQUENCE_ERROR
+	   || fp_info->ftt == FTT_INVALID_FR)
+    {
+      new_element = frv_queue_program_interrupt (current_cpu, FRV_FP_EXCEPTION);
+      new_element->u.fp_info = *fp_info;
+    }
+
+  return new_element;
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_division_exception_interrupt (SIM_CPU *current_cpu, enum frv_dtt dtt)
+{
+  struct frv_interrupt_queue_element *new_element =
+    frv_queue_program_interrupt (current_cpu, FRV_DIVISION_EXCEPTION);
+
+  new_element->u.dtt = dtt;
+
+  return new_element;
+}
+
+/* Check for interrupts caused by illegal insn access.  These conditions are
+   checked in the order specified by the fr400 and fr500 LSI specs.  */
+void
+frv_detect_insn_access_interrupts (SIM_CPU *current_cpu, SCACHE *sc)
+{
+
+  const CGEN_INSN *insn = sc->argbuf.idesc->idata;
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  FRV_VLIW *vliw = CPU_VLIW (current_cpu);
+
+  /* Check for vliw constraints.  */
+  if (vliw->constraint_violation)
+    frv_queue_illegal_instruction_interrupt (current_cpu, insn);
+  /* Check for non-excepting insns.  */
+  else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NON_EXCEPTING)
+      && ! GET_H_PSR_NEM ())
+    frv_queue_non_implemented_instruction_interrupt (current_cpu, insn);
+  /* Check for conditional insns.  */
+  else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONDITIONAL)
+      && ! GET_H_PSR_CM ())
+    frv_queue_non_implemented_instruction_interrupt (current_cpu, insn);
+  /* Make sure floating point support is enabled.  */
+  else if (! GET_H_PSR_EF ())
+    {
+      /* Generate fp_disabled if it is a floating point insn or if PSR.EM is
+	 off and the insns accesses a fp register.  */
+      if (frv_is_float_insn (insn)
+	  || (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS)
+	      && ! GET_H_PSR_EM ()))
+	frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED);
+    }
+  /* Make sure media support is enabled.  */
+  else if (! GET_H_PSR_EM ())
+    {
+      /* Generate mp_disabled if it is a media insn.  */
+      if (frv_is_media_insn (insn) || CGEN_INSN_NUM (insn) == FRV_INSN_MTRAP)
+	frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
+    }
+  /* Check for privileged insns.  */
+  else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRIVILEGED) &&
+	   ! GET_H_PSR_S ())
+    frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
+#if 0 /* disable for now until we find out how FSR0.QNE gets reset.  */
+  else
+    {
+      /* Enter the halt state if FSR0.QNE is set and we are executing a
+	 floating point insn, a media insn or an insn which access a FR
+	 register.  */
+      SI fsr0 = GET_FSR (0);
+      if (GET_FSR_QNE (fsr0)
+	  && (frv_is_float_insn (insn) || frv_is_media_insn (insn)
+	      || CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS)))
+	{
+	  sim_engine_halt (sd, current_cpu, NULL, GET_H_PC (), sim_stopped,
+			   SIM_SIGINT);
+	}
+    }
+#endif
+}
+
+/* Record the current VLIW slot in the given interrupt queue element.  */
+void
+frv_set_interrupt_queue_slot (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
+)
+{
+  FRV_VLIW *vliw = CPU_VLIW (current_cpu);
+  int slot = vliw->next_slot - 1;
+  item->slot = (*vliw->current_vliw)[slot];
+}
+
+/* Handle an individual interrupt.  */
+static void
+handle_interrupt (SIM_CPU *current_cpu, IADDR pc)
+{
+  struct frv_interrupt *interrupt;
+  int writeback_done = 0;
+  while (1)
+    {
+      /* Interrupts are queued in priority order with the highest priority
+	 last.  */
+      int index = frv_interrupt_state.queue_index - 1;
+      struct frv_interrupt_queue_element *item
+	= & frv_interrupt_state.queue[index];
+      interrupt = & frv_interrupt_table[item->kind];
+
+      switch (interrupt->iclass)
+	{
+	case FRV_EXTERNAL_INTERRUPT:
+	  /* Perform writeback first. This may cause a higher priority
+	     interrupt.  */
+	  if (! writeback_done)
+	    {
+	      frvbf_perform_writeback (current_cpu);
+	      writeback_done = 1;
+	      continue;
+	    }
+	  frv_external_interrupt (current_cpu, item, pc);
+	  return;
+	case FRV_SOFTWARE_INTERRUPT:
+	  frv_interrupt_state.queue_index = index;
+	  frv_software_interrupt (current_cpu, item, pc);
+	  return;
+	case FRV_PROGRAM_INTERRUPT:
+	  /* If the program interrupt is not strict (imprecise), then perform
+	     writeback first. This may, in turn, cause a higher priority
+	     interrupt.  */
+	  if (! interrupt->precise && ! writeback_done)
+	    {
+	      frv_interrupt_state.imprecise_interrupt = item;
+	      frvbf_perform_writeback (current_cpu);
+	      writeback_done = 1;
+	      continue;
+	    }
+	  frv_interrupt_state.queue_index = index;
+	  frv_program_interrupt (current_cpu, item, pc);
+	  return;
+	case FRV_BREAK_INTERRUPT:
+	  frv_interrupt_state.queue_index = index;
+	  frv_break_interrupt (current_cpu, interrupt, pc);
+	  return;
+	case FRV_RESET_INTERRUPT:
+	  break;
+	default:
+	  break;
+	}
+      frv_interrupt_state.queue_index = index;
+      break; /* out of loop.  */
+    }
+
+  /* We should never get here.  */
+  {
+    SIM_DESC sd = CPU_STATE (current_cpu);
+    sim_engine_abort (sd, current_cpu, pc,
+		      "interrupt class not supported %d\n",
+		      interrupt->iclass);
+  }
+}
+
+/* Check to see the if the RSTR.HR or RSTR.SR bits have been set.  If so, handle
+   the appropriate reset interrupt.  */
+static int
+check_reset (SIM_CPU *current_cpu, IADDR pc)
+{
+  int hsr0;
+  int hr;
+  int sr;
+  SI rstr;
+  FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+  IADDR address = RSTR_ADDRESS;
+
+  /* We don't want this to show up in the cache statistics, so read the
+     cache passively.  */
+  if (! frv_cache_read_passive_SI (cache, address, & rstr))
+    rstr = sim_core_read_unaligned_4 (current_cpu, pc, read_map, address);
+
+  hr = GET_RSTR_HR (rstr);
+  sr = GET_RSTR_SR (rstr);
+
+  if (! hr && ! sr)
+    return 0; /* no reset.  */
+
+  /* Reinitialize the machine state.  */
+  if (hr)
+    frv_hardware_reset (current_cpu);
+  else
+    frv_software_reset (current_cpu);
+
+  /* Branch to the reset address.  */
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_SA (hsr0))
+    SET_H_PC (0xff000000);
+  else
+    SET_H_PC (0);
+
+  return 1; /* reset */
+}
+
+/* Process any pending interrupt(s) after a group of parallel insns.  */
+void
+frv_process_interrupts (SIM_CPU *current_cpu)
+{
+  SI NE_flags[2];
+  /* Need to save the pc here because writeback may change it (due to a
+     branch).  */
+  IADDR pc = CPU_PC_GET (current_cpu);
+
+  /* Check for a reset before anything else.  */
+  if (check_reset (current_cpu, pc))
+    return;
+
+  /* First queue the writes for any accumulated NE flags.  */
+  if (frv_interrupt_state.f_ne_flags[0] != 0
+      || frv_interrupt_state.f_ne_flags[1] != 0)
+    {
+      GET_NE_FLAGS (NE_flags, H_SPR_FNER0);
+      NE_flags[0] |= frv_interrupt_state.f_ne_flags[0];
+      NE_flags[1] |= frv_interrupt_state.f_ne_flags[1];
+      SET_NE_FLAGS (H_SPR_FNER0, NE_flags);
+    }
+
+  /* If there is no interrupt pending, then perform parallel writeback.  This
+     may cause an interrupt.  */
+  if (frv_interrupt_state.queue_index <= 0)
+    frvbf_perform_writeback (current_cpu);
+
+  /* If there is an interrupt pending, then process it.  */
+  if (frv_interrupt_state.queue_index > 0)
+    handle_interrupt (current_cpu, pc);
+}
+
+/* Find the next available ESR and return its index */
+static int
+esr_for_data_access_exception (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
+)
+{
+  if (item->slot == UNIT_I0)
+    return 8; /* Use ESR8, EPCR8, EAR8, EDR8.  */
+
+  return 9; /* Use ESR9, EPCR9, EAR9.  */
+}
+
+/* Set the next available EDR register with the data which was to be stored
+   and return the index of the register.  */
+static int
+set_edr_register (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, int edr_index
+)
+{
+  /* EDR0, EDR4 and EDR8 are available as blocks of 4.
+       SI data uses EDR3, EDR7 and EDR11
+       DI data uses EDR2, EDR6 and EDR10
+       XI data uses EDR0, EDR4 and EDR8.  */
+  int i;
+  edr_index += 4 - item->u.data_written.length;
+  for (i = 0; i < item->u.data_written.length; ++i)
+    SET_EDR (edr_index + i, item->u.data_written.words[i]);
+
+  return edr_index;
+};
+
+/* Clear ESFR0, EPCRx, ESRx, EARx and EDRx.  */
+static void
+clear_exception_status_registers (SIM_CPU *current_cpu)
+{
+  int i;
+  /* It is only necessary to clear the flag bits indicating which registers
+     are valid.  */
+  SET_ESFR (0, 0);
+  SET_ESFR (1, 0);
+
+  for (i = 0; i <= 2; ++i)
+    {
+      SI esr = GET_ESR (i);
+      CLEAR_ESR_VALID (esr);
+      SET_ESR (i, esr);
+    }
+  for (i = 8; i <= 13; ++i)
+    {
+      SI esr = GET_ESR (i);
+      CLEAR_ESR_VALID (esr);
+      SET_ESR (i, esr);
+    }
+}
+
+/* Record state for media exception.  */
+void
+frv_set_mp_exception_registers (
+  SIM_CPU *current_cpu, enum frv_msr_mtt mtt, int sie
+)
+{
+  /* Record the interrupt factor in MSR0.  */
+  SI msr0 = GET_MSR (0);
+  if (GET_MSR_MTT (msr0) == MTT_NONE)
+    SET_MSR_MTT (msr0, mtt);
+
+  /* Also set the OVF bit in the appropriate MSR as well as MSR0.AOVF.  */
+  if (mtt == MTT_OVERFLOW)
+    {
+      FRV_VLIW *vliw = CPU_VLIW (current_cpu);
+      int slot = vliw->next_slot - 1;
+
+      /* If this insn is in the M2 slot, then set MSR1.OVF and MSR1.SIE,
+	 otherwise set MSR0.OVF and MSR0.SIE.  */
+      if ((*vliw->current_vliw)[slot] == UNIT_FM1)
+	{
+	  SI msr = GET_MSR (1);
+	  OR_MSR_SIE (msr, sie);
+	  SET_MSR_OVF (msr);
+	  SET_MSR (1, msr);
+	}
+      else
+	{
+	  OR_MSR_SIE (msr0, sie);
+	  SET_MSR_OVF (msr0);
+	}
+
+      /* Regardless of the slot, set MSR0.AOVF.  */
+      SET_MSR_AOVF (msr0);
+    }
+
+  SET_MSR (0, msr0);
+}
+
+/* Determine the correct FQ register to use for the given exception.
+   Return -1 if a register is not available.  */
+static int
+fq_for_exception (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
+)
+{
+  SI fq;
+  struct frv_fp_exception_info *fp_info = & item->u.fp_info;
+
+  /* For fp_exception overflow, underflow or inexact, use FQ0 or FQ1.  */
+  if (fp_info->ftt == FTT_IEEE_754_EXCEPTION
+      && (fp_info->fsr_mask & (FSR_OVERFLOW | FSR_UNDERFLOW | FSR_INEXACT)))
+    {
+      fq = GET_FQ (0);
+      if (! GET_FQ_VALID (fq))
+	return 0; /* FQ0 is available.  */
+      fq = GET_FQ (1);
+      if (! GET_FQ_VALID (fq))
+	return 1; /* FQ1 is available.  */
+
+      /* No FQ register is available */
+      {
+	SIM_DESC sd = CPU_STATE (current_cpu);
+	IADDR pc = CPU_PC_GET (current_cpu);
+	sim_engine_abort (sd, current_cpu, pc, "No FQ register available\n");
+      }
+      return -1;
+    }
+  /* For other exceptions, use FQ2 if the insn was in slot F0/I0 and FQ3
+     otherwise.  */
+  if (item->slot == UNIT_FM0 || item->slot == UNIT_I0)
+    return 2;
+
+  return 3;
+}
+
+/* Set FSR0, FQ0-FQ9, depending on the interrupt.  */
+static void
+set_fp_exception_registers (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
+)
+{
+  int fq_index;
+  SI fq;
+  SI insn;
+  SI fsr0;
+  IADDR pc;
+  struct frv_fp_exception_info *fp_info;
+
+  /* Select an FQ and update it with the exception information.  */
+  fq_index = fq_for_exception (current_cpu, item);
+  if (fq_index == -1)
+    return;
+
+  fp_info = & item->u.fp_info;
+  fq = GET_FQ (fq_index);
+  SET_FQ_MIV (fq, MIV_FLOAT);
+  SET_FQ_SIE (fq, SIE_NIL);
+  SET_FQ_FTT (fq, fp_info->ftt);
+  SET_FQ_CEXC (fq, fp_info->fsr_mask);
+  SET_FQ_VALID (fq);
+  SET_FQ (fq_index, fq);
+
+  /* Write the failing insn into FQx.OPC.  */
+  pc = item->vpc;
+  insn = GETMEMSI (current_cpu, pc, pc);
+  SET_FQ_OPC (fq_index, insn);
+
+  /* Update the fsr.  */
+  fsr0 = GET_FSR (0);
+  SET_FSR_QNE (fsr0); /* FQ not empty */
+  SET_FSR_FTT (fsr0, fp_info->ftt);
+  SET_FSR (0, fsr0);
+}
+
+/* Record the state of a division exception in the ISR.  */
+static void
+set_isr_exception_fields (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
+)
+{
+  USI isr = GET_ISR ();
+  int dtt = GET_ISR_DTT (isr);
+  dtt |= item->u.dtt;
+  SET_ISR_DTT (isr, dtt);
+  SET_ISR (isr);
+}
+
+/* Set ESFR0, EPCRx, ESRx, EARx and EDRx, according to the given program
+   interrupt.  */
+static void
+set_exception_status_registers (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
+)
+{
+  struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind];
+  int slot = (item->vpc - previous_vliw_pc) / 4;
+  int reg_index = -1;
+  int set_ear = 0;
+  int set_edr = 0;
+  int set_daec = 0;
+  int set_epcr = 0;
+  SI esr = 0;
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+  /* If the interrupt is strict (precise) or the interrupt is on the insns
+     in the I0 pipe, then set the 0 registers.  */
+  if (interrupt->precise)
+    {
+      reg_index = 0;
+      if (interrupt->kind == FRV_REGISTER_EXCEPTION)
+	SET_ESR_REC (esr, item->u.rec);
+      else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION)
+	SET_ESR_IAEC (esr, item->u.iaec);
+      set_epcr = 1;
+    }
+  else
+    {
+      switch (interrupt->kind)
+	{
+	case FRV_DIVISION_EXCEPTION:
+	  set_isr_exception_fields (current_cpu, item);
+	  /* fall thru to set reg_index.  */
+	case FRV_COMMIT_EXCEPTION:
+	  if (item->slot == UNIT_I0)
+	    reg_index = 0;
+	  else if (item->slot == UNIT_I1)
+	    reg_index = 1;
+	  set_epcr = 1;
+	  break;
+	case FRV_DATA_STORE_ERROR:
+	  reg_index = 14; /* Use ESR15, EPCR15.  */
+	  break;
+	case FRV_DATA_ACCESS_ERROR:
+	  reg_index = 15; /* Use ESR15, EPCR15.  */
+	  if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
+	    set_ear = 1;
+	  break;
+	case FRV_DATA_ACCESS_EXCEPTION:
+	  set_daec = 1;
+	  /* fall through */
+	case FRV_DATA_ACCESS_MMU_MISS:
+	case FRV_MEM_ADDRESS_NOT_ALIGNED:
+	  /* Get the appropriate ESR, EPCR, EAR and EDR.
+	     EAR will be set. EDR will not be set if this is a store insn.  */
+	  set_ear = 1;
+	  if (item->u.data_written.length != 0)
+	    set_edr = 1;
+	  reg_index = esr_for_data_access_exception (current_cpu, item);
+	  set_epcr = 1;
+	  break;
+	case FRV_MP_EXCEPTION:
+	  break; /* MSR0-1, FQ0-9 are already set.  */
+	case FRV_FP_EXCEPTION:
+	  set_fp_exception_registers (current_cpu, item);
+	  break;
+	default:
+	  {
+	    SIM_DESC sd = CPU_STATE (current_cpu);
+	    IADDR pc = CPU_PC_GET (current_cpu);
+	    sim_engine_abort (sd, current_cpu, pc,
+			      "invalid non-strict program interrupt kind: %d\n",
+			      interrupt->kind);
+	    break;
+	  }
+	}
+    } /* non-strict (imprecise) interrupt */
+
+  /* Now fill in the selected exception status registers.  */
+  if (reg_index != -1)
+    {
+      /* Now set the exception status registers.  */
+      SET_ESFR_FLAG (reg_index);
+      SET_ESR_EC (esr, interrupt->ec);
+
+      if (set_epcr)
+	{
+	  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+	    SET_EPCR (reg_index, previous_vliw_pc);
+	  else
+	    SET_EPCR (reg_index, item->vpc);
+	}
+
+      if (set_ear)
+	{
+	  SET_EAR (reg_index, item->eaddress);
+	  SET_ESR_EAV (esr);
+	}
+      else
+	CLEAR_ESR_EAV (esr);
+
+      if (set_edr)
+	{
+	  int edn = set_edr_register (current_cpu, item, 0/* EDR0-3 */);
+	  SET_ESR_EDN (esr, edn);
+	  SET_ESR_EDV (esr);
+	}
+      else
+	CLEAR_ESR_EDV (esr);
+
+      if (set_daec)
+	SET_ESR_DAEC (esr, item->u.daec);
+
+      SET_ESR_VALID (esr);
+      SET_ESR (reg_index, esr);
+    }
+}
+
+/* Check for compound interrupts.
+   Returns NULL if no interrupt is to be processed.  */
+static struct frv_interrupt *
+check_for_compound_interrupt (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
+)
+{
+  struct frv_interrupt *interrupt;
+
+  /* Set the exception status registers for the original interrupt.  */
+  set_exception_status_registers (current_cpu, item);
+  interrupt = & frv_interrupt_table[item->kind];
+
+  if (! interrupt->precise)
+    {
+      IADDR vpc = 0;
+      int mask = 0;
+
+      vpc = item->vpc;
+      mask = (1 << item->kind);
+
+      /* Look for more queued program interrupts which are non-deferred
+	 (pending inhibit), imprecise (non-strict) different than an interrupt
+	 already found and caused by a different insn.  A bit mask is used
+	 to keep track of interrupts which have already been detected.  */
+      while (item != frv_interrupt_state.queue)
+	{
+	  enum frv_interrupt_kind kind;
+	  struct frv_interrupt *next_interrupt;
+	  --item;
+	  kind = item->kind;
+	  next_interrupt = & frv_interrupt_table[kind];
+
+	  if (next_interrupt->iclass != FRV_PROGRAM_INTERRUPT)
+	    break; /* no program interrupts left.  */
+
+	  if (item->vpc == vpc)
+	    continue; /* caused by the same insn.  */
+
+	  vpc = item->vpc;
+	  if (! next_interrupt->precise && ! next_interrupt->deferred)
+	    {
+	      if (! (mask & (1 << kind)))
+		{
+		  /* Set the exception status registers for the additional
+		     interrupt.  */
+		  set_exception_status_registers (current_cpu, item);
+		  mask |= (1 << kind);
+		  interrupt = & frv_interrupt_table[FRV_COMPOUND_EXCEPTION];
+		}
+	    }
+	}
+    }
+
+  /* Return with either the original interrupt, a compound_exception,
+     or no exception.  */
+  return interrupt;
+}
+
+/* Handle a program interrupt.  */
+void
+frv_program_interrupt (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, IADDR pc
+)
+{
+  struct frv_interrupt *interrupt;
+
+  clear_exception_status_registers (current_cpu);
+  /* If two or more non-deferred imprecise (non-strict) interrupts occur
+     on two or more insns, then generate a compound_exception.  */
+  interrupt = check_for_compound_interrupt (current_cpu, item);
+  if (interrupt != NULL)
+    {
+      frv_program_or_software_interrupt (current_cpu, interrupt, pc);
+      frv_clear_interrupt_classes (FRV_SOFTWARE_INTERRUPT,
+				   FRV_PROGRAM_INTERRUPT);
+    }
+}
+
+/* Handle a software interrupt.  */
+void
+frv_software_interrupt (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, IADDR pc
+)
+{
+  struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind];
+  frv_program_or_software_interrupt (current_cpu, interrupt, pc);
+}
+
+/* Handle a program interrupt or a software interrupt in non-operating mode.  */
+void
+frv_non_operating_interrupt (
+  SIM_CPU *current_cpu, enum frv_interrupt_kind kind, IADDR pc
+)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  switch (kind)
+    {
+    case FRV_INTERRUPT_LEVEL_1:
+    case FRV_INTERRUPT_LEVEL_2:
+    case FRV_INTERRUPT_LEVEL_3:
+    case FRV_INTERRUPT_LEVEL_4:
+    case FRV_INTERRUPT_LEVEL_5:
+    case FRV_INTERRUPT_LEVEL_6:
+    case FRV_INTERRUPT_LEVEL_7:
+    case FRV_INTERRUPT_LEVEL_8:
+    case FRV_INTERRUPT_LEVEL_9:
+    case FRV_INTERRUPT_LEVEL_10:
+    case FRV_INTERRUPT_LEVEL_11:
+    case FRV_INTERRUPT_LEVEL_12:
+    case FRV_INTERRUPT_LEVEL_13:
+    case FRV_INTERRUPT_LEVEL_14:
+    case FRV_INTERRUPT_LEVEL_15:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: external %d\n", kind + 1);
+      break;
+    case FRV_TRAP_INSTRUCTION:
+      break; /* handle as in operating mode.  */
+    case FRV_COMMIT_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: commit_exception\n");
+      break;
+    case FRV_DIVISION_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: division_exception\n");
+      break;
+    case FRV_DATA_STORE_ERROR:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: data_store_error\n");
+      break;
+    case FRV_DATA_ACCESS_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: data_access_exception\n");
+      break;
+    case FRV_DATA_ACCESS_MMU_MISS:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: data_access_mmu_miss\n");
+      break;
+    case FRV_DATA_ACCESS_ERROR:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: data_access_error\n");
+      break;
+    case FRV_MP_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: mp_exception\n");
+      break;
+    case FRV_FP_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: fp_exception\n");
+      break;
+    case FRV_MEM_ADDRESS_NOT_ALIGNED:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: mem_address_not_aligned\n");
+      break;
+    case FRV_REGISTER_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: register_exception\n");
+      break;
+    case FRV_MP_DISABLED:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: mp_disabled\n");
+      break;
+    case FRV_FP_DISABLED:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: fp_disabled\n");
+      break;
+    case FRV_PRIVILEGED_INSTRUCTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: privileged_instruction\n");
+      break;
+    case FRV_ILLEGAL_INSTRUCTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: illegal_instruction\n");
+      break;
+    case FRV_INSTRUCTION_ACCESS_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: instruction_access_exception\n");
+      break;
+    case FRV_INSTRUCTION_ACCESS_MMU_MISS:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: instruction_access_mmu_miss\n");
+      break;
+    case FRV_INSTRUCTION_ACCESS_ERROR:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: insn_access_error\n");
+      break;
+    case FRV_COMPOUND_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: compound_exception\n");
+      break;
+    case FRV_BREAK_EXCEPTION:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: break_exception\n");
+      break;
+    case FRV_RESET:
+      sim_engine_abort (sd, current_cpu, pc,
+			"interrupt: reset\n");
+      break;
+    default:
+      sim_engine_abort (sd, current_cpu, pc,
+			"unhandled interrupt kind: %d\n", kind);
+      break;
+    }
+}
+
+/* Handle a break interrupt.  */
+void
+frv_break_interrupt (
+  SIM_CPU *current_cpu, struct frv_interrupt *interrupt, IADDR current_pc
+)
+{
+  IADDR new_pc;
+
+  /* BPCSR=PC
+     BPSR.BS=PSR.S
+     BPSR.BET=PSR.ET
+     PSR.S=1
+     PSR.ET=0
+     TBR.TT=0xff
+     PC=TBR
+  */
+  /* Must set PSR.S first to allow access to supervisor-only spr registers.  */
+  SET_H_BPSR_BS (GET_H_PSR_S ());
+  SET_H_BPSR_BET (GET_H_PSR_ET ());
+  SET_H_PSR_S (1);
+  SET_H_PSR_ET (0);
+  /* Must set PSR.S first to allow access to supervisor-only spr registers.  */
+  SET_H_SPR (H_SPR_BPCSR, current_pc);
+
+  /* Set the new PC in the TBR.  */
+  SET_H_TBR_TT (interrupt->handler_offset);
+  new_pc = GET_H_SPR (H_SPR_TBR);
+  SET_H_PC (new_pc);
+
+  CPU_DEBUG_STATE (current_cpu) = 1;
+}
+
+/* Handle a program interrupt or a software interrupt.  */
+void
+frv_program_or_software_interrupt (
+  SIM_CPU *current_cpu, struct frv_interrupt *interrupt, IADDR current_pc
+)
+{
+  USI new_pc;
+  int original_psr_et;
+
+  /* PCSR=PC
+     PSR.PS=PSR.S
+     PSR.ET=0
+     PSR.S=1
+     if PSR.ESR==1
+       SR0 through SR3=GR4 through GR7
+       TBR.TT=interrupt handler offset
+       PC=TBR
+  */
+  original_psr_et = GET_H_PSR_ET ();
+
+  SET_H_PSR_PS (GET_H_PSR_S ());
+  SET_H_PSR_ET (0);
+  SET_H_PSR_S (1);
+
+  /* Must set PSR.S first to allow access to supervisor-only spr registers.  */
+  /* The PCSR depends on the precision of the interrupt.  */
+  if (interrupt->precise)
+    SET_H_SPR (H_SPR_PCSR, previous_vliw_pc);
+  else
+    SET_H_SPR (H_SPR_PCSR, current_pc);
+
+  /* Set the new PC in the TBR.  */
+  SET_H_TBR_TT (interrupt->handler_offset);
+  new_pc = GET_H_SPR (H_SPR_TBR);
+  SET_H_PC (new_pc);
+
+  /* If PSR.ET was not originally set, then enter the stopped state.  */
+  if (! original_psr_et)
+    {
+      SIM_DESC sd = CPU_STATE (current_cpu);
+      frv_non_operating_interrupt (current_cpu, interrupt->kind, current_pc);
+      sim_engine_halt (sd, current_cpu, NULL, new_pc, sim_stopped, SIM_SIGINT);
+    }
+}
+
+/* Handle a program interrupt or a software interrupt.  */
+void
+frv_external_interrupt (
+  SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, IADDR pc
+)
+{
+  USI new_pc;
+  struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind];
+
+  /* Don't process the interrupt if PSR.ET is not set or if it is masked.
+     Interrupt 15 is processed even if it appears to be masked.  */
+  if (! GET_H_PSR_ET ()
+      || (interrupt->kind != FRV_INTERRUPT_LEVEL_15
+	  && interrupt->kind < GET_H_PSR_PIL ()))
+    return; /* Leave it for later.  */
+
+  /* Remove the interrupt from the queue.  */
+  --frv_interrupt_state.queue_index;
+
+  /* PCSR=PC
+     PSR.PS=PSR.S
+     PSR.ET=0
+     PSR.S=1
+     if PSR.ESR==1
+       SR0 through SR3=GR4 through GR7
+       TBR.TT=interrupt handler offset
+       PC=TBR
+  */
+  SET_H_PSR_PS (GET_H_PSR_S ());
+  SET_H_PSR_ET (0);
+  SET_H_PSR_S (1);
+  /* Must set PSR.S first to allow access to supervisor-only spr registers.  */
+  SET_H_SPR (H_SPR_PCSR, GET_H_PC ());
+
+  /* Set the new PC in the TBR.  */
+  SET_H_TBR_TT (interrupt->handler_offset);
+  new_pc = GET_H_SPR (H_SPR_TBR);
+  SET_H_PC (new_pc);
+}
+
+/* Clear interrupts which fall within the range of classes given.  */
+void
+frv_clear_interrupt_classes (
+  enum frv_interrupt_class low_class, enum frv_interrupt_class high_class
+)
+{
+  int i;
+  int j;
+  int limit = frv_interrupt_state.queue_index;
+
+  /* Find the lowest priority interrupt to be removed.  */
+  for (i = 0; i < limit; ++i)
+    {
+      enum frv_interrupt_kind kind = frv_interrupt_state.queue[i].kind;
+      struct frv_interrupt* interrupt = & frv_interrupt_table[kind];
+      if (interrupt->iclass >= low_class)
+	break;
+    }
+
+  /* Find the highest priority interrupt to be removed.  */
+  for (j = limit - 1; j >= i; --j)
+    {
+      enum frv_interrupt_kind kind = frv_interrupt_state.queue[j].kind;
+      struct frv_interrupt* interrupt = & frv_interrupt_table[kind];
+      if (interrupt->iclass <= high_class)
+	break;
+    }
+
+  /* Shuffle the remaining high priority interrupts down into the empty space
+     left by the deleted interrupts.  */
+  if (j >= i)
+    {
+      for (++j; j < limit; ++j)
+	frv_interrupt_state.queue[i++] = frv_interrupt_state.queue[j];
+      frv_interrupt_state.queue_index -= (j - i);
+    }
+}
+
+/* Save data written to memory into the interrupt state so that it can be
+   copied to the appropriate EDR register, if necessary, in the event of an
+   interrupt.  */
+void
+frv_save_data_written_for_interrupts (
+  SIM_CPU *current_cpu, CGEN_WRITE_QUEUE_ELEMENT *item
+)
+{
+  /* Record the slot containing the insn doing the write in the
+     interrupt state.  */
+  frv_interrupt_state.slot = CGEN_WRITE_QUEUE_ELEMENT_PIPE (item);
+
+  /* Now record any data written to memory in the interrupt state.  */
+  switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
+    {
+    case CGEN_BI_WRITE:
+    case CGEN_QI_WRITE:
+    case CGEN_SI_WRITE:
+    case CGEN_SF_WRITE:
+    case CGEN_PC_WRITE:
+    case CGEN_FN_HI_WRITE:
+    case CGEN_FN_SI_WRITE:
+    case CGEN_FN_SF_WRITE:
+    case CGEN_FN_DI_WRITE:
+    case CGEN_FN_DF_WRITE:
+    case CGEN_FN_XI_WRITE:
+    case CGEN_FN_PC_WRITE:
+      break; /* Ignore writes to registers.  */
+    case CGEN_MEM_QI_WRITE:
+      frv_interrupt_state.data_written.length = 1;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.mem_qi_write.value;
+      break;
+    case CGEN_MEM_HI_WRITE:
+      frv_interrupt_state.data_written.length = 1;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.mem_hi_write.value;
+      break;
+    case CGEN_MEM_SI_WRITE:
+      frv_interrupt_state.data_written.length = 1;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.mem_si_write.value;
+      break;
+    case CGEN_MEM_DI_WRITE:
+      frv_interrupt_state.data_written.length = 2;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.mem_di_write.value >> 32;
+      frv_interrupt_state.data_written.words[1]
+	= item->kinds.mem_di_write.value;
+      break;
+    case CGEN_MEM_DF_WRITE:
+      frv_interrupt_state.data_written.length = 2;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.mem_df_write.value >> 32;
+      frv_interrupt_state.data_written.words[1]
+	= item->kinds.mem_df_write.value;
+      break;
+    case CGEN_MEM_XI_WRITE:
+      frv_interrupt_state.data_written.length = 4;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.mem_xi_write.value[0];
+      frv_interrupt_state.data_written.words[1]
+	= item->kinds.mem_xi_write.value[1];
+      frv_interrupt_state.data_written.words[2]
+	= item->kinds.mem_xi_write.value[2];
+      frv_interrupt_state.data_written.words[3]
+	= item->kinds.mem_xi_write.value[3];
+      break;
+    case CGEN_FN_MEM_QI_WRITE:
+      frv_interrupt_state.data_written.length = 1;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.fn_mem_qi_write.value;
+      break;
+    case CGEN_FN_MEM_HI_WRITE:
+      frv_interrupt_state.data_written.length = 1;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.fn_mem_hi_write.value;
+      break;
+    case CGEN_FN_MEM_SI_WRITE:
+      frv_interrupt_state.data_written.length = 1;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.fn_mem_si_write.value;
+      break;
+    case CGEN_FN_MEM_DI_WRITE:
+      frv_interrupt_state.data_written.length = 2;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.fn_mem_di_write.value >> 32;
+      frv_interrupt_state.data_written.words[1]
+	= item->kinds.fn_mem_di_write.value;
+      break;
+    case CGEN_FN_MEM_DF_WRITE:
+      frv_interrupt_state.data_written.length = 2;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.fn_mem_df_write.value >> 32;
+      frv_interrupt_state.data_written.words[1]
+	= item->kinds.fn_mem_df_write.value;
+      break;
+    case CGEN_FN_MEM_XI_WRITE:
+      frv_interrupt_state.data_written.length = 4;
+      frv_interrupt_state.data_written.words[0]
+	= item->kinds.fn_mem_xi_write.value[0];
+      frv_interrupt_state.data_written.words[1]
+	= item->kinds.fn_mem_xi_write.value[1];
+      frv_interrupt_state.data_written.words[2]
+	= item->kinds.fn_mem_xi_write.value[2];
+      frv_interrupt_state.data_written.words[3]
+	= item->kinds.fn_mem_xi_write.value[3];
+      break;
+    default:
+      {
+	SIM_DESC sd = CPU_STATE (current_cpu);
+	IADDR pc = CPU_PC_GET (current_cpu);
+	sim_engine_abort (sd, current_cpu, pc,
+			  "unknown write kind during save for interrupt\n");
+      }
+      break;
+    }
+}
diff --git a/sim/frv/memory.c b/sim/frv/memory.c
new file mode 100644
index 00000000000..603f7bbff8a
--- /dev/null
+++ b/sim/frv/memory.c
@@ -0,0 +1,750 @@
+/* frv memory model.
+   Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "bfd.h"
+
+/* Check for alignment and access restrictions.  Return the corrected address.
+ */
+static SI
+fr400_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  /* Check access restrictions for double word loads only.  */
+  if (align_mask == 7)
+    {
+      if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff)
+	frv_queue_data_access_error_interrupt (current_cpu, address);
+    }
+  return address;
+}
+
+static SI
+fr500_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  if (address & align_mask)
+    {
+      frv_queue_mem_address_not_aligned_interrupt (current_cpu, address);
+      address &= ~align_mask;
+    }
+
+  if ((USI)address >= 0xfeff0600 && (USI)address <= 0xfeff7fff
+      || (USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff)
+    frv_queue_data_access_error_interrupt (current_cpu, address);
+
+  return address;
+}
+
+static SI
+check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      address = fr400_check_data_read_address (current_cpu, address,
+					       align_mask);
+      break;
+    case bfd_mach_frvtomcat:
+    case bfd_mach_fr500:
+    case bfd_mach_frv:
+      address = fr500_check_data_read_address (current_cpu, address,
+					       align_mask);
+      break;
+    default:
+      break;
+    }
+
+  return address;
+}
+
+static SI
+fr400_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  if (address & align_mask)
+    {
+      /* Make sure that this exception is not masked.  */
+      USI isr = GET_ISR ();
+      if (! GET_ISR_EMAM (isr))
+	{
+	  /* Bad alignment causes a data_access_error on fr400.  */
+	  frv_queue_data_access_error_interrupt (current_cpu, address);
+	}
+      address &= ~align_mask;
+    }
+  /* Nothing to check.  */
+  return address;
+}
+
+static SI
+fr500_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  if ((USI)address >= 0xfe000000 && (USI)address <= 0xfe003fff
+      || (USI)address >= 0xfe004000 && (USI)address <= 0xfe3fffff
+      || (USI)address >= 0xfe400000 && (USI)address <= 0xfe403fff
+      || (USI)address >= 0xfe404000 && (USI)address <= 0xfe7fffff)
+    frv_queue_data_access_exception_interrupt (current_cpu);
+
+  return address;
+}
+
+static SI
+check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      address = fr400_check_readwrite_address (current_cpu, address,
+						    align_mask);
+      break;
+    case bfd_mach_frvtomcat:
+    case bfd_mach_fr500:
+    case bfd_mach_frv:
+      address = fr500_check_readwrite_address (current_cpu, address,
+						    align_mask);
+      break;
+    default:
+      break;
+    }
+
+  return address;
+}
+
+static PCADDR
+fr400_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
+			       int align_mask)
+{
+  if (address & align_mask)
+    {
+      frv_queue_instruction_access_error_interrupt (current_cpu);
+      address &= ~align_mask;
+    }
+  else if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff)
+    frv_queue_instruction_access_error_interrupt (current_cpu);
+
+  return address;
+}
+
+static PCADDR
+fr500_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
+			       int align_mask)
+{
+  if (address & align_mask)
+    {
+      frv_queue_mem_address_not_aligned_interrupt (current_cpu, address);
+      address &= ~align_mask;
+    }
+
+  if ((USI)address >= 0xfeff0600 && (USI)address <= 0xfeff7fff
+      || (USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff)
+    frv_queue_instruction_access_error_interrupt (current_cpu);
+  else if ((USI)address >= 0xfe004000 && (USI)address <= 0xfe3fffff
+	   || (USI)address >= 0xfe400000 && (USI)address <= 0xfe403fff
+	   || (USI)address >= 0xfe404000 && (USI)address <= 0xfe7fffff)
+    frv_queue_instruction_access_exception_interrupt (current_cpu);
+  else
+    {
+      USI hsr0 = GET_HSR0 ();
+      if (! GET_HSR0_RME (hsr0)
+	  && (USI)address >= 0xfe000000 && (USI)address <= 0xfe003fff)
+	frv_queue_instruction_access_exception_interrupt (current_cpu);
+    }
+
+  return address;
+}
+
+static PCADDR
+check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      address = fr400_check_insn_read_address (current_cpu, address,
+					       align_mask);
+      break;
+    case bfd_mach_frvtomcat:
+    case bfd_mach_fr500:
+    case bfd_mach_frv:
+      address = fr500_check_insn_read_address (current_cpu, address,
+					       align_mask);
+      break;
+    default:
+      break;
+    }
+
+  return address;
+}
+
+/* Memory reads.  */
+QI
+frvbf_read_mem_QI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  USI hsr0 = GET_HSR0 ();
+  FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+
+  /* Check for access exceptions.  */
+  address = check_data_read_address (current_cpu, address, 0);
+  address = check_readwrite_address (current_cpu, address, 0);
+  
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 1;
+      CPU_LOAD_SIGNED (current_cpu) = 1;
+      return 0xb7; /* any random value */
+    }
+
+  if (GET_HSR0_DCE (hsr0))
+    {
+      int cycles;
+      cycles = frv_cache_read (cache, 0, address);
+      if (cycles != 0)
+	return CACHE_RETURN_DATA (cache, 0, address, QI, 1);
+    }
+
+  return GETMEMQI (current_cpu, pc, address);
+}
+
+UQI
+frvbf_read_mem_UQI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  USI hsr0 = GET_HSR0 ();
+  FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+
+  /* Check for access exceptions.  */
+  address = check_data_read_address (current_cpu, address, 0);
+  address = check_readwrite_address (current_cpu, address, 0);
+  
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 1;
+      CPU_LOAD_SIGNED (current_cpu) = 0;
+      return 0xb7; /* any random value */
+    }
+
+  if (GET_HSR0_DCE (hsr0))
+    {
+      int cycles;
+      cycles = frv_cache_read (cache, 0, address);
+      if (cycles != 0)
+	return CACHE_RETURN_DATA (cache, 0, address, UQI, 1);
+    }
+
+  return GETMEMUQI (current_cpu, pc, address);
+}
+
+HI
+frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  USI hsr0;
+  FRV_CACHE *cache;
+
+  /* Check for access exceptions.  */
+  address = check_data_read_address (current_cpu, address, 1);
+  address = check_readwrite_address (current_cpu, address, 1);
+  
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  hsr0 = GET_HSR0 ();
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 2;
+      CPU_LOAD_SIGNED (current_cpu) = 1;
+      return 0xb711; /* any random value */
+    }
+
+  if (GET_HSR0_DCE (hsr0))
+    {
+      int cycles;
+      cycles = frv_cache_read (cache, 0, address);
+      if (cycles != 0)
+	return CACHE_RETURN_DATA (cache, 0, address, HI, 2);
+    }
+
+  return GETMEMHI (current_cpu, pc, address);
+}
+
+UHI
+frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  USI hsr0;
+  FRV_CACHE *cache;
+
+  /* Check for access exceptions.  */
+  address = check_data_read_address (current_cpu, address, 1);
+  address = check_readwrite_address (current_cpu, address, 1);
+  
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  hsr0 = GET_HSR0 ();
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 2;
+      CPU_LOAD_SIGNED (current_cpu) = 0;
+      return 0xb711; /* any random value */
+    }
+
+  if (GET_HSR0_DCE (hsr0))
+    {
+      int cycles;
+      cycles = frv_cache_read (cache, 0, address);
+      if (cycles != 0)
+	return CACHE_RETURN_DATA (cache, 0, address, UHI, 2);
+    }
+
+  return GETMEMUHI (current_cpu, pc, address);
+}
+
+SI
+frvbf_read_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  FRV_CACHE *cache;
+  USI hsr0;
+
+  /* Check for access exceptions.  */
+  address = check_data_read_address (current_cpu, address, 3);
+  address = check_readwrite_address (current_cpu, address, 3);
+  
+  hsr0 = GET_HSR0 ();
+  cache = CPU_DATA_CACHE (current_cpu);
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 4;
+      return 0x37111319; /* any random value */
+    }
+
+  if (GET_HSR0_DCE (hsr0))
+    {
+      int cycles;
+      cycles = frv_cache_read (cache, 0, address);
+      if (cycles != 0)
+	return CACHE_RETURN_DATA (cache, 0, address, SI, 4);
+    }
+
+  return GETMEMSI (current_cpu, pc, address);
+}
+
+SI
+frvbf_read_mem_WI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  return frvbf_read_mem_SI (current_cpu, pc, address);
+}
+
+DI
+frvbf_read_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  USI hsr0;
+  FRV_CACHE *cache;
+
+  /* Check for access exceptions.  */
+  address = check_data_read_address (current_cpu, address, 7);
+  address = check_readwrite_address (current_cpu, address, 7);
+  
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  hsr0 = GET_HSR0 ();
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 8;
+      return 0x37111319; /* any random value */
+    }
+
+  if (GET_HSR0_DCE (hsr0))
+    {
+      int cycles;
+      cycles = frv_cache_read (cache, 0, address);
+      if (cycles != 0)
+	return CACHE_RETURN_DATA (cache, 0, address, DI, 8);
+    }
+
+  return GETMEMDI (current_cpu, pc, address);
+}
+
+DF
+frvbf_read_mem_DF (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+  USI hsr0;
+  FRV_CACHE *cache;
+
+  /* Check for access exceptions.  */
+  address = check_data_read_address (current_cpu, address, 7);
+  address = check_readwrite_address (current_cpu, address, 7);
+  
+  /* If we need to count cycles, then the cache operation will be
+     initiated from the model profiling functions.
+     See frvbf_model_....  */
+  hsr0 = GET_HSR0 ();
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      CPU_LOAD_ADDRESS (current_cpu) = address;
+      CPU_LOAD_LENGTH (current_cpu) = 8;
+      return 0x37111319; /* any random value */
+    }
+
+  if (GET_HSR0_DCE (hsr0))
+    {
+      int cycles;
+      cycles = frv_cache_read (cache, 0, address);
+      if (cycles != 0)
+	return CACHE_RETURN_DATA (cache, 0, address, DF, 8);
+    }
+
+  return GETMEMDF (current_cpu, pc, address);
+}
+
+USI
+frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc)
+{
+  USI hsr0;
+  vpc = check_insn_read_address (current_cpu, vpc, 3);
+
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_ICE (hsr0))
+    {
+      FRV_CACHE *cache;
+      USI value;
+
+      /* We don't want this to show up in the cache statistics.  That read
+	 is done in frvbf_simulate_insn_prefetch.  So read the cache or memory
+	 passively here.  */
+      cache = CPU_INSN_CACHE (current_cpu);
+      if (frv_cache_read_passive_SI (cache, vpc, &value))
+	return value;
+    }
+  return sim_core_read_unaligned_4 (current_cpu, vpc, read_map, vpc);
+}
+
+static SI
+fr400_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  if (address & align_mask)
+    {
+      /* On the fr400, this causes a data_access_error.  */
+      /* Make sure that this exception is not masked.  */
+      USI isr = GET_ISR ();
+      if (! GET_ISR_EMAM (isr))
+	{
+	  /* Bad alignment causes a data_access_error on fr400.  */
+	  frv_queue_data_access_error_interrupt (current_cpu, address);
+	}
+      address &= ~align_mask;
+    }
+  if (align_mask == 7
+      && address >= 0xfe800000 && address <= 0xfeffffff)
+    frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR);
+
+  return address;
+}
+
+static SI
+fr500_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  if (address & align_mask)
+    {
+      struct frv_interrupt_queue_element *item =
+	frv_queue_mem_address_not_aligned_interrupt (current_cpu, address);
+      /* Record the correct vliw slot with the interrupt.  */
+      if (item != NULL)
+	item->slot = frv_interrupt_state.slot;
+      address &= ~align_mask;
+    }
+  if (address >= 0xfeff0600 && address <= 0xfeff7fff
+      || address >= 0xfe800000 && address <= 0xfefeffff)
+    frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR);
+
+  return address;
+}
+
+static SI
+check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      address = fr400_check_write_address (current_cpu, address, align_mask);
+      break;
+    case bfd_mach_frvtomcat:
+    case bfd_mach_fr500:
+    case bfd_mach_frv:
+      address = fr500_check_write_address (current_cpu, address, align_mask);
+      break;
+    default:
+      break;
+    }
+  return address;
+}
+
+void
+frvbf_write_mem_QI (SIM_CPU *current_cpu, IADDR pc, SI address, QI value)
+{
+  USI hsr0;
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_qi_write (current_cpu, frvbf_mem_set_QI, address, value);
+  else
+    sim_queue_mem_qi_write (current_cpu, address, value);
+  frv_set_write_queue_slot (current_cpu);
+}
+
+void
+frvbf_write_mem_UQI (SIM_CPU *current_cpu, IADDR pc, SI address, UQI value)
+{
+  frvbf_write_mem_QI (current_cpu, pc, address, value);
+}
+
+void
+frvbf_write_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
+{
+  USI hsr0;
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_hi_write (current_cpu, frvbf_mem_set_HI, address, value);
+  else
+    sim_queue_mem_hi_write (current_cpu, address, value);
+  frv_set_write_queue_slot (current_cpu);
+}
+
+void
+frvbf_write_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address, UHI value)
+{
+  frvbf_write_mem_HI (current_cpu, pc, address, value);
+}
+
+void
+frvbf_write_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
+{
+  USI hsr0;
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_si_write (current_cpu, frvbf_mem_set_SI, address, value);
+  else
+    sim_queue_mem_si_write (current_cpu, address, value);
+  frv_set_write_queue_slot (current_cpu);
+}
+
+void
+frvbf_write_mem_WI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
+{
+  frvbf_write_mem_SI (current_cpu, pc, address, value);
+}
+
+void
+frvbf_write_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
+{
+  USI hsr0;
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_di_write (current_cpu, frvbf_mem_set_DI, address, value);
+  else
+    sim_queue_mem_di_write (current_cpu, address, value);
+  frv_set_write_queue_slot (current_cpu);
+}
+
+void
+frvbf_write_mem_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value)
+{
+  USI hsr0;
+  hsr0 = GET_HSR0 ();
+  if (GET_HSR0_DCE (hsr0))
+    sim_queue_fn_mem_df_write (current_cpu, frvbf_mem_set_DF, address, value);
+  else
+    sim_queue_mem_df_write (current_cpu, address, value);
+  frv_set_write_queue_slot (current_cpu);
+}
+
+/* Memory writes.  These do the actual writing through the cache.  */
+void
+frvbf_mem_set_QI (SIM_CPU *current_cpu, IADDR pc, SI address, QI value)
+{
+  FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+
+  /* Check for access errors.  */
+  address = check_write_address (current_cpu, address, 0);
+  address = check_readwrite_address (current_cpu, address, 0);
+
+  /* If we need to count cycles, then submit the write request to the cache
+     and let it prioritize the request.  Otherwise perform the write now.  */
+  if (model_insn)
+    {
+      int slot = UNIT_I0;
+      frv_cache_request_store (cache, address, slot, (char *)&value,
+			       sizeof (value));
+    }
+  else
+    frv_cache_write (cache, address, (char *)&value, sizeof (value));
+}
+
+void
+frvbf_mem_set_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
+{
+  FRV_CACHE *cache;
+
+  /* Check for access errors.  */
+  address = check_write_address (current_cpu, address, 1);
+  address = check_readwrite_address (current_cpu, address, 1);
+
+  /* If we need to count cycles, then submit the write request to the cache
+     and let it prioritize the request.  Otherwise perform the write now.  */
+  value = H2T_2 (value);
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      int slot = UNIT_I0;
+      frv_cache_request_store (cache, address, slot,
+			       (char *)&value, sizeof (value));
+    }
+  else
+    frv_cache_write (cache, address, (char *)&value, sizeof (value));
+}
+
+void
+frvbf_mem_set_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
+{
+  FRV_CACHE *cache;
+
+  /* Check for access errors.  */
+  address = check_write_address (current_cpu, address, 3);
+  address = check_readwrite_address (current_cpu, address, 3);
+
+  /* If we need to count cycles, then submit the write request to the cache
+     and let it prioritize the request.  Otherwise perform the write now.  */
+  cache = CPU_DATA_CACHE (current_cpu);
+  value = H2T_4 (value);
+  if (model_insn)
+    {
+      int slot = UNIT_I0;
+      frv_cache_request_store (cache, address, slot,
+			       (char *)&value, sizeof (value));
+    }
+  else
+    frv_cache_write (cache, address, (char *)&value, sizeof (value));
+}
+
+void
+frvbf_mem_set_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
+{
+  FRV_CACHE *cache;
+
+  /* Check for access errors.  */
+  address = check_write_address (current_cpu, address, 7);
+  address = check_readwrite_address (current_cpu, address, 7);
+
+  /* If we need to count cycles, then submit the write request to the cache
+     and let it prioritize the request.  Otherwise perform the write now.  */
+  value = H2T_8 (value);
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      int slot = UNIT_I0;
+      frv_cache_request_store (cache, address, slot,
+			       (char *)&value, sizeof (value));
+    }
+  else
+    frv_cache_write (cache, address, (char *)&value, sizeof (value));
+}
+
+void
+frvbf_mem_set_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value)
+{
+  FRV_CACHE *cache;
+
+  /* Check for access errors.  */
+  address = check_write_address (current_cpu, address, 7);
+  address = check_readwrite_address (current_cpu, address, 7);
+
+  /* If we need to count cycles, then submit the write request to the cache
+     and let it prioritize the request.  Otherwise perform the write now.  */
+  value = H2T_8 (value);
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      int slot = UNIT_I0;
+      frv_cache_request_store (cache, address, slot,
+			       (char *)&value, sizeof (value));
+    }
+  else
+    frv_cache_write (cache, address, (char *)&value, sizeof (value));
+}
+
+void
+frvbf_mem_set_XI (SIM_CPU *current_cpu, IADDR pc, SI address, SI *value)
+{
+  int i;
+  FRV_CACHE *cache;
+
+  /* Check for access errors.  */
+  address = check_write_address (current_cpu, address, 0xf);
+  address = check_readwrite_address (current_cpu, address, 0xf);
+
+  /* TODO -- reverse word order as well?  */
+  for (i = 0; i < 4; ++i)
+    value[i] = H2T_4 (value[i]);
+
+  /* If we need to count cycles, then submit the write request to the cache
+     and let it prioritize the request.  Otherwise perform the write now.  */
+  cache = CPU_DATA_CACHE (current_cpu);
+  if (model_insn)
+    {
+      int slot = UNIT_I0;
+      frv_cache_request_store (cache, address, slot, (char*)value, 16);
+    }
+  else
+    frv_cache_write (cache, address, (char*)value, 16);
+}
+
+/* Record the current VLIW slot on the element at the top of the write queue.
+*/
+void
+frv_set_write_queue_slot (SIM_CPU *current_cpu)
+{
+  FRV_VLIW *vliw = CPU_VLIW (current_cpu);
+  int slot = vliw->next_slot - 1;
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
+  int ix = CGEN_WRITE_QUEUE_INDEX (q) - 1;
+  CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, ix);
+  CGEN_WRITE_QUEUE_ELEMENT_PIPE (item) = (*vliw->current_vliw)[slot];
+}
diff --git a/sim/frv/mloop.in b/sim/frv/mloop.in
new file mode 100644
index 00000000000..2d1726da573
--- /dev/null
+++ b/sim/frv/mloop.in
@@ -0,0 +1,514 @@
+# Simulator main loop for frv. -*- C -*-
+# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+# Contributed by Red Hat.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same.
+# It can't provide more than this.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
+         int fast_p)
+{
+  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
+  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+  if (! fast_p)
+    {
+      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+    }
+  return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+  SEM_PC vpc;
+
+  /* Force gr0 to zero before every insn.  */
+  @cpu@_h_gr_set (current_cpu, 0, 0);
+
+  if (fast_p)
+    {
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+    }
+  else
+    {
+      ARGBUF *abuf = &sc->argbuf;
+      const IDESC *idesc = abuf->idesc;
+#if WITH_SCACHE_PBB
+      int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
+#else
+      int virtual_p = 0;
+#endif
+
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-before */
+	  if (ARGBUF_PROFILE_P (abuf))
+	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
+	  if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf)))
+	    {
+	      @cpu@_model_insn_before (current_cpu, sc->first_insn_p);
+	      model_insn = FRV_INSN_MODEL_PASS_1;
+	      if (idesc->timing->model_fn != NULL)
+		(*idesc->timing->model_fn) (current_cpu, sc);
+	    }
+	  else
+	    model_insn = FRV_INSN_NO_MODELING;
+	  TRACE_INSN_INIT (current_cpu, abuf, 1);
+	  TRACE_INSN (current_cpu, idesc->idata,
+		      (const struct argbuf *) abuf, abuf->addr);
+	}
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-after */
+	  if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf)))
+	    {
+	      int cycles;
+	      if (idesc->timing->model_fn != NULL)
+		{
+		  model_insn = FRV_INSN_MODEL_PASS_2;
+		  cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+		}
+	      else
+		cycles = 1;
+	      @cpu@_model_insn_after (current_cpu, sc->last_insn_p, cycles);
+	    }
+	  TRACE_INSN_FINI (current_cpu, abuf, 1);
+	}
+    }
+
+  return vpc;
+}
+
+static void
+@cpu@_parallel_write_init (SIM_CPU *current_cpu)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
+  CGEN_WRITE_QUEUE_CLEAR (q);
+  previous_vliw_pc = CPU_PC_GET(current_cpu);
+  frv_interrupt_state.f_ne_flags[0] = 0;
+  frv_interrupt_state.f_ne_flags[1] = 0;
+  frv_interrupt_state.imprecise_interrupt = NULL;
+}
+
+static void
+@cpu@_parallel_write_queued (SIM_CPU *current_cpu)
+{
+  int i;
+
+  FRV_VLIW *vliw = CPU_VLIW (current_cpu);
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
+
+  /* Loop over the queued writes, executing them. Set the pc to the address
+     of the insn which queued each write for the proper context in case an
+     interrupt is caused. Restore the proper pc after the writes are
+     completed.  */
+  IADDR save_pc = CPU_PC_GET (current_cpu);
+  IADDR new_pc  = save_pc;
+  int branch_taken = 0;
+  int limit = CGEN_WRITE_QUEUE_INDEX (q);
+  frv_interrupt_state.data_written.length = 0;
+
+  for (i = 0; i < limit; ++i)
+    {
+      CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, i);
+
+      /* If an imprecise interrupt was generated, then, check whether the
+	 result should still be written.  */
+      if (frv_interrupt_state.imprecise_interrupt != NULL)
+	{
+	  /* Only check writes by the insn causing the exception.  */
+	  if (CGEN_WRITE_QUEUE_ELEMENT_IADDR (item)
+	      == frv_interrupt_state.imprecise_interrupt->vpc)
+	    {
+	      /* Execute writes of floating point operations resulting in
+		 overflow, underflow or inexact.  */
+	      if (frv_interrupt_state.imprecise_interrupt->kind
+		  == FRV_FP_EXCEPTION)
+		{
+		  if ((frv_interrupt_state.imprecise_interrupt
+		       ->u.fp_info.fsr_mask
+		       & ~(FSR_INEXACT | FSR_OVERFLOW | FSR_UNDERFLOW)))
+		    continue; /* Don't execute */
+		}
+	      /* Execute writes marked as 'forced'.  */
+	      else if (! (CGEN_WRITE_QUEUE_ELEMENT_FLAGS (item)
+			  & FRV_WRITE_QUEUE_FORCE_WRITE))
+		continue; /* Don't execute */
+	    }
+	}
+
+      /* Only execute the first branch on the queue.  */
+      if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE
+          || CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_FN_PC_WRITE)
+	{
+	  if (branch_taken)
+	    continue;
+	  branch_taken = 1;
+	  if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE)
+	    new_pc = item->kinds.pc_write.value;
+          else
+	    new_pc = item->kinds.fn_pc_write.value;
+	}
+
+      CPU_PC_SET (current_cpu, CGEN_WRITE_QUEUE_ELEMENT_IADDR (item));
+      frv_save_data_written_for_interrupts (current_cpu, item);
+      cgen_write_queue_element_execute (current_cpu, item);
+    }
+
+  /* Update the LR with the address of the next insn if the flag is set.
+     This flag gets set in frvbf_set_write_next_vliw_to_LR by the JMPL,
+     JMPIL and CALL insns.  */
+  if (frvbf_write_next_vliw_addr_to_LR)
+    {
+      frvbf_h_spr_set_handler (current_cpu, H_SPR_LR, save_pc);
+      frvbf_write_next_vliw_addr_to_LR = 0;
+    }
+
+  CPU_PC_SET (current_cpu, new_pc);
+  CGEN_WRITE_QUEUE_CLEAR (q);
+}
+
+void
+@cpu@_perform_writeback (SIM_CPU *current_cpu)
+{
+  @cpu@_parallel_write_queued (current_cpu);
+}
+
+static unsigned cache_reqno = 0x80000000; /* Start value is for debugging.  */
+
+#if 0 /* experimental */
+/* FR400 has single prefetch.  */
+static void
+fr400_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc)
+{
+  int cur_ix;
+  FRV_CACHE *cache;
+
+/* The cpu receives 8 bytes worth of insn data for each fetch aligned
+   on 8 byte boundary.  */
+#define FR400_FETCH_SIZE 8
+
+  cur_ix = LS;
+  vpc &= ~(FR400_FETCH_SIZE - 1);
+  cache = CPU_INSN_CACHE (current_cpu);
+
+  /* Request a load of the current address buffer, if necessary.  */
+  if (frv_insn_fetch_buffer[cur_ix].address != vpc)
+    {
+      frv_insn_fetch_buffer[cur_ix].address = vpc;
+      frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++;
+      if (FRV_COUNT_CYCLES (current_cpu, 1))
+	frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno,
+				frv_insn_fetch_buffer[cur_ix].address,
+				UNIT_I0 + cur_ix);
+    }
+
+  /* Wait for the current address buffer to be loaded, if necessary.  */
+  if (FRV_COUNT_CYCLES (current_cpu, 1))
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+      int wait;
+
+      /* Account for any branch penalty.  */
+      if (ps->branch_penalty > 0 && ! ps->past_first_p)
+	{
+	  frv_model_advance_cycles (current_cpu, ps->branch_penalty);
+	  frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty,
+				       "Branch penalty:");
+	  ps->branch_penalty = 0;
+	}
+
+      /* Account for insn fetch latency.  */
+      wait = 0;
+      while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
+	{
+	  frv_model_advance_cycles (current_cpu, 1);
+	  ++wait;
+	}
+      frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:");
+      return;
+    }
+
+  /* Otherwise just load the insns directly from the cache.
+   */
+  if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
+    {
+      frv_cache_read (cache, cur_ix, vpc);
+      frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
+    }
+}
+#endif /* experimental */
+
+/* FR500 has dual prefetch.  */
+static void
+simulate_dual_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc, int fetch_size)
+{
+  int i;
+  int cur_ix, pre_ix;
+  SI pre_address;
+  FRV_CACHE *cache;
+
+  /* See if the pc is within the addresses specified by either of the
+     fetch buffers.  If so, that will be the current buffer. Otherwise,
+     arbitrarily select the LD buffer as the current one since it gets
+     priority in the case of interfering load requests.  */
+  cur_ix = LD;
+  vpc &= ~(fetch_size - 1);
+  for (i = LS; i < FRV_CACHE_PIPELINES; ++i)
+    {
+      if (frv_insn_fetch_buffer[i].address == vpc)
+	{
+	  cur_ix = i;
+	  break;
+	}
+    }
+  cache = CPU_INSN_CACHE (current_cpu);
+
+  /* Request a load of the current address buffer, if necessary.  */
+  if (frv_insn_fetch_buffer[cur_ix].address != vpc)
+    {
+      frv_insn_fetch_buffer[cur_ix].address = vpc;
+      frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++;
+      if (FRV_COUNT_CYCLES (current_cpu, 1))
+	frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno,
+				frv_insn_fetch_buffer[cur_ix].address,
+				UNIT_I0 + cur_ix);
+    }
+
+  /* If the prefetch buffer does not represent the next sequential address, then
+     request a load of the next sequential address.  */
+  pre_ix = (cur_ix + 1) % FRV_CACHE_PIPELINES;
+  pre_address = vpc + fetch_size;
+  if (frv_insn_fetch_buffer[pre_ix].address != pre_address)
+    {
+      frv_insn_fetch_buffer[pre_ix].address = pre_address;
+      frv_insn_fetch_buffer[pre_ix].reqno = cache_reqno++;
+      if (FRV_COUNT_CYCLES (current_cpu, 1))
+	frv_cache_request_load (cache, frv_insn_fetch_buffer[pre_ix].reqno,
+				frv_insn_fetch_buffer[pre_ix].address,
+				UNIT_I0 + pre_ix);
+    }
+
+  /* If counting cycles, account for any branch penalty and/or insn fetch
+     latency here.  */
+  if (FRV_COUNT_CYCLES (current_cpu, 1))
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+      int wait;
+
+      /* Account for any branch penalty.  */
+      if (ps->branch_penalty > 0 && ! ps->past_first_p)
+	{
+	  frv_model_advance_cycles (current_cpu, ps->branch_penalty);
+	  frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty,
+				       "Branch penalty:");
+	  ps->branch_penalty = 0;
+	}
+
+      /* Account for insn fetch latency.  */
+      wait = 0;
+      while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
+	{
+	  frv_model_advance_cycles (current_cpu, 1);
+	  ++wait;
+	}
+      frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:");
+      return;
+    }
+
+  /* Otherwise just load the insns directly from the cache.
+   */
+  if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
+    {
+      frv_cache_read (cache, cur_ix, vpc);
+      frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
+    }
+  if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO)
+    {
+      frv_cache_read (cache, pre_ix, pre_address);
+      frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO;
+    }
+}
+
+static void
+@cpu@_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc)
+{
+  SI hsr0;
+  SIM_DESC sd;
+
+  /* Nothing to do if not counting cycles and the cache is not enabled.  */
+  hsr0 = GET_HSR0 ();
+  if (! GET_HSR0_ICE (hsr0) && ! FRV_COUNT_CYCLES (current_cpu, 1))
+    return;
+
+  /* Different machines handle prefetch defferently.  */
+  sd = CPU_STATE (current_cpu);
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      simulate_dual_insn_prefetch (current_cpu, vpc, 8);
+      break;
+    case bfd_mach_frvtomcat:
+    case bfd_mach_fr500:
+    case bfd_mach_frv:
+      simulate_dual_insn_prefetch (current_cpu, vpc, 16);
+      break;
+    default:
+      break;
+    }
+}
+
+int frv_save_profile_model_p;
+EOF
+
+;;
+
+xinit)
+
+cat <<EOF
+/*xxxinit*/
+  /* If the timer is enabled, then we will enable model profiling during
+     execution.  This is because the timer needs accurate cycles counts to
+     work properly.  Save the original setting of model profiling.  */
+  if (frv_interrupt_state.timer.enabled)
+    frv_save_profile_model_p = PROFILE_MODEL_P (current_cpu);
+EOF
+
+;;
+
+xextract-simple | xextract-scache)
+
+# Inputs:  current_cpu, vpc, sc, FAST_P
+# Outputs: sc filled in
+# SET_LAST_INSN_P(last_p) called to indicate whether insn is last one
+
+cat <<EOF
+{
+  CGEN_INSN_INT insn = frvbf_read_imem_USI (current_cpu, vpc);
+  extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
+  SET_LAST_INSN_P ((insn & 0x80000000) != 0);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, vpc, FAST_P
+# Outputs:
+#   vpc contains the address of the next insn to execute
+#   pc of current_cpu must be up to date (=vpc) upon exit
+#   CPU_INSN_COUNT (current_cpu) must be updated by number of insns executed
+#
+# Unlike the non-parallel case, this version is responsible for doing the
+# scache lookup.
+
+cat <<EOF
+{
+  FRV_VLIW *vliw;
+  int first_insn_p = 1;
+  int last_insn_p = 0;
+  int ninsns;
+
+  /* If the timer is enabled, then enable model profiling.  This is because
+     the timer needs accurate cycles counts to work properly.  */
+  if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
+    sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "1");
+
+  /* Init parallel-write queue and vliw.  */
+  @cpu@_parallel_write_init (current_cpu);
+  vliw = CPU_VLIW (current_cpu);
+  frv_vliw_reset (vliw, STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach,
+                  CPU_ELF_FLAGS (current_cpu));
+
+  for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns)
+    {
+      SCACHE *sc;
+      const CGEN_INSN *insn;
+      int error;
+      /* Go through the motions of finding the insns in the cache.  */
+      @cpu@_simulate_insn_prefetch (current_cpu, vpc);
+
+      sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
+      sc->first_insn_p = first_insn_p;
+      last_insn_p = sc->last_insn_p;
+
+      /* Add the insn to the vliw and set up the interrupt state.  */
+      insn = sc->argbuf.idesc->idata;
+      error = frv_vliw_add_insn (vliw, insn);
+      if (! error)
+        frv_vliw_setup_insn (current_cpu, insn);
+      frv_detect_insn_access_interrupts (current_cpu, sc);
+
+      vpc = execute (current_cpu, sc, FAST_P);
+
+      SET_H_PC (vpc); /* needed for interrupt handling */
+      first_insn_p = 0;
+    }
+
+  /* If the timer is enabled, and model profiling was not originally enabled,
+     then turn it off again.  This is the only place we can currently gain
+     control to do this.  */
+  if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
+    sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0");
+
+  /* Check for interrupts.  Also handles writeback if necessary.  */
+  frv_process_interrupts (current_cpu);
+
+  CPU_INSN_COUNT (current_cpu) += ninsns;
+}
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac
diff --git a/sim/frv/model.c b/sim/frv/model.c
new file mode 100644
index 00000000000..f24d827e51d
--- /dev/null
+++ b/sim/frv/model.c
@@ -0,0 +1,72726 @@
+/* Simulator model support for frvbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+   mechanism.  After all, this is information for profiling.  */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn.  */
+
+static int
+model_frv_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_udiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_smul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_umul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_scan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csmul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csrl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cscan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_addcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_andcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_orcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_xorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_srlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_smulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_umulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_caddcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csubcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csmulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_candcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_corcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cxorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csrlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_addxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_udivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nudivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_smuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_umuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_scani (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_addicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_andicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_oricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_xoricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_smulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_umulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sllicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_srlicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sraicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_addxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_addxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmpb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmpba (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_setlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sethi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_setlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lddc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lddcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nlddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rsth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rsthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_std (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stdc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rstqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stdcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_csthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cstdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sthi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_sthfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stdi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stdfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_stqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_swapi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cswap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movgfq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movfgq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmovgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmovfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmovgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmovfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movgs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_movsg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fblg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fblt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bctrlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_beqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_blelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_blslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bhilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bceqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bclelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bclslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bchilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bcnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_jmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_calll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_jmpil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_callil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rett (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_rei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_teq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_thi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fteq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftlg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fto (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tils (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tihi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tinc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tin (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tip (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tinv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftilg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftiue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftiul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftiuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftiug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftiule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ftio (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mtrap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_andcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_orcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_xorcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nandcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_norcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_andncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_orncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nandncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_norncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_notcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ccklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ccknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ccknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cjmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ccalll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_ici (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_dci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_icei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_dcei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_dcf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_dcef (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_witlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_wdtlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_itlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_dtlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_icpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_dcpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_icul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_dcul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_bar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_membar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clrgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clrfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clrga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_clrfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_commitgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_commitfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_commitga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_commitfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fitod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdtoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmovd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fnegd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fabsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fsqrtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_faddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmuld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdivd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fcmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmaddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fmsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_nfdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mhsetlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mhsethis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mhdsets (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mhsetloh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mhsethih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mhdseth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mrotri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mwcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mwcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mdcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_maveh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msrlhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mdrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcplhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcpli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqsaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msathu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcmpsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcmpuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mabshs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_maddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_maddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mmrdhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mclracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mclracc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_frv_fnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_udiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_smul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_umul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_scan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csmul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csrl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cscan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_addcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_andcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_orcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_xorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_srlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_smulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_umulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_caddcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csubcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csmulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_candcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_corcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cxorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csrlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_addxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_udivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nudivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_smuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_umuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_scani (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_addicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_andicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_oricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_xoricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_smulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_umulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sllicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_srlicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sraicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_addxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_addxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmpb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmpba (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_setlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_GRkhi = -1;
+    INT out_GRklo = -1;
+    out_GRklo = FLD (out_GRklo);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sethi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_GRkhi = -1;
+    INT out_GRklo = -1;
+    out_GRkhi = FLD (out_GRkhi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_setlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lddc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lddcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nlddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRdoublek = FLD (out_FRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rsth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rsthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_std (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stdc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rstqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stdcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_csthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cstdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sthi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_sthfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stdi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRdoublek = FLD (in_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stdfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRdoublek = FLD (in_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_stqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_swapi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cswap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movgfq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movfgq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmovgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmovfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmovgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmovfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movgs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_spr = -1;
+    in_GRj = FLD (in_GRj);
+    out_spr = FLD (out_spr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_movsg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_spr = -1;
+    INT out_GRj = -1;
+    in_spr = FLD (in_spr);
+    out_GRj = FLD (out_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fblg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fblt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bctrlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_beqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_blelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_blslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bhilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bceqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bclelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bclslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bchilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bcnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_jmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_calll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_jmpil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_callil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rett (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_rei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_teq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_thi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fteq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftlg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fto (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tils (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tihi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tinc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tin (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tip (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tinv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftilg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftiue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftiul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftiuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftiug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftiule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ftio (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mtrap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_andcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_orcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_xorcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nandcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_norcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_andncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_orncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nandncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_norncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_notcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ccklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ccknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ccknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cjmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ccalll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_ici (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_dci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_icei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_dcei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_dcf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_dcef (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_witlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_wdtlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_itlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_dtlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_icpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_dcpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_icul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_dcul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_bar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_barrier (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_membar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_membar (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clrgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clrfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clrga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_clrfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_commitgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_commitfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_commitga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_commitfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fitod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 1;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdtoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 2;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_float_dual_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, out_FRk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRintj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT out_FRk = -1;
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmovd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT out_FRk = -1;
+    cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT out_FRk = -1;
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT out_FRk = -1;
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fnegd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fabsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT out_FRk = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_float_dual_sqrt (current_cpu, idesc, 0, referenced, in_FRj, out_FRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT out_FRk = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_float_dual_sqrt (current_cpu, idesc, 0, referenced, in_FRj, out_FRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fsqrtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRj = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT out_FRk = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_faddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublei = FLD (in_FRdoublei);
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublei = FLD (in_FRdoublei);
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmuld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublei = FLD (in_FRdoublei);
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdivd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublei = FLD (in_FRdoublei);
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FCCi_2 = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FCCi_2 = FLD (out_FCCi_2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fcmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FCCi_2 = -1;
+    in_FRdoublei = FLD (in_FRdoublei);
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FCCi_2 = FLD (out_FCCi_2);
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FCCi_2 = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FCCi_2 = FLD (out_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT out_FCCi_2 = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FCCi_2 = FLD (out_FCCi_2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_dual_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmaddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublei = FLD (in_FRdoublei);
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRdoublei = FLD (in_FRdoublei);
+    in_FRdoublej = FLD (in_FRdoublej);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fmsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT in_FRdoublei = -1;
+    INT in_FRdoublej = -1;
+    INT out_FRk = -1;
+    INT out_FRdoublek = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FRk = FLD (out_FRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_nfdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRi = -1;
+    INT in_FRj = -1;
+    INT out_FCCi_2 = -1;
+    in_FRi = FLD (in_FRi);
+    in_FRj = FLD (in_FRj);
+    out_FCCi_2 = FLD (out_FCCi_2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_float_dual_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mhsetlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mhsethis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mhdsets (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mhsetloh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mhsethih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mhdseth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mrotri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mwcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mwcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRintj = FLD (in_FRintj);
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 2;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRintj = FLD (in_FRintj);
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 2;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mdcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_maveh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msrlhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mdrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcplhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcpli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqsaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msathu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcmpsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcmpuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mabshs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_maddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_maddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mmrdhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 17)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 19)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 19)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr500_u_media_quad_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr500_u_media_quad_complex (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr500_u_media_quad_arith (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintkeven);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintk);
+    in_FRinti = FLD (in_FRintieven);
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media_dual_unpack (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintkeven);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_media_dual_btoh (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintkeven);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr500_u_media_dual_btoh (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintk);
+    in_FRintj = FLD (in_FRintjeven);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintk);
+    in_FRintj = FLD (in_FRintjeven);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media_dual_btohe (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr500_u_media_dual_btohe (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mclracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mclracc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 2;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_ACCGi = FLD (in_ACCGi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 3;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 5;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT in_ACC40Si = -1;
+    INT in_ACCGi = -1;
+    INT out_FRintk = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    INT out_ACCGk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_ACCGk = FLD (out_ACCGk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 7;
+    cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_fnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_udiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_smul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_umul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_scan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csmul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csrl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cscan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_addcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_andcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_orcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_xorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_srlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_smulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_umulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_caddcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csubcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csmulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_candcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_corcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cxorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csrlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_addxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_udivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nudivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_smuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_umuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_scani (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_addicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_andicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_oricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_xoricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_smulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_umulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sllicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_srlicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sraicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_addxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_addxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmpb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmpba (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_setlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sethi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_setlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lddc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lddcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nlddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rsth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rsthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_std (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stdc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rstqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stdcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_csthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cstdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sthi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_sthfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stdi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stdfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_stqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_swapi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cswap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movgfq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movfgq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmovgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmovfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmovgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmovfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movgs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_movsg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fblg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fblt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bctrlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_beqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_blelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_blslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bhilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bceqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bclelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bclslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bchilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bcnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_jmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_calll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_jmpil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_callil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rett (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_rei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_teq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_thi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fteq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftlg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fto (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tils (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tihi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tinc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tin (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tip (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tinv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftilg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftiue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftiul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftiuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftiug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftiule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ftio (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mtrap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_andcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_orcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_xorcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nandcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_norcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_andncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_orncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nandncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_norncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_notcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ccklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ccknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ccknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cjmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ccalll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_ici (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_dci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_icei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_dcei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_dcf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_dcef (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_witlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_wdtlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_itlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_dtlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_icpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_dcpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_icul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_dcul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_bar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_membar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clrgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clrfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clrga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_clrfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_commitgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_commitfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_commitga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_commitfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fitod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdtoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmovd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fnegd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fabsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fsqrtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_faddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmuld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdivd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fcmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmaddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fmsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_nfdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mhsetlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mhsethis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mhdsets (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mhsetloh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mhsethih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mhdseth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mrotri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mwcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mwcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mdcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_maveh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msrlhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mdrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcplhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcpli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqsaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msathu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcmpsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcmpuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mabshs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_maddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_maddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mmrdhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mclracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mclracc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_fnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_udiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_smul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_umul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_scan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csmul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csrl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cscan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_addcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_andcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_orcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_xorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_srlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_smulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_umulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_caddcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csubcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csmulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_candcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_corcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cxorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csrlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_addxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_udivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_smuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_umuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_scani (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_addicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_andicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_oricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_xoricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_smulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_umulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRdoublek = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sllicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_srlicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sraicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_addxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_addxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmpb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmpba (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_ICCi_1 = FLD (out_ICCi_1);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_setlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_GRkhi = -1;
+    INT out_GRklo = -1;
+    out_GRklo = FLD (out_GRklo);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sethi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_GRkhi = -1;
+    INT out_GRklo = -1;
+    out_GRkhi = FLD (out_GRkhi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_setlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_ICCi_1 = -1;
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lddc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lddcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    out_FRdoublek = FLD (out_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nlddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rsth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rsthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_std (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stdc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rstqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stdcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    INT out_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRdoublek = FLD (out_GRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 7)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    INT out_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_FRdoublek = FLD (out_FRdoublek);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRk = FLD (in_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_csthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRintk = FLD (in_FRintk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_GRdoublek = FLD (in_GRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cstdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FRdoublek = FLD (in_FRdoublek);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sthi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRk = FLD (in_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_sthfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRintk = FLD (in_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stdi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_GRk = -1;
+    INT in_GRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRdoublek = FLD (in_GRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stdfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_FRintk = -1;
+    INT in_FRdoublek = -1;
+    in_GRi = FLD (in_GRi);
+    in_FRdoublek = FLD (in_FRdoublek);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_stqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_swapi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    in_GRi = FLD (in_GRi);
+    out_GRk = FLD (out_GRk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cswap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT out_GRk = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    out_GRk = FLD (out_GRk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movgfq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movfgq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmovgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmovfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmovgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_FRintk = -1;
+    in_GRj = FLD (in_GRj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmovfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintk = -1;
+    INT out_GRj = -1;
+    in_FRintk = FLD (in_FRintk);
+    out_GRj = FLD (out_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movgs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRj = -1;
+    INT out_spr = -1;
+    in_GRj = FLD (in_GRj);
+    out_spr = FLD (out_spr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_movsg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_spr = -1;
+    INT out_GRj = -1;
+    in_spr = FLD (in_spr);
+    out_GRj = FLD (out_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fblg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fblt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bctrlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_beqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_blelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_blslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bhilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bceqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bclelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bclslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bchilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bcnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_ICCi_2 = FLD (in_ICCi_2);
+    referenced |= 1 << 2;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_FCCi_2 = FLD (in_FCCi_2);
+    referenced |= 1 << 3;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_jmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_calll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_jmpil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_callil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rett (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_rei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_teq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_thi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fteq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftlg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fto (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tils (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tihi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tinc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tin (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tip (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tinv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_ICCi_2 = FLD (in_ICCi_2);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftilg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftiue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftiul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftiuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftiug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftiule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ftio (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_FCCi_2 = FLD (in_FCCi_2);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mtrap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_andcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_orcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_xorcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nandcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_norcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_andncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_orncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nandncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_norncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_notcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ccklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ccknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ccknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_ICCi_3 = FLD (in_ICCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ICCi_3 = -1;
+    INT in_FCCi_3 = -1;
+    in_FCCi_3 = FLD (in_FCCi_3);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cjmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ccalll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    INT in_ICCi_2 = -1;
+    INT in_FCCi_2 = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+    cycles += frvbf_model_fr400_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_ici (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_dci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_icei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_dcei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_dcf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_dcef (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_witlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_wdtlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_itlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_dtlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_icpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_dcpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    in_GRj = FLD (in_GRj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_icul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_dcul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_GRi = -1;
+    INT in_GRj = -1;
+    in_GRi = FLD (in_GRi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_bar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_barrier (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_membar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_membar (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clrgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clrfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clrga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_clrfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_commitgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_commitfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_commitga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_commitfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fitod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdtoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmovd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fnegd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fabsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fsqrtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_faddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmuld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdivd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fcmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmaddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fmsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_nfdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhsetlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_FRkhi = -1;
+    INT out_FRklo = -1;
+    out_FRklo = FLD (out_FRklo);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhsethis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_FRkhi = -1;
+    INT out_FRklo = -1;
+    out_FRkhi = FLD (out_FRkhi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhdsets (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhsetloh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_FRkhi = -1;
+    INT out_FRklo = -1;
+    out_FRklo = FLD (out_FRklo);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhsethih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT out_FRkhi = -1;
+    INT out_FRklo = -1;
+    out_FRkhi = FLD (out_FRkhi);
+    referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhdseth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mrotri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mwcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mwcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_FRintk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_FRintk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_FRintk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_FRintk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT out_FRintk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintkeven);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_maveh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msrlhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_6 (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcplhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqsaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msathu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcmpsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FCCk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FCCk = FLD (out_FCCk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcmpuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FCCk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_FCCk = FLD (out_FCCk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mabshs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRintj = FLD (in_FRintj);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_maddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_maddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT out_ACC40Sk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT out_ACC40Sk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT out_ACC40Sk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT out_ACC40Sk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT out_ACC40Sk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_2_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT out_ACC40Sk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_2_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmrdhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 17)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 19)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Uk = FLD (out_ACC40Uk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 19)) referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    in_FRinti = FLD (in_FRinti);
+    in_FRintj = FLD (in_FRintj);
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_ACC40Uk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRintieven);
+    in_FRintj = FLD (in_FRintjeven);
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_FRintk = FLD (out_FRintkeven);
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+    cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRinti = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintkeven);
+    cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintk);
+    in_FRintj = FLD (in_FRintjeven);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_FRintj = -1;
+    INT out_FRintk = -1;
+    out_FRintk = FLD (out_FRintk);
+    in_FRintj = FLD (in_FRintjeven);
+    referenced |= 1 << 1;
+    cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mclracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mclracc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_FRintk = -1;
+    cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_FRintk = -1;
+    in_ACC40Si = FLD (in_ACC40Si);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACCGi = -1;
+    INT in_FRinti = -1;
+    INT out_ACCGk = -1;
+    INT out_FRintk = -1;
+    in_ACCGi = FLD (in_ACCGi);
+    out_FRintk = FLD (out_FRintk);
+    referenced |= 1 << 0;
+    referenced |= 1 << 3;
+    cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACC40Si = -1;
+    INT in_FRintj = -1;
+    INT out_ACC40Sk = -1;
+    INT out_FRintk = -1;
+    out_ACC40Sk = FLD (out_ACC40Sk);
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_ACCGi = -1;
+    INT in_FRinti = -1;
+    INT out_ACCGk = -1;
+    INT out_FRintk = -1;
+    in_FRinti = FLD (in_FRinti);
+    out_ACCGk = FLD (out_ACCGk);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_udiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_smul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_umul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_scan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csmul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csrl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cscan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_addcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_andcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_orcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_xorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_srlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_smulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_umulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_caddcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csubcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csmulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_candcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_corcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cxorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csrlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_addxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_udivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nudivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_smuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_umuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_scani (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_addicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_andicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_oricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_xoricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_smulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_umulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sllicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_srlicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sraicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_addxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_addxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmpb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmpba (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_setlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sethi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_setlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lddc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lddcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nlddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rsth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rsthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_std (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stdc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rstqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stdcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_csthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cstdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sthi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_sthfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stdi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stdfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_stqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_swapi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cswap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movgfq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movfgq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmovgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmovfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmovgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmovfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movgs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_movsg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fblg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fblt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bctrlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_beqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_blelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_blslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bhilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bceqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bclelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bclslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bchilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bcnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_jmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_calll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_jmpil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_callil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rett (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_rei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_teq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_thi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fteq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftlg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fto (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tils (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tihi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tinc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tin (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tip (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tinv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftilg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftiue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftiul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftiuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftiug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftiule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ftio (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mtrap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_andcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_orcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_xorcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nandcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_norcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_andncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_orncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nandncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_norncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_notcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ccklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ccknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ccknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cjmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ccalll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_ici (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_dci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_icei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_dcei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_dcf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_dcef (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_witlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_wdtlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_itlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_dtlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_icpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_dcpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_icul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_dcul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_bar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_membar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clrgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clrfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clrga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_clrfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_commitgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_commitfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_commitga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_commitfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fitod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdtoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmovd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fnegd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fabsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fsqrtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_faddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmuld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdivd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fcmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmaddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fmsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_nfdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mhsetlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mhsethis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mhdsets (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mhsetloh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mhsethih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mhdseth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mrotri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mwcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mwcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mdcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_maveh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msrlhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mdrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcplhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcpli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqsaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msathu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcmpsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcmpuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mabshs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_maddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_maddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mmrdhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mclracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mclracc.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_simple_fnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+  }
+  return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+   entries with it.  */
+
+/* Model timing data for `frv'.  */
+
+static const INSN_TIMING frv_timing[] = {
+  { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADD, model_frv_add, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUB, model_frv_sub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_AND, model_frv_and, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_OR, model_frv_or, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XOR, model_frv_xor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOT, model_frv_not, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SDIV, model_frv_sdiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NSDIV, model_frv_nsdiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UDIV, model_frv_udiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NUDIV, model_frv_nudiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMUL, model_frv_smul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMUL, model_frv_umul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLL, model_frv_sll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRL, model_frv_srl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRA, model_frv_sra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SCAN, model_frv_scan, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CADD, model_frv_cadd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSUB, model_frv_csub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CAND, model_frv_cand, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COR, model_frv_cor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CXOR, model_frv_cxor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CNOT, model_frv_cnot, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSMUL, model_frv_csmul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSDIV, model_frv_csdiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CUDIV, model_frv_cudiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSLL, model_frv_csll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRL, model_frv_csrl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRA, model_frv_csra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSCAN, model_frv_cscan, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDCC, model_frv_addcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBCC, model_frv_subcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCC, model_frv_andcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCC, model_frv_orcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCC, model_frv_xorcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLCC, model_frv_sllcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLCC, model_frv_srlcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRACC, model_frv_sracc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULCC, model_frv_smulcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULCC, model_frv_umulcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CADDCC, model_frv_caddcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSUBCC, model_frv_csubcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSMULCC, model_frv_csmulcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CANDCC, model_frv_candcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CORCC, model_frv_corcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CXORCC, model_frv_cxorcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSLLCC, model_frv_csllcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRLCC, model_frv_csrlcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRACC, model_frv_csracc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDX, model_frv_addx, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBX, model_frv_subx, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXCC, model_frv_addxcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXCC, model_frv_subxcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDI, model_frv_addi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBI, model_frv_subi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDI, model_frv_andi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORI, model_frv_ori, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORI, model_frv_xori, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SDIVI, model_frv_sdivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NSDIVI, model_frv_nsdivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UDIVI, model_frv_udivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NUDIVI, model_frv_nudivi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULI, model_frv_smuli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULI, model_frv_umuli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLI, model_frv_slli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLI, model_frv_srli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRAI, model_frv_srai, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SCANI, model_frv_scani, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDICC, model_frv_addicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBICC, model_frv_subicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDICC, model_frv_andicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORICC, model_frv_oricc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORICC, model_frv_xoricc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULICC, model_frv_smulicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULICC, model_frv_umulicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLICC, model_frv_sllicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLICC, model_frv_srlicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRAICC, model_frv_sraicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXI, model_frv_addxi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXI, model_frv_subxi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXICC, model_frv_addxicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXICC, model_frv_subxicc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMPB, model_frv_cmpb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMPBA, model_frv_cmpba, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETLO, model_frv_setlo, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETHI, model_frv_sethi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETLOS, model_frv_setlos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSB, model_frv_ldsb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUB, model_frv_ldub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSH, model_frv_ldsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUH, model_frv_lduh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LD, model_frv_ld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBF, model_frv_ldbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHF, model_frv_ldhf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDF, model_frv_ldf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDC, model_frv_ldc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSB, model_frv_nldsb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUB, model_frv_nldub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSH, model_frv_nldsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUH, model_frv_nlduh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLD, model_frv_nld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBF, model_frv_nldbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHF, model_frv_nldhf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDF, model_frv_nldf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDD, model_frv_ldd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDF, model_frv_lddf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDC, model_frv_lddc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDD, model_frv_nldd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDF, model_frv_nlddf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQ, model_frv_ldq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQF, model_frv_ldqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQC, model_frv_ldqc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQ, model_frv_nldq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQF, model_frv_nldqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBU, model_frv_ldsbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUBU, model_frv_ldubu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSHU, model_frv_ldshu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUHU, model_frv_lduhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDU, model_frv_ldu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSBU, model_frv_nldsbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBU, model_frv_nldubu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHU, model_frv_nldshu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHU, model_frv_nlduhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDU, model_frv_nldu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBFU, model_frv_ldbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHFU, model_frv_ldhfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDFU, model_frv_ldfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDCU, model_frv_ldcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFU, model_frv_nldbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFU, model_frv_nldhfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFU, model_frv_nldfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDU, model_frv_lddu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDU, model_frv_nlddu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDFU, model_frv_lddfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDCU, model_frv_lddcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFU, model_frv_nlddfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQU, model_frv_ldqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQU, model_frv_nldqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFU, model_frv_ldqfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQCU, model_frv_ldqcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFU, model_frv_nldqfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBI, model_frv_ldsbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSHI, model_frv_ldshi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDI, model_frv_ldi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUBI, model_frv_ldubi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUHI, model_frv_lduhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBFI, model_frv_ldbfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHFI, model_frv_ldhfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDFI, model_frv_ldfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSBI, model_frv_nldsbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBI, model_frv_nldubi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHI, model_frv_nldshi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHI, model_frv_nlduhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDI, model_frv_nldi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFI, model_frv_nldbfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFI, model_frv_nldhfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFI, model_frv_nldfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDI, model_frv_lddi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDFI, model_frv_lddfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDI, model_frv_nlddi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFI, model_frv_nlddfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQI, model_frv_ldqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFI, model_frv_ldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQI, model_frv_nldqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFI, model_frv_nldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STB, model_frv_stb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STH, model_frv_sth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ST, model_frv_st, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBF, model_frv_stbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHF, model_frv_sthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STF, model_frv_stf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STC, model_frv_stc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTB, model_frv_rstb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTH, model_frv_rsth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RST, model_frv_rst, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTBF, model_frv_rstbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTHF, model_frv_rsthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTF, model_frv_rstf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STD, model_frv_std, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDF, model_frv_stdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDC, model_frv_stdc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTD, model_frv_rstd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTDF, model_frv_rstdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQ, model_frv_stq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQF, model_frv_stqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQC, model_frv_stqc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQ, model_frv_rstq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQF, model_frv_rstqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBU, model_frv_stbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHU, model_frv_sthu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STU, model_frv_stu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBFU, model_frv_stbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHFU, model_frv_sthfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STFU, model_frv_stfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STCU, model_frv_stcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDU, model_frv_stdu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDFU, model_frv_stdfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDCU, model_frv_stdcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQU, model_frv_stqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFU, model_frv_stqfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQCU, model_frv_stqcu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSB, model_frv_cldsb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUB, model_frv_cldub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSH, model_frv_cldsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUH, model_frv_clduh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLD, model_frv_cld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDBF, model_frv_cldbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDHF, model_frv_cldhf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDF, model_frv_cldf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDD, model_frv_cldd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDF, model_frv_clddf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDQ, model_frv_cldq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSBU, model_frv_cldsbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUBU, model_frv_cldubu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSHU, model_frv_cldshu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUHU, model_frv_clduhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDU, model_frv_cldu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDBFU, model_frv_cldbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDHFU, model_frv_cldhfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDFU, model_frv_cldfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDU, model_frv_clddu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDFU, model_frv_clddfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDQU, model_frv_cldqu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTB, model_frv_cstb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTH, model_frv_csth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CST, model_frv_cst, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBF, model_frv_cstbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHF, model_frv_csthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTF, model_frv_cstf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTD, model_frv_cstd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDF, model_frv_cstdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTQ, model_frv_cstq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBU, model_frv_cstbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHU, model_frv_csthu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTU, model_frv_cstu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBFU, model_frv_cstbfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHFU, model_frv_csthfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTFU, model_frv_cstfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDU, model_frv_cstdu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDFU, model_frv_cstdfu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBI, model_frv_stbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHI, model_frv_sthi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STI, model_frv_sti, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBFI, model_frv_stbfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHFI, model_frv_sthfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STFI, model_frv_stfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDI, model_frv_stdi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDFI, model_frv_stdfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQI, model_frv_stqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFI, model_frv_stqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAP, model_frv_swap, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAPI, model_frv_swapi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSWAP, model_frv_cswap, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGF, model_frv_movgf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFG, model_frv_movfg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGFD, model_frv_movgfd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGD, model_frv_movfgd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGFQ, model_frv_movgfq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGQ, model_frv_movfgq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGF, model_frv_cmovgf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVFG, model_frv_cmovfg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGFD, model_frv_cmovgfd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVFGD, model_frv_cmovfgd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGS, model_frv_movgs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVSG, model_frv_movsg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BRA, model_frv_bra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNO, model_frv_bno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BEQ, model_frv_beq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNE, model_frv_bne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLE, model_frv_ble, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGT, model_frv_bgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLT, model_frv_blt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGE, model_frv_bge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLS, model_frv_bls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BHI, model_frv_bhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BC, model_frv_bc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNC, model_frv_bnc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BN, model_frv_bn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BP, model_frv_bp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BV, model_frv_bv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNV, model_frv_bnv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBRA, model_frv_fbra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNO, model_frv_fbno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNE, model_frv_fbne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBEQ, model_frv_fbeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLG, model_frv_fblg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUE, model_frv_fbue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUL, model_frv_fbul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGE, model_frv_fbge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLT, model_frv_fblt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGE, model_frv_fbuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUG, model_frv_fbug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLE, model_frv_fble, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGT, model_frv_fbgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULE, model_frv_fbule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBU, model_frv_fbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBO, model_frv_fbo, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCTRLR, model_frv_bctrlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BRALR, model_frv_bralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNOLR, model_frv_bnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BEQLR, model_frv_beqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNELR, model_frv_bnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLELR, model_frv_blelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGTLR, model_frv_bgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLTLR, model_frv_bltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGELR, model_frv_bgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLSLR, model_frv_blslr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BHILR, model_frv_bhilr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLR, model_frv_bclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNCLR, model_frv_bnclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNLR, model_frv_bnlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BPLR, model_frv_bplr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BVLR, model_frv_bvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNVLR, model_frv_bnvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBRALR, model_frv_fbralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNOLR, model_frv_fbnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBEQLR, model_frv_fbeqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNELR, model_frv_fbnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLGLR, model_frv_fblglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUELR, model_frv_fbuelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULLR, model_frv_fbullr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGELR, model_frv_fbgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLTLR, model_frv_fbltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGELR, model_frv_fbugelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGLR, model_frv_fbuglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLELR, model_frv_fblelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGTLR, model_frv_fbgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULELR, model_frv_fbulelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULR, model_frv_fbulr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBOLR, model_frv_fbolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCRALR, model_frv_bcralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNOLR, model_frv_bcnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCEQLR, model_frv_bceqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNELR, model_frv_bcnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLELR, model_frv_bclelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCGTLR, model_frv_bcgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLTLR, model_frv_bcltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCGELR, model_frv_bcgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLSLR, model_frv_bclslr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCHILR, model_frv_bchilr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCCLR, model_frv_bcclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNCLR, model_frv_bcnclr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNLR, model_frv_bcnlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCPLR, model_frv_bcplr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCVLR, model_frv_bcvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNVLR, model_frv_bcnvlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBRALR, model_frv_fcbralr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBNOLR, model_frv_fcbnolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBEQLR, model_frv_fcbeqlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBNELR, model_frv_fcbnelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLGLR, model_frv_fcblglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUELR, model_frv_fcbuelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULLR, model_frv_fcbullr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBGELR, model_frv_fcbgelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLTLR, model_frv_fcbltlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUGELR, model_frv_fcbugelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUGLR, model_frv_fcbuglr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLELR, model_frv_fcblelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBGTLR, model_frv_fcbgtlr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULELR, model_frv_fcbulelr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULR, model_frv_fcbulr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBOLR, model_frv_fcbolr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_JMPL, model_frv_jmpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLL, model_frv_calll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_JMPIL, model_frv_jmpil, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLIL, model_frv_callil, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALL, model_frv_call, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RETT, model_frv_rett, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_REI, model_frv_rei, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TRA, model_frv_tra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNO, model_frv_tno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TEQ, model_frv_teq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNE, model_frv_tne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLE, model_frv_tle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TGT, model_frv_tgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLT, model_frv_tlt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TGE, model_frv_tge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLS, model_frv_tls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_THI, model_frv_thi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TC, model_frv_tc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNC, model_frv_tnc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TN, model_frv_tn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TP, model_frv_tp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TV, model_frv_tv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNV, model_frv_tnv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTRA, model_frv_ftra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTNO, model_frv_ftno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTNE, model_frv_ftne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTEQ, model_frv_fteq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLG, model_frv_ftlg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUE, model_frv_ftue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUL, model_frv_ftul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTGE, model_frv_ftge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLT, model_frv_ftlt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUGE, model_frv_ftuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUG, model_frv_ftug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLE, model_frv_ftle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTGT, model_frv_ftgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTULE, model_frv_ftule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTU, model_frv_ftu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTO, model_frv_fto, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIRA, model_frv_tira, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINO, model_frv_tino, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIEQ, model_frv_tieq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINE, model_frv_tine, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILE, model_frv_tile, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIGT, model_frv_tigt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILT, model_frv_tilt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIGE, model_frv_tige, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILS, model_frv_tils, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIHI, model_frv_tihi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIC, model_frv_tic, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINC, model_frv_tinc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIN, model_frv_tin, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIP, model_frv_tip, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIV, model_frv_tiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINV, model_frv_tinv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIRA, model_frv_ftira, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTINO, model_frv_ftino, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTINE, model_frv_ftine, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIEQ, model_frv_ftieq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILG, model_frv_ftilg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUE, model_frv_ftiue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUL, model_frv_ftiul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIGE, model_frv_ftige, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILT, model_frv_ftilt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUGE, model_frv_ftiuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUG, model_frv_ftiug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILE, model_frv_ftile, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIGT, model_frv_ftigt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIULE, model_frv_ftiule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIU, model_frv_ftiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIO, model_frv_ftio, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BREAK, model_frv_break, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MTRAP, model_frv_mtrap, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCR, model_frv_andcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCR, model_frv_orcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCR, model_frv_xorcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDCR, model_frv_nandcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORCR, model_frv_norcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDNCR, model_frv_andncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORNCR, model_frv_orncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDNCR, model_frv_nandncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORNCR, model_frv_norncr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOTCR, model_frv_notcr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKRA, model_frv_ckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNO, model_frv_ckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKEQ, model_frv_ckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNE, model_frv_ckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLE, model_frv_ckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKGT, model_frv_ckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLT, model_frv_cklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKGE, model_frv_ckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLS, model_frv_ckls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKHI, model_frv_ckhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKC, model_frv_ckc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNC, model_frv_cknc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKN, model_frv_ckn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKP, model_frv_ckp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKV, model_frv_ckv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNV, model_frv_cknv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKRA, model_frv_fckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKNO, model_frv_fckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKNE, model_frv_fckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKEQ, model_frv_fckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLG, model_frv_fcklg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUE, model_frv_fckue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUL, model_frv_fckul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKGE, model_frv_fckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLT, model_frv_fcklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUGE, model_frv_fckuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUG, model_frv_fckug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLE, model_frv_fckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKGT, model_frv_fckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKULE, model_frv_fckule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKU, model_frv_fcku, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKO, model_frv_fcko, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKRA, model_frv_cckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNO, model_frv_cckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKEQ, model_frv_cckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNE, model_frv_cckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLE, model_frv_cckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKGT, model_frv_cckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLT, model_frv_ccklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKGE, model_frv_cckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLS, model_frv_cckls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKHI, model_frv_cckhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKC, model_frv_cckc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNC, model_frv_ccknc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKN, model_frv_cckn, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKP, model_frv_cckp, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKV, model_frv_cckv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNV, model_frv_ccknv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKRA, model_frv_cfckra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKNO, model_frv_cfckno, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKNE, model_frv_cfckne, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKEQ, model_frv_cfckeq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLG, model_frv_cfcklg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUE, model_frv_cfckue, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUL, model_frv_cfckul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKGE, model_frv_cfckge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLT, model_frv_cfcklt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUGE, model_frv_cfckuge, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUG, model_frv_cfckug, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLE, model_frv_cfckle, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKGT, model_frv_cfckgt, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKULE, model_frv_cfckule, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKU, model_frv_cfcku, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKO, model_frv_cfcko, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CJMPL, model_frv_cjmpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCALLL, model_frv_ccalll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICI, model_frv_ici, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCI, model_frv_dci, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICEI, model_frv_icei, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCEI, model_frv_dcei, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCF, model_frv_dcf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCEF, model_frv_dcef, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WITLB, model_frv_witlb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WDTLB, model_frv_wdtlb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ITLBI, model_frv_itlbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DTLBI, model_frv_dtlbi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICPL, model_frv_icpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCPL, model_frv_dcpl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICUL, model_frv_icul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCUL, model_frv_dcul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BAR, model_frv_bar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEMBAR, model_frv_membar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP1, model_frv_cop1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP2, model_frv_cop2, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGR, model_frv_clrgr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFR, model_frv_clrfr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGA, model_frv_clrga, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFA, model_frv_clrfa, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGR, model_frv_commitgr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFR, model_frv_commitfr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGA, model_frv_commitga, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFA, model_frv_commitfa, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOS, model_frv_fitos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSTOI, model_frv_fstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOD, model_frv_fitod, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDTOI, model_frv_fdtoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDITOS, model_frv_fditos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSTOI, model_frv_fdstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDITOS, model_frv_nfditos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSTOI, model_frv_nfdstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFITOS, model_frv_cfitos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSTOI, model_frv_cfstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFITOS, model_frv_nfitos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSTOI, model_frv_nfstoi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVS, model_frv_fmovs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVD, model_frv_fmovd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMOVS, model_frv_fdmovs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMOVS, model_frv_cfmovs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGS, model_frv_fnegs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGD, model_frv_fnegd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDNEGS, model_frv_fdnegs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFNEGS, model_frv_cfnegs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSS, model_frv_fabss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSD, model_frv_fabsd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDABSS, model_frv_fdabss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFABSS, model_frv_cfabss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTS, model_frv_fsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSQRTS, model_frv_fdsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSQRTS, model_frv_nfdsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTD, model_frv_fsqrtd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSQRTS, model_frv_cfsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSQRTS, model_frv_nfsqrts, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDS, model_frv_fadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBS, model_frv_fsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULS, model_frv_fmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVS, model_frv_fdivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDD, model_frv_faddd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBD, model_frv_fsubd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULD, model_frv_fmuld, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVD, model_frv_fdivd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFADDS, model_frv_cfadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSUBS, model_frv_cfsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMULS, model_frv_cfmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFDIVS, model_frv_cfdivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFADDS, model_frv_nfadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSUBS, model_frv_nfsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMULS, model_frv_nfmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDIVS, model_frv_nfdivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPS, model_frv_fcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPD, model_frv_fcmpd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCMPS, model_frv_cfcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDCMPS, model_frv_fdcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDS, model_frv_fmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBS, model_frv_fmsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDD, model_frv_fmaddd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBD, model_frv_fmsubd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMADDS, model_frv_fdmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMADDS, model_frv_nfdmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMADDS, model_frv_cfmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSUBS, model_frv_cfmsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMADDS, model_frv_nfmadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSUBS, model_frv_nfmsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAS, model_frv_fmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSS, model_frv_fmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMAS, model_frv_fdmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMSS, model_frv_fdmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMAS, model_frv_nfdmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMSS, model_frv_nfdmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMAS, model_frv_cfmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSS, model_frv_cfmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAD, model_frv_fmad, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSD, model_frv_fmsd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMAS, model_frv_nfmas, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSS, model_frv_nfmss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDADDS, model_frv_fdadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSUBS, model_frv_fdsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULS, model_frv_fdmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDDIVS, model_frv_fddivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSADS, model_frv_fdsads, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULCS, model_frv_fdmulcs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULCS, model_frv_nfdmulcs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDADDS, model_frv_nfdadds, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSUBS, model_frv_nfdsubs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULS, model_frv_nfdmuls, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDDIVS, model_frv_nfddivs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSADS, model_frv_nfdsads, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDCMPS, model_frv_nfdcmps, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOS, model_frv_mhsetlos, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIS, model_frv_mhsethis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETS, model_frv_mhdsets, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOH, model_frv_mhsetloh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIH, model_frv_mhsethih, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETH, model_frv_mhdseth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAND, model_frv_mand, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOR, model_frv_mor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MXOR, model_frv_mxor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMAND, model_frv_cmand, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOR, model_frv_cmor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMXOR, model_frv_cmxor, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MNOT, model_frv_mnot, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMNOT, model_frv_cmnot, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MROTLI, model_frv_mrotli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MROTRI, model_frv_mrotri, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWCUT, model_frv_mwcut, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWCUTI, model_frv_mwcuti, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUT, model_frv_mcut, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTI, model_frv_mcuti, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTSS, model_frv_mcutss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTSSI, model_frv_mcutssi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDCUTSSI, model_frv_mdcutssi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAVEH, model_frv_maveh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSLLHI, model_frv_msllhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSRLHI, model_frv_msrlhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSRAHI, model_frv_msrahi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDROTLI, model_frv_mdrotli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLHI, model_frv_mcplhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLI, model_frv_mcpli, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHS, model_frv_msaths, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSATHS, model_frv_mqsaths, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHU, model_frv_msathu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCMPSH, model_frv_mcmpsh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCMPUH, model_frv_mcmpuh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MABSHS, model_frv_mabshs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDHSS, model_frv_maddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDHUS, model_frv_maddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBHSS, model_frv_msubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBHUS, model_frv_msubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMADDHSS, model_frv_cmaddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMADDHUS, model_frv_cmaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHSS, model_frv_cmsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHUS, model_frv_cmsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQADDHSS, model_frv_mqaddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQADDHUS, model_frv_mqaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHSS, model_frv_mqsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHUS, model_frv_mqsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHSS, model_frv_cmqaddhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHUS, model_frv_cmqaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHSS, model_frv_cmqsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHUS, model_frv_cmqsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDACCS, model_frv_maddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBACCS, model_frv_msubaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDADDACCS, model_frv_mdaddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDSUBACCS, model_frv_mdsubaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MASACCS, model_frv_masaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDASACCS, model_frv_mdasaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULHS, model_frv_mmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULHU, model_frv_mmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULXHS, model_frv_mmulxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULXHU, model_frv_mmulxhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMULHS, model_frv_cmmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMULHU, model_frv_cmmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULHS, model_frv_mqmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULHU, model_frv_mqmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHS, model_frv_mqmulxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHU, model_frv_mqmulxhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHS, model_frv_cmqmulhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHU, model_frv_cmqmulhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMACHS, model_frv_mmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMACHU, model_frv_mmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMRDHS, model_frv_mmrdhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMRDHU, model_frv_mmrdhu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMACHS, model_frv_cmmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMACHU, model_frv_cmmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACHS, model_frv_mqmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACHU, model_frv_mqmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHS, model_frv_cmqmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHU, model_frv_cmqmachu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQXMACHS, model_frv_mqxmachs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQXMACXHS, model_frv_mqxmacxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACXHS, model_frv_mqmacxhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXRS, model_frv_mcpxrs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXRU, model_frv_mcpxru, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXIS, model_frv_mcpxis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXIU, model_frv_mcpxiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRS, model_frv_cmcpxrs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRU, model_frv_cmcpxru, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIS, model_frv_cmcpxis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIU, model_frv_cmcpxiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRS, model_frv_mqcpxrs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRU, model_frv_mqcpxru, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIS, model_frv_mqcpxis, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIU, model_frv_mqcpxiu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHW, model_frv_mexpdhw, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHW, model_frv_cmexpdhw, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHD, model_frv_mexpdhd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHD, model_frv_cmexpdhd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MPACKH, model_frv_mpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDPACKH, model_frv_mdpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MUNPACKH, model_frv_munpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDUNPACKH, model_frv_mdunpackh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MBTOH, model_frv_mbtoh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMBTOH, model_frv_cmbtoh, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHTOB, model_frv_mhtob, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMHTOB, model_frv_cmhtob, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MBTOHE, model_frv_mbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMBTOHE, model_frv_cmbtohe, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCLRACC, model_frv_mclracc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MRDACC, model_frv_mrdacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MRDACCG, model_frv_mrdaccg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWTACC, model_frv_mwtacc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWTACCG, model_frv_mwtaccg, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP1, model_frv_mcop1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP2, model_frv_mcop2, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNOP, model_frv_fnop, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+};
+
+/* Model timing data for `fr500'.  */
+
+static const INSN_TIMING fr500_timing[] = {
+  { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADD, model_fr500_add, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUB, model_fr500_sub, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_AND, model_fr500_and, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_OR, model_fr500_or, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XOR, model_fr500_xor, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_NOT, model_fr500_not, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SDIV, model_fr500_sdiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NSDIV, model_fr500_nsdiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_UDIV, model_fr500_udiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NUDIV, model_fr500_nudiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_SMUL, model_fr500_smul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMUL, model_fr500_umul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_SLL, model_fr500_sll, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRL, model_fr500_srl, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRA, model_fr500_sra, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SCAN, model_fr500_scan, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CADD, model_fr500_cadd, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSUB, model_fr500_csub, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CAND, model_fr500_cand, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_COR, model_fr500_cor, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CXOR, model_fr500_cxor, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CNOT, model_fr500_cnot, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSMUL, model_fr500_csmul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_CSDIV, model_fr500_csdiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_CUDIV, model_fr500_cudiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_CSLL, model_fr500_csll, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRL, model_fr500_csrl, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRA, model_fr500_csra, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSCAN, model_fr500_cscan, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDCC, model_fr500_addcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBCC, model_fr500_subcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ANDCC, model_fr500_andcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ORCC, model_fr500_orcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XORCC, model_fr500_xorcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SLLCC, model_fr500_sllcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRLCC, model_fr500_srlcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRACC, model_fr500_sracc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SMULCC, model_fr500_smulcc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMULCC, model_fr500_umulcc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_CADDCC, model_fr500_caddcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSUBCC, model_fr500_csubcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSMULCC, model_fr500_csmulcc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_CANDCC, model_fr500_candcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CORCC, model_fr500_corcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CXORCC, model_fr500_cxorcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSLLCC, model_fr500_csllcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRLCC, model_fr500_csrlcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRACC, model_fr500_csracc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDX, model_fr500_addx, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBX, model_fr500_subx, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDXCC, model_fr500_addxcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBXCC, model_fr500_subxcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDI, model_fr500_addi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBI, model_fr500_subi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ANDI, model_fr500_andi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ORI, model_fr500_ori, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XORI, model_fr500_xori, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SDIVI, model_fr500_sdivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NSDIVI, model_fr500_nsdivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_UDIVI, model_fr500_udivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NUDIVI, model_fr500_nudivi, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_SMULI, model_fr500_smuli, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMULI, model_fr500_umuli, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_SLLI, model_fr500_slli, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRLI, model_fr500_srli, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRAI, model_fr500_srai, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SCANI, model_fr500_scani, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDICC, model_fr500_addicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBICC, model_fr500_subicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ANDICC, model_fr500_andicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ORICC, model_fr500_oricc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XORICC, model_fr500_xoricc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SMULICC, model_fr500_smulicc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMULICC, model_fr500_umulicc, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_SLLICC, model_fr500_sllicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRLICC, model_fr500_srlicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRAICC, model_fr500_sraicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDXI, model_fr500_addxi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBXI, model_fr500_subxi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDXICC, model_fr500_addxicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBXICC, model_fr500_subxicc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CMPB, model_fr500_cmpb, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMPBA, model_fr500_cmpba, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETLO, model_fr500_setlo, { { (int) UNIT_FR500_U_SET_HILO, 1, 1 } } },
+  { FRVBF_INSN_SETHI, model_fr500_sethi, { { (int) UNIT_FR500_U_SET_HILO, 1, 1 } } },
+  { FRVBF_INSN_SETLOS, model_fr500_setlos, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_LDSB, model_fr500_ldsb, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUB, model_fr500_ldub, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSH, model_fr500_ldsh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUH, model_fr500_lduh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LD, model_fr500_ld, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDBF, model_fr500_ldbf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDHF, model_fr500_ldhf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDF, model_fr500_ldf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDC, model_fr500_ldc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSB, model_fr500_nldsb, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDUB, model_fr500_nldub, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDSH, model_fr500_nldsh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDUH, model_fr500_nlduh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLD, model_fr500_nld, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDBF, model_fr500_nldbf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDHF, model_fr500_nldhf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDF, model_fr500_nldf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDD, model_fr500_ldd, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDF, model_fr500_lddf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDC, model_fr500_lddc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDD, model_fr500_nldd, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDDF, model_fr500_nlddf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQ, model_fr500_ldq, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQF, model_fr500_ldqf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQC, model_fr500_ldqc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQ, model_fr500_nldq, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDQF, model_fr500_nldqf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSBU, model_fr500_ldsbu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUBU, model_fr500_ldubu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSHU, model_fr500_ldshu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUHU, model_fr500_lduhu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDU, model_fr500_ldu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDSBU, model_fr500_nldsbu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDUBU, model_fr500_nldubu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDSHU, model_fr500_nldshu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDUHU, model_fr500_nlduhu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDU, model_fr500_nldu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDBFU, model_fr500_ldbfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDHFU, model_fr500_ldhfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDFU, model_fr500_ldfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDCU, model_fr500_ldcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFU, model_fr500_nldbfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDHFU, model_fr500_nldhfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDFU, model_fr500_nldfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDU, model_fr500_lddu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDDU, model_fr500_nlddu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDFU, model_fr500_lddfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDCU, model_fr500_lddcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFU, model_fr500_nlddfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQU, model_fr500_ldqu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDQU, model_fr500_nldqu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQFU, model_fr500_ldqfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQCU, model_fr500_ldqcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFU, model_fr500_nldqfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSBI, model_fr500_ldsbi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSHI, model_fr500_ldshi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDI, model_fr500_ldi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUBI, model_fr500_ldubi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUHI, model_fr500_lduhi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDBFI, model_fr500_ldbfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDHFI, model_fr500_ldhfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDFI, model_fr500_ldfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDSBI, model_fr500_nldsbi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDUBI, model_fr500_nldubi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDSHI, model_fr500_nldshi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDUHI, model_fr500_nlduhi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDI, model_fr500_nldi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDBFI, model_fr500_nldbfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDHFI, model_fr500_nldhfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDFI, model_fr500_nldfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDI, model_fr500_lddi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDFI, model_fr500_lddfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDDI, model_fr500_nlddi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDDFI, model_fr500_nlddfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQI, model_fr500_ldqi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDQFI, model_fr500_ldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDQI, model_fr500_nldqi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDQFI, model_fr500_nldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_STB, model_fr500_stb, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STH, model_fr500_sth, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_ST, model_fr500_st, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBF, model_fr500_stbf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHF, model_fr500_sthf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STF, model_fr500_stf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STC, model_fr500_stc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTB, model_fr500_rstb, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_RSTH, model_fr500_rsth, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_RST, model_fr500_rst, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_RSTBF, model_fr500_rstbf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_RSTHF, model_fr500_rsthf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_RSTF, model_fr500_rstf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_STD, model_fr500_std, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDF, model_fr500_stdf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDC, model_fr500_stdc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTD, model_fr500_rstd, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_RSTDF, model_fr500_rstdf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQ, model_fr500_stq, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQF, model_fr500_stqf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQC, model_fr500_stqc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQ, model_fr500_rstq, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_RSTQF, model_fr500_rstqf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBU, model_fr500_stbu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHU, model_fr500_sthu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STU, model_fr500_stu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBFU, model_fr500_stbfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHFU, model_fr500_sthfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STFU, model_fr500_stfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STCU, model_fr500_stcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDU, model_fr500_stdu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDFU, model_fr500_stdfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDCU, model_fr500_stdcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQU, model_fr500_stqu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQFU, model_fr500_stqfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQCU, model_fr500_stqcu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSB, model_fr500_cldsb, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUB, model_fr500_cldub, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDSH, model_fr500_cldsh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUH, model_fr500_clduh, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLD, model_fr500_cld, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDBF, model_fr500_cldbf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDHF, model_fr500_cldhf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDF, model_fr500_cldf, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDD, model_fr500_cldd, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDDF, model_fr500_clddf, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDQ, model_fr500_cldq, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDSBU, model_fr500_cldsbu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUBU, model_fr500_cldubu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDSHU, model_fr500_cldshu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUHU, model_fr500_clduhu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDU, model_fr500_cldu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDBFU, model_fr500_cldbfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDHFU, model_fr500_cldhfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDFU, model_fr500_cldfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDDU, model_fr500_clddu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDDFU, model_fr500_clddfu, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDQU, model_fr500_cldqu, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CSTB, model_fr500_cstb, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTH, model_fr500_csth, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CST, model_fr500_cst, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTBF, model_fr500_cstbf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTHF, model_fr500_csthf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTF, model_fr500_cstf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTD, model_fr500_cstd, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTDF, model_fr500_cstdf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTQ, model_fr500_cstq, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTBU, model_fr500_cstbu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTHU, model_fr500_csthu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTU, model_fr500_cstu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTBFU, model_fr500_cstbfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTHFU, model_fr500_csthfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTFU, model_fr500_cstfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTDU, model_fr500_cstdu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTDFU, model_fr500_cstdfu, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBI, model_fr500_stbi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHI, model_fr500_sthi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STI, model_fr500_sti, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBFI, model_fr500_stbfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHFI, model_fr500_sthfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STFI, model_fr500_stfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDI, model_fr500_stdi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDFI, model_fr500_stdfi, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQI, model_fr500_stqi, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQFI, model_fr500_stqfi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAP, model_fr500_swap, { { (int) UNIT_FR500_U_SWAP, 1, 1 } } },
+  { FRVBF_INSN_SWAPI, model_fr500_swapi, { { (int) UNIT_FR500_U_SWAP, 1, 1 } } },
+  { FRVBF_INSN_CSWAP, model_fr500_cswap, { { (int) UNIT_FR500_U_SWAP, 1, 1 } } },
+  { FRVBF_INSN_MOVGF, model_fr500_movgf, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_MOVFG, model_fr500_movfg, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_MOVGFD, model_fr500_movgfd, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_MOVFGD, model_fr500_movfgd, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_MOVGFQ, model_fr500_movgfq, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGQ, model_fr500_movfgq, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGF, model_fr500_cmovgf, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_CMOVFG, model_fr500_cmovfg, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_CMOVGFD, model_fr500_cmovgfd, { { (int) UNIT_FR500_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_CMOVFGD, model_fr500_cmovfgd, { { (int) UNIT_FR500_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_MOVGS, model_fr500_movgs, { { (int) UNIT_FR500_U_GR2SPR, 1, 1 } } },
+  { FRVBF_INSN_MOVSG, model_fr500_movsg, { { (int) UNIT_FR500_U_SPR2GR, 1, 1 } } },
+  { FRVBF_INSN_BRA, model_fr500_bra, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNO, model_fr500_bno, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BEQ, model_fr500_beq, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNE, model_fr500_bne, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLE, model_fr500_ble, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGT, model_fr500_bgt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLT, model_fr500_blt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGE, model_fr500_bge, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLS, model_fr500_bls, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BHI, model_fr500_bhi, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BC, model_fr500_bc, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNC, model_fr500_bnc, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BN, model_fr500_bn, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BP, model_fr500_bp, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BV, model_fr500_bv, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNV, model_fr500_bnv, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBRA, model_fr500_fbra, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNO, model_fr500_fbno, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNE, model_fr500_fbne, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBEQ, model_fr500_fbeq, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLG, model_fr500_fblg, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUE, model_fr500_fbue, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUL, model_fr500_fbul, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGE, model_fr500_fbge, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLT, model_fr500_fblt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUGE, model_fr500_fbuge, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUG, model_fr500_fbug, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLE, model_fr500_fble, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGT, model_fr500_fbgt, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULE, model_fr500_fbule, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBU, model_fr500_fbu, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBO, model_fr500_fbo, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCTRLR, model_fr500_bctrlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BRALR, model_fr500_bralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNOLR, model_fr500_bnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BEQLR, model_fr500_beqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNELR, model_fr500_bnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLELR, model_fr500_blelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGTLR, model_fr500_bgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLTLR, model_fr500_bltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGELR, model_fr500_bgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLSLR, model_fr500_blslr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BHILR, model_fr500_bhilr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLR, model_fr500_bclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNCLR, model_fr500_bnclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNLR, model_fr500_bnlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BPLR, model_fr500_bplr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BVLR, model_fr500_bvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNVLR, model_fr500_bnvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBRALR, model_fr500_fbralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNOLR, model_fr500_fbnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBEQLR, model_fr500_fbeqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNELR, model_fr500_fbnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLGLR, model_fr500_fblglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUELR, model_fr500_fbuelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULLR, model_fr500_fbullr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGELR, model_fr500_fbgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLTLR, model_fr500_fbltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUGELR, model_fr500_fbugelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUGLR, model_fr500_fbuglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLELR, model_fr500_fblelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGTLR, model_fr500_fbgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULELR, model_fr500_fbulelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULR, model_fr500_fbulr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBOLR, model_fr500_fbolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCRALR, model_fr500_bcralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNOLR, model_fr500_bcnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCEQLR, model_fr500_bceqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNELR, model_fr500_bcnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLELR, model_fr500_bclelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCGTLR, model_fr500_bcgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLTLR, model_fr500_bcltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCGELR, model_fr500_bcgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLSLR, model_fr500_bclslr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCHILR, model_fr500_bchilr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCCLR, model_fr500_bcclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNCLR, model_fr500_bcnclr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNLR, model_fr500_bcnlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCPLR, model_fr500_bcplr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCVLR, model_fr500_bcvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNVLR, model_fr500_bcnvlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBRALR, model_fr500_fcbralr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBNOLR, model_fr500_fcbnolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBEQLR, model_fr500_fcbeqlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBNELR, model_fr500_fcbnelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBLGLR, model_fr500_fcblglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBUELR, model_fr500_fcbuelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBULLR, model_fr500_fcbullr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBGELR, model_fr500_fcbgelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBLTLR, model_fr500_fcbltlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBUGELR, model_fr500_fcbugelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBUGLR, model_fr500_fcbuglr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBLELR, model_fr500_fcblelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBGTLR, model_fr500_fcbgtlr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBULELR, model_fr500_fcbulelr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBULR, model_fr500_fcbulr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBOLR, model_fr500_fcbolr, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_JMPL, model_fr500_jmpl, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CALLL, model_fr500_calll, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_JMPIL, model_fr500_jmpil, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CALLIL, model_fr500_callil, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CALL, model_fr500_call, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_RETT, model_fr500_rett, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_REI, model_fr500_rei, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TRA, model_fr500_tra, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNO, model_fr500_tno, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TEQ, model_fr500_teq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNE, model_fr500_tne, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TLE, model_fr500_tle, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TGT, model_fr500_tgt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TLT, model_fr500_tlt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TGE, model_fr500_tge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TLS, model_fr500_tls, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_THI, model_fr500_thi, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TC, model_fr500_tc, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNC, model_fr500_tnc, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TN, model_fr500_tn, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TP, model_fr500_tp, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TV, model_fr500_tv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNV, model_fr500_tnv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTRA, model_fr500_ftra, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTNO, model_fr500_ftno, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTNE, model_fr500_ftne, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTEQ, model_fr500_fteq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTLG, model_fr500_ftlg, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUE, model_fr500_ftue, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUL, model_fr500_ftul, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTGE, model_fr500_ftge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTLT, model_fr500_ftlt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUGE, model_fr500_ftuge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUG, model_fr500_ftug, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTLE, model_fr500_ftle, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTGT, model_fr500_ftgt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTULE, model_fr500_ftule, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTU, model_fr500_ftu, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTO, model_fr500_fto, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIRA, model_fr500_tira, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINO, model_fr500_tino, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIEQ, model_fr500_tieq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINE, model_fr500_tine, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TILE, model_fr500_tile, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIGT, model_fr500_tigt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TILT, model_fr500_tilt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIGE, model_fr500_tige, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TILS, model_fr500_tils, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIHI, model_fr500_tihi, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIC, model_fr500_tic, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINC, model_fr500_tinc, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIN, model_fr500_tin, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIP, model_fr500_tip, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIV, model_fr500_tiv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINV, model_fr500_tinv, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIRA, model_fr500_ftira, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTINO, model_fr500_ftino, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTINE, model_fr500_ftine, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIEQ, model_fr500_ftieq, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTILG, model_fr500_ftilg, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUE, model_fr500_ftiue, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUL, model_fr500_ftiul, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIGE, model_fr500_ftige, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTILT, model_fr500_ftilt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUGE, model_fr500_ftiuge, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUG, model_fr500_ftiug, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTILE, model_fr500_ftile, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIGT, model_fr500_ftigt, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIULE, model_fr500_ftiule, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIU, model_fr500_ftiu, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIO, model_fr500_ftio, { { (int) UNIT_FR500_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_BREAK, model_fr500_break, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MTRAP, model_fr500_mtrap, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCR, model_fr500_andcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCR, model_fr500_orcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCR, model_fr500_xorcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDCR, model_fr500_nandcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORCR, model_fr500_norcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDNCR, model_fr500_andncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORNCR, model_fr500_orncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDNCR, model_fr500_nandncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORNCR, model_fr500_norncr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOTCR, model_fr500_notcr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKRA, model_fr500_ckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNO, model_fr500_ckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKEQ, model_fr500_ckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNE, model_fr500_ckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKLE, model_fr500_ckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKGT, model_fr500_ckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKLT, model_fr500_cklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKGE, model_fr500_ckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKLS, model_fr500_ckls, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKHI, model_fr500_ckhi, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKC, model_fr500_ckc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNC, model_fr500_cknc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKN, model_fr500_ckn, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKP, model_fr500_ckp, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKV, model_fr500_ckv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNV, model_fr500_cknv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKRA, model_fr500_fckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKNO, model_fr500_fckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKNE, model_fr500_fckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKEQ, model_fr500_fckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKLG, model_fr500_fcklg, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUE, model_fr500_fckue, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUL, model_fr500_fckul, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKGE, model_fr500_fckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKLT, model_fr500_fcklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUGE, model_fr500_fckuge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUG, model_fr500_fckug, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKLE, model_fr500_fckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKGT, model_fr500_fckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKULE, model_fr500_fckule, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKU, model_fr500_fcku, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKO, model_fr500_fcko, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKRA, model_fr500_cckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNO, model_fr500_cckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKEQ, model_fr500_cckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNE, model_fr500_cckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKLE, model_fr500_cckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKGT, model_fr500_cckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKLT, model_fr500_ccklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKGE, model_fr500_cckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKLS, model_fr500_cckls, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKHI, model_fr500_cckhi, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKC, model_fr500_cckc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNC, model_fr500_ccknc, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKN, model_fr500_cckn, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKP, model_fr500_cckp, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKV, model_fr500_cckv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNV, model_fr500_ccknv, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKRA, model_fr500_cfckra, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKNO, model_fr500_cfckno, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKNE, model_fr500_cfckne, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKEQ, model_fr500_cfckeq, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKLG, model_fr500_cfcklg, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUE, model_fr500_cfckue, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUL, model_fr500_cfckul, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKGE, model_fr500_cfckge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKLT, model_fr500_cfcklt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUGE, model_fr500_cfckuge, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUG, model_fr500_cfckug, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKLE, model_fr500_cfckle, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKGT, model_fr500_cfckgt, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKULE, model_fr500_cfckule, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKU, model_fr500_cfcku, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKO, model_fr500_cfcko, { { (int) UNIT_FR500_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CJMPL, model_fr500_cjmpl, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CCALLL, model_fr500_ccalll, { { (int) UNIT_FR500_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_ICI, model_fr500_ici, { { (int) UNIT_FR500_U_ICI, 1, 1 } } },
+  { FRVBF_INSN_DCI, model_fr500_dci, { { (int) UNIT_FR500_U_DCI, 1, 1 } } },
+  { FRVBF_INSN_ICEI, model_fr500_icei, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCEI, model_fr500_dcei, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCF, model_fr500_dcf, { { (int) UNIT_FR500_U_DCF, 1, 1 } } },
+  { FRVBF_INSN_DCEF, model_fr500_dcef, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WITLB, model_fr500_witlb, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WDTLB, model_fr500_wdtlb, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ITLBI, model_fr500_itlbi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DTLBI, model_fr500_dtlbi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICPL, model_fr500_icpl, { { (int) UNIT_FR500_U_ICPL, 1, 1 } } },
+  { FRVBF_INSN_DCPL, model_fr500_dcpl, { { (int) UNIT_FR500_U_DCPL, 1, 1 } } },
+  { FRVBF_INSN_ICUL, model_fr500_icul, { { (int) UNIT_FR500_U_ICUL, 1, 1 } } },
+  { FRVBF_INSN_DCUL, model_fr500_dcul, { { (int) UNIT_FR500_U_DCUL, 1, 1 } } },
+  { FRVBF_INSN_BAR, model_fr500_bar, { { (int) UNIT_FR500_U_BARRIER, 1, 1 } } },
+  { FRVBF_INSN_MEMBAR, model_fr500_membar, { { (int) UNIT_FR500_U_MEMBAR, 1, 1 } } },
+  { FRVBF_INSN_COP1, model_fr500_cop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP2, model_fr500_cop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGR, model_fr500_clrgr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFR, model_fr500_clrfr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGA, model_fr500_clrga, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFA, model_fr500_clrfa, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGR, model_fr500_commitgr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFR, model_fr500_commitfr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGA, model_fr500_commitga, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFA, model_fr500_commitfa, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOS, model_fr500_fitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_FSTOI, model_fr500_fstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_FITOD, model_fr500_fitod, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_FDTOI, model_fr500_fdtoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_FDITOS, model_fr500_fditos, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_FDSTOI, model_fr500_fdstoi, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_NFDITOS, model_fr500_nfditos, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_NFDSTOI, model_fr500_nfdstoi, { { (int) UNIT_FR500_U_FLOAT_DUAL_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_CFITOS, model_fr500_cfitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_CFSTOI, model_fr500_cfstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_NFITOS, model_fr500_nfitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_NFSTOI, model_fr500_nfstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
+  { FRVBF_INSN_FMOVS, model_fr500_fmovs, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } },
+  { FRVBF_INSN_FMOVD, model_fr500_fmovd, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } },
+  { FRVBF_INSN_FDMOVS, model_fr500_fdmovs, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } },
+  { FRVBF_INSN_CFMOVS, model_fr500_cfmovs, { { (int) UNIT_FR500_U_FR2FR, 1, 1 } } },
+  { FRVBF_INSN_FNEGS, model_fr500_fnegs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FNEGD, model_fr500_fnegd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDNEGS, model_fr500_fdnegs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFNEGS, model_fr500_cfnegs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FABSS, model_fr500_fabss, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FABSD, model_fr500_fabsd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDABSS, model_fr500_fdabss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFABSS, model_fr500_cfabss, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FSQRTS, model_fr500_fsqrts, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } },
+  { FRVBF_INSN_FDSQRTS, model_fr500_fdsqrts, { { (int) UNIT_FR500_U_FLOAT_DUAL_SQRT, 1, 1 } } },
+  { FRVBF_INSN_NFDSQRTS, model_fr500_nfdsqrts, { { (int) UNIT_FR500_U_FLOAT_DUAL_SQRT, 1, 1 } } },
+  { FRVBF_INSN_FSQRTD, model_fr500_fsqrtd, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } },
+  { FRVBF_INSN_CFSQRTS, model_fr500_cfsqrts, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } },
+  { FRVBF_INSN_NFSQRTS, model_fr500_nfsqrts, { { (int) UNIT_FR500_U_FLOAT_SQRT, 1, 1 } } },
+  { FRVBF_INSN_FADDS, model_fr500_fadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FSUBS, model_fr500_fsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMULS, model_fr500_fmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDIVS, model_fr500_fdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } },
+  { FRVBF_INSN_FADDD, model_fr500_faddd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FSUBD, model_fr500_fsubd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMULD, model_fr500_fmuld, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDIVD, model_fr500_fdivd, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFADDS, model_fr500_cfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFSUBS, model_fr500_cfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFMULS, model_fr500_cfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFDIVS, model_fr500_cfdivs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFADDS, model_fr500_nfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFSUBS, model_fr500_nfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFMULS, model_fr500_nfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDIVS, model_fr500_nfdivs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FCMPS, model_fr500_fcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
+  { FRVBF_INSN_FCMPD, model_fr500_fcmpd, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
+  { FRVBF_INSN_CFCMPS, model_fr500_cfcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
+  { FRVBF_INSN_FDCMPS, model_fr500_fdcmps, { { (int) UNIT_FR500_U_FLOAT_DUAL_COMPARE, 1, 1 } } },
+  { FRVBF_INSN_FMADDS, model_fr500_fmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMSUBS, model_fr500_fmsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMADDD, model_fr500_fmaddd, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMSUBD, model_fr500_fmsubd, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDMADDS, model_fr500_fdmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDMADDS, model_fr500_nfdmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFMADDS, model_fr500_cfmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFMSUBS, model_fr500_cfmsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFMADDS, model_fr500_nfmadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFMSUBS, model_fr500_nfmsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMAS, model_fr500_fmas, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMSS, model_fr500_fmss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDMAS, model_fr500_fdmas, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMSS, model_fr500_fdmss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMAS, model_fr500_nfdmas, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMSS, model_fr500_nfdmss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMAS, model_fr500_cfmas, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CFMSS, model_fr500_cfmss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FMAD, model_fr500_fmad, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSD, model_fr500_fmsd, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMAS, model_fr500_nfmas, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFMSS, model_fr500_nfmss, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDADDS, model_fr500_fdadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDSUBS, model_fr500_fdsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDMULS, model_fr500_fdmuls, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDDIVS, model_fr500_fddivs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDSADS, model_fr500_fdsads, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_FDMULCS, model_fr500_fdmulcs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDMULCS, model_fr500_nfdmulcs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDADDS, model_fr500_nfdadds, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDSUBS, model_fr500_nfdsubs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDMULS, model_fr500_nfdmuls, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDDIVS, model_fr500_nfddivs, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDSADS, model_fr500_nfdsads, { { (int) UNIT_FR500_U_FLOAT_DUAL_ARITH, 1, 1 } } },
+  { FRVBF_INSN_NFDCMPS, model_fr500_nfdcmps, { { (int) UNIT_FR500_U_FLOAT_DUAL_COMPARE, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOS, model_fr500_mhsetlos, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIS, model_fr500_mhsethis, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETS, model_fr500_mhdsets, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOH, model_fr500_mhsetloh, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIH, model_fr500_mhsethih, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETH, model_fr500_mhdseth, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAND, model_fr500_mand, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MOR, model_fr500_mor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MXOR, model_fr500_mxor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMAND, model_fr500_cmand, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMOR, model_fr500_cmor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMXOR, model_fr500_cmxor, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MNOT, model_fr500_mnot, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMNOT, model_fr500_cmnot, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MROTLI, model_fr500_mrotli, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MROTRI, model_fr500_mrotri, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MWCUT, model_fr500_mwcut, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MWCUTI, model_fr500_mwcuti, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCUT, model_fr500_mcut, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCUTI, model_fr500_mcuti, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCUTSS, model_fr500_mcutss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCUTSSI, model_fr500_mcutssi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MDCUTSSI, model_fr500_mdcutssi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAVEH, model_fr500_maveh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MSLLHI, model_fr500_msllhi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MSRLHI, model_fr500_msrlhi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MSRAHI, model_fr500_msrahi, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MDROTLI, model_fr500_mdrotli, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLHI, model_fr500_mcplhi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLI, model_fr500_mcpli, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHS, model_fr500_msaths, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MQSATHS, model_fr500_mqsaths, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHU, model_fr500_msathu, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCMPSH, model_fr500_mcmpsh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCMPUH, model_fr500_mcmpuh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MABSHS, model_fr500_mabshs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDHSS, model_fr500_maddhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MADDHUS, model_fr500_maddhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MSUBHSS, model_fr500_msubhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MSUBHUS, model_fr500_msubhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMADDHSS, model_fr500_cmaddhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMADDHUS, model_fr500_cmaddhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHSS, model_fr500_cmsubhss, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHUS, model_fr500_cmsubhus, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MQADDHSS, model_fr500_mqaddhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_MQADDHUS, model_fr500_mqaddhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHSS, model_fr500_mqsubhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHUS, model_fr500_mqsubhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHSS, model_fr500_cmqaddhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHUS, model_fr500_cmqaddhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHSS, model_fr500_cmqsubhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHUS, model_fr500_cmqsubhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_MADDACCS, model_fr500_maddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBACCS, model_fr500_msubaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDADDACCS, model_fr500_mdaddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDSUBACCS, model_fr500_mdsubaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MASACCS, model_fr500_masaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDASACCS, model_fr500_mdasaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULHS, model_fr500_mmulhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MMULHU, model_fr500_mmulhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MMULXHS, model_fr500_mmulxhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MMULXHU, model_fr500_mmulxhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMMULHS, model_fr500_cmmulhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMMULHU, model_fr500_cmmulhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQMULHS, model_fr500_mqmulhs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQMULHU, model_fr500_mqmulhu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHS, model_fr500_mqmulxhs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHU, model_fr500_mqmulxhu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHS, model_fr500_cmqmulhs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHU, model_fr500_cmqmulhu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_MMACHS, model_fr500_mmachs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MMACHU, model_fr500_mmachu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MMRDHS, model_fr500_mmrdhs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MMRDHU, model_fr500_mmrdhu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMMACHS, model_fr500_cmmachs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMMACHU, model_fr500_cmmachu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQMACHS, model_fr500_mqmachs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQMACHU, model_fr500_mqmachu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHS, model_fr500_cmqmachs, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHU, model_fr500_cmqmachu, { { (int) UNIT_FR500_U_MEDIA_QUAD_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQXMACHS, model_fr500_mqxmachs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQXMACXHS, model_fr500_mqxmacxhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACXHS, model_fr500_mqmacxhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXRS, model_fr500_mcpxrs, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCPXRU, model_fr500_mcpxru, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCPXIS, model_fr500_mcpxis, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MCPXIU, model_fr500_mcpxiu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRS, model_fr500_cmcpxrs, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRU, model_fr500_cmcpxru, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIS, model_fr500_cmcpxis, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIU, model_fr500_cmcpxiu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRS, model_fr500_mqcpxrs, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRU, model_fr500_mqcpxru, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIS, model_fr500_mqcpxis, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIU, model_fr500_mqcpxiu, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHW, model_fr500_mexpdhw, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHW, model_fr500_cmexpdhw, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHD, model_fr500_mexpdhd, { { (int) UNIT_FR500_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHD, model_fr500_cmexpdhd, { { (int) UNIT_FR500_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_MPACKH, model_fr500_mpackh, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MDPACKH, model_fr500_mdpackh, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+  { FRVBF_INSN_MUNPACKH, model_fr500_munpackh, { { (int) UNIT_FR500_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_MDUNPACKH, model_fr500_mdunpackh, { { (int) UNIT_FR500_U_MEDIA_DUAL_UNPACK, 1, 1 } } },
+  { FRVBF_INSN_MBTOH, model_fr500_mbtoh, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOH, 1, 1 } } },
+  { FRVBF_INSN_CMBTOH, model_fr500_cmbtoh, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOH, 1, 1 } } },
+  { FRVBF_INSN_MHTOB, model_fr500_mhtob, { { (int) UNIT_FR500_U_MEDIA_DUAL_HTOB, 1, 1 } } },
+  { FRVBF_INSN_CMHTOB, model_fr500_cmhtob, { { (int) UNIT_FR500_U_MEDIA_DUAL_HTOB, 1, 1 } } },
+  { FRVBF_INSN_MBTOHE, model_fr500_mbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } },
+  { FRVBF_INSN_CMBTOHE, model_fr500_cmbtohe, { { (int) UNIT_FR500_U_MEDIA_DUAL_BTOHE, 1, 1 } } },
+  { FRVBF_INSN_MCLRACC, model_fr500_mclracc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MRDACC, model_fr500_mrdacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MRDACCG, model_fr500_mrdaccg, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MWTACC, model_fr500_mwtacc, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MWTACCG, model_fr500_mwtaccg, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+  { FRVBF_INSN_MCOP1, model_fr500_mcop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP2, model_fr500_mcop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNOP, model_fr500_fnop, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+};
+
+/* Model timing data for `tomcat'.  */
+
+static const INSN_TIMING tomcat_timing[] = {
+  { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADD, model_tomcat_add, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUB, model_tomcat_sub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_AND, model_tomcat_and, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_OR, model_tomcat_or, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XOR, model_tomcat_xor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOT, model_tomcat_not, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SDIV, model_tomcat_sdiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NSDIV, model_tomcat_nsdiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UDIV, model_tomcat_udiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NUDIV, model_tomcat_nudiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMUL, model_tomcat_smul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMUL, model_tomcat_umul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLL, model_tomcat_sll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRL, model_tomcat_srl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRA, model_tomcat_sra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SCAN, model_tomcat_scan, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CADD, model_tomcat_cadd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSUB, model_tomcat_csub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CAND, model_tomcat_cand, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COR, model_tomcat_cor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CXOR, model_tomcat_cxor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CNOT, model_tomcat_cnot, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSMUL, model_tomcat_csmul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSDIV, model_tomcat_csdiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CUDIV, model_tomcat_cudiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSLL, model_tomcat_csll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRL, model_tomcat_csrl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRA, model_tomcat_csra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSCAN, model_tomcat_cscan, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDCC, model_tomcat_addcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBCC, model_tomcat_subcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCC, model_tomcat_andcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCC, model_tomcat_orcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCC, model_tomcat_xorcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLCC, model_tomcat_sllcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLCC, model_tomcat_srlcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRACC, model_tomcat_sracc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULCC, model_tomcat_smulcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULCC, model_tomcat_umulcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CADDCC, model_tomcat_caddcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSUBCC, model_tomcat_csubcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSMULCC, model_tomcat_csmulcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CANDCC, model_tomcat_candcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CORCC, model_tomcat_corcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CXORCC, model_tomcat_cxorcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSLLCC, model_tomcat_csllcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRLCC, model_tomcat_csrlcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRACC, model_tomcat_csracc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDX, model_tomcat_addx, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBX, model_tomcat_subx, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXCC, model_tomcat_addxcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXCC, model_tomcat_subxcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDI, model_tomcat_addi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBI, model_tomcat_subi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDI, model_tomcat_andi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORI, model_tomcat_ori, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORI, model_tomcat_xori, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SDIVI, model_tomcat_sdivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NSDIVI, model_tomcat_nsdivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UDIVI, model_tomcat_udivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NUDIVI, model_tomcat_nudivi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULI, model_tomcat_smuli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULI, model_tomcat_umuli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLI, model_tomcat_slli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLI, model_tomcat_srli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRAI, model_tomcat_srai, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SCANI, model_tomcat_scani, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDICC, model_tomcat_addicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBICC, model_tomcat_subicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDICC, model_tomcat_andicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORICC, model_tomcat_oricc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORICC, model_tomcat_xoricc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULICC, model_tomcat_smulicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULICC, model_tomcat_umulicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLICC, model_tomcat_sllicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLICC, model_tomcat_srlicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRAICC, model_tomcat_sraicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXI, model_tomcat_addxi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXI, model_tomcat_subxi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXICC, model_tomcat_addxicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXICC, model_tomcat_subxicc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMPB, model_tomcat_cmpb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMPBA, model_tomcat_cmpba, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETLO, model_tomcat_setlo, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETHI, model_tomcat_sethi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETLOS, model_tomcat_setlos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSB, model_tomcat_ldsb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUB, model_tomcat_ldub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSH, model_tomcat_ldsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUH, model_tomcat_lduh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LD, model_tomcat_ld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBF, model_tomcat_ldbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHF, model_tomcat_ldhf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDF, model_tomcat_ldf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDC, model_tomcat_ldc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSB, model_tomcat_nldsb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUB, model_tomcat_nldub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSH, model_tomcat_nldsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUH, model_tomcat_nlduh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLD, model_tomcat_nld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBF, model_tomcat_nldbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHF, model_tomcat_nldhf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDF, model_tomcat_nldf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDD, model_tomcat_ldd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDF, model_tomcat_lddf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDC, model_tomcat_lddc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDD, model_tomcat_nldd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDF, model_tomcat_nlddf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQ, model_tomcat_ldq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQF, model_tomcat_ldqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQC, model_tomcat_ldqc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQ, model_tomcat_nldq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQF, model_tomcat_nldqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBU, model_tomcat_ldsbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUBU, model_tomcat_ldubu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSHU, model_tomcat_ldshu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUHU, model_tomcat_lduhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDU, model_tomcat_ldu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSBU, model_tomcat_nldsbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBU, model_tomcat_nldubu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHU, model_tomcat_nldshu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHU, model_tomcat_nlduhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDU, model_tomcat_nldu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBFU, model_tomcat_ldbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHFU, model_tomcat_ldhfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDFU, model_tomcat_ldfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDCU, model_tomcat_ldcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFU, model_tomcat_nldbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFU, model_tomcat_nldhfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFU, model_tomcat_nldfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDU, model_tomcat_lddu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDU, model_tomcat_nlddu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDFU, model_tomcat_lddfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDCU, model_tomcat_lddcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFU, model_tomcat_nlddfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQU, model_tomcat_ldqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQU, model_tomcat_nldqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFU, model_tomcat_ldqfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQCU, model_tomcat_ldqcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFU, model_tomcat_nldqfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBI, model_tomcat_ldsbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSHI, model_tomcat_ldshi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDI, model_tomcat_ldi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUBI, model_tomcat_ldubi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUHI, model_tomcat_lduhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBFI, model_tomcat_ldbfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHFI, model_tomcat_ldhfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDFI, model_tomcat_ldfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSBI, model_tomcat_nldsbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBI, model_tomcat_nldubi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHI, model_tomcat_nldshi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHI, model_tomcat_nlduhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDI, model_tomcat_nldi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFI, model_tomcat_nldbfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFI, model_tomcat_nldhfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFI, model_tomcat_nldfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDI, model_tomcat_lddi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDFI, model_tomcat_lddfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDI, model_tomcat_nlddi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFI, model_tomcat_nlddfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQI, model_tomcat_ldqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFI, model_tomcat_ldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQI, model_tomcat_nldqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFI, model_tomcat_nldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STB, model_tomcat_stb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STH, model_tomcat_sth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ST, model_tomcat_st, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBF, model_tomcat_stbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHF, model_tomcat_sthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STF, model_tomcat_stf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STC, model_tomcat_stc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTB, model_tomcat_rstb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTH, model_tomcat_rsth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RST, model_tomcat_rst, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTBF, model_tomcat_rstbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTHF, model_tomcat_rsthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTF, model_tomcat_rstf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STD, model_tomcat_std, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDF, model_tomcat_stdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDC, model_tomcat_stdc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTD, model_tomcat_rstd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTDF, model_tomcat_rstdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQ, model_tomcat_stq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQF, model_tomcat_stqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQC, model_tomcat_stqc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQ, model_tomcat_rstq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQF, model_tomcat_rstqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBU, model_tomcat_stbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHU, model_tomcat_sthu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STU, model_tomcat_stu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBFU, model_tomcat_stbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHFU, model_tomcat_sthfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STFU, model_tomcat_stfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STCU, model_tomcat_stcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDU, model_tomcat_stdu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDFU, model_tomcat_stdfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDCU, model_tomcat_stdcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQU, model_tomcat_stqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFU, model_tomcat_stqfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQCU, model_tomcat_stqcu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSB, model_tomcat_cldsb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUB, model_tomcat_cldub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSH, model_tomcat_cldsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUH, model_tomcat_clduh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLD, model_tomcat_cld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDBF, model_tomcat_cldbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDHF, model_tomcat_cldhf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDF, model_tomcat_cldf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDD, model_tomcat_cldd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDF, model_tomcat_clddf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDQ, model_tomcat_cldq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSBU, model_tomcat_cldsbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUBU, model_tomcat_cldubu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSHU, model_tomcat_cldshu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUHU, model_tomcat_clduhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDU, model_tomcat_cldu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDBFU, model_tomcat_cldbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDHFU, model_tomcat_cldhfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDFU, model_tomcat_cldfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDU, model_tomcat_clddu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDFU, model_tomcat_clddfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDQU, model_tomcat_cldqu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTB, model_tomcat_cstb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTH, model_tomcat_csth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CST, model_tomcat_cst, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBF, model_tomcat_cstbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHF, model_tomcat_csthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTF, model_tomcat_cstf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTD, model_tomcat_cstd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDF, model_tomcat_cstdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTQ, model_tomcat_cstq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBU, model_tomcat_cstbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHU, model_tomcat_csthu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTU, model_tomcat_cstu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBFU, model_tomcat_cstbfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHFU, model_tomcat_csthfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTFU, model_tomcat_cstfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDU, model_tomcat_cstdu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDFU, model_tomcat_cstdfu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBI, model_tomcat_stbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHI, model_tomcat_sthi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STI, model_tomcat_sti, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBFI, model_tomcat_stbfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHFI, model_tomcat_sthfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STFI, model_tomcat_stfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDI, model_tomcat_stdi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDFI, model_tomcat_stdfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQI, model_tomcat_stqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFI, model_tomcat_stqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAP, model_tomcat_swap, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAPI, model_tomcat_swapi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSWAP, model_tomcat_cswap, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGF, model_tomcat_movgf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFG, model_tomcat_movfg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGFD, model_tomcat_movgfd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGD, model_tomcat_movfgd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGFQ, model_tomcat_movgfq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGQ, model_tomcat_movfgq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGF, model_tomcat_cmovgf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVFG, model_tomcat_cmovfg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGFD, model_tomcat_cmovgfd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVFGD, model_tomcat_cmovfgd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGS, model_tomcat_movgs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVSG, model_tomcat_movsg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BRA, model_tomcat_bra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNO, model_tomcat_bno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BEQ, model_tomcat_beq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNE, model_tomcat_bne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLE, model_tomcat_ble, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGT, model_tomcat_bgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLT, model_tomcat_blt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGE, model_tomcat_bge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLS, model_tomcat_bls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BHI, model_tomcat_bhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BC, model_tomcat_bc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNC, model_tomcat_bnc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BN, model_tomcat_bn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BP, model_tomcat_bp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BV, model_tomcat_bv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNV, model_tomcat_bnv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBRA, model_tomcat_fbra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNO, model_tomcat_fbno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNE, model_tomcat_fbne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBEQ, model_tomcat_fbeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLG, model_tomcat_fblg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUE, model_tomcat_fbue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUL, model_tomcat_fbul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGE, model_tomcat_fbge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLT, model_tomcat_fblt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGE, model_tomcat_fbuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUG, model_tomcat_fbug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLE, model_tomcat_fble, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGT, model_tomcat_fbgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULE, model_tomcat_fbule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBU, model_tomcat_fbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBO, model_tomcat_fbo, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCTRLR, model_tomcat_bctrlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BRALR, model_tomcat_bralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNOLR, model_tomcat_bnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BEQLR, model_tomcat_beqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNELR, model_tomcat_bnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLELR, model_tomcat_blelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGTLR, model_tomcat_bgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLTLR, model_tomcat_bltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGELR, model_tomcat_bgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLSLR, model_tomcat_blslr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BHILR, model_tomcat_bhilr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLR, model_tomcat_bclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNCLR, model_tomcat_bnclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNLR, model_tomcat_bnlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BPLR, model_tomcat_bplr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BVLR, model_tomcat_bvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNVLR, model_tomcat_bnvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBRALR, model_tomcat_fbralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNOLR, model_tomcat_fbnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBEQLR, model_tomcat_fbeqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNELR, model_tomcat_fbnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLGLR, model_tomcat_fblglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUELR, model_tomcat_fbuelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULLR, model_tomcat_fbullr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGELR, model_tomcat_fbgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLTLR, model_tomcat_fbltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGELR, model_tomcat_fbugelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGLR, model_tomcat_fbuglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLELR, model_tomcat_fblelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGTLR, model_tomcat_fbgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULELR, model_tomcat_fbulelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULR, model_tomcat_fbulr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBOLR, model_tomcat_fbolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCRALR, model_tomcat_bcralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNOLR, model_tomcat_bcnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCEQLR, model_tomcat_bceqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNELR, model_tomcat_bcnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLELR, model_tomcat_bclelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCGTLR, model_tomcat_bcgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLTLR, model_tomcat_bcltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCGELR, model_tomcat_bcgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLSLR, model_tomcat_bclslr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCHILR, model_tomcat_bchilr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCCLR, model_tomcat_bcclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNCLR, model_tomcat_bcnclr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNLR, model_tomcat_bcnlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCPLR, model_tomcat_bcplr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCVLR, model_tomcat_bcvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNVLR, model_tomcat_bcnvlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBRALR, model_tomcat_fcbralr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBNOLR, model_tomcat_fcbnolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBEQLR, model_tomcat_fcbeqlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBNELR, model_tomcat_fcbnelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLGLR, model_tomcat_fcblglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUELR, model_tomcat_fcbuelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULLR, model_tomcat_fcbullr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBGELR, model_tomcat_fcbgelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLTLR, model_tomcat_fcbltlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUGELR, model_tomcat_fcbugelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUGLR, model_tomcat_fcbuglr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLELR, model_tomcat_fcblelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBGTLR, model_tomcat_fcbgtlr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULELR, model_tomcat_fcbulelr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULR, model_tomcat_fcbulr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBOLR, model_tomcat_fcbolr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_JMPL, model_tomcat_jmpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLL, model_tomcat_calll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_JMPIL, model_tomcat_jmpil, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLIL, model_tomcat_callil, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALL, model_tomcat_call, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RETT, model_tomcat_rett, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_REI, model_tomcat_rei, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TRA, model_tomcat_tra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNO, model_tomcat_tno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TEQ, model_tomcat_teq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNE, model_tomcat_tne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLE, model_tomcat_tle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TGT, model_tomcat_tgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLT, model_tomcat_tlt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TGE, model_tomcat_tge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLS, model_tomcat_tls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_THI, model_tomcat_thi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TC, model_tomcat_tc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNC, model_tomcat_tnc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TN, model_tomcat_tn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TP, model_tomcat_tp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TV, model_tomcat_tv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNV, model_tomcat_tnv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTRA, model_tomcat_ftra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTNO, model_tomcat_ftno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTNE, model_tomcat_ftne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTEQ, model_tomcat_fteq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLG, model_tomcat_ftlg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUE, model_tomcat_ftue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUL, model_tomcat_ftul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTGE, model_tomcat_ftge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLT, model_tomcat_ftlt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUGE, model_tomcat_ftuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUG, model_tomcat_ftug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLE, model_tomcat_ftle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTGT, model_tomcat_ftgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTULE, model_tomcat_ftule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTU, model_tomcat_ftu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTO, model_tomcat_fto, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIRA, model_tomcat_tira, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINO, model_tomcat_tino, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIEQ, model_tomcat_tieq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINE, model_tomcat_tine, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILE, model_tomcat_tile, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIGT, model_tomcat_tigt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILT, model_tomcat_tilt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIGE, model_tomcat_tige, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILS, model_tomcat_tils, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIHI, model_tomcat_tihi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIC, model_tomcat_tic, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINC, model_tomcat_tinc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIN, model_tomcat_tin, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIP, model_tomcat_tip, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIV, model_tomcat_tiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINV, model_tomcat_tinv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIRA, model_tomcat_ftira, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTINO, model_tomcat_ftino, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTINE, model_tomcat_ftine, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIEQ, model_tomcat_ftieq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILG, model_tomcat_ftilg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUE, model_tomcat_ftiue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUL, model_tomcat_ftiul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIGE, model_tomcat_ftige, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILT, model_tomcat_ftilt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUGE, model_tomcat_ftiuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUG, model_tomcat_ftiug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILE, model_tomcat_ftile, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIGT, model_tomcat_ftigt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIULE, model_tomcat_ftiule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIU, model_tomcat_ftiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIO, model_tomcat_ftio, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BREAK, model_tomcat_break, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MTRAP, model_tomcat_mtrap, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCR, model_tomcat_andcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCR, model_tomcat_orcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCR, model_tomcat_xorcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDCR, model_tomcat_nandcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORCR, model_tomcat_norcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDNCR, model_tomcat_andncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORNCR, model_tomcat_orncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDNCR, model_tomcat_nandncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORNCR, model_tomcat_norncr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOTCR, model_tomcat_notcr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKRA, model_tomcat_ckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNO, model_tomcat_ckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKEQ, model_tomcat_ckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNE, model_tomcat_ckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLE, model_tomcat_ckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKGT, model_tomcat_ckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLT, model_tomcat_cklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKGE, model_tomcat_ckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLS, model_tomcat_ckls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKHI, model_tomcat_ckhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKC, model_tomcat_ckc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNC, model_tomcat_cknc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKN, model_tomcat_ckn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKP, model_tomcat_ckp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKV, model_tomcat_ckv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNV, model_tomcat_cknv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKRA, model_tomcat_fckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKNO, model_tomcat_fckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKNE, model_tomcat_fckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKEQ, model_tomcat_fckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLG, model_tomcat_fcklg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUE, model_tomcat_fckue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUL, model_tomcat_fckul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKGE, model_tomcat_fckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLT, model_tomcat_fcklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUGE, model_tomcat_fckuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUG, model_tomcat_fckug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLE, model_tomcat_fckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKGT, model_tomcat_fckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKULE, model_tomcat_fckule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKU, model_tomcat_fcku, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKO, model_tomcat_fcko, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKRA, model_tomcat_cckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNO, model_tomcat_cckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKEQ, model_tomcat_cckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNE, model_tomcat_cckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLE, model_tomcat_cckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKGT, model_tomcat_cckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLT, model_tomcat_ccklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKGE, model_tomcat_cckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLS, model_tomcat_cckls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKHI, model_tomcat_cckhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKC, model_tomcat_cckc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNC, model_tomcat_ccknc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKN, model_tomcat_cckn, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKP, model_tomcat_cckp, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKV, model_tomcat_cckv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNV, model_tomcat_ccknv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKRA, model_tomcat_cfckra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKNO, model_tomcat_cfckno, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKNE, model_tomcat_cfckne, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKEQ, model_tomcat_cfckeq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLG, model_tomcat_cfcklg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUE, model_tomcat_cfckue, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUL, model_tomcat_cfckul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKGE, model_tomcat_cfckge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLT, model_tomcat_cfcklt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUGE, model_tomcat_cfckuge, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUG, model_tomcat_cfckug, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLE, model_tomcat_cfckle, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKGT, model_tomcat_cfckgt, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKULE, model_tomcat_cfckule, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKU, model_tomcat_cfcku, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKO, model_tomcat_cfcko, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CJMPL, model_tomcat_cjmpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCALLL, model_tomcat_ccalll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICI, model_tomcat_ici, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCI, model_tomcat_dci, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICEI, model_tomcat_icei, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCEI, model_tomcat_dcei, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCF, model_tomcat_dcf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCEF, model_tomcat_dcef, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WITLB, model_tomcat_witlb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WDTLB, model_tomcat_wdtlb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ITLBI, model_tomcat_itlbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DTLBI, model_tomcat_dtlbi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICPL, model_tomcat_icpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCPL, model_tomcat_dcpl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICUL, model_tomcat_icul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCUL, model_tomcat_dcul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BAR, model_tomcat_bar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEMBAR, model_tomcat_membar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP1, model_tomcat_cop1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP2, model_tomcat_cop2, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGR, model_tomcat_clrgr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFR, model_tomcat_clrfr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGA, model_tomcat_clrga, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFA, model_tomcat_clrfa, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGR, model_tomcat_commitgr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFR, model_tomcat_commitfr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGA, model_tomcat_commitga, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFA, model_tomcat_commitfa, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOS, model_tomcat_fitos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSTOI, model_tomcat_fstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOD, model_tomcat_fitod, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDTOI, model_tomcat_fdtoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDITOS, model_tomcat_fditos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSTOI, model_tomcat_fdstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDITOS, model_tomcat_nfditos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSTOI, model_tomcat_nfdstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFITOS, model_tomcat_cfitos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSTOI, model_tomcat_cfstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFITOS, model_tomcat_nfitos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSTOI, model_tomcat_nfstoi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVS, model_tomcat_fmovs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVD, model_tomcat_fmovd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMOVS, model_tomcat_fdmovs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMOVS, model_tomcat_cfmovs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGS, model_tomcat_fnegs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGD, model_tomcat_fnegd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDNEGS, model_tomcat_fdnegs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFNEGS, model_tomcat_cfnegs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSS, model_tomcat_fabss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSD, model_tomcat_fabsd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDABSS, model_tomcat_fdabss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFABSS, model_tomcat_cfabss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTS, model_tomcat_fsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSQRTS, model_tomcat_fdsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSQRTS, model_tomcat_nfdsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTD, model_tomcat_fsqrtd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSQRTS, model_tomcat_cfsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSQRTS, model_tomcat_nfsqrts, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDS, model_tomcat_fadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBS, model_tomcat_fsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULS, model_tomcat_fmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVS, model_tomcat_fdivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDD, model_tomcat_faddd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBD, model_tomcat_fsubd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULD, model_tomcat_fmuld, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVD, model_tomcat_fdivd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFADDS, model_tomcat_cfadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSUBS, model_tomcat_cfsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMULS, model_tomcat_cfmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFDIVS, model_tomcat_cfdivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFADDS, model_tomcat_nfadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSUBS, model_tomcat_nfsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMULS, model_tomcat_nfmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDIVS, model_tomcat_nfdivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPS, model_tomcat_fcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPD, model_tomcat_fcmpd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCMPS, model_tomcat_cfcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDCMPS, model_tomcat_fdcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDS, model_tomcat_fmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBS, model_tomcat_fmsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDD, model_tomcat_fmaddd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBD, model_tomcat_fmsubd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMADDS, model_tomcat_fdmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMADDS, model_tomcat_nfdmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMADDS, model_tomcat_cfmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSUBS, model_tomcat_cfmsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMADDS, model_tomcat_nfmadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSUBS, model_tomcat_nfmsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAS, model_tomcat_fmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSS, model_tomcat_fmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMAS, model_tomcat_fdmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMSS, model_tomcat_fdmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMAS, model_tomcat_nfdmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMSS, model_tomcat_nfdmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMAS, model_tomcat_cfmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSS, model_tomcat_cfmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAD, model_tomcat_fmad, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSD, model_tomcat_fmsd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMAS, model_tomcat_nfmas, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSS, model_tomcat_nfmss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDADDS, model_tomcat_fdadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSUBS, model_tomcat_fdsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULS, model_tomcat_fdmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDDIVS, model_tomcat_fddivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSADS, model_tomcat_fdsads, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULCS, model_tomcat_fdmulcs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULCS, model_tomcat_nfdmulcs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDADDS, model_tomcat_nfdadds, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSUBS, model_tomcat_nfdsubs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULS, model_tomcat_nfdmuls, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDDIVS, model_tomcat_nfddivs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSADS, model_tomcat_nfdsads, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDCMPS, model_tomcat_nfdcmps, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOS, model_tomcat_mhsetlos, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIS, model_tomcat_mhsethis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETS, model_tomcat_mhdsets, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOH, model_tomcat_mhsetloh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIH, model_tomcat_mhsethih, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETH, model_tomcat_mhdseth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAND, model_tomcat_mand, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOR, model_tomcat_mor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MXOR, model_tomcat_mxor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMAND, model_tomcat_cmand, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOR, model_tomcat_cmor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMXOR, model_tomcat_cmxor, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MNOT, model_tomcat_mnot, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMNOT, model_tomcat_cmnot, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MROTLI, model_tomcat_mrotli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MROTRI, model_tomcat_mrotri, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWCUT, model_tomcat_mwcut, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWCUTI, model_tomcat_mwcuti, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUT, model_tomcat_mcut, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTI, model_tomcat_mcuti, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTSS, model_tomcat_mcutss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTSSI, model_tomcat_mcutssi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDCUTSSI, model_tomcat_mdcutssi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAVEH, model_tomcat_maveh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSLLHI, model_tomcat_msllhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSRLHI, model_tomcat_msrlhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSRAHI, model_tomcat_msrahi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDROTLI, model_tomcat_mdrotli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLHI, model_tomcat_mcplhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLI, model_tomcat_mcpli, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHS, model_tomcat_msaths, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSATHS, model_tomcat_mqsaths, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHU, model_tomcat_msathu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCMPSH, model_tomcat_mcmpsh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCMPUH, model_tomcat_mcmpuh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MABSHS, model_tomcat_mabshs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDHSS, model_tomcat_maddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDHUS, model_tomcat_maddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBHSS, model_tomcat_msubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBHUS, model_tomcat_msubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMADDHSS, model_tomcat_cmaddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMADDHUS, model_tomcat_cmaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHSS, model_tomcat_cmsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHUS, model_tomcat_cmsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQADDHSS, model_tomcat_mqaddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQADDHUS, model_tomcat_mqaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHSS, model_tomcat_mqsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHUS, model_tomcat_mqsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHSS, model_tomcat_cmqaddhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHUS, model_tomcat_cmqaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHSS, model_tomcat_cmqsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHUS, model_tomcat_cmqsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDACCS, model_tomcat_maddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBACCS, model_tomcat_msubaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDADDACCS, model_tomcat_mdaddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDSUBACCS, model_tomcat_mdsubaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MASACCS, model_tomcat_masaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDASACCS, model_tomcat_mdasaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULHS, model_tomcat_mmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULHU, model_tomcat_mmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULXHS, model_tomcat_mmulxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULXHU, model_tomcat_mmulxhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMULHS, model_tomcat_cmmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMULHU, model_tomcat_cmmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULHS, model_tomcat_mqmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULHU, model_tomcat_mqmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHS, model_tomcat_mqmulxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHU, model_tomcat_mqmulxhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHS, model_tomcat_cmqmulhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHU, model_tomcat_cmqmulhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMACHS, model_tomcat_mmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMACHU, model_tomcat_mmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMRDHS, model_tomcat_mmrdhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMRDHU, model_tomcat_mmrdhu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMACHS, model_tomcat_cmmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMACHU, model_tomcat_cmmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACHS, model_tomcat_mqmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACHU, model_tomcat_mqmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHS, model_tomcat_cmqmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHU, model_tomcat_cmqmachu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQXMACHS, model_tomcat_mqxmachs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQXMACXHS, model_tomcat_mqxmacxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACXHS, model_tomcat_mqmacxhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXRS, model_tomcat_mcpxrs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXRU, model_tomcat_mcpxru, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXIS, model_tomcat_mcpxis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXIU, model_tomcat_mcpxiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRS, model_tomcat_cmcpxrs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRU, model_tomcat_cmcpxru, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIS, model_tomcat_cmcpxis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIU, model_tomcat_cmcpxiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRS, model_tomcat_mqcpxrs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRU, model_tomcat_mqcpxru, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIS, model_tomcat_mqcpxis, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIU, model_tomcat_mqcpxiu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHW, model_tomcat_mexpdhw, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHW, model_tomcat_cmexpdhw, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHD, model_tomcat_mexpdhd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHD, model_tomcat_cmexpdhd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MPACKH, model_tomcat_mpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDPACKH, model_tomcat_mdpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MUNPACKH, model_tomcat_munpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDUNPACKH, model_tomcat_mdunpackh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MBTOH, model_tomcat_mbtoh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMBTOH, model_tomcat_cmbtoh, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHTOB, model_tomcat_mhtob, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMHTOB, model_tomcat_cmhtob, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MBTOHE, model_tomcat_mbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMBTOHE, model_tomcat_cmbtohe, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCLRACC, model_tomcat_mclracc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MRDACC, model_tomcat_mrdacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MRDACCG, model_tomcat_mrdaccg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWTACC, model_tomcat_mwtacc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWTACCG, model_tomcat_mwtaccg, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP1, model_tomcat_mcop1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP2, model_tomcat_mcop2, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNOP, model_tomcat_fnop, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+};
+
+/* Model timing data for `fr400'.  */
+
+static const INSN_TIMING fr400_timing[] = {
+  { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADD, model_fr400_add, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUB, model_fr400_sub, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_AND, model_fr400_and, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_OR, model_fr400_or, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XOR, model_fr400_xor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_NOT, model_fr400_not, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SDIV, model_fr400_sdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_UDIV, model_fr400_udiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_SLL, model_fr400_sll, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRL, model_fr400_srl, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRA, model_fr400_sra, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SCAN, model_fr400_scan, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CADD, model_fr400_cadd, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSUB, model_fr400_csub, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CAND, model_fr400_cand, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_COR, model_fr400_cor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CXOR, model_fr400_cxor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CNOT, model_fr400_cnot, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSMUL, model_fr400_csmul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_CSDIV, model_fr400_csdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_CUDIV, model_fr400_cudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_CSLL, model_fr400_csll, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRL, model_fr400_csrl, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRA, model_fr400_csra, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSCAN, model_fr400_cscan, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDCC, model_fr400_addcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBCC, model_fr400_subcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ANDCC, model_fr400_andcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ORCC, model_fr400_orcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XORCC, model_fr400_xorcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SLLCC, model_fr400_sllcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRLCC, model_fr400_srlcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRACC, model_fr400_sracc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SMULCC, model_fr400_smulcc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMULCC, model_fr400_umulcc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_CADDCC, model_fr400_caddcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSUBCC, model_fr400_csubcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSMULCC, model_fr400_csmulcc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_CANDCC, model_fr400_candcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CORCC, model_fr400_corcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CXORCC, model_fr400_cxorcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSLLCC, model_fr400_csllcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRLCC, model_fr400_csrlcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CSRACC, model_fr400_csracc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDX, model_fr400_addx, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBX, model_fr400_subx, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDXCC, model_fr400_addxcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBXCC, model_fr400_subxcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDI, model_fr400_addi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBI, model_fr400_subi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ANDI, model_fr400_andi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ORI, model_fr400_ori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XORI, model_fr400_xori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SDIVI, model_fr400_sdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_UDIVI, model_fr400_udivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
+  { FRVBF_INSN_SMULI, model_fr400_smuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMULI, model_fr400_umuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_SLLI, model_fr400_slli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRLI, model_fr400_srli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRAI, model_fr400_srai, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SCANI, model_fr400_scani, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDICC, model_fr400_addicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBICC, model_fr400_subicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ANDICC, model_fr400_andicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ORICC, model_fr400_oricc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_XORICC, model_fr400_xoricc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SMULICC, model_fr400_smulicc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_UMULICC, model_fr400_umulicc, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+  { FRVBF_INSN_SLLICC, model_fr400_sllicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRLICC, model_fr400_srlicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SRAICC, model_fr400_sraicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDXI, model_fr400_addxi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBXI, model_fr400_subxi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_ADDXICC, model_fr400_addxicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SUBXICC, model_fr400_subxicc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CMPB, model_fr400_cmpb, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_CMPBA, model_fr400_cmpba, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_SETLO, model_fr400_setlo, { { (int) UNIT_FR400_U_SET_HILO, 1, 1 } } },
+  { FRVBF_INSN_SETHI, model_fr400_sethi, { { (int) UNIT_FR400_U_SET_HILO, 1, 1 } } },
+  { FRVBF_INSN_SETLOS, model_fr400_setlos, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+  { FRVBF_INSN_LDSB, model_fr400_ldsb, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUB, model_fr400_ldub, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSH, model_fr400_ldsh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUH, model_fr400_lduh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LD, model_fr400_ld, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDBF, model_fr400_ldbf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDHF, model_fr400_ldhf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDF, model_fr400_ldf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDC, model_fr400_ldc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSB, model_fr400_nldsb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUB, model_fr400_nldub, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSH, model_fr400_nldsh, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUH, model_fr400_nlduh, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLD, model_fr400_nld, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBF, model_fr400_nldbf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHF, model_fr400_nldhf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDF, model_fr400_nldf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDD, model_fr400_ldd, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDF, model_fr400_lddf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDC, model_fr400_lddc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDD, model_fr400_nldd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDF, model_fr400_nlddf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQ, model_fr400_ldq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQF, model_fr400_ldqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQC, model_fr400_ldqc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQ, model_fr400_nldq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQF, model_fr400_nldqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBU, model_fr400_ldsbu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUBU, model_fr400_ldubu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSHU, model_fr400_ldshu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUHU, model_fr400_lduhu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDU, model_fr400_ldu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDSBU, model_fr400_nldsbu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBU, model_fr400_nldubu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHU, model_fr400_nldshu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHU, model_fr400_nlduhu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDU, model_fr400_nldu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBFU, model_fr400_ldbfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDHFU, model_fr400_ldhfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDFU, model_fr400_ldfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDCU, model_fr400_ldcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFU, model_fr400_nldbfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFU, model_fr400_nldhfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFU, model_fr400_nldfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDU, model_fr400_lddu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDDU, model_fr400_nlddu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDFU, model_fr400_lddfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDCU, model_fr400_lddcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFU, model_fr400_nlddfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQU, model_fr400_ldqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQU, model_fr400_nldqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFU, model_fr400_ldqfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQCU, model_fr400_ldqcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFU, model_fr400_nldqfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBI, model_fr400_ldsbi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDSHI, model_fr400_ldshi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDI, model_fr400_ldi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUBI, model_fr400_ldubi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDUHI, model_fr400_lduhi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDBFI, model_fr400_ldbfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDHFI, model_fr400_ldhfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDFI, model_fr400_ldfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDSBI, model_fr400_nldsbi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBI, model_fr400_nldubi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHI, model_fr400_nldshi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHI, model_fr400_nlduhi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDI, model_fr400_nldi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFI, model_fr400_nldbfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFI, model_fr400_nldhfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFI, model_fr400_nldfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDI, model_fr400_lddi, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_LDDFI, model_fr400_lddfi, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_NLDDI, model_fr400_nlddi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFI, model_fr400_nlddfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQI, model_fr400_ldqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFI, model_fr400_ldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQI, model_fr400_nldqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFI, model_fr400_nldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STB, model_fr400_stb, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STH, model_fr400_sth, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_ST, model_fr400_st, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBF, model_fr400_stbf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHF, model_fr400_sthf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STF, model_fr400_stf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STC, model_fr400_stc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTB, model_fr400_rstb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTH, model_fr400_rsth, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RST, model_fr400_rst, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTBF, model_fr400_rstbf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTHF, model_fr400_rsthf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTF, model_fr400_rstf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STD, model_fr400_std, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDF, model_fr400_stdf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDC, model_fr400_stdc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTD, model_fr400_rstd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTDF, model_fr400_rstdf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQ, model_fr400_stq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQF, model_fr400_stqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQC, model_fr400_stqc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQ, model_fr400_rstq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQF, model_fr400_rstqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBU, model_fr400_stbu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHU, model_fr400_sthu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STU, model_fr400_stu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBFU, model_fr400_stbfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHFU, model_fr400_sthfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STFU, model_fr400_stfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STCU, model_fr400_stcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDU, model_fr400_stdu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDFU, model_fr400_stdfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDCU, model_fr400_stdcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQU, model_fr400_stqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFU, model_fr400_stqfu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQCU, model_fr400_stqcu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSB, model_fr400_cldsb, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUB, model_fr400_cldub, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDSH, model_fr400_cldsh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUH, model_fr400_clduh, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLD, model_fr400_cld, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDBF, model_fr400_cldbf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDHF, model_fr400_cldhf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDF, model_fr400_cldf, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDD, model_fr400_cldd, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDDF, model_fr400_clddf, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDQ, model_fr400_cldq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSBU, model_fr400_cldsbu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUBU, model_fr400_cldubu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDSHU, model_fr400_cldshu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDUHU, model_fr400_clduhu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDU, model_fr400_cldu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDBFU, model_fr400_cldbfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDHFU, model_fr400_cldhfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDFU, model_fr400_cldfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDDU, model_fr400_clddu, { { (int) UNIT_FR400_U_GR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDDFU, model_fr400_clddfu, { { (int) UNIT_FR400_U_FR_LOAD, 1, 1 } } },
+  { FRVBF_INSN_CLDQU, model_fr400_cldqu, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTB, model_fr400_cstb, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTH, model_fr400_csth, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CST, model_fr400_cst, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTBF, model_fr400_cstbf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTHF, model_fr400_csthf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTF, model_fr400_cstf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTD, model_fr400_cstd, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTDF, model_fr400_cstdf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTQ, model_fr400_cstq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBU, model_fr400_cstbu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTHU, model_fr400_csthu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTU, model_fr400_cstu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTBFU, model_fr400_cstbfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTHFU, model_fr400_csthfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTFU, model_fr400_cstfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTDU, model_fr400_cstdu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_CSTDFU, model_fr400_cstdfu, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBI, model_fr400_stbi, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHI, model_fr400_sthi, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STI, model_fr400_sti, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STBFI, model_fr400_stbfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STHFI, model_fr400_sthfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STFI, model_fr400_stfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDI, model_fr400_stdi, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STDFI, model_fr400_stdfi, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
+  { FRVBF_INSN_STQI, model_fr400_stqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFI, model_fr400_stqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAP, model_fr400_swap, { { (int) UNIT_FR400_U_SWAP, 1, 1 } } },
+  { FRVBF_INSN_SWAPI, model_fr400_swapi, { { (int) UNIT_FR400_U_SWAP, 1, 1 } } },
+  { FRVBF_INSN_CSWAP, model_fr400_cswap, { { (int) UNIT_FR400_U_SWAP, 1, 1 } } },
+  { FRVBF_INSN_MOVGF, model_fr400_movgf, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_MOVFG, model_fr400_movfg, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_MOVGFD, model_fr400_movgfd, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_MOVFGD, model_fr400_movfgd, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_MOVGFQ, model_fr400_movgfq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGQ, model_fr400_movfgq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGF, model_fr400_cmovgf, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_CMOVFG, model_fr400_cmovfg, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_CMOVGFD, model_fr400_cmovgfd, { { (int) UNIT_FR400_U_GR2FR, 1, 1 } } },
+  { FRVBF_INSN_CMOVFGD, model_fr400_cmovfgd, { { (int) UNIT_FR400_U_FR2GR, 1, 1 } } },
+  { FRVBF_INSN_MOVGS, model_fr400_movgs, { { (int) UNIT_FR400_U_GR2SPR, 1, 1 } } },
+  { FRVBF_INSN_MOVSG, model_fr400_movsg, { { (int) UNIT_FR400_U_SPR2GR, 1, 1 } } },
+  { FRVBF_INSN_BRA, model_fr400_bra, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNO, model_fr400_bno, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BEQ, model_fr400_beq, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNE, model_fr400_bne, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLE, model_fr400_ble, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGT, model_fr400_bgt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLT, model_fr400_blt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGE, model_fr400_bge, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLS, model_fr400_bls, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BHI, model_fr400_bhi, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BC, model_fr400_bc, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNC, model_fr400_bnc, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BN, model_fr400_bn, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BP, model_fr400_bp, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BV, model_fr400_bv, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNV, model_fr400_bnv, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBRA, model_fr400_fbra, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNO, model_fr400_fbno, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNE, model_fr400_fbne, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBEQ, model_fr400_fbeq, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLG, model_fr400_fblg, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUE, model_fr400_fbue, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUL, model_fr400_fbul, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGE, model_fr400_fbge, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLT, model_fr400_fblt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUGE, model_fr400_fbuge, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUG, model_fr400_fbug, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLE, model_fr400_fble, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGT, model_fr400_fbgt, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULE, model_fr400_fbule, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBU, model_fr400_fbu, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBO, model_fr400_fbo, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCTRLR, model_fr400_bctrlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BRALR, model_fr400_bralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNOLR, model_fr400_bnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BEQLR, model_fr400_beqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNELR, model_fr400_bnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLELR, model_fr400_blelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGTLR, model_fr400_bgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLTLR, model_fr400_bltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BGELR, model_fr400_bgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BLSLR, model_fr400_blslr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BHILR, model_fr400_bhilr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLR, model_fr400_bclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNCLR, model_fr400_bnclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNLR, model_fr400_bnlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BPLR, model_fr400_bplr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BVLR, model_fr400_bvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BNVLR, model_fr400_bnvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBRALR, model_fr400_fbralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNOLR, model_fr400_fbnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBEQLR, model_fr400_fbeqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBNELR, model_fr400_fbnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLGLR, model_fr400_fblglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUELR, model_fr400_fbuelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULLR, model_fr400_fbullr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGELR, model_fr400_fbgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLTLR, model_fr400_fbltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUGELR, model_fr400_fbugelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBUGLR, model_fr400_fbuglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBLELR, model_fr400_fblelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBGTLR, model_fr400_fbgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULELR, model_fr400_fbulelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBULR, model_fr400_fbulr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FBOLR, model_fr400_fbolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCRALR, model_fr400_bcralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNOLR, model_fr400_bcnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCEQLR, model_fr400_bceqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNELR, model_fr400_bcnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLELR, model_fr400_bclelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCGTLR, model_fr400_bcgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLTLR, model_fr400_bcltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCGELR, model_fr400_bcgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCLSLR, model_fr400_bclslr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCHILR, model_fr400_bchilr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCCLR, model_fr400_bcclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNCLR, model_fr400_bcnclr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNLR, model_fr400_bcnlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCPLR, model_fr400_bcplr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCVLR, model_fr400_bcvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_BCNVLR, model_fr400_bcnvlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBRALR, model_fr400_fcbralr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBNOLR, model_fr400_fcbnolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBEQLR, model_fr400_fcbeqlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBNELR, model_fr400_fcbnelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBLGLR, model_fr400_fcblglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBUELR, model_fr400_fcbuelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBULLR, model_fr400_fcbullr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBGELR, model_fr400_fcbgelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBLTLR, model_fr400_fcbltlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBUGELR, model_fr400_fcbugelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBUGLR, model_fr400_fcbuglr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBLELR, model_fr400_fcblelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBGTLR, model_fr400_fcbgtlr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBULELR, model_fr400_fcbulelr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBULR, model_fr400_fcbulr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_FCBOLR, model_fr400_fcbolr, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_JMPL, model_fr400_jmpl, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CALLL, model_fr400_calll, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_JMPIL, model_fr400_jmpil, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CALLIL, model_fr400_callil, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CALL, model_fr400_call, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_RETT, model_fr400_rett, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_REI, model_fr400_rei, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TRA, model_fr400_tra, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNO, model_fr400_tno, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TEQ, model_fr400_teq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNE, model_fr400_tne, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TLE, model_fr400_tle, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TGT, model_fr400_tgt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TLT, model_fr400_tlt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TGE, model_fr400_tge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TLS, model_fr400_tls, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_THI, model_fr400_thi, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TC, model_fr400_tc, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNC, model_fr400_tnc, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TN, model_fr400_tn, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TP, model_fr400_tp, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TV, model_fr400_tv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TNV, model_fr400_tnv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTRA, model_fr400_ftra, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTNO, model_fr400_ftno, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTNE, model_fr400_ftne, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTEQ, model_fr400_fteq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTLG, model_fr400_ftlg, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUE, model_fr400_ftue, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUL, model_fr400_ftul, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTGE, model_fr400_ftge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTLT, model_fr400_ftlt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUGE, model_fr400_ftuge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTUG, model_fr400_ftug, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTLE, model_fr400_ftle, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTGT, model_fr400_ftgt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTULE, model_fr400_ftule, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTU, model_fr400_ftu, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTO, model_fr400_fto, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIRA, model_fr400_tira, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINO, model_fr400_tino, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIEQ, model_fr400_tieq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINE, model_fr400_tine, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TILE, model_fr400_tile, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIGT, model_fr400_tigt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TILT, model_fr400_tilt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIGE, model_fr400_tige, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TILS, model_fr400_tils, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIHI, model_fr400_tihi, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIC, model_fr400_tic, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINC, model_fr400_tinc, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIN, model_fr400_tin, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIP, model_fr400_tip, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TIV, model_fr400_tiv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_TINV, model_fr400_tinv, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIRA, model_fr400_ftira, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTINO, model_fr400_ftino, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTINE, model_fr400_ftine, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIEQ, model_fr400_ftieq, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTILG, model_fr400_ftilg, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUE, model_fr400_ftiue, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUL, model_fr400_ftiul, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIGE, model_fr400_ftige, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTILT, model_fr400_ftilt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUGE, model_fr400_ftiuge, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIUG, model_fr400_ftiug, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTILE, model_fr400_ftile, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIGT, model_fr400_ftigt, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIULE, model_fr400_ftiule, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIU, model_fr400_ftiu, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_FTIO, model_fr400_ftio, { { (int) UNIT_FR400_U_TRAP, 1, 1 } } },
+  { FRVBF_INSN_BREAK, model_fr400_break, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MTRAP, model_fr400_mtrap, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCR, model_fr400_andcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCR, model_fr400_orcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCR, model_fr400_xorcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDCR, model_fr400_nandcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORCR, model_fr400_norcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDNCR, model_fr400_andncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORNCR, model_fr400_orncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDNCR, model_fr400_nandncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORNCR, model_fr400_norncr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOTCR, model_fr400_notcr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKRA, model_fr400_ckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNO, model_fr400_ckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKEQ, model_fr400_ckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNE, model_fr400_ckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKLE, model_fr400_ckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKGT, model_fr400_ckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKLT, model_fr400_cklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKGE, model_fr400_ckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKLS, model_fr400_ckls, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKHI, model_fr400_ckhi, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKC, model_fr400_ckc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNC, model_fr400_cknc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKN, model_fr400_ckn, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKP, model_fr400_ckp, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKV, model_fr400_ckv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CKNV, model_fr400_cknv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKRA, model_fr400_fckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKNO, model_fr400_fckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKNE, model_fr400_fckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKEQ, model_fr400_fckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKLG, model_fr400_fcklg, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUE, model_fr400_fckue, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUL, model_fr400_fckul, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKGE, model_fr400_fckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKLT, model_fr400_fcklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUGE, model_fr400_fckuge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKUG, model_fr400_fckug, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKLE, model_fr400_fckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKGT, model_fr400_fckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKULE, model_fr400_fckule, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKU, model_fr400_fcku, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_FCKO, model_fr400_fcko, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKRA, model_fr400_cckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNO, model_fr400_cckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKEQ, model_fr400_cckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNE, model_fr400_cckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKLE, model_fr400_cckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKGT, model_fr400_cckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKLT, model_fr400_ccklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKGE, model_fr400_cckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKLS, model_fr400_cckls, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKHI, model_fr400_cckhi, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKC, model_fr400_cckc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNC, model_fr400_ccknc, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKN, model_fr400_cckn, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKP, model_fr400_cckp, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKV, model_fr400_cckv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CCKNV, model_fr400_ccknv, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKRA, model_fr400_cfckra, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKNO, model_fr400_cfckno, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKNE, model_fr400_cfckne, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKEQ, model_fr400_cfckeq, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKLG, model_fr400_cfcklg, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUE, model_fr400_cfckue, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUL, model_fr400_cfckul, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKGE, model_fr400_cfckge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKLT, model_fr400_cfcklt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUGE, model_fr400_cfckuge, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKUG, model_fr400_cfckug, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKLE, model_fr400_cfckle, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKGT, model_fr400_cfckgt, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKULE, model_fr400_cfckule, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKU, model_fr400_cfcku, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CFCKO, model_fr400_cfcko, { { (int) UNIT_FR400_U_CHECK, 1, 1 } } },
+  { FRVBF_INSN_CJMPL, model_fr400_cjmpl, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_CCALLL, model_fr400_ccalll, { { (int) UNIT_FR400_U_BRANCH, 1, 1 } } },
+  { FRVBF_INSN_ICI, model_fr400_ici, { { (int) UNIT_FR400_U_ICI, 1, 1 } } },
+  { FRVBF_INSN_DCI, model_fr400_dci, { { (int) UNIT_FR400_U_DCI, 1, 1 } } },
+  { FRVBF_INSN_ICEI, model_fr400_icei, { { (int) UNIT_FR400_U_ICI, 1, 1 } } },
+  { FRVBF_INSN_DCEI, model_fr400_dcei, { { (int) UNIT_FR400_U_DCI, 1, 1 } } },
+  { FRVBF_INSN_DCF, model_fr400_dcf, { { (int) UNIT_FR400_U_DCF, 1, 1 } } },
+  { FRVBF_INSN_DCEF, model_fr400_dcef, { { (int) UNIT_FR400_U_DCF, 1, 1 } } },
+  { FRVBF_INSN_WITLB, model_fr400_witlb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WDTLB, model_fr400_wdtlb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ITLBI, model_fr400_itlbi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DTLBI, model_fr400_dtlbi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICPL, model_fr400_icpl, { { (int) UNIT_FR400_U_ICPL, 1, 1 } } },
+  { FRVBF_INSN_DCPL, model_fr400_dcpl, { { (int) UNIT_FR400_U_DCPL, 1, 1 } } },
+  { FRVBF_INSN_ICUL, model_fr400_icul, { { (int) UNIT_FR400_U_ICUL, 1, 1 } } },
+  { FRVBF_INSN_DCUL, model_fr400_dcul, { { (int) UNIT_FR400_U_DCUL, 1, 1 } } },
+  { FRVBF_INSN_BAR, model_fr400_bar, { { (int) UNIT_FR400_U_BARRIER, 1, 1 } } },
+  { FRVBF_INSN_MEMBAR, model_fr400_membar, { { (int) UNIT_FR400_U_MEMBAR, 1, 1 } } },
+  { FRVBF_INSN_COP1, model_fr400_cop1, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP2, model_fr400_cop2, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGR, model_fr400_clrgr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFR, model_fr400_clrfr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGA, model_fr400_clrga, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFA, model_fr400_clrfa, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGR, model_fr400_commitgr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFR, model_fr400_commitfr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGA, model_fr400_commitga, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFA, model_fr400_commitfa, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOS, model_fr400_fitos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSTOI, model_fr400_fstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOD, model_fr400_fitod, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDTOI, model_fr400_fdtoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDITOS, model_fr400_fditos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSTOI, model_fr400_fdstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDITOS, model_fr400_nfditos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSTOI, model_fr400_nfdstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFITOS, model_fr400_cfitos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSTOI, model_fr400_cfstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFITOS, model_fr400_nfitos, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSTOI, model_fr400_nfstoi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVS, model_fr400_fmovs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVD, model_fr400_fmovd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMOVS, model_fr400_fdmovs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMOVS, model_fr400_cfmovs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGS, model_fr400_fnegs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGD, model_fr400_fnegd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDNEGS, model_fr400_fdnegs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFNEGS, model_fr400_cfnegs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSS, model_fr400_fabss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSD, model_fr400_fabsd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDABSS, model_fr400_fdabss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFABSS, model_fr400_cfabss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTS, model_fr400_fsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSQRTS, model_fr400_fdsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSQRTS, model_fr400_nfdsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTD, model_fr400_fsqrtd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSQRTS, model_fr400_cfsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSQRTS, model_fr400_nfsqrts, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDS, model_fr400_fadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBS, model_fr400_fsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULS, model_fr400_fmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVS, model_fr400_fdivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDD, model_fr400_faddd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBD, model_fr400_fsubd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULD, model_fr400_fmuld, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVD, model_fr400_fdivd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFADDS, model_fr400_cfadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSUBS, model_fr400_cfsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMULS, model_fr400_cfmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFDIVS, model_fr400_cfdivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFADDS, model_fr400_nfadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSUBS, model_fr400_nfsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMULS, model_fr400_nfmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDIVS, model_fr400_nfdivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPS, model_fr400_fcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPD, model_fr400_fcmpd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCMPS, model_fr400_cfcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDCMPS, model_fr400_fdcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDS, model_fr400_fmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBS, model_fr400_fmsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDD, model_fr400_fmaddd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBD, model_fr400_fmsubd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMADDS, model_fr400_fdmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMADDS, model_fr400_nfdmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMADDS, model_fr400_cfmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSUBS, model_fr400_cfmsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMADDS, model_fr400_nfmadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSUBS, model_fr400_nfmsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAS, model_fr400_fmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSS, model_fr400_fmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMAS, model_fr400_fdmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMSS, model_fr400_fdmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMAS, model_fr400_nfdmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMSS, model_fr400_nfdmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMAS, model_fr400_cfmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSS, model_fr400_cfmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAD, model_fr400_fmad, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSD, model_fr400_fmsd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMAS, model_fr400_nfmas, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSS, model_fr400_nfmss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDADDS, model_fr400_fdadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSUBS, model_fr400_fdsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULS, model_fr400_fdmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDDIVS, model_fr400_fddivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSADS, model_fr400_fdsads, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULCS, model_fr400_fdmulcs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULCS, model_fr400_nfdmulcs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDADDS, model_fr400_nfdadds, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSUBS, model_fr400_nfdsubs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULS, model_fr400_nfdmuls, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDDIVS, model_fr400_nfddivs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSADS, model_fr400_nfdsads, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDCMPS, model_fr400_nfdcmps, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOS, model_fr400_mhsetlos, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIS, model_fr400_mhsethis, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } },
+  { FRVBF_INSN_MHDSETS, model_fr400_mhdsets, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOH, model_fr400_mhsetloh, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIH, model_fr400_mhsethih, { { (int) UNIT_FR400_U_MEDIA_HILO, 1, 1 } } },
+  { FRVBF_INSN_MHDSETH, model_fr400_mhdseth, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MAND, model_fr400_mand, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MOR, model_fr400_mor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MXOR, model_fr400_mxor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMAND, model_fr400_cmand, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMOR, model_fr400_cmor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMXOR, model_fr400_cmxor, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MNOT, model_fr400_mnot, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMNOT, model_fr400_cmnot, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MROTLI, model_fr400_mrotli, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MROTRI, model_fr400_mrotri, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MWCUT, model_fr400_mwcut, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MWCUTI, model_fr400_mwcuti, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MCUT, model_fr400_mcut, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
+  { FRVBF_INSN_MCUTI, model_fr400_mcuti, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
+  { FRVBF_INSN_MCUTSS, model_fr400_mcutss, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
+  { FRVBF_INSN_MCUTSSI, model_fr400_mcutssi, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
+  { FRVBF_INSN_MDCUTSSI, model_fr400_mdcutssi, { { (int) UNIT_FR400_U_MEDIA_4_ACC_DUAL, 1, 1 } } },
+  { FRVBF_INSN_MAVEH, model_fr400_maveh, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MSLLHI, model_fr400_msllhi, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MSRLHI, model_fr400_msrlhi, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MSRAHI, model_fr400_msrahi, { { (int) UNIT_FR400_U_MEDIA_6, 1, 1 } } },
+  { FRVBF_INSN_MDROTLI, model_fr400_mdrotli, { { (int) UNIT_FR400_U_MEDIA_3_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MCPLHI, model_fr400_mcplhi, { { (int) UNIT_FR400_U_MEDIA_3_DUAL, 1, 1 } } },
+  { FRVBF_INSN_MCPLI, model_fr400_mcpli, { { (int) UNIT_FR400_U_MEDIA_3_DUAL, 1, 1 } } },
+  { FRVBF_INSN_MSATHS, model_fr400_msaths, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MQSATHS, model_fr400_mqsaths, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MSATHU, model_fr400_msathu, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MCMPSH, model_fr400_mcmpsh, { { (int) UNIT_FR400_U_MEDIA_7, 1, 1 } } },
+  { FRVBF_INSN_MCMPUH, model_fr400_mcmpuh, { { (int) UNIT_FR400_U_MEDIA_7, 1, 1 } } },
+  { FRVBF_INSN_MABSHS, model_fr400_mabshs, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MADDHSS, model_fr400_maddhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MADDHUS, model_fr400_maddhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MSUBHSS, model_fr400_msubhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MSUBHUS, model_fr400_msubhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMADDHSS, model_fr400_cmaddhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMADDHUS, model_fr400_cmaddhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHSS, model_fr400_cmsubhss, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHUS, model_fr400_cmsubhus, { { (int) UNIT_FR400_U_MEDIA_1, 1, 1 } } },
+  { FRVBF_INSN_MQADDHSS, model_fr400_mqaddhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQADDHUS, model_fr400_mqaddhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHSS, model_fr400_mqsubhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHUS, model_fr400_mqsubhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHSS, model_fr400_cmqaddhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHUS, model_fr400_cmqaddhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHSS, model_fr400_cmqsubhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHUS, model_fr400_cmqsubhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MADDACCS, model_fr400_maddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } },
+  { FRVBF_INSN_MSUBACCS, model_fr400_msubaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } },
+  { FRVBF_INSN_MDADDACCS, model_fr400_mdaddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC_DUAL, 1, 1 } } },
+  { FRVBF_INSN_MDSUBACCS, model_fr400_mdsubaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC_DUAL, 1, 1 } } },
+  { FRVBF_INSN_MASACCS, model_fr400_masaccs, { { (int) UNIT_FR400_U_MEDIA_2_ADD_SUB, 1, 1 } } },
+  { FRVBF_INSN_MDASACCS, model_fr400_mdasaccs, { { (int) UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, 1, 1 } } },
+  { FRVBF_INSN_MMULHS, model_fr400_mmulhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MMULHU, model_fr400_mmulhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MMULXHS, model_fr400_mmulxhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MMULXHU, model_fr400_mmulxhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMMULHS, model_fr400_cmmulhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMMULHU, model_fr400_cmmulhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MQMULHS, model_fr400_mqmulhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQMULHU, model_fr400_mqmulhu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHS, model_fr400_mqmulxhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHU, model_fr400_mqmulxhu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHS, model_fr400_cmqmulhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHU, model_fr400_cmqmulhu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MMACHS, model_fr400_mmachs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MMACHU, model_fr400_mmachu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MMRDHS, model_fr400_mmrdhs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MMRDHU, model_fr400_mmrdhu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMMACHS, model_fr400_cmmachs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMMACHU, model_fr400_cmmachu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MQMACHS, model_fr400_mqmachs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQMACHU, model_fr400_mqmachu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHS, model_fr400_cmqmachs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHU, model_fr400_cmqmachu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQXMACHS, model_fr400_mqxmachs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQXMACXHS, model_fr400_mqxmacxhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQMACXHS, model_fr400_mqmacxhs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MCPXRS, model_fr400_mcpxrs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MCPXRU, model_fr400_mcpxru, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MCPXIS, model_fr400_mcpxis, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MCPXIU, model_fr400_mcpxiu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRS, model_fr400_cmcpxrs, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRU, model_fr400_cmcpxru, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIS, model_fr400_cmcpxis, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIU, model_fr400_cmcpxiu, { { (int) UNIT_FR400_U_MEDIA_2, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRS, model_fr400_mqcpxrs, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRU, model_fr400_mqcpxru, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIS, model_fr400_mqcpxis, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIU, model_fr400_mqcpxiu, { { (int) UNIT_FR400_U_MEDIA_2_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHW, model_fr400_mexpdhw, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHW, model_fr400_cmexpdhw, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHD, model_fr400_mexpdhd, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHD, model_fr400_cmexpdhd, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_MPACKH, model_fr400_mpackh, { { (int) UNIT_FR400_U_MEDIA_3, 1, 1 } } },
+  { FRVBF_INSN_MDPACKH, model_fr400_mdpackh, { { (int) UNIT_FR400_U_MEDIA_3_QUAD, 1, 1 } } },
+  { FRVBF_INSN_MUNPACKH, model_fr400_munpackh, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_MDUNPACKH, model_fr400_mdunpackh, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MBTOH, model_fr400_mbtoh, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_CMBTOH, model_fr400_cmbtoh, { { (int) UNIT_FR400_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+  { FRVBF_INSN_MHTOB, model_fr400_mhtob, { { (int) UNIT_FR400_U_MEDIA_DUAL_HTOB, 1, 1 } } },
+  { FRVBF_INSN_CMHTOB, model_fr400_cmhtob, { { (int) UNIT_FR400_U_MEDIA_DUAL_HTOB, 1, 1 } } },
+  { FRVBF_INSN_MBTOHE, model_fr400_mbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMBTOHE, model_fr400_cmbtohe, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCLRACC, model_fr400_mclracc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
+  { FRVBF_INSN_MRDACC, model_fr400_mrdacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
+  { FRVBF_INSN_MRDACCG, model_fr400_mrdaccg, { { (int) UNIT_FR400_U_MEDIA_4_ACCG, 1, 1 } } },
+  { FRVBF_INSN_MWTACC, model_fr400_mwtacc, { { (int) UNIT_FR400_U_MEDIA_4, 1, 1 } } },
+  { FRVBF_INSN_MWTACCG, model_fr400_mwtaccg, { { (int) UNIT_FR400_U_MEDIA_4_ACCG, 1, 1 } } },
+  { FRVBF_INSN_MCOP1, model_fr400_mcop1, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP2, model_fr400_mcop2, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNOP, model_fr400_fnop, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+};
+
+/* Model timing data for `simple'.  */
+
+static const INSN_TIMING simple_timing[] = {
+  { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADD, model_simple_add, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUB, model_simple_sub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_AND, model_simple_and, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_OR, model_simple_or, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XOR, model_simple_xor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOT, model_simple_not, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SDIV, model_simple_sdiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NSDIV, model_simple_nsdiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UDIV, model_simple_udiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NUDIV, model_simple_nudiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMUL, model_simple_smul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMUL, model_simple_umul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLL, model_simple_sll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRL, model_simple_srl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRA, model_simple_sra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SCAN, model_simple_scan, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CADD, model_simple_cadd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSUB, model_simple_csub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CAND, model_simple_cand, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COR, model_simple_cor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CXOR, model_simple_cxor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CNOT, model_simple_cnot, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSMUL, model_simple_csmul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSDIV, model_simple_csdiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CUDIV, model_simple_cudiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSLL, model_simple_csll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRL, model_simple_csrl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRA, model_simple_csra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSCAN, model_simple_cscan, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDCC, model_simple_addcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBCC, model_simple_subcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCC, model_simple_andcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCC, model_simple_orcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCC, model_simple_xorcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLCC, model_simple_sllcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLCC, model_simple_srlcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRACC, model_simple_sracc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULCC, model_simple_smulcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULCC, model_simple_umulcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CADDCC, model_simple_caddcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSUBCC, model_simple_csubcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSMULCC, model_simple_csmulcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CANDCC, model_simple_candcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CORCC, model_simple_corcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CXORCC, model_simple_cxorcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSLLCC, model_simple_csllcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRLCC, model_simple_csrlcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSRACC, model_simple_csracc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDX, model_simple_addx, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBX, model_simple_subx, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXCC, model_simple_addxcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXCC, model_simple_subxcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDI, model_simple_addi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBI, model_simple_subi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDI, model_simple_andi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORI, model_simple_ori, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORI, model_simple_xori, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SDIVI, model_simple_sdivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NSDIVI, model_simple_nsdivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UDIVI, model_simple_udivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NUDIVI, model_simple_nudivi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULI, model_simple_smuli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULI, model_simple_umuli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLI, model_simple_slli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLI, model_simple_srli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRAI, model_simple_srai, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SCANI, model_simple_scani, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDICC, model_simple_addicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBICC, model_simple_subicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDICC, model_simple_andicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORICC, model_simple_oricc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORICC, model_simple_xoricc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SMULICC, model_simple_smulicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_UMULICC, model_simple_umulicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SLLICC, model_simple_sllicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRLICC, model_simple_srlicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SRAICC, model_simple_sraicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXI, model_simple_addxi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXI, model_simple_subxi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ADDXICC, model_simple_addxicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SUBXICC, model_simple_subxicc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMPB, model_simple_cmpb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMPBA, model_simple_cmpba, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETLO, model_simple_setlo, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETHI, model_simple_sethi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SETLOS, model_simple_setlos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSB, model_simple_ldsb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUB, model_simple_ldub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSH, model_simple_ldsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUH, model_simple_lduh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LD, model_simple_ld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBF, model_simple_ldbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHF, model_simple_ldhf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDF, model_simple_ldf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDC, model_simple_ldc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSB, model_simple_nldsb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUB, model_simple_nldub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSH, model_simple_nldsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUH, model_simple_nlduh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLD, model_simple_nld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBF, model_simple_nldbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHF, model_simple_nldhf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDF, model_simple_nldf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDD, model_simple_ldd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDF, model_simple_lddf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDC, model_simple_lddc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDD, model_simple_nldd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDF, model_simple_nlddf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQ, model_simple_ldq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQF, model_simple_ldqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQC, model_simple_ldqc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQ, model_simple_nldq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQF, model_simple_nldqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBU, model_simple_ldsbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUBU, model_simple_ldubu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSHU, model_simple_ldshu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUHU, model_simple_lduhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDU, model_simple_ldu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSBU, model_simple_nldsbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBU, model_simple_nldubu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHU, model_simple_nldshu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHU, model_simple_nlduhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDU, model_simple_nldu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBFU, model_simple_ldbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHFU, model_simple_ldhfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDFU, model_simple_ldfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDCU, model_simple_ldcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFU, model_simple_nldbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFU, model_simple_nldhfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFU, model_simple_nldfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDU, model_simple_lddu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDU, model_simple_nlddu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDFU, model_simple_lddfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDCU, model_simple_lddcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFU, model_simple_nlddfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQU, model_simple_ldqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQU, model_simple_nldqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFU, model_simple_ldqfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQCU, model_simple_ldqcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFU, model_simple_nldqfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSBI, model_simple_ldsbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDSHI, model_simple_ldshi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDI, model_simple_ldi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUBI, model_simple_ldubi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDUHI, model_simple_lduhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDBFI, model_simple_ldbfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDHFI, model_simple_ldhfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDFI, model_simple_ldfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSBI, model_simple_nldsbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUBI, model_simple_nldubi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDSHI, model_simple_nldshi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDUHI, model_simple_nlduhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDI, model_simple_nldi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDBFI, model_simple_nldbfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDHFI, model_simple_nldhfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDFI, model_simple_nldfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDI, model_simple_lddi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDDFI, model_simple_lddfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDI, model_simple_nlddi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDDFI, model_simple_nlddfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQI, model_simple_ldqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_LDQFI, model_simple_ldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQI, model_simple_nldqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NLDQFI, model_simple_nldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STB, model_simple_stb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STH, model_simple_sth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ST, model_simple_st, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBF, model_simple_stbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHF, model_simple_sthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STF, model_simple_stf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STC, model_simple_stc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTB, model_simple_rstb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTH, model_simple_rsth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RST, model_simple_rst, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTBF, model_simple_rstbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTHF, model_simple_rsthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTF, model_simple_rstf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STD, model_simple_std, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDF, model_simple_stdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDC, model_simple_stdc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTD, model_simple_rstd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTDF, model_simple_rstdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQ, model_simple_stq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQF, model_simple_stqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQC, model_simple_stqc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQ, model_simple_rstq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RSTQF, model_simple_rstqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBU, model_simple_stbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHU, model_simple_sthu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STU, model_simple_stu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBFU, model_simple_stbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHFU, model_simple_sthfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STFU, model_simple_stfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STCU, model_simple_stcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDU, model_simple_stdu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDFU, model_simple_stdfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDCU, model_simple_stdcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQU, model_simple_stqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFU, model_simple_stqfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQCU, model_simple_stqcu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSB, model_simple_cldsb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUB, model_simple_cldub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSH, model_simple_cldsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUH, model_simple_clduh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLD, model_simple_cld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDBF, model_simple_cldbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDHF, model_simple_cldhf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDF, model_simple_cldf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDD, model_simple_cldd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDF, model_simple_clddf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDQ, model_simple_cldq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSBU, model_simple_cldsbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUBU, model_simple_cldubu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDSHU, model_simple_cldshu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDUHU, model_simple_clduhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDU, model_simple_cldu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDBFU, model_simple_cldbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDHFU, model_simple_cldhfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDFU, model_simple_cldfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDU, model_simple_clddu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDDFU, model_simple_clddfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLDQU, model_simple_cldqu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTB, model_simple_cstb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTH, model_simple_csth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CST, model_simple_cst, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBF, model_simple_cstbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHF, model_simple_csthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTF, model_simple_cstf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTD, model_simple_cstd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDF, model_simple_cstdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTQ, model_simple_cstq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBU, model_simple_cstbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHU, model_simple_csthu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTU, model_simple_cstu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTBFU, model_simple_cstbfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTHFU, model_simple_csthfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTFU, model_simple_cstfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDU, model_simple_cstdu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSTDFU, model_simple_cstdfu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBI, model_simple_stbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHI, model_simple_sthi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STI, model_simple_sti, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STBFI, model_simple_stbfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STHFI, model_simple_sthfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STFI, model_simple_stfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDI, model_simple_stdi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STDFI, model_simple_stdfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQI, model_simple_stqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_STQFI, model_simple_stqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAP, model_simple_swap, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_SWAPI, model_simple_swapi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CSWAP, model_simple_cswap, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGF, model_simple_movgf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFG, model_simple_movfg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGFD, model_simple_movgfd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGD, model_simple_movfgd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGFQ, model_simple_movgfq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVFGQ, model_simple_movfgq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGF, model_simple_cmovgf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVFG, model_simple_cmovfg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVGFD, model_simple_cmovgfd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOVFGD, model_simple_cmovfgd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVGS, model_simple_movgs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOVSG, model_simple_movsg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BRA, model_simple_bra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNO, model_simple_bno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BEQ, model_simple_beq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNE, model_simple_bne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLE, model_simple_ble, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGT, model_simple_bgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLT, model_simple_blt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGE, model_simple_bge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLS, model_simple_bls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BHI, model_simple_bhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BC, model_simple_bc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNC, model_simple_bnc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BN, model_simple_bn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BP, model_simple_bp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BV, model_simple_bv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNV, model_simple_bnv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBRA, model_simple_fbra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNO, model_simple_fbno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNE, model_simple_fbne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBEQ, model_simple_fbeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLG, model_simple_fblg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUE, model_simple_fbue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUL, model_simple_fbul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGE, model_simple_fbge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLT, model_simple_fblt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGE, model_simple_fbuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUG, model_simple_fbug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLE, model_simple_fble, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGT, model_simple_fbgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULE, model_simple_fbule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBU, model_simple_fbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBO, model_simple_fbo, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCTRLR, model_simple_bctrlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BRALR, model_simple_bralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNOLR, model_simple_bnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BEQLR, model_simple_beqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNELR, model_simple_bnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLELR, model_simple_blelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGTLR, model_simple_bgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLTLR, model_simple_bltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BGELR, model_simple_bgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BLSLR, model_simple_blslr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BHILR, model_simple_bhilr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLR, model_simple_bclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNCLR, model_simple_bnclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNLR, model_simple_bnlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BPLR, model_simple_bplr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BVLR, model_simple_bvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BNVLR, model_simple_bnvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBRALR, model_simple_fbralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNOLR, model_simple_fbnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBEQLR, model_simple_fbeqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBNELR, model_simple_fbnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLGLR, model_simple_fblglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUELR, model_simple_fbuelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULLR, model_simple_fbullr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGELR, model_simple_fbgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLTLR, model_simple_fbltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGELR, model_simple_fbugelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBUGLR, model_simple_fbuglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBLELR, model_simple_fblelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBGTLR, model_simple_fbgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULELR, model_simple_fbulelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBULR, model_simple_fbulr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FBOLR, model_simple_fbolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCRALR, model_simple_bcralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNOLR, model_simple_bcnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCEQLR, model_simple_bceqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNELR, model_simple_bcnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLELR, model_simple_bclelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCGTLR, model_simple_bcgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLTLR, model_simple_bcltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCGELR, model_simple_bcgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCLSLR, model_simple_bclslr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCHILR, model_simple_bchilr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCCLR, model_simple_bcclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNCLR, model_simple_bcnclr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNLR, model_simple_bcnlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCPLR, model_simple_bcplr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCVLR, model_simple_bcvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BCNVLR, model_simple_bcnvlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBRALR, model_simple_fcbralr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBNOLR, model_simple_fcbnolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBEQLR, model_simple_fcbeqlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBNELR, model_simple_fcbnelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLGLR, model_simple_fcblglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUELR, model_simple_fcbuelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULLR, model_simple_fcbullr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBGELR, model_simple_fcbgelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLTLR, model_simple_fcbltlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUGELR, model_simple_fcbugelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBUGLR, model_simple_fcbuglr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBLELR, model_simple_fcblelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBGTLR, model_simple_fcbgtlr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULELR, model_simple_fcbulelr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBULR, model_simple_fcbulr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCBOLR, model_simple_fcbolr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_JMPL, model_simple_jmpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLL, model_simple_calll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_JMPIL, model_simple_jmpil, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALLIL, model_simple_callil, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CALL, model_simple_call, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_RETT, model_simple_rett, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_REI, model_simple_rei, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TRA, model_simple_tra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNO, model_simple_tno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TEQ, model_simple_teq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNE, model_simple_tne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLE, model_simple_tle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TGT, model_simple_tgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLT, model_simple_tlt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TGE, model_simple_tge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TLS, model_simple_tls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_THI, model_simple_thi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TC, model_simple_tc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNC, model_simple_tnc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TN, model_simple_tn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TP, model_simple_tp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TV, model_simple_tv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TNV, model_simple_tnv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTRA, model_simple_ftra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTNO, model_simple_ftno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTNE, model_simple_ftne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTEQ, model_simple_fteq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLG, model_simple_ftlg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUE, model_simple_ftue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUL, model_simple_ftul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTGE, model_simple_ftge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLT, model_simple_ftlt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUGE, model_simple_ftuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTUG, model_simple_ftug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTLE, model_simple_ftle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTGT, model_simple_ftgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTULE, model_simple_ftule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTU, model_simple_ftu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTO, model_simple_fto, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIRA, model_simple_tira, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINO, model_simple_tino, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIEQ, model_simple_tieq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINE, model_simple_tine, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILE, model_simple_tile, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIGT, model_simple_tigt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILT, model_simple_tilt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIGE, model_simple_tige, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TILS, model_simple_tils, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIHI, model_simple_tihi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIC, model_simple_tic, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINC, model_simple_tinc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIN, model_simple_tin, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIP, model_simple_tip, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TIV, model_simple_tiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_TINV, model_simple_tinv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIRA, model_simple_ftira, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTINO, model_simple_ftino, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTINE, model_simple_ftine, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIEQ, model_simple_ftieq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILG, model_simple_ftilg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUE, model_simple_ftiue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUL, model_simple_ftiul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIGE, model_simple_ftige, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILT, model_simple_ftilt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUGE, model_simple_ftiuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIUG, model_simple_ftiug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTILE, model_simple_ftile, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIGT, model_simple_ftigt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIULE, model_simple_ftiule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIU, model_simple_ftiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FTIO, model_simple_ftio, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BREAK, model_simple_break, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MTRAP, model_simple_mtrap, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDCR, model_simple_andcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORCR, model_simple_orcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_XORCR, model_simple_xorcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDCR, model_simple_nandcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORCR, model_simple_norcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ANDNCR, model_simple_andncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ORNCR, model_simple_orncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NANDNCR, model_simple_nandncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NORNCR, model_simple_norncr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NOTCR, model_simple_notcr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKRA, model_simple_ckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNO, model_simple_ckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKEQ, model_simple_ckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNE, model_simple_ckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLE, model_simple_ckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKGT, model_simple_ckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLT, model_simple_cklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKGE, model_simple_ckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKLS, model_simple_ckls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKHI, model_simple_ckhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKC, model_simple_ckc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNC, model_simple_cknc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKN, model_simple_ckn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKP, model_simple_ckp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKV, model_simple_ckv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CKNV, model_simple_cknv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKRA, model_simple_fckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKNO, model_simple_fckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKNE, model_simple_fckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKEQ, model_simple_fckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLG, model_simple_fcklg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUE, model_simple_fckue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUL, model_simple_fckul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKGE, model_simple_fckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLT, model_simple_fcklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUGE, model_simple_fckuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKUG, model_simple_fckug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKLE, model_simple_fckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKGT, model_simple_fckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKULE, model_simple_fckule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKU, model_simple_fcku, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCKO, model_simple_fcko, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKRA, model_simple_cckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNO, model_simple_cckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKEQ, model_simple_cckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNE, model_simple_cckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLE, model_simple_cckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKGT, model_simple_cckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLT, model_simple_ccklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKGE, model_simple_cckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKLS, model_simple_cckls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKHI, model_simple_cckhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKC, model_simple_cckc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNC, model_simple_ccknc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKN, model_simple_cckn, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKP, model_simple_cckp, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKV, model_simple_cckv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCKNV, model_simple_ccknv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKRA, model_simple_cfckra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKNO, model_simple_cfckno, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKNE, model_simple_cfckne, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKEQ, model_simple_cfckeq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLG, model_simple_cfcklg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUE, model_simple_cfckue, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUL, model_simple_cfckul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKGE, model_simple_cfckge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLT, model_simple_cfcklt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUGE, model_simple_cfckuge, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKUG, model_simple_cfckug, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKLE, model_simple_cfckle, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKGT, model_simple_cfckgt, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKULE, model_simple_cfckule, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKU, model_simple_cfcku, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCKO, model_simple_cfcko, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CJMPL, model_simple_cjmpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CCALLL, model_simple_ccalll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICI, model_simple_ici, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCI, model_simple_dci, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICEI, model_simple_icei, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCEI, model_simple_dcei, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCF, model_simple_dcf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCEF, model_simple_dcef, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WITLB, model_simple_witlb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_WDTLB, model_simple_wdtlb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ITLBI, model_simple_itlbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DTLBI, model_simple_dtlbi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICPL, model_simple_icpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCPL, model_simple_dcpl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_ICUL, model_simple_icul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_DCUL, model_simple_dcul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_BAR, model_simple_bar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEMBAR, model_simple_membar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP1, model_simple_cop1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COP2, model_simple_cop2, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGR, model_simple_clrgr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFR, model_simple_clrfr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRGA, model_simple_clrga, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CLRFA, model_simple_clrfa, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGR, model_simple_commitgr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFR, model_simple_commitfr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITGA, model_simple_commitga, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_COMMITFA, model_simple_commitfa, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOS, model_simple_fitos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSTOI, model_simple_fstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FITOD, model_simple_fitod, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDTOI, model_simple_fdtoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDITOS, model_simple_fditos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSTOI, model_simple_fdstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDITOS, model_simple_nfditos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSTOI, model_simple_nfdstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFITOS, model_simple_cfitos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSTOI, model_simple_cfstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFITOS, model_simple_nfitos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSTOI, model_simple_nfstoi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVS, model_simple_fmovs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMOVD, model_simple_fmovd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMOVS, model_simple_fdmovs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMOVS, model_simple_cfmovs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGS, model_simple_fnegs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNEGD, model_simple_fnegd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDNEGS, model_simple_fdnegs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFNEGS, model_simple_cfnegs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSS, model_simple_fabss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FABSD, model_simple_fabsd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDABSS, model_simple_fdabss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFABSS, model_simple_cfabss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTS, model_simple_fsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSQRTS, model_simple_fdsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSQRTS, model_simple_nfdsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSQRTD, model_simple_fsqrtd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSQRTS, model_simple_cfsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSQRTS, model_simple_nfsqrts, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDS, model_simple_fadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBS, model_simple_fsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULS, model_simple_fmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVS, model_simple_fdivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FADDD, model_simple_faddd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FSUBD, model_simple_fsubd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMULD, model_simple_fmuld, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDIVD, model_simple_fdivd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFADDS, model_simple_cfadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFSUBS, model_simple_cfsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMULS, model_simple_cfmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFDIVS, model_simple_cfdivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFADDS, model_simple_nfadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFSUBS, model_simple_nfsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMULS, model_simple_nfmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDIVS, model_simple_nfdivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPS, model_simple_fcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FCMPD, model_simple_fcmpd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFCMPS, model_simple_cfcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDCMPS, model_simple_fdcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDS, model_simple_fmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBS, model_simple_fmsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMADDD, model_simple_fmaddd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSUBD, model_simple_fmsubd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMADDS, model_simple_fdmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMADDS, model_simple_nfdmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMADDS, model_simple_cfmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSUBS, model_simple_cfmsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMADDS, model_simple_nfmadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSUBS, model_simple_nfmsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAS, model_simple_fmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSS, model_simple_fmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMAS, model_simple_fdmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMSS, model_simple_fdmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMAS, model_simple_nfdmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMSS, model_simple_nfdmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMAS, model_simple_cfmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CFMSS, model_simple_cfmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMAD, model_simple_fmad, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FMSD, model_simple_fmsd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMAS, model_simple_nfmas, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFMSS, model_simple_nfmss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDADDS, model_simple_fdadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSUBS, model_simple_fdsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULS, model_simple_fdmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDDIVS, model_simple_fddivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDSADS, model_simple_fdsads, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FDMULCS, model_simple_fdmulcs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULCS, model_simple_nfdmulcs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDADDS, model_simple_nfdadds, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSUBS, model_simple_nfdsubs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDMULS, model_simple_nfdmuls, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDDIVS, model_simple_nfddivs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDSADS, model_simple_nfdsads, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_NFDCMPS, model_simple_nfdcmps, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOS, model_simple_mhsetlos, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIS, model_simple_mhsethis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETS, model_simple_mhdsets, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETLOH, model_simple_mhsetloh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHSETHIH, model_simple_mhsethih, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHDSETH, model_simple_mhdseth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAND, model_simple_mand, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MOR, model_simple_mor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MXOR, model_simple_mxor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMAND, model_simple_cmand, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMOR, model_simple_cmor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMXOR, model_simple_cmxor, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MNOT, model_simple_mnot, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMNOT, model_simple_cmnot, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MROTLI, model_simple_mrotli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MROTRI, model_simple_mrotri, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWCUT, model_simple_mwcut, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWCUTI, model_simple_mwcuti, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUT, model_simple_mcut, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTI, model_simple_mcuti, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTSS, model_simple_mcutss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCUTSSI, model_simple_mcutssi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDCUTSSI, model_simple_mdcutssi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MAVEH, model_simple_maveh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSLLHI, model_simple_msllhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSRLHI, model_simple_msrlhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSRAHI, model_simple_msrahi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDROTLI, model_simple_mdrotli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLHI, model_simple_mcplhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPLI, model_simple_mcpli, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHS, model_simple_msaths, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSATHS, model_simple_mqsaths, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSATHU, model_simple_msathu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCMPSH, model_simple_mcmpsh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCMPUH, model_simple_mcmpuh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MABSHS, model_simple_mabshs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDHSS, model_simple_maddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDHUS, model_simple_maddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBHSS, model_simple_msubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBHUS, model_simple_msubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMADDHSS, model_simple_cmaddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMADDHUS, model_simple_cmaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHSS, model_simple_cmsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMSUBHUS, model_simple_cmsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQADDHSS, model_simple_mqaddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQADDHUS, model_simple_mqaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHSS, model_simple_mqsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQSUBHUS, model_simple_mqsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHSS, model_simple_cmqaddhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQADDHUS, model_simple_cmqaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHSS, model_simple_cmqsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQSUBHUS, model_simple_cmqsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MADDACCS, model_simple_maddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MSUBACCS, model_simple_msubaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDADDACCS, model_simple_mdaddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDSUBACCS, model_simple_mdsubaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MASACCS, model_simple_masaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDASACCS, model_simple_mdasaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULHS, model_simple_mmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULHU, model_simple_mmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULXHS, model_simple_mmulxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMULXHU, model_simple_mmulxhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMULHS, model_simple_cmmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMULHU, model_simple_cmmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULHS, model_simple_mqmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULHU, model_simple_mqmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHS, model_simple_mqmulxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMULXHU, model_simple_mqmulxhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHS, model_simple_cmqmulhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMULHU, model_simple_cmqmulhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMACHS, model_simple_mmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMACHU, model_simple_mmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMRDHS, model_simple_mmrdhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MMRDHU, model_simple_mmrdhu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMACHS, model_simple_cmmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMMACHU, model_simple_cmmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACHS, model_simple_mqmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACHU, model_simple_mqmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHS, model_simple_cmqmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMQMACHU, model_simple_cmqmachu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQXMACHS, model_simple_mqxmachs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQXMACXHS, model_simple_mqxmacxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQMACXHS, model_simple_mqmacxhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXRS, model_simple_mcpxrs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXRU, model_simple_mcpxru, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXIS, model_simple_mcpxis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCPXIU, model_simple_mcpxiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRS, model_simple_cmcpxrs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXRU, model_simple_cmcpxru, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIS, model_simple_cmcpxis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMCPXIU, model_simple_cmcpxiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRS, model_simple_mqcpxrs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXRU, model_simple_mqcpxru, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIS, model_simple_mqcpxis, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MQCPXIU, model_simple_mqcpxiu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHW, model_simple_mexpdhw, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHW, model_simple_cmexpdhw, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MEXPDHD, model_simple_mexpdhd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMEXPDHD, model_simple_cmexpdhd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MPACKH, model_simple_mpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDPACKH, model_simple_mdpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MUNPACKH, model_simple_munpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MDUNPACKH, model_simple_mdunpackh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MBTOH, model_simple_mbtoh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMBTOH, model_simple_cmbtoh, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MHTOB, model_simple_mhtob, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMHTOB, model_simple_cmhtob, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MBTOHE, model_simple_mbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_CMBTOHE, model_simple_cmbtohe, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCLRACC, model_simple_mclracc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MRDACC, model_simple_mrdacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MRDACCG, model_simple_mrdaccg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWTACC, model_simple_mwtacc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MWTACCG, model_simple_mwtaccg, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP1, model_simple_mcop1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_MCOP2, model_simple_mcop2, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+  { FRVBF_INSN_FNOP, model_simple_fnop, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+frv_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FRV_DATA));
+}
+
+static void
+fr500_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR500_DATA));
+}
+
+static void
+tomcat_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TOMCAT_DATA));
+}
+
+static void
+fr400_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR400_DATA));
+}
+
+static void
+simple_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SIMPLE_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL frv_models[] =
+{
+  { "frv", & frv_mach, MODEL_FRV, TIMING_DATA (& frv_timing[0]), frv_model_init },
+  { 0 }
+};
+
+static const MODEL fr500_models[] =
+{
+  { "fr500", & fr500_mach, MODEL_FR500, TIMING_DATA (& fr500_timing[0]), fr500_model_init },
+  { 0 }
+};
+
+static const MODEL tomcat_models[] =
+{
+  { "tomcat", & tomcat_mach, MODEL_TOMCAT, TIMING_DATA (& tomcat_timing[0]), tomcat_model_init },
+  { 0 }
+};
+
+static const MODEL fr400_models[] =
+{
+  { "fr400", & fr400_mach, MODEL_FR400, TIMING_DATA (& fr400_timing[0]), fr400_model_init },
+  { 0 }
+};
+
+static const MODEL simple_models[] =
+{
+  { "simple", & simple_mach, MODEL_SIMPLE, TIMING_DATA (& simple_timing[0]), simple_model_init },
+  { 0 }
+};
+
+/* The properties of this cpu's implementation.  */
+
+static const MACH_IMP_PROPERTIES frvbf_imp_properties =
+{
+  sizeof (SIM_CPU),
+#if WITH_SCACHE
+  sizeof (SCACHE)
+#else
+  0
+#endif
+};
+
+
+static void
+frvbf_prepare_run (SIM_CPU *cpu)
+{
+  if (CPU_IDESC (cpu) == NULL)
+    frvbf_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+frvbf_get_idata (SIM_CPU *cpu, int inum)
+{
+  return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+frv_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = frvbf_fetch_register;
+  CPU_REG_STORE (cpu) = frvbf_store_register;
+  CPU_PC_FETCH (cpu) = frvbf_h_pc_get;
+  CPU_PC_STORE (cpu) = frvbf_h_pc_set;
+  CPU_GET_IDATA (cpu) = frvbf_get_idata;
+  CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#endif
+}
+
+const MACH frv_mach =
+{
+  "frv", "frv", MACH_FRV,
+  32, 32, & frv_models[0], & frvbf_imp_properties,
+  frv_init_cpu,
+  frvbf_prepare_run
+};
+
+static void
+fr500_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = frvbf_fetch_register;
+  CPU_REG_STORE (cpu) = frvbf_store_register;
+  CPU_PC_FETCH (cpu) = frvbf_h_pc_get;
+  CPU_PC_STORE (cpu) = frvbf_h_pc_set;
+  CPU_GET_IDATA (cpu) = frvbf_get_idata;
+  CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#endif
+}
+
+const MACH fr500_mach =
+{
+  "fr500", "fr500", MACH_FR500,
+  32, 32, & fr500_models[0], & frvbf_imp_properties,
+  fr500_init_cpu,
+  frvbf_prepare_run
+};
+
+static void
+tomcat_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = frvbf_fetch_register;
+  CPU_REG_STORE (cpu) = frvbf_store_register;
+  CPU_PC_FETCH (cpu) = frvbf_h_pc_get;
+  CPU_PC_STORE (cpu) = frvbf_h_pc_set;
+  CPU_GET_IDATA (cpu) = frvbf_get_idata;
+  CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#endif
+}
+
+const MACH tomcat_mach =
+{
+  "tomcat", "tomcat", MACH_TOMCAT,
+  32, 32, & tomcat_models[0], & frvbf_imp_properties,
+  tomcat_init_cpu,
+  frvbf_prepare_run
+};
+
+static void
+fr400_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = frvbf_fetch_register;
+  CPU_REG_STORE (cpu) = frvbf_store_register;
+  CPU_PC_FETCH (cpu) = frvbf_h_pc_get;
+  CPU_PC_STORE (cpu) = frvbf_h_pc_set;
+  CPU_GET_IDATA (cpu) = frvbf_get_idata;
+  CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#endif
+}
+
+const MACH fr400_mach =
+{
+  "fr400", "fr400", MACH_FR400,
+  32, 32, & fr400_models[0], & frvbf_imp_properties,
+  fr400_init_cpu,
+  frvbf_prepare_run
+};
+
+static void
+simple_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = frvbf_fetch_register;
+  CPU_REG_STORE (cpu) = frvbf_store_register;
+  CPU_PC_FETCH (cpu) = frvbf_h_pc_get;
+  CPU_PC_STORE (cpu) = frvbf_h_pc_set;
+  CPU_GET_IDATA (cpu) = frvbf_get_idata;
+  CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#endif
+}
+
+const MACH simple_mach =
+{
+  "simple", "simple", MACH_SIMPLE,
+  32, 32, & simple_models[0], & frvbf_imp_properties,
+  simple_init_cpu,
+  frvbf_prepare_run
+};
+
diff --git a/sim/frv/options.c b/sim/frv/options.c
new file mode 100644
index 00000000000..039a01fbc3d
--- /dev/null
+++ b/sim/frv/options.c
@@ -0,0 +1,237 @@
+/* FRV simulator memory option handling.
+   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "sim-assert.h"
+#include "sim-options.h"
+
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+
+/* FRV specific command line options. */
+
+enum {
+  OPTION_FRV_DATA_CACHE = OPTION_START,
+  OPTION_FRV_INSN_CACHE,
+  OPTION_FRV_PROFILE_CACHE,
+  OPTION_FRV_PROFILE_PARALLEL,
+  OPTION_FRV_TIMER,
+  OPTION_FRV_MEMORY_LATENCY
+};
+
+static DECLARE_OPTION_HANDLER (frv_option_handler);
+
+const OPTION frv_options[] =
+{
+  { {"profile", optional_argument, NULL, 'p'},
+      'p', "on|off", "Perform profiling",
+      frv_option_handler },
+  { {"data-cache", optional_argument, NULL, OPTION_FRV_DATA_CACHE },
+      '\0', "WAYS[,SETS[,LINESIZE]]", "Enable data cache",
+      frv_option_handler },
+  { {"insn-cache", optional_argument, NULL, OPTION_FRV_INSN_CACHE },
+      '\0', "WAYS[,SETS[,LINESIZE]]", "Enable instruction cache",
+      frv_option_handler },
+  { {"profile-cache", optional_argument, NULL, OPTION_FRV_PROFILE_CACHE },
+      '\0', "on|off", "Profile caches",
+      frv_option_handler },
+  { {"profile-parallel", optional_argument, NULL, OPTION_FRV_PROFILE_PARALLEL },
+      '\0', "on|off", "Profile parallelism",
+      frv_option_handler },
+  { {"timer", required_argument, NULL, OPTION_FRV_TIMER },
+      '\0', "CYCLES,INTERRUPT", "Set Interrupt Timer",
+      frv_option_handler },
+  { {"memory-latency", required_argument, NULL, OPTION_FRV_MEMORY_LATENCY },
+      '\0', "CYCLES", "Set Latency of memory",
+      frv_option_handler },
+  { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
+};
+
+static char *
+parse_size (char *chp, address_word *nr_bytes)
+{
+  /* <nr_bytes> */
+  *nr_bytes = strtoul (chp, &chp, 0);
+  return chp;
+}
+
+static address_word
+check_pow2 (address_word value, char *argname, char *optname, SIM_DESC sd)
+{
+  if ((value & (value - 1)) != 0)
+    {
+      sim_io_eprintf (sd, "%s argument to %s must be a power of 2\n",
+		      argname, optname);
+      return 0; /* will enable default value.  */
+    }
+
+  return value;
+}
+
+static void
+parse_cache_option (SIM_DESC sd, char *arg, char *cache_name, int is_data_cache)
+{
+  int i;
+  address_word ways = 0, sets = 0, linesize = 0;
+  if (arg != NULL)
+    {
+      char *chp = arg;
+      /* parse the arguments */
+      chp = parse_size (chp, &ways);
+      ways = check_pow2 (ways, "WAYS", cache_name, sd);
+      if (*chp == ',')
+	{
+	  chp = parse_size (chp + 1, &sets);
+	  sets = check_pow2 (sets, "SETS", cache_name, sd);
+	  if (*chp == ',')
+	    {
+	      chp = parse_size (chp + 1, &linesize);
+	      linesize = check_pow2 (linesize, "LINESIZE", cache_name, sd);
+	    }
+	}
+    }
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+    {
+      SIM_CPU *current_cpu = STATE_CPU (sd, i);
+      FRV_CACHE *cache = is_data_cache ? CPU_DATA_CACHE (current_cpu)
+	                               : CPU_INSN_CACHE (current_cpu);
+      cache->ways = ways;
+      cache->sets = sets;
+      cache->line_size = linesize;
+      frv_cache_init (current_cpu, cache);
+    }
+}
+
+static SIM_RC
+frv_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
+		    char *arg, int is_command)
+{
+  switch (opt)
+    {
+    case 'p' :
+      if (! WITH_PROFILE)
+	sim_io_eprintf (sd, "Profiling not compiled in, `-p' ignored\n");
+      else
+	{
+	  unsigned mask = PROFILE_USEFUL_MASK;
+	  if (WITH_PROFILE_CACHE_P)
+	    mask |= (1 << PROFILE_CACHE_IDX);
+	  if (WITH_PROFILE_PARALLEL_P)
+	    mask |= (1 << PROFILE_PARALLEL_IDX);
+	  return set_profile_option_mask (sd, "profile", mask, arg);
+	}
+      break;
+
+    case OPTION_FRV_DATA_CACHE:
+      parse_cache_option (sd, arg, "data_cache", 1/*is_data_cache*/);
+      return SIM_RC_OK;
+
+    case OPTION_FRV_INSN_CACHE:
+      parse_cache_option (sd, arg, "insn_cache", 0/*is_data_cache*/);
+      return SIM_RC_OK;
+
+    case OPTION_FRV_PROFILE_CACHE:
+      if (WITH_PROFILE_CACHE_P)
+	return sim_profile_set_option (sd, "-cache", PROFILE_CACHE_IDX, arg);
+      else
+	sim_io_eprintf (sd, "Cache profiling not compiled in, `--profile-cache' ignored\n");
+      break;
+
+    case OPTION_FRV_PROFILE_PARALLEL:
+      if (WITH_PROFILE_PARALLEL_P)
+	{
+	  unsigned mask
+	    = (1 << PROFILE_MODEL_IDX) | (1 << PROFILE_PARALLEL_IDX);
+	  return set_profile_option_mask (sd, "-parallel", mask, arg);
+	}
+      else
+	sim_io_eprintf (sd, "Parallel profiling not compiled in, `--profile-parallel' ignored\n");
+      break;
+
+    case OPTION_FRV_TIMER:
+      {
+	char *chp = arg;
+	address_word cycles, interrupt;
+	chp = parse_size (chp, &cycles);
+	if (chp == arg)
+	  {
+	    sim_io_eprintf (sd, "Cycle count required for --timer\n");
+	    return SIM_RC_FAIL;
+	  }
+	if (*chp != ',')
+	  {
+	    sim_io_eprintf (sd, "Interrupt number required for --timer\n");
+	    return SIM_RC_FAIL;
+	  }
+	chp = parse_size (chp + 1, &interrupt);
+	if (interrupt < 1 || interrupt > 15)
+	  {
+	    sim_io_eprintf (sd, "Interrupt number for --timer must be greater than 0 and less that 16\n");
+	    return SIM_RC_FAIL;
+	  }
+	frv_interrupt_state.timer.enabled = 1;
+	frv_interrupt_state.timer.value = cycles;
+	frv_interrupt_state.timer.current = 0;
+	frv_interrupt_state.timer.interrupt =
+	  FRV_INTERRUPT_LEVEL_1 + interrupt - 1;
+      }
+      return SIM_RC_OK;
+
+    case OPTION_FRV_MEMORY_LATENCY:
+      {
+	int i;
+	char *chp = arg;
+	address_word cycles;
+	chp = parse_size (chp, &cycles);
+	if (chp == arg)
+	  {
+	    sim_io_eprintf (sd, "Cycle count required for --memory-latency\n");
+	    return SIM_RC_FAIL;
+	  }
+	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+	  {
+	    SIM_CPU *current_cpu = STATE_CPU (sd, i);
+	    FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu);
+	    FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu);
+	    insn_cache->memory_latency = cycles;
+	    data_cache->memory_latency = cycles;
+	  }
+      }
+      return SIM_RC_OK;
+
+    default:
+      sim_io_eprintf (sd, "Unknown FRV option %d\n", opt);
+      return SIM_RC_FAIL;
+
+    }
+
+  return SIM_RC_FAIL;
+}
diff --git a/sim/frv/pipeline.c b/sim/frv/pipeline.c
new file mode 100644
index 00000000000..90d55c7a54f
--- /dev/null
+++ b/sim/frv/pipeline.c
@@ -0,0 +1,92 @@
+/* frv vliw model.
+   Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+
+/* Simulator specific vliw related functions.  Additional vliw related
+   code used by both the simulator and the assembler is in frv.opc.  */
+
+int insns_in_slot[UNIT_NUM_UNITS] = {0};
+
+void
+frv_vliw_setup_insn (SIM_CPU *current_cpu, const CGEN_INSN *insn)
+{
+  FRV_VLIW *vliw;
+  int index;
+
+  /* Always clear the NE index which indicates the target register
+     of a non excepting insn. This will be reset by the insn if
+     necessary.  */
+  frv_interrupt_state.ne_index = NE_NOFLAG;
+
+  vliw = CPU_VLIW (current_cpu);
+  index = vliw->next_slot - 1;
+  if (frv_is_float_insn (insn))
+    {
+      /* If the insn is to be added and is a floating point insn and
+	 it is the first floating point insn in the vliw, then clear
+	 FSR0.FTT.  */
+      int i;
+      for (i = 0; i < index; ++i)
+	if (frv_is_float_major (vliw->major[i], vliw->mach))
+	  break; /* found float insn.  */
+      if (i >= index)
+	{
+	  SI fsr0 = GET_FSR (0);
+	  SET_FSR_FTT (fsr0, FTT_NONE);
+	  SET_FSR (0, fsr0);
+	}
+    }
+  else if (frv_is_media_insn (insn))
+    {
+      /* Clear the appropriate MSR fields depending on which slot
+	 this insn is in.  */
+      CGEN_ATTR_VALUE_TYPE preserve_ovf;
+      SI msr0 = GET_MSR (0);
+
+      preserve_ovf = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRESERVE_OVF);
+      if ((*vliw->current_vliw)[index] == UNIT_FM0)
+	{
+	  if (! preserve_ovf)
+	    {
+	      /* Clear MSR0.OVF and MSR0.SIE.  */
+	      CLEAR_MSR_SIE (msr0);
+	      CLEAR_MSR_OVF (msr0);
+	    }
+	}
+      else
+	{
+	  if (! preserve_ovf)
+	    {
+	      /* Clear MSR1.OVF and MSR1.SIE.  */
+	      SI msr1 = GET_MSR (1);
+	      CLEAR_MSR_SIE (msr1);
+	      CLEAR_MSR_OVF (msr1);
+	      SET_MSR (1, msr1);
+	    }
+	}
+      SET_MSR (0, msr0);
+    } /* Insn is a media insns.  */
+  COUNT_INSNS_IN_SLOT ((*vliw->current_vliw)[index]);
+}
+
diff --git a/sim/frv/profile-fr400.c b/sim/frv/profile-fr400.c
new file mode 100644
index 00000000000..9baddd12121
--- /dev/null
+++ b/sim/frv/profile-fr400.c
@@ -0,0 +1,2175 @@
+/* frv simulator fr400 dependent profiling code.
+
+   Copyright (C) 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+#if WITH_PROFILE_MODEL_P
+
+#include "profile.h"
+#include "profile-fr400.h"
+
+/* These functions get and set flags representing the use of
+   registers/resources.  */
+static void set_use_not_fp_load (SIM_CPU *, INT);
+static void set_use_not_media_p4 (SIM_CPU *, INT);
+static void set_use_not_media_p6 (SIM_CPU *, INT);
+
+static void set_acc_use_not_media_p2 (SIM_CPU *, INT);
+static void set_acc_use_not_media_p4 (SIM_CPU *, INT);
+
+void
+fr400_reset_gr_flags (SIM_CPU *cpu, INT fr)
+{
+  set_use_not_gr_complex (cpu, fr);
+}
+
+void
+fr400_reset_fr_flags (SIM_CPU *cpu, INT fr)
+{
+  set_use_not_fp_load  (cpu, fr);
+  set_use_not_media_p4 (cpu, fr);
+  set_use_not_media_p6 (cpu, fr);
+}
+
+void
+fr400_reset_acc_flags (SIM_CPU *cpu, INT acc)
+{
+  set_acc_use_not_media_p2 (cpu, acc);
+  set_acc_use_not_media_p4 (cpu, acc);
+}
+
+static void
+set_use_is_fp_load (SIM_CPU *cpu, INT fr, INT fr_double)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    {
+      fr400_reset_fr_flags (cpu, fr);
+      d->cur_fp_load |= (((DI)1) << fr);
+    }
+  if (fr_double != -1)
+    {
+      fr400_reset_fr_flags (cpu, fr_double);
+      d->cur_fp_load |= (((DI)1) << fr_double);
+      if (fr_double < 63)
+	{
+	  fr400_reset_fr_flags (cpu, fr_double + 1);
+	  d->cur_fp_load |= (((DI)1) << (fr_double + 1));
+	}
+    }
+
+}
+
+static void
+set_use_not_fp_load (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    d->cur_fp_load &= ~(((DI)1) << fr);
+}
+
+static int
+use_is_fp_load (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    return (d->prev_fp_load >> fr) & 1;
+  return 0;
+}
+
+static void
+set_acc_use_is_media_p2 (SIM_CPU *cpu, INT acc)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (acc != -1)
+    {
+      fr400_reset_acc_flags (cpu, acc);
+      d->cur_acc_p2 |= (((DI)1) << acc);
+    }
+}
+
+static void
+set_acc_use_not_media_p2 (SIM_CPU *cpu, INT acc)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (acc != -1)
+    d->cur_acc_p2 &= ~(((DI)1) << acc);
+}
+
+static int
+acc_use_is_media_p2 (SIM_CPU *cpu, INT acc)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (acc != -1)
+    return d->cur_acc_p2 & (((DI)1) << acc);
+  return 0;
+}
+
+static void
+set_use_is_media_p4 (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    {
+      fr400_reset_fr_flags (cpu, fr);
+      d->cur_fr_p4 |= (((DI)1) << fr);
+    }
+}
+
+static void
+set_use_not_media_p4 (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    d->cur_fr_p4 &= ~(((DI)1) << fr);
+}
+
+static int
+use_is_media_p4 (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    return d->cur_fr_p4 & (((DI)1) << fr);
+  return 0;
+}
+
+static void
+set_acc_use_is_media_p4 (SIM_CPU *cpu, INT acc)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (acc != -1)
+    {
+      fr400_reset_acc_flags (cpu, acc);
+      d->cur_acc_p4 |= (((DI)1) << acc);
+    }
+}
+
+static void
+set_acc_use_not_media_p4 (SIM_CPU *cpu, INT acc)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (acc != -1)
+    d->cur_acc_p4 &= ~(((DI)1) << acc);
+}
+
+static int
+acc_use_is_media_p4 (SIM_CPU *cpu, INT acc)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (acc != -1)
+    return d->cur_acc_p4 & (((DI)1) << acc);
+  return 0;
+}
+
+static void
+set_use_is_media_p6 (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    {
+      fr400_reset_fr_flags (cpu, fr);
+      d->cur_fr_p6 |= (((DI)1) << fr);
+    }
+}
+
+static void
+set_use_not_media_p6 (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    d->cur_fr_p6 &= ~(((DI)1) << fr);
+}
+
+static int
+use_is_media_p6 (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+  if (fr != -1)
+    return d->cur_fr_p6 & (((DI)1) << fr);
+  return 0;
+}
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+void
+fr400_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+  if (first_p)
+    {
+      MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      ps->cur_gr_complex = ps->prev_gr_complex;
+      d->cur_fp_load = d->prev_fp_load;
+      d->cur_fr_p4 = d->prev_fr_p4;
+      d->cur_fr_p6 = d->prev_fr_p6;
+      d->cur_acc_p2 = d->prev_acc_p2;
+      d->cur_acc_p4 = d->prev_acc_p4;
+    }
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+void
+fr400_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+  if (last_p)
+    {
+      MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu);
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      ps->prev_gr_complex = ps->cur_gr_complex;
+      d->prev_fp_load = d->cur_fp_load;
+      d->prev_fr_p4 = d->cur_fr_p4;
+      d->prev_fr_p6 = d->cur_fr_p6;
+      d->prev_acc_p2 = d->cur_acc_p2;
+      d->prev_acc_p4 = d->cur_acc_p4;
+    }
+}
+
+int
+frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_GRi, INT in_GRj, INT out_GRk,
+			     INT out_ICCi_1)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced,
+				      in_GRi, in_GRj, out_GRk, out_ICCi_1);
+}
+
+int
+frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced,
+				   in_GRi, in_GRj, out_GRk, out_ICCi_1);
+}
+
+int
+frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+  int cycles;
+  FRV_VLIW *vliw;
+  int slot;
+
+  /* icc0-icc4 are the upper 4 fields of the CCR.  */
+  if (out_ICCi_1 >= 0)
+    out_ICCi_1 += 4;
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  slot = (*vliw->current_vliw)[slot] - UNIT_I0;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi != out_GRk && in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_GR (cpu, out_GRk);
+      vliw_wait_for_CCR (cpu, out_ICCi_1);
+      vliw_wait_for_idiv_resource (cpu, slot);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_GR (cpu, out_GRk);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* GRk has a latency of 19 cycles!  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_GR_latency (cpu, out_GRk, cycles + 19);
+  set_use_is_gr_complex (cpu, out_GRk);
+
+  /* ICCi_1 has a latency of 18 cycles.  */
+  update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
+
+  /* the idiv resource has a latency of 18 cycles!  */
+  update_idiv_resource_latency (cpu, slot, cycles + 18);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_GRi, INT in_GRj,
+			    INT in_ICCi_2, INT in_ICCi_3)
+{
+#define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2)
+  FRV_PROFILE_STATE *ps;
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* Modelling for this unit is the same as for fr500 in pass 1.  */
+      return frvbf_model_fr500_u_branch (cpu, idesc, unit_num, referenced,
+					 in_GRi, in_GRj, in_ICCi_2, in_ICCi_3);
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* Compute the branch penalty, based on the the prediction and the out
+     come.  When counting branches taken or not taken, don't consider branches
+     after the first taken branch in a vliw insn.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  if (! ps->vliw_branch_taken)
+    {
+      int penalty;
+      /* (1 << 4): The pc is the 5th element in inputs, outputs.
+	 ??? can be cleaned up */
+      PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+      int taken = (referenced & (1 << 4)) != 0;
+      if (taken)
+	{
+	  ++PROFILE_MODEL_TAKEN_COUNT (p);
+	  ps->vliw_branch_taken = 1;
+	  if (BRANCH_PREDICTED (ps))
+	    penalty = 1;
+	  else
+	    penalty = 3;
+	}
+      else
+	{
+	  ++PROFILE_MODEL_UNTAKEN_COUNT (p);
+	  if (BRANCH_PREDICTED (ps))
+	    penalty = 3;
+	  else
+	    penalty = 0;
+	}
+      if (penalty > 0)
+	{
+	  /* Additional 1 cycle penalty if the branch address is not 8 byte
+	     aligned.  */
+	  if (ps->branch_address & 7)
+	    ++penalty;
+	  update_branch_penalty (cpu, penalty);
+	  PROFILE_MODEL_CTI_STALL_CYCLES (p) += penalty;
+	}
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj,
+			  INT in_ICCi_2, INT in_FCCi_2)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced,
+				   in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+}
+
+int
+frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_ICCi_3, INT in_FCCi_3)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
+				    in_ICCi_3, in_FCCi_3);
+}
+
+int
+frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT out_GRkhi, INT out_GRklo)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced,
+				       out_GRkhi, out_GRklo);
+}
+
+int
+frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_GRi, INT in_GRj,
+			     INT out_GRk, INT out_GRdoublek)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_gr_load (cpu, idesc, unit_num, referenced,
+				      in_GRi, in_GRj, out_GRk, out_GRdoublek);
+}
+
+int
+frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
+			      int unit_num, int referenced,
+			      INT in_GRi, INT in_GRj,
+			      INT in_GRk, INT in_GRdoublek)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
+				       in_GRi, in_GRj, in_GRk, in_GRdoublek);
+}
+
+int
+frvbf_model_fr400_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_GRi, INT in_GRj,
+			     INT out_FRk, INT out_FRdoublek)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* Pass 1 is the same as for fr500.  */
+      return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced,
+					  in_GRi, in_GRj, out_FRk,
+					  out_FRdoublek);
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The latency of FRk for a load will depend on how long it takes to retrieve
+     the the data from the cache or memory.  */
+  update_FR_latency_for_load (cpu, out_FRk, cycles);
+  update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
+
+  set_use_is_fp_load (cpu, out_FRk, out_FRdoublek);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
+			      int unit_num, int referenced,
+			      INT in_GRi, INT in_GRj,
+			      INT in_FRk, INT in_FRdoublek)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      if (in_FRk >= 0)
+	{
+	  if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk))
+	    decrease_FR_busy (cpu, in_FRk, 1);
+	  else
+	    enforce_full_fr_latency (cpu, in_FRk);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_FR (cpu, in_FRk);
+      vliw_wait_for_FRdouble (cpu, in_FRdoublek);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_FR (cpu, in_FRk);
+      load_wait_for_FRdouble (cpu, in_FRdoublek);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_swap (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj, INT out_GRk)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced,
+				   in_GRi, in_GRj, out_GRk);
+}
+
+int
+frvbf_model_fr400_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_FRk, INT out_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_FRk >= 0)
+	{
+	  if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk))
+	    decrease_FR_busy (cpu, in_FRk, 1);
+	  else
+	    enforce_full_fr_latency (cpu, in_FRk);
+	}
+      vliw_wait_for_FR (cpu, in_FRk);
+      vliw_wait_for_GR (cpu, out_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_FR (cpu, in_FRk);
+      load_wait_for_GR (cpu, out_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* The latency of GRj is 2 cycles.  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_GR_latency (cpu, out_GRj, cycles + 2);
+  set_use_is_gr_complex (cpu, out_GRj);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_spr, INT out_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
+				     in_spr, out_GRj);
+}
+
+int
+frvbf_model_fr400_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_GRj, INT out_FRk)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* Pass 1 is the same as for fr500.  */
+      frvbf_model_fr500_u_gr2fr (cpu, idesc, unit_num, referenced,
+				 in_GRj, out_FRk);
+    }
+
+  /* The latency of FRk is 1 cycles.  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_FR_latency (cpu, out_FRk, cycles + 1);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_GRj, INT out_spr)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced,
+				     in_GRj, out_spr);
+}
+
+/* Top up the post-processing time of the given FR by the given number of
+   cycles.  */
+static void
+update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* If a load is pending on this register, then add the cycles to
+	 the post processing time for this register. Otherwise apply it
+	 directly to the latency of the register.  */
+      if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
+	{
+	  int *fr = ps->fr_latency;
+	  fr[out_FR] += cycles;
+	}
+      else
+	ps->fr_ptime[out_FR] += cycles;
+    }
+}
+
+static void
+update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* If a load is pending on this register, then add the cycles to
+	 the post processing time for this register. Otherwise apply it
+	 directly to the latency of the register.  */
+      if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
+	{
+	  int *fr = ps->fr_latency;
+	  fr[out_FR] += cycles;
+	  if (out_FR < 63)
+	    fr[out_FR + 1] += cycles;
+	}
+      else
+	{
+	  /* On the fr400, loads are available to media insns one cycle early,
+	     so knock one cycle off the post processing time to account for
+	     this.  */
+	  ps->fr_ptime[out_FR] += cycles - 1;
+	  if (out_FR < 63)
+	    ps->fr_ptime[out_FR + 1] += cycles - 1;
+	}
+    }
+}
+
+int
+frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_FRi, INT in_FRj,
+			     INT out_FRk)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+  const CGEN_INSN *insn;
+  int busy_adjustment[] = {0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  insn = idesc->idata;
+
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (in_FRi >= 0)
+    {
+      if (use_is_fp_load (cpu, in_FRi))
+	{
+	  busy_adjustment[0] = 1;
+	  decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRi);
+    }
+  if (in_FRj >= 0 && in_FRj != in_FRi)
+    {
+      if (use_is_fp_load (cpu, in_FRj))
+	{
+	  busy_adjustment[1] = 1;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  if (in_FRi >= 0)
+    fr[in_FRi] += busy_adjustment[0];
+  if (in_FRj >= 0)
+    fr[in_FRj] += busy_adjustment[1];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing has no latency.  */
+  if (out_FRk >= 0)
+    {
+      update_FR_latency (cpu, out_FRk, ps->post_wait);
+      update_FR_ptime (cpu, out_FRk, 0);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
+				  int unit_num, int referenced,
+				  INT in_FRi, INT in_FRj,
+				  INT out_FRk)
+{
+  int cycles;
+  INT dual_FRi;
+  INT dual_FRj;
+  INT dual_FRk;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  dual_FRi = DUAL_REG (in_FRi);
+  dual_FRj = DUAL_REG (in_FRj);
+  dual_FRk = DUAL_REG (out_FRk);
+
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (use_is_fp_load (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 1;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi))
+    {
+      busy_adjustment[1] = 1;
+      decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
+    }
+  else
+    enforce_full_fr_latency (cpu, dual_FRi);
+  if (in_FRj != in_FRi)
+    {
+      if (use_is_fp_load (cpu, in_FRj))
+	{
+	  busy_adjustment[2] = 1;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+      if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj))
+	{
+	  busy_adjustment[3] = 1;
+	  decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
+	}
+      else
+	enforce_full_fr_latency (cpu, dual_FRj);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, dual_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, dual_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  if (dual_FRi >= 0)
+    fr[dual_FRi] += busy_adjustment[1];
+  fr[in_FRj] += busy_adjustment[2];
+  if (dual_FRj >= 0)
+    fr[dual_FRj] += busy_adjustment[3];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+
+  /* Once initiated, post-processing has no latency.  */
+  update_FR_ptime (cpu, out_FRk, 0);
+
+  if (dual_FRk >= 0)
+    {
+      update_FR_latency (cpu, dual_FRk, ps->post_wait);
+      update_FR_ptime (cpu, dual_FRk, 0);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
+				int unit_num, int referenced,
+				INT out_FRkhi, INT out_FRklo)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, out_FRkhi);
+  post_wait_for_FR (cpu, out_FRklo);
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing has no latency.  */
+  if (out_FRkhi >= 0)
+    {
+      update_FR_latency (cpu, out_FRkhi, ps->post_wait);
+      update_FR_ptime (cpu, out_FRkhi, 0);
+    }
+  if (out_FRklo >= 0)
+    {
+      update_FR_latency (cpu, out_FRklo, ps->post_wait);
+      update_FR_ptime (cpu, out_FRklo, 0);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_FRi, INT in_FRj,
+			     INT out_ACC40Sk, INT out_ACC40Uk)
+{
+  int cycles;
+  INT dual_ACC40Sk;
+  INT dual_ACC40Uk;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
+  int *fr;
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  dual_ACC40Sk = DUAL_REG (out_ACC40Sk);
+  dual_ACC40Uk = DUAL_REG (out_ACC40Uk);
+
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (in_FRi >= 0)
+    {
+      if (use_is_fp_load (cpu, in_FRi))
+	{
+	  busy_adjustment[0] = 1;
+	  decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRi);
+    }
+  if (in_FRj >= 0 && in_FRj != in_FRi)
+    {
+      if (use_is_fp_load (cpu, in_FRj))
+	{
+	  busy_adjustment[1] = 1;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+    }
+  if (out_ACC40Sk >= 0)
+    {
+      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
+	{
+	  busy_adjustment[2] = 1;
+	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
+	}
+    }
+  if (dual_ACC40Sk >= 0)
+    {
+      if (acc_use_is_media_p2 (cpu, dual_ACC40Sk))
+	{
+	  busy_adjustment[3] = 1;
+	  decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]);
+	}
+    }
+  if (out_ACC40Uk >= 0)
+    {
+      if (acc_use_is_media_p2 (cpu, out_ACC40Uk))
+	{
+	  busy_adjustment[4] = 1;
+	  decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
+	}
+    }
+  if (dual_ACC40Uk >= 0)
+    {
+      if (acc_use_is_media_p2 (cpu, dual_ACC40Uk))
+	{
+	  busy_adjustment[5] = 1;
+	  decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, dual_ACC40Sk);
+  post_wait_for_ACC (cpu, out_ACC40Uk);
+  post_wait_for_ACC (cpu, dual_ACC40Uk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  acc = ps->acc_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  fr[in_FRj] += busy_adjustment[1];
+  if (out_ACC40Sk >= 0)
+    acc[out_ACC40Sk] += busy_adjustment[2];
+  if (dual_ACC40Sk >= 0)
+    acc[dual_ACC40Sk] += busy_adjustment[3];
+  if (out_ACC40Uk >= 0)
+    acc[out_ACC40Uk] += busy_adjustment[4];
+  if (dual_ACC40Uk >= 0)
+    acc[dual_ACC40Uk] += busy_adjustment[5];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycles.  */
+  if (out_ACC40Sk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
+    }
+  if (dual_ACC40Sk >= 0)
+    {
+      update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, dual_ACC40Sk);
+    }
+  if (out_ACC40Uk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, out_ACC40Uk);
+    }
+  if (dual_ACC40Uk >= 0)
+    {
+      update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, dual_ACC40Uk);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
+				  int unit_num, int referenced,
+				  INT in_FRi, INT in_FRj,
+				  INT out_ACC40Sk, INT out_ACC40Uk)
+{
+  int cycles;
+  INT dual_FRi;
+  INT dual_FRj;
+  INT ACC40Sk_1;
+  INT ACC40Sk_2;
+  INT ACC40Sk_3;
+  INT ACC40Uk_1;
+  INT ACC40Uk_2;
+  INT ACC40Uk_3;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0};
+  int *fr;
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  dual_FRi = DUAL_REG (in_FRi);
+  dual_FRj = DUAL_REG (in_FRj);
+  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+  ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
+  ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
+  ACC40Uk_1 = DUAL_REG (out_ACC40Uk);
+  ACC40Uk_2 = DUAL_REG (ACC40Uk_1);
+  ACC40Uk_3 = DUAL_REG (ACC40Uk_2);
+
+  ps = CPU_PROFILE_STATE (cpu);
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (use_is_fp_load (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 1;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi))
+    {
+      busy_adjustment[1] = 1;
+      decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
+    }
+  else
+    enforce_full_fr_latency (cpu, dual_FRi);
+  if (in_FRj != in_FRi)
+    {
+      if (use_is_fp_load (cpu, in_FRj))
+	{
+	  busy_adjustment[2] = 1;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+      if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj))
+	{
+	  busy_adjustment[3] = 1;
+	  decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
+	}
+      else
+	enforce_full_fr_latency (cpu, dual_FRj);
+    }
+  if (out_ACC40Sk >= 0)
+    {
+      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
+	{
+	  busy_adjustment[4] = 1;
+	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
+	}
+      if (ACC40Sk_1 >= 0)
+	{
+	  if (acc_use_is_media_p2 (cpu, ACC40Sk_1))
+	    {
+	      busy_adjustment[5] = 1;
+	      decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
+	    }
+	}
+      if (ACC40Sk_2 >= 0)
+	{
+	  if (acc_use_is_media_p2 (cpu, ACC40Sk_2))
+	    {
+	      busy_adjustment[6] = 1;
+	      decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
+	    }
+	}
+      if (ACC40Sk_3 >= 0)
+	{
+	  if (acc_use_is_media_p2 (cpu, ACC40Sk_3))
+	    {
+	      busy_adjustment[7] = 1;
+	      decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
+	    }
+	}
+    }
+  else if (out_ACC40Uk >= 0)
+    {
+      if (acc_use_is_media_p2 (cpu, out_ACC40Uk))
+	{
+	  busy_adjustment[4] = 1;
+	  decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
+	}
+      if (ACC40Uk_1 >= 0)
+	{
+	  if (acc_use_is_media_p2 (cpu, ACC40Uk_1))
+	    {
+	      busy_adjustment[5] = 1;
+	      decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]);
+	    }
+	}
+      if (ACC40Uk_2 >= 0)
+	{
+	  if (acc_use_is_media_p2 (cpu, ACC40Uk_2))
+	    {
+	      busy_adjustment[6] = 1;
+	      decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]);
+	    }
+	}
+      if (ACC40Uk_3 >= 0)
+	{
+	  if (acc_use_is_media_p2 (cpu, ACC40Uk_3))
+	    {
+	      busy_adjustment[7] = 1;
+	      decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]);
+	    }
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, dual_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, ACC40Sk_1);
+  post_wait_for_ACC (cpu, ACC40Sk_2);
+  post_wait_for_ACC (cpu, ACC40Sk_3);
+  post_wait_for_ACC (cpu, out_ACC40Uk);
+  post_wait_for_ACC (cpu, ACC40Uk_1);
+  post_wait_for_ACC (cpu, ACC40Uk_2);
+  post_wait_for_ACC (cpu, ACC40Uk_3);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  acc = ps->acc_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  if (dual_FRi >= 0)
+    fr[dual_FRi] += busy_adjustment[1];
+  fr[in_FRj] += busy_adjustment[2];
+  if (dual_FRj > 0)
+    fr[dual_FRj] += busy_adjustment[3];
+  if (out_ACC40Sk >= 0)
+    {
+      acc[out_ACC40Sk] += busy_adjustment[4];
+      if (ACC40Sk_1 >= 0)
+	acc[ACC40Sk_1] += busy_adjustment[5];
+      if (ACC40Sk_2 >= 0)
+	acc[ACC40Sk_2] += busy_adjustment[6];
+      if (ACC40Sk_3 >= 0)
+	acc[ACC40Sk_3] += busy_adjustment[7];
+    }
+  else if (out_ACC40Uk >= 0)
+    {
+      acc[out_ACC40Uk] += busy_adjustment[4];
+      if (ACC40Uk_1 >= 0)
+	acc[ACC40Uk_1] += busy_adjustment[5];
+      if (ACC40Uk_2 >= 0)
+	acc[ACC40Uk_2] += busy_adjustment[6];
+      if (ACC40Uk_3 >= 0)
+	acc[ACC40Uk_3] += busy_adjustment[7];
+    }
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_ACC40Sk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+
+      set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
+      if (ACC40Sk_1 >= 0)
+	{
+	  update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+
+	  set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
+	}
+      if (ACC40Sk_2 >= 0)
+	{
+	  update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
+
+	  set_acc_use_is_media_p2 (cpu, ACC40Sk_2);
+	}
+      if (ACC40Sk_3 >= 0)
+	{
+	  update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
+
+	  set_acc_use_is_media_p2 (cpu, ACC40Sk_3);
+	}
+    }
+  else if (out_ACC40Uk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
+
+      set_acc_use_is_media_p2 (cpu, out_ACC40Uk);
+      if (ACC40Uk_1 >= 0)
+	{
+	  update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);
+
+	  set_acc_use_is_media_p2 (cpu, ACC40Uk_1);
+	}
+      if (ACC40Uk_2 >= 0)
+	{
+	  update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);
+
+	  set_acc_use_is_media_p2 (cpu, ACC40Uk_2);
+	}
+      if (ACC40Uk_3 >= 0)
+	{
+	  update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);
+
+	  set_acc_use_is_media_p2 (cpu, ACC40Uk_3);
+	}
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
+				 int unit_num, int referenced,
+				 INT in_ACC40Si, INT out_ACC40Sk)
+{
+  int cycles;
+  INT ACC40Si_1;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0};
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ACC40Si_1 = DUAL_REG (in_ACC40Si);
+
+  ps = CPU_PROFILE_STATE (cpu);
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
+    {
+      busy_adjustment[0] = 1;
+      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
+    }
+  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
+    {
+      busy_adjustment[1] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
+    }
+  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1
+      && acc_use_is_media_p2 (cpu, out_ACC40Sk))
+    {
+      busy_adjustment[2] = 1;
+      decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
+    }
+
+  /* The post processing must wait if there is a dependency on a register
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_ACC (cpu, in_ACC40Si);
+  post_wait_for_ACC (cpu, ACC40Si_1);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  acc = ps->acc_busy;
+  acc[in_ACC40Si] += busy_adjustment[0];
+  if (ACC40Si_1 >= 0)
+    acc[ACC40Si_1] += busy_adjustment[1];
+  acc[out_ACC40Sk] += busy_adjustment[2];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
+				      int unit_num, int referenced,
+				      INT in_ACC40Si, INT out_ACC40Sk)
+{
+  int cycles;
+  INT ACC40Si_1;
+  INT ACC40Si_2;
+  INT ACC40Si_3;
+  INT ACC40Sk_1;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ACC40Si_1 = DUAL_REG (in_ACC40Si);
+  ACC40Si_2 = DUAL_REG (ACC40Si_1);
+  ACC40Si_3 = DUAL_REG (ACC40Si_2);
+  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+
+  ps = CPU_PROFILE_STATE (cpu);
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
+    {
+      busy_adjustment[0] = 1;
+      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
+    }
+  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
+    {
+      busy_adjustment[1] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
+    }
+  if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2))
+    {
+      busy_adjustment[2] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]);
+    }
+  if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3))
+    {
+      busy_adjustment[3] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]);
+    }
+  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1
+      && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3)
+    {
+      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
+	{
+	  busy_adjustment[4] = 1;
+	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
+	}
+    }
+  if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1
+      && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3)
+    {
+      if (acc_use_is_media_p2 (cpu, ACC40Sk_1))
+	{
+	  busy_adjustment[5] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a register
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_ACC (cpu, in_ACC40Si);
+  post_wait_for_ACC (cpu, ACC40Si_1);
+  post_wait_for_ACC (cpu, ACC40Si_2);
+  post_wait_for_ACC (cpu, ACC40Si_3);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, ACC40Sk_1);
+
+  /* Restore the busy cycles of the registers we used.  */
+  acc = ps->acc_busy;
+  acc[in_ACC40Si] += busy_adjustment[0];
+  if (ACC40Si_1 >= 0)
+    acc[ACC40Si_1] += busy_adjustment[1];
+  if (ACC40Si_2 >= 0)
+    acc[ACC40Si_2] += busy_adjustment[2];
+  if (ACC40Si_3 >= 0)
+    acc[ACC40Si_3] += busy_adjustment[3];
+  acc[out_ACC40Sk] += busy_adjustment[4];
+  if (ACC40Sk_1 >= 0)
+    acc[ACC40Sk_1] += busy_adjustment[5];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
+  if (ACC40Sk_1 >= 0)
+    {
+      update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
+				     int unit_num, int referenced,
+				     INT in_ACC40Si, INT out_ACC40Sk)
+{
+  int cycles;
+  INT ACC40Si_1;
+  INT ACC40Sk_1;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0};
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ACC40Si_1 = DUAL_REG (in_ACC40Si);
+  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+
+  ps = CPU_PROFILE_STATE (cpu);
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
+    {
+      busy_adjustment[0] = 1;
+      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
+    }
+  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
+    {
+      busy_adjustment[1] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
+    }
+  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1)
+    {
+      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
+	{
+	  busy_adjustment[2] = 1;
+	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
+	}
+    }
+  if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1)
+    {
+      if (acc_use_is_media_p2 (cpu, ACC40Sk_1))
+	{
+	  busy_adjustment[3] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[3]);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a register
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_ACC (cpu, in_ACC40Si);
+  post_wait_for_ACC (cpu, ACC40Si_1);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, ACC40Sk_1);
+
+  /* Restore the busy cycles of the registers we used.  */
+  acc = ps->acc_busy;
+  acc[in_ACC40Si] += busy_adjustment[0];
+  if (ACC40Si_1 >= 0)
+    acc[ACC40Si_1] += busy_adjustment[1];
+  acc[out_ACC40Sk] += busy_adjustment[2];
+  if (ACC40Sk_1 >= 0)
+    acc[ACC40Sk_1] += busy_adjustment[3];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
+  if (ACC40Sk_1 >= 0)
+    {
+      update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
+					  int unit_num, int referenced,
+					  INT in_ACC40Si, INT out_ACC40Sk)
+{
+  int cycles;
+  INT ACC40Si_1;
+  INT ACC40Si_2;
+  INT ACC40Si_3;
+  INT ACC40Sk_1;
+  INT ACC40Sk_2;
+  INT ACC40Sk_3;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ACC40Si_1 = DUAL_REG (in_ACC40Si);
+  ACC40Si_2 = DUAL_REG (ACC40Si_1);
+  ACC40Si_3 = DUAL_REG (ACC40Si_2);
+  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+  ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
+  ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
+
+  ps = CPU_PROFILE_STATE (cpu);
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (acc_use_is_media_p2 (cpu, in_ACC40Si))
+    {
+      busy_adjustment[0] = 1;
+      decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]);
+    }
+  if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1))
+    {
+      busy_adjustment[1] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]);
+    }
+  if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2))
+    {
+      busy_adjustment[2] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]);
+    }
+  if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3))
+    {
+      busy_adjustment[3] = 1;
+      decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]);
+    }
+  if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1
+      && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3)
+    {
+      if (acc_use_is_media_p2 (cpu, out_ACC40Sk))
+	{
+	  busy_adjustment[4] = 1;
+	  decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
+	}
+    }
+  if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1
+      && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3)
+    {
+      if (acc_use_is_media_p2 (cpu, ACC40Sk_1))
+	{
+	  busy_adjustment[5] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
+	}
+    }
+  if (ACC40Sk_2 != in_ACC40Si && ACC40Sk_2 != ACC40Si_1
+      && ACC40Sk_2 != ACC40Si_2 && ACC40Sk_2 != ACC40Si_3)
+    {
+      if (acc_use_is_media_p2 (cpu, ACC40Sk_2))
+	{
+	  busy_adjustment[6] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
+	}
+    }
+  if (ACC40Sk_3 != in_ACC40Si && ACC40Sk_3 != ACC40Si_1
+      && ACC40Sk_3 != ACC40Si_2 && ACC40Sk_3 != ACC40Si_3)
+    {
+      if (acc_use_is_media_p2 (cpu, ACC40Sk_3))
+	{
+	  busy_adjustment[7] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a register
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_ACC (cpu, in_ACC40Si);
+  post_wait_for_ACC (cpu, ACC40Si_1);
+  post_wait_for_ACC (cpu, ACC40Si_2);
+  post_wait_for_ACC (cpu, ACC40Si_3);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, ACC40Sk_1);
+  post_wait_for_ACC (cpu, ACC40Sk_2);
+  post_wait_for_ACC (cpu, ACC40Sk_3);
+
+  /* Restore the busy cycles of the registers we used.  */
+  acc = ps->acc_busy;
+  acc[in_ACC40Si] += busy_adjustment[0];
+  if (ACC40Si_1 >= 0)
+    acc[ACC40Si_1] += busy_adjustment[1];
+  if (ACC40Si_2 >= 0)
+    acc[ACC40Si_2] += busy_adjustment[2];
+  if (ACC40Si_3 >= 0)
+    acc[ACC40Si_3] += busy_adjustment[3];
+  acc[out_ACC40Sk] += busy_adjustment[4];
+  if (ACC40Sk_1 >= 0)
+    acc[ACC40Sk_1] += busy_adjustment[5];
+  if (ACC40Sk_2 >= 0)
+    acc[ACC40Sk_2] += busy_adjustment[6];
+  if (ACC40Sk_3 >= 0)
+    acc[ACC40Sk_3] += busy_adjustment[7];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+  set_acc_use_is_media_p2 (cpu, out_ACC40Sk);
+  if (ACC40Sk_1 >= 0)
+    {
+      update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, ACC40Sk_1);
+    }
+  if (ACC40Sk_2 >= 0)
+    {
+      update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, ACC40Sk_2);
+    }
+  if (ACC40Sk_3 >= 0)
+    {
+      update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
+      set_acc_use_is_media_p2 (cpu, ACC40Sk_3);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_FRi, INT in_FRj,
+			     INT out_FRk)
+{
+  /* Modelling is the same as media unit 1.  */
+  return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
+				      in_FRi, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr400_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
+				  int unit_num, int referenced,
+				  INT in_FRi, INT out_FRk)
+{
+  int cycles;
+  INT dual_FRi;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  dual_FRi = DUAL_REG (in_FRi);
+
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (use_is_fp_load (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 1;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi))
+    {
+      busy_adjustment[1] = 1;
+      decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
+    }
+  else
+    enforce_full_fr_latency (cpu, dual_FRi);
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, dual_FRi);
+  post_wait_for_FR (cpu, out_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  if (dual_FRi >= 0)
+    fr[dual_FRi] += busy_adjustment[1];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+
+  /* Once initiated, post-processing has no latency.  */
+  update_FR_ptime (cpu, out_FRk, 0);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
+				  int unit_num, int referenced,
+				  INT in_FRi, INT in_FRj,
+				  INT out_FRk)
+{
+  /* Modelling is the same as media unit 1.  */
+  return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
+					   in_FRi, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_ACC40Si, INT in_FRj,
+			     INT out_ACC40Sk, INT out_FRk)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+  const CGEN_INSN *insn;
+  int busy_adjustment[] = {0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  insn = idesc->idata;
+
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (in_FRj >= 0)
+    {
+      if (use_is_fp_load (cpu, in_FRj))
+	{
+	  busy_adjustment[0] = 1;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_ACC (cpu, in_ACC40Si);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_FRk >= 0)
+    {
+      update_FR_latency (cpu, out_FRk, ps->post_wait);
+      update_FR_ptime (cpu, out_FRk, 1);
+      /* Mark this use of the register as media unit 4.  */
+      set_use_is_media_p4 (cpu, out_FRk);
+    }
+  else if (out_ACC40Sk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait);
+      update_ACC_ptime (cpu, out_ACC40Sk, 1);
+      /* Mark this use of the register as media unit 4.  */
+      set_acc_use_is_media_p4 (cpu, out_ACC40Sk);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
+				  int unit_num, int referenced,
+				  INT in_ACCGi, INT in_FRinti,
+				  INT out_ACCGk, INT out_FRintk)
+{
+  /* Modelling is the same as media-4 unit except use accumulator guards
+     as input instead of accumulators.  */
+  return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
+				      in_ACCGi, in_FRinti,
+				      out_ACCGk, out_FRintk);
+}
+
+int
+frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
+				      int unit_num, int referenced,
+				      INT in_ACC40Si, INT out_FRk)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+  const CGEN_INSN *insn;
+  INT ACC40Si_1;
+  INT FRk_1;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  ACC40Si_1 = DUAL_REG (in_ACC40Si);
+  FRk_1 = DUAL_REG (out_FRk);
+
+  insn = idesc->idata;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_ACC (cpu, in_ACC40Si);
+  post_wait_for_ACC (cpu, ACC40Si_1);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, FRk_1);
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_FRk >= 0)
+    {
+      update_FR_latency (cpu, out_FRk, ps->post_wait);
+      update_FR_ptime (cpu, out_FRk, 1);
+      /* Mark this use of the register as media unit 4.  */
+      set_use_is_media_p4 (cpu, out_FRk);
+    }
+  if (FRk_1 >= 0)
+    {
+      update_FR_latency (cpu, FRk_1, ps->post_wait);
+      update_FR_ptime (cpu, FRk_1, 1);
+      /* Mark this use of the register as media unit 4.  */
+      set_use_is_media_p4 (cpu, FRk_1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_FRi, INT out_FRk)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+  const CGEN_INSN *insn;
+  int busy_adjustment[] = {0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  insn = idesc->idata;
+
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (in_FRi >= 0)
+    {
+      if (use_is_fp_load (cpu, in_FRi))
+	{
+	  busy_adjustment[0] = 1;
+	  decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRi);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, out_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  if (in_FRi >= 0)
+    fr[in_FRi] += busy_adjustment[0];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_FRk >= 0)
+    {
+      update_FR_latency (cpu, out_FRk, ps->post_wait);
+      update_FR_ptime (cpu, out_FRk, 1);
+
+      /* Mark this use of the register as media unit 1.  */
+      set_use_is_media_p6 (cpu, out_FRk);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_FRinti, INT in_FRintj,
+			     INT out_FCCk)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps = CPU_PROFILE_STATE (cpu);
+
+  /* The latency of the registers may be less than previously recorded,
+     depending on how they were used previously.
+     See Table 13-8 in the LSI.  */
+  if (in_FRinti >= 0)
+    {
+      if (use_is_fp_load (cpu, in_FRinti))
+	{
+	  busy_adjustment[0] = 1;
+	  decrease_FR_busy (cpu, in_FRinti, busy_adjustment[0]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRinti);
+    }
+  if (in_FRintj >= 0 && in_FRintj != in_FRinti)
+    {
+      if (use_is_fp_load (cpu, in_FRintj))
+	{
+	  busy_adjustment[1] = 1;
+	  decrease_FR_busy (cpu, in_FRintj, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRintj);
+    }
+
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRinti);
+  post_wait_for_FR (cpu, in_FRintj);
+  post_wait_for_CCR (cpu, out_FCCk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  if (in_FRinti >= 0)
+    fr[in_FRinti] += busy_adjustment[0];
+  if (in_FRintj >= 0)
+    fr[in_FRintj] += busy_adjustment[1];
+
+  /* The latency of FCCi_2 will be the latency of the other inputs plus 1
+     cycle.  */
+  update_CCR_latency (cpu, out_FCCk, ps->post_wait + 1);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
+				       int unit_num, int referenced,
+				       INT in_FRi,
+				       INT out_FRk)
+{
+  /* Insns using this unit are media-3 class insns, with a dual FRk output.  */
+  int cycles;
+  INT dual_FRk;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  dual_FRk = DUAL_REG (out_FRk);
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_fp_load (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 1;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, dual_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRi] += busy_adjustment[0];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing has no latency.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_ptime (cpu, out_FRk, 0);
+
+  if (dual_FRk >= 0)
+    {
+      update_FR_latency (cpu, dual_FRk, ps->post_wait);
+      update_FR_ptime (cpu, dual_FRk, 0);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
+				     int unit_num, int referenced,
+				     INT in_FRj,
+				     INT out_FRk)
+{
+  /* Insns using this unit are media-3 class insns, with a dual FRj input.  */
+  int cycles;
+  INT dual_FRj;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  dual_FRj = DUAL_REG (in_FRj);
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_fp_load (cpu, in_FRj))
+    {
+      busy_adjustment[0] = 1;
+      decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRj);
+  if (dual_FRj >= 0)
+    {
+      if (use_is_fp_load (cpu, dual_FRj))
+	{
+	  busy_adjustment[1] = 1;
+	  decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, dual_FRj);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRj] += busy_adjustment[0];
+  if (dual_FRj >= 0)
+    fr[dual_FRj] += busy_adjustment[1];
+
+  /* The latency of the output register will be at least the latency of the
+     other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+
+  /* Once initiated, post-processing has no latency.  */
+  update_FR_ptime (cpu, out_FRk, 0);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr400_u_ici (SIM_CPU *cpu, const IDESC *idesc,
+			 int unit_num, int referenced,
+			 INT in_GRi, INT in_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
+				  in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr400_u_dci (SIM_CPU *cpu, const IDESC *idesc,
+			 int unit_num, int referenced,
+			 INT in_GRi, INT in_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
+				  in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr400_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
+			 int unit_num, int referenced,
+			 INT in_GRi, INT in_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
+				  in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr400_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
+				   in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr400_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
+				   in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr400_u_icul (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
+				   in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr400_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
+				   in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr400_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
+}
+
+int
+frvbf_model_fr400_u_membar (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced)
+{
+  /* Modelling for this unit is the same as for fr500.  */
+  return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/frv/profile-fr400.h b/sim/frv/profile-fr400.h
new file mode 100644
index 00000000000..cee8cf12da1
--- /dev/null
+++ b/sim/frv/profile-fr400.h
@@ -0,0 +1,31 @@
+/* Profiling definitions for the fr400 model of the FRV simulator
+   Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef PROFILE_FR400_H
+#define PROFILE_FR400_H
+
+void fr400_model_insn_before (SIM_CPU *, int);
+void fr400_model_insn_after (SIM_CPU *, int, int);
+
+void fr400_reset_gr_flags (SIM_CPU *, INT);
+void fr400_reset_fr_flags (SIM_CPU *, INT);
+void fr400_reset_acc_flags (SIM_CPU *, INT);
+
+#endif /* PROFILE_FR400_H */
diff --git a/sim/frv/profile-fr500.c b/sim/frv/profile-fr500.c
new file mode 100644
index 00000000000..0cc8c7df274
--- /dev/null
+++ b/sim/frv/profile-fr500.c
@@ -0,0 +1,3060 @@
+/* frv simulator fr500 dependent profiling code.
+
+   Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+#if WITH_PROFILE_MODEL_P
+
+#include "profile.h"
+#include "profile-fr500.h"
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+void
+fr500_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+  if (first_p)
+    {
+      MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      ps->cur_gr_complex = ps->prev_gr_complex;
+      d->cur_fpop     = d->prev_fpop;
+      d->cur_media    = d->prev_media;
+      d->cur_cc_complex = d->prev_cc_complex;
+    }
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+void
+fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+  if (last_p)
+    {
+      MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      ps->prev_gr_complex = ps->cur_gr_complex;
+      d->prev_fpop     = d->cur_fpop;
+      d->prev_media    = d->cur_media;
+      d->prev_cc_complex = d->cur_cc_complex;
+    }
+}
+
+static void
+set_use_is_fpop (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  fr500_reset_fr_flags (cpu, (fr));
+  d->cur_fpop |=  (((DI)1) << (fr));
+}
+
+static void
+set_use_not_fpop (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  d->cur_fpop &= ~(((DI)1) << (fr));
+}
+
+static int
+use_is_fpop (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  return d->prev_fpop & (((DI)1) << (fr));
+}
+
+static void
+set_use_is_media ( SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  fr500_reset_fr_flags (cpu, (fr));
+  d->cur_media |=  (((DI)1) << (fr));
+}
+
+static void
+set_use_not_media (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  d->cur_media &= ~(((DI)1) << (fr));
+}
+
+static int
+use_is_media (SIM_CPU *cpu, INT fr)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  return d->prev_media & (((DI)1) << (fr));
+}
+
+static void
+set_use_is_cc_complex (SIM_CPU *cpu, INT cc)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  fr500_reset_cc_flags (cpu, cc);
+  d->cur_cc_complex |= (((DI)1) << (cc));
+}
+
+static void
+set_use_not_cc_complex (SIM_CPU *cpu, INT cc)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  d->cur_cc_complex &= ~(((DI)1) << (cc));
+}
+
+static int
+use_is_cc_complex (SIM_CPU *cpu, INT cc)
+{
+  MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
+  return d->prev_cc_complex &   (((DI)1) << (cc));
+}
+
+void
+fr500_reset_fr_flags (SIM_CPU *cpu, INT fr)
+{
+  set_use_not_fpop (cpu, fr);
+  set_use_not_media (cpu, fr);
+}
+
+void
+fr500_reset_cc_flags (SIM_CPU *cpu, INT cc)
+{
+  set_use_not_cc_complex (cpu, cc);
+}
+
+/* Latency of floating point registers may be less than recorded when followed
+   by another floating point insn.  */
+static void
+adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
+			    int cycles)
+{
+  /* If the registers were previously used in a floating point op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  if (in_FRi >= 0)
+    if (use_is_fpop (cpu, in_FRi))
+      decrease_FR_busy (cpu, in_FRi, cycles);
+    else
+      enforce_full_fr_latency (cpu, in_FRi);
+  
+  if (in_FRj >= 0 && in_FRj != in_FRi)
+    if (use_is_fpop (cpu, in_FRj))
+      decrease_FR_busy (cpu, in_FRj, cycles);
+    else
+      enforce_full_fr_latency (cpu, in_FRj);
+
+  if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
+    if (use_is_fpop (cpu, out_FRk))
+      decrease_FR_busy (cpu, out_FRk, cycles);
+    else
+      enforce_full_fr_latency (cpu, out_FRk);
+}
+
+/* Latency of floating point registers may be less than recorded when followed
+   by another floating point insn.  */
+static void
+adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
+			    int cycles)
+{
+  /* If the registers were previously used in a floating point op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
+  if (in_FRi >= 0)  ++in_FRi;
+  if (in_FRj >= 0)  ++in_FRj;
+  if (out_FRk >= 0) ++out_FRk;
+  adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
+}
+
+/* Latency of floating point registers is less than recorded when followed
+   by another floating point insn.  */
+static void
+restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
+			     int cycles)
+{
+  /* If the registers were previously used in a floating point op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi))
+    increase_FR_busy (cpu, in_FRi, cycles);
+  if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj))
+    increase_FR_busy (cpu, in_FRj, cycles);
+  if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk))
+    increase_FR_busy (cpu, out_FRk, cycles);
+}
+
+/* Latency of floating point registers is less than recorded when followed
+   by another floating point insn.  */
+static void
+restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
+			    int cycles)
+{
+  /* If the registers were previously used in a floating point op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
+  if (in_FRi >= 0)  ++in_FRi;
+  if (in_FRj >= 0)  ++in_FRj;
+  if (out_FRk >= 0) ++out_FRk;
+  restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
+}
+
+int
+frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_GRi, INT in_GRj, INT out_GRk,
+			     INT out_ICCi_1)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* icc0-icc4 are the upper 4 fields of the CCR.  */
+      if (out_ICCi_1 >= 0)
+	out_ICCi_1 += 4;
+
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi != out_GRk && in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_GR (cpu, out_GRk);
+      vliw_wait_for_CCR (cpu, out_ICCi_1);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_GR (cpu, out_GRk);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* GRk is available immediately to the next VLIW insn as is ICCi_1.  */
+  cycles = idesc->timing->units[unit_num].done;
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+  int cycles;
+  /* icc0-icc4 are the upper 4 fields of the CCR.  */
+  if (out_ICCi_1 >= 0)
+    out_ICCi_1 += 4;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi != out_GRk && in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_GRdouble (cpu, out_GRk);
+      vliw_wait_for_CCR (cpu, out_ICCi_1);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_GRdouble (cpu, out_GRk);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* GRk has a latency of 2 cycles.  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_GRdouble_latency (cpu, out_GRk, cycles + 2);
+  set_use_is_gr_complex (cpu, out_GRk);
+  set_use_is_gr_complex (cpu, out_GRk + 1);
+
+  /* ICCi_1 has a latency of 1 cycle.  */
+  update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+  int cycles;
+  FRV_VLIW *vliw;
+  int slot;
+
+  /* icc0-icc4 are the upper 4 fields of the CCR.  */
+  if (out_ICCi_1 >= 0)
+    out_ICCi_1 += 4;
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  slot = (*vliw->current_vliw)[slot] - UNIT_I0;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi != out_GRk && in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_GR (cpu, out_GRk);
+      vliw_wait_for_CCR (cpu, out_ICCi_1);
+      vliw_wait_for_idiv_resource (cpu, slot);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_GR (cpu, out_GRk);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* GRk has a latency of 19 cycles!  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_GR_latency (cpu, out_GRk, cycles + 19);
+  set_use_is_gr_complex (cpu, out_GRk);
+
+  /* ICCi_1 has a latency of 19 cycles.  */
+  update_CCR_latency (cpu, out_ICCi_1, cycles + 19);
+  set_use_is_cc_complex (cpu, out_ICCi_1);
+
+  /* the idiv resource has a latency of 18 cycles!  */
+  update_idiv_resource_latency (cpu, slot, cycles + 18);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_GRi, INT in_GRj,
+			    INT in_ICCi_2, INT in_FCCi_2)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* icc0-icc4 are the upper 4 fields of the CCR.  */
+      if (in_ICCi_2 >= 0)
+	in_ICCi_2 += 4;
+
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_CCR (cpu, in_ICCi_2);
+      vliw_wait_for_CCR (cpu, in_FCCi_2);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* When counting branches taken or not taken, don't consider branches after
+     the first taken branch in a vliw insn.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  if (! ps->vliw_branch_taken)
+    {
+      /* (1 << 4): The pc is the 5th element in inputs, outputs.
+	 ??? can be cleaned up */
+      PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+      int taken = (referenced & (1 << 4)) != 0;
+      if (taken)
+	{
+	  ++PROFILE_MODEL_TAKEN_COUNT (p);
+	  ps->vliw_branch_taken = 1;
+	}
+      else
+	++PROFILE_MODEL_UNTAKEN_COUNT (p);
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj,
+			  INT in_ICCi_2, INT in_FCCi_2)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* icc0-icc4 are the upper 4 fields of the CCR.  */
+      if (in_ICCi_2 >= 0)
+	in_ICCi_2 += 4;
+
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_CCR (cpu, in_ICCi_2);
+      vliw_wait_for_CCR (cpu, in_FCCi_2);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_ICCi_3, INT in_FCCi_3)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* icc0-icc4 are the upper 4 fields of the CCR.  */
+      if (in_ICCi_3 >= 0)
+	in_ICCi_3 += 4;
+
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.  */
+      vliw_wait_for_CCR (cpu, in_ICCi_3);
+      vliw_wait_for_CCR (cpu, in_FCCi_3);
+      handle_resource_wait (cpu);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT out_GRkhi, INT out_GRklo)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a GR
+	 which is not ready yet.  */
+      vliw_wait_for_GR (cpu, out_GRkhi);
+      vliw_wait_for_GR (cpu, out_GRklo);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, out_GRkhi);
+      load_wait_for_GR (cpu, out_GRklo);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* GRk is available immediately to the next VLIW insn.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  set_use_not_gr_complex (cpu, out_GRkhi);
+  set_use_not_gr_complex (cpu, out_GRklo);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_GRi, INT in_GRj,
+			     INT out_GRk, INT out_GRdoublek)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi != out_GRk && in_GRi != out_GRdoublek
+	  && in_GRi != out_GRdoublek + 1 && in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek
+	  && in_GRj != out_GRdoublek + 1 && in_GRj >= 0)
+
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_GR (cpu, out_GRk);
+      vliw_wait_for_GRdouble (cpu, out_GRdoublek);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_GR (cpu, out_GRk);
+      load_wait_for_GRdouble (cpu, out_GRdoublek);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The latency of GRk for a load will depend on how long it takes to retrieve
+     the the data from the cache or memory.  */
+  update_GR_latency_for_load (cpu, out_GRk, cycles);
+  update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
+
+  set_use_is_gr_complex (cpu, out_GRk);
+  set_use_is_gr_complex (cpu, out_GRdoublek);
+  set_use_is_gr_complex (cpu, out_GRdoublek + 1);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
+			      int unit_num, int referenced,
+			      INT in_GRi, INT in_GRj,
+			      INT in_GRk, INT in_GRdoublek)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRk))
+	    decrease_GR_busy (cpu, in_GRk, 1);
+	}
+      if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj
+          && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj
+	  && in_GRdoublek >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRdoublek))
+	    decrease_GR_busy (cpu, in_GRdoublek, 1);
+	  if (use_is_gr_complex (cpu, in_GRdoublek + 1))
+	    decrease_GR_busy (cpu, in_GRdoublek + 1, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_GR (cpu, in_GRk);
+      vliw_wait_for_GRdouble (cpu, in_GRdoublek);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_GR (cpu, in_GRk);
+      load_wait_for_GRdouble (cpu, in_GRdoublek);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc,
+				int unit_num, int referenced,
+				INT in_GRi, INT in_GRj,
+				INT in_GRk, INT in_GRdoublek)
+{
+  int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
+					     in_GRi, in_GRj, in_GRk,
+					     in_GRdoublek);
+
+  if (model_insn == FRV_INSN_MODEL_PASS_2)
+    {
+      if (CPU_RSTR_INVALIDATE(cpu))
+	request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_GRi, INT in_GRj,
+			     INT out_FRk, INT out_FRdoublek)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      if (out_FRk >= 0)
+	{
+	  if (use_is_media (cpu, out_FRk))
+	    decrease_FR_busy (cpu, out_FRk, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
+	}
+      if (out_FRdoublek >= 0)
+	{
+	  if (use_is_media (cpu, out_FRdoublek))
+	    decrease_FR_busy (cpu, out_FRdoublek, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1);
+	  if (use_is_media (cpu, out_FRdoublek + 1))
+	    decrease_FR_busy (cpu, out_FRdoublek + 1, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_FR (cpu, out_FRk);
+      vliw_wait_for_FRdouble (cpu, out_FRdoublek);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_FR (cpu, out_FRk);
+      load_wait_for_FRdouble (cpu, out_FRdoublek);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The latency of FRk for a load will depend on how long it takes to retrieve
+     the the data from the cache or memory.  */
+  update_FR_latency_for_load (cpu, out_FRk, cycles);
+  update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
+
+  fr500_reset_fr_flags (cpu, out_FRk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
+			      int unit_num, int referenced,
+			      INT in_GRi, INT in_GRj,
+			      INT in_FRk, INT in_FRdoublek)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      if (in_FRk >= 0)
+	{
+	  if (use_is_media (cpu, in_FRk))
+	    decrease_FR_busy (cpu, in_FRk, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, -1, in_FRk, 1);
+	}
+      if (in_FRdoublek >= 0)
+	{
+	  if (use_is_media (cpu, in_FRdoublek))
+	    decrease_FR_busy (cpu, in_FRdoublek, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1);
+	  if (use_is_media (cpu, in_FRdoublek + 1))
+	    decrease_FR_busy (cpu, in_FRdoublek + 1, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_FR (cpu, in_FRk);
+      vliw_wait_for_FRdouble (cpu, in_FRdoublek);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_FR (cpu, in_FRk);
+      load_wait_for_FRdouble (cpu, in_FRdoublek);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc,
+				int unit_num, int referenced,
+				INT in_GRi, INT in_GRj,
+				INT in_FRk, INT in_FRdoublek)
+{
+  int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced,
+					     in_GRi, in_GRj, in_FRk,
+					     in_FRdoublek);
+
+  if (model_insn == FRV_INSN_MODEL_PASS_2)
+    {
+      if (CPU_RSTR_INVALIDATE(cpu))
+	request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj, INT out_GRk)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi != out_GRk && in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_GR (cpu, out_GRk);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_GR (cpu, out_GRk);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The latency of GRk will depend on how long it takes to swap
+     the the data from the cache or memory.  */
+  update_GR_latency_for_swap (cpu, out_GRk, cycles);
+  set_use_is_gr_complex (cpu, out_GRk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_FRj, INT out_FRk)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.  */
+      if (in_FRj >= 0)
+	{
+	  if (use_is_media (cpu, in_FRj))
+	    decrease_FR_busy (cpu, in_FRj, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, in_FRj, -1, 1);
+	}
+      if (out_FRk >= 0 && out_FRk != in_FRj)
+	{
+	  if (use_is_media (cpu, out_FRk))
+	    decrease_FR_busy (cpu, out_FRk, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
+	}
+      vliw_wait_for_FR (cpu, in_FRj);
+      vliw_wait_for_FR (cpu, out_FRk);
+      handle_resource_wait (cpu);
+      load_wait_for_FR (cpu, in_FRj);
+      load_wait_for_FR (cpu, out_FRk);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* The latency of FRj is 3 cycles.  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_FR_latency (cpu, out_FRk, cycles + 3);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_FRk, INT out_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.  */
+      if (in_FRk >= 0)
+	{
+	  if (use_is_media (cpu, in_FRk))
+	    decrease_FR_busy (cpu, in_FRk, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, in_FRk, -1, 1);
+	}
+      vliw_wait_for_FR (cpu, in_FRk);
+      vliw_wait_for_GR (cpu, out_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_FR (cpu, in_FRk);
+      load_wait_for_GR (cpu, out_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* The latency of GRj is 2 cycles.  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_GR_latency (cpu, out_GRj, cycles + 2);
+  set_use_is_gr_complex (cpu, out_GRj);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_spr, INT out_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 SPR registers appear to have no latency effects.  */
+      vliw_wait_for_GR (cpu, out_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, out_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+#if 0 /* no latency?  */
+  /* The latency of GRj is 2 cycles.  */
+  update_GR_latency (cpu, out_GRj, cycles + 2);
+#endif
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_GRj, INT out_FRk)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      if (out_FRk >= 0)
+	{
+	  if (use_is_media (cpu, out_FRk))
+	    decrease_FR_busy (cpu, out_FRk, 1);
+	  else
+	    adjust_float_register_busy (cpu, -1, out_FRk, -1, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRj);
+      vliw_wait_for_FR (cpu, out_FRk);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRj);
+      load_wait_for_FR (cpu, out_FRk);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  /* The latency of FRk is 2 cycles.  */
+  cycles = idesc->timing->units[unit_num].done;
+  update_FR_latency (cpu, out_FRk, cycles + 2);
+
+  /* Mark this use of the register as NOT a floating point op.  */
+  fr500_reset_fr_flags (cpu, out_FRk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_GRj, INT out_spr)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+
+#if 0
+  /* The latency of spr is ? cycles.  */
+  update_SPR_latency (cpu, out_spr, cycles + ?);
+#endif
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc,
+			 int unit_num, int referenced,
+			 INT in_GRi, INT in_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles);
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc,
+			 int unit_num, int referenced,
+			 INT in_GRi, INT in_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
+			 int unit_num, int referenced,
+			 INT in_GRi, INT in_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles);
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles);
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles);
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles);
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT in_GRi, INT in_GRj)
+{
+  int cycles;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      /* The entire VLIW insn must wait if there is a dependency on a register
+	 which is not ready yet.
+	 The latency of the registers may be less than previously recorded,
+	 depending on how they were used previously.
+	 See Table 13-8 in the LSI.  */
+      if (in_GRi >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRi))
+	    decrease_GR_busy (cpu, in_GRi, 1);
+	}
+      if (in_GRj != in_GRi && in_GRj >= 0)
+	{
+	  if (use_is_gr_complex (cpu, in_GRj))
+	    decrease_GR_busy (cpu, in_GRj, 1);
+	}
+      vliw_wait_for_GR (cpu, in_GRi);
+      vliw_wait_for_GR (cpu, in_GRj);
+      handle_resource_wait (cpu);
+      load_wait_for_GR (cpu, in_GRi);
+      load_wait_for_GR (cpu, in_GRj);
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles);
+  return cycles;
+}
+
+/* Top up the post-processing time of the given FR by the given number of
+   cycles.  */
+static void
+update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* If a load is pending on this register, then add the cycles to
+	 the post processing time for this register. Otherwise apply it
+	 directly to the latency of the register.  */
+      if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
+	{
+	  int *fr = ps->fr_latency;
+	  fr[out_FR] += cycles;
+	}
+      else
+	ps->fr_ptime[out_FR] += cycles;
+    }
+}
+
+static void
+update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* If a load is pending on this register, then add the cycles to
+	 the post processing time for this register. Otherwise apply it
+	 directly to the latency of the register.  */
+      if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
+	{
+	  int *fr = ps->fr_latency;
+	  fr[out_FR] += cycles;
+	  if (out_FR < 63)
+	    fr[out_FR + 1] += cycles;
+	}
+      else
+	{
+	  ps->fr_ptime[out_FR] += cycles;
+	  if (out_FR < 63)
+	    ps->fr_ptime[out_FR + 1] += cycles;
+	}
+    }
+}
+
+int
+frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
+				 int unit_num, int referenced,
+				 INT in_FRi, INT in_FRj,
+				 INT in_FRdoublei, INT in_FRdoublej,
+				 INT out_FRk, INT out_FRdoublek)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
+  adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
+			       1);
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FRdouble (cpu, in_FRdoublei);
+  post_wait_for_FRdouble (cpu, in_FRdoublej);
+  post_wait_for_FRdouble (cpu, out_FRdoublek);
+  restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
+  restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
+				1);
+
+  /* The latency of FRk will be at least the latency of the other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+
+  /* Once initiated, post-processing will take 3 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 3);
+  update_FRdouble_ptime (cpu, out_FRdoublek, 3);
+
+  /* Mark this use of the register as a floating point op.  */
+  if (out_FRk >= 0)
+    set_use_is_fpop (cpu, out_FRk);
+  if (out_FRdoublek >= 0)
+    {
+      set_use_is_fpop (cpu, out_FRdoublek);
+      if (out_FRdoublek < 63)
+	set_use_is_fpop (cpu, out_FRdoublek + 1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc,
+				      int unit_num, int referenced,
+				      INT in_FRi, INT in_FRj,
+				      INT in_FRdoublei, INT in_FRdoublej,
+				      INT out_FRk, INT out_FRdoublek)
+{
+  int cycles;
+  INT dual_FRi;
+  INT dual_FRj;
+  INT dual_FRk;
+  INT dual_FRdoublei;
+  INT dual_FRdoublej;
+  INT dual_FRdoublek;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  dual_FRi = DUAL_REG (in_FRi);
+  dual_FRj = DUAL_REG (in_FRj);
+  dual_FRk = DUAL_REG (out_FRk);
+  dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei);
+  dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej);
+  dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek);
+
+  adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
+  adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
+  adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
+			       1);
+  adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
+			       dual_FRdoublek, 1);
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, dual_FRi);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_FR (cpu, dual_FRk);
+  post_wait_for_FRdouble (cpu, in_FRdoublei);
+  post_wait_for_FRdouble (cpu, in_FRdoublej);
+  post_wait_for_FRdouble (cpu, out_FRdoublek);
+  post_wait_for_FRdouble (cpu, dual_FRdoublei);
+  post_wait_for_FRdouble (cpu, dual_FRdoublej);
+  post_wait_for_FRdouble (cpu, dual_FRdoublek);
+  restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
+  restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
+  restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
+				1);
+  restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
+				dual_FRdoublek, 1);
+
+  /* The latency of FRk will be at least the latency of the other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_latency (cpu, dual_FRk, ps->post_wait);
+  update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+  update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait);
+
+  /* Once initiated, post-processing will take 3 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 3);
+  update_FR_ptime (cpu, dual_FRk, 3);
+  update_FRdouble_ptime (cpu, out_FRdoublek, 3);
+  update_FRdouble_ptime (cpu, dual_FRdoublek, 3);
+
+  /* Mark this use of the register as a floating point op.  */
+  if (out_FRk >= 0)
+    set_use_is_fpop (cpu, out_FRk);
+  if (dual_FRk >= 0)
+    set_use_is_fpop (cpu, dual_FRk);
+  if (out_FRdoublek >= 0)
+    {
+      set_use_is_fpop (cpu, out_FRdoublek);
+      if (out_FRdoublek < 63)
+	set_use_is_fpop (cpu, out_FRdoublek + 1);
+    }
+  if (dual_FRdoublek >= 0)
+    {
+      set_use_is_fpop (cpu, dual_FRdoublek);
+      if (dual_FRdoublek < 63)
+	set_use_is_fpop (cpu, dual_FRdoublek + 1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc,
+			       int unit_num, int referenced,
+			       INT in_FRi, INT in_FRj, INT out_FRk)
+{
+  int cycles;
+  FRV_VLIW *vliw;
+  int slot;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+  post_wait_for_fdiv (cpu, slot);
+  restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
+
+  /* The latency of FRk will be at least the latency of the other inputs.  */
+  /* Once initiated, post-processing will take 10 cycles.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_ptime (cpu, out_FRk, 10);
+
+  /* The latency of the fdiv unit will be at least the latency of the other
+     inputs.  Once initiated, post-processing will take 9 cycles.  */
+  update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9);
+
+  /* Mark this use of the register as a floating point op.  */
+  set_use_is_fpop (cpu, out_FRk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc,
+				int unit_num, int referenced,
+				INT in_FRj, INT in_FRdoublej,
+				INT out_FRk, INT out_FRdoublek)
+{
+  int cycles;
+  FRV_VLIW *vliw;
+  int slot;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FRdouble (cpu, in_FRdoublej);
+  post_wait_for_FRdouble (cpu, out_FRdoublek);
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+  post_wait_for_fsqrt (cpu, slot);
+  restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
+
+  /* The latency of FRk will be at least the latency of the other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+
+  /* Once initiated, post-processing will take 15 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 15);
+  update_FRdouble_ptime (cpu, out_FRdoublek, 15);
+
+  /* The latency of the sqrt unit will be the latency of the other
+     inputs plus 14 cycles.  */
+  update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
+
+  /* Mark this use of the register as a floating point op.  */
+  if (out_FRk >= 0)
+    set_use_is_fpop (cpu, out_FRk);
+  if (out_FRdoublek >= 0)
+    {
+      set_use_is_fpop (cpu, out_FRdoublek);
+      if (out_FRdoublek < 63)
+	set_use_is_fpop (cpu, out_FRdoublek + 1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc,
+				     int unit_num, int referenced,
+				     INT in_FRj, INT out_FRk)
+{
+  int cycles;
+  FRV_VLIW *vliw;
+  int slot;
+  INT dual_FRj;
+  INT dual_FRk;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  dual_FRj = DUAL_REG (in_FRj);
+  dual_FRk = DUAL_REG (out_FRk);
+  adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_FR (cpu, dual_FRk);
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+  post_wait_for_fsqrt (cpu, slot);
+  restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
+
+  /* The latency of FRk will be at least the latency of the other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_latency (cpu, dual_FRk, ps->post_wait);
+
+  /* Once initiated, post-processing will take 15 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 15);
+  update_FR_ptime (cpu, dual_FRk, 15);
+
+  /* The latency of the sqrt unit will be at least the latency of the other
+     inputs.  */
+  update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
+
+  /* Mark this use of the register as a floating point op.  */
+  if (out_FRk >= 0)
+    set_use_is_fpop (cpu, out_FRk);
+  if (dual_FRk >= 0)
+    set_use_is_fpop (cpu, dual_FRk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
+				   int unit_num, int referenced,
+				   INT in_FRi, INT in_FRj,
+				   INT in_FRdoublei, INT in_FRdoublej,
+				   INT out_FCCi_2)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FRdouble (cpu, in_FRdoublei);
+  post_wait_for_FRdouble (cpu, in_FRdoublej);
+  post_wait_for_CCR (cpu, out_FCCi_2);
+  restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
+
+  /* The latency of FCCi_2 will be the latency of the other inputs plus 3
+     cycles.  */
+  update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
+					int unit_num, int referenced,
+					INT in_FRi, INT in_FRj,
+					INT out_FCCi_2)
+{
+  int cycles;
+  INT dual_FRi;
+  INT dual_FRj;
+  INT dual_FCCi_2;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  dual_FRi = DUAL_REG (in_FRi);
+  dual_FRj = DUAL_REG (in_FRj);
+  dual_FCCi_2 = out_FCCi_2 + 1;
+  adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
+  adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, dual_FRi);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_CCR (cpu, out_FCCi_2);
+  post_wait_for_CCR (cpu, dual_FCCi_2);
+  restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
+  restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
+
+  /* The latency of FCCi_2 will be the latency of the other inputs plus 3
+     cycles.  */
+  update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
+  update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
+				   int unit_num, int referenced,
+				   INT in_FRj, INT in_FRintj, INT in_FRdoublej,
+				   INT out_FRk, INT out_FRintk,
+				   INT out_FRdoublek)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
+  adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, in_FRintj);
+  post_wait_for_FRdouble (cpu, in_FRdoublej);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, out_FRintk);
+  post_wait_for_FRdouble (cpu, out_FRdoublek);
+  restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
+  restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
+
+  /* The latency of FRk will be at least the latency of the other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_latency (cpu, out_FRintk, ps->post_wait);
+  update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+
+  /* Once initiated, post-processing will take 3 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 3);
+  update_FR_ptime (cpu, out_FRintk, 3);
+  update_FRdouble_ptime (cpu, out_FRdoublek, 3);
+
+  /* Mark this use of the register as a floating point op.  */
+  if (out_FRk >= 0)
+    set_use_is_fpop (cpu, out_FRk);
+  if (out_FRintk >= 0)
+    set_use_is_fpop (cpu, out_FRintk);
+  if (out_FRdoublek >= 0)
+    {
+      set_use_is_fpop (cpu, out_FRdoublek);
+      set_use_is_fpop (cpu, out_FRdoublek + 1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc,
+					int unit_num, int referenced,
+					INT in_FRj, INT in_FRintj,
+					INT out_FRk, INT out_FRintk)
+{
+  int cycles;
+  INT dual_FRj;
+  INT dual_FRintj;
+  INT dual_FRk;
+  INT dual_FRintk;
+  FRV_PROFILE_STATE *ps;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  ps->post_wait = cycles;
+  dual_FRj = DUAL_REG (in_FRj);
+  dual_FRintj = DUAL_REG (in_FRintj);
+  dual_FRk = DUAL_REG (out_FRk);
+  dual_FRintk = DUAL_REG (out_FRintk);
+  adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
+  adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
+  adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, in_FRintj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, out_FRintk);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_FR (cpu, dual_FRintj);
+  post_wait_for_FR (cpu, dual_FRk);
+  post_wait_for_FR (cpu, dual_FRintk);
+  restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
+  restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
+  restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
+  restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
+
+  /* The latency of FRk will be at least the latency of the other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_latency (cpu, out_FRintk, ps->post_wait);
+  update_FR_latency (cpu, dual_FRk, ps->post_wait);
+  update_FR_latency (cpu, dual_FRintk, ps->post_wait);
+
+  /* Once initiated, post-processing will take 3 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 3);
+  update_FR_ptime (cpu, out_FRintk, 3);
+  update_FR_ptime (cpu, dual_FRk, 3);
+  update_FR_ptime (cpu, dual_FRintk, 3);
+
+  /* Mark this use of the register as a floating point op.  */
+  if (out_FRk >= 0)
+    set_use_is_fpop (cpu, out_FRk);
+  if (out_FRintk >= 0)
+    set_use_is_fpop (cpu, out_FRintk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi,
+			   INT out_FRk,
+			   INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk)
+{
+  int cycles;
+  FRV_PROFILE_STATE *ps;
+  const CGEN_INSN *insn;
+  int is_media_s1;
+  int is_media_s2;
+  int busy_adjustment[] = {0, 0, 0};
+  int *fr;
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  insn = idesc->idata;
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  if (in_FRi >= 0)
+    {
+      if (use_is_media (cpu, in_FRi))
+	{
+	  busy_adjustment[0] = 2;
+	  decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRi);
+    }
+  if (in_FRj >= 0 && in_FRj != in_FRi)
+    {
+      if (use_is_media (cpu, in_FRj))
+	{
+	  busy_adjustment[1] = 2;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+    }
+  if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
+    {
+      if (use_is_media (cpu, out_FRk))
+	{
+	  busy_adjustment[2] = 2;
+	  decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, out_FRk);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_ACC (cpu, in_ACC40Si);
+  post_wait_for_ACC (cpu, in_ACCGi);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, out_ACC40Uk);
+  post_wait_for_ACC (cpu, out_ACCGk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  if (in_FRi >= 0)
+    fr[in_FRi] += busy_adjustment[0];
+  if (in_FRj >= 0)
+    fr[in_FRj] += busy_adjustment[1];
+  if (out_FRk >= 0)
+    fr[out_FRk] += busy_adjustment[2];
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 3 cycles.  */
+  if (out_FRk >= 0)
+    {
+      update_FR_latency (cpu, out_FRk, ps->post_wait);
+      update_FR_ptime (cpu, out_FRk, 3);
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, out_FRk);
+    }
+  /* The latency of tht output accumulator will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_ACC40Sk >= 0)
+    update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+  if (out_ACC40Uk >= 0)
+    update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
+  if (out_ACCGk >= 0)
+    update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc,
+				       int unit_num, int referenced,
+				       INT in_FRi, INT in_FRj,
+				       INT out_FRk)
+{
+  int cycles;
+  INT dual_FRi;
+  INT dual_FRj;
+  INT dual_FRk;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  dual_FRi = DUAL_REG (in_FRi);
+  dual_FRj = DUAL_REG (in_FRj);
+  dual_FRk = DUAL_REG (out_FRk);
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  if (use_is_media (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi))
+    {
+      busy_adjustment[1] = 2;
+      decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
+    }
+  else
+    enforce_full_fr_latency (cpu, dual_FRi);
+  if (in_FRj != in_FRi)
+    {
+      if (use_is_media (cpu, in_FRj))
+	{
+	  busy_adjustment[2] = 2;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+      if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj))
+	{
+	  busy_adjustment[3] = 2;
+	  decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
+	}
+      else
+	enforce_full_fr_latency (cpu, dual_FRj + 1);
+    }
+  if (out_FRk != in_FRi && out_FRk != in_FRj)
+    {
+      if (use_is_media (cpu, out_FRk))
+	{
+	  busy_adjustment[4] = 2;
+	  decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]);
+	}
+      else
+	enforce_full_fr_latency (cpu, out_FRk);
+      if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk))
+	{
+	  busy_adjustment[5] = 2;
+	  decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]);
+	}
+      else
+	enforce_full_fr_latency (cpu, dual_FRk);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, dual_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, dual_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  if (dual_FRi >= 0)
+    fr[dual_FRi] += busy_adjustment[1];
+  fr[in_FRj] += busy_adjustment[2];
+  if (dual_FRj >= 0)
+    fr[dual_FRj] += busy_adjustment[3];
+  fr[out_FRk] += busy_adjustment[4];
+  if (dual_FRk >= 0)
+    fr[dual_FRk] += busy_adjustment[5];
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+
+  /* Once initiated, post-processing will take 3 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 3);
+
+  /* Mark this use of the register as a media op.  */
+  set_use_is_media (cpu, out_FRk);
+  if (dual_FRk >= 0)
+    {
+      update_FR_latency (cpu, dual_FRk, ps->post_wait);
+      update_FR_ptime (cpu, dual_FRk, 3);
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, dual_FRk);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc,
+				    int unit_num, int referenced,
+				    INT in_FRi, INT in_FRj,
+				    INT out_ACC40Sk, INT out_ACC40Uk)
+{
+  int cycles;
+  INT dual_ACC40Sk;
+  INT dual_ACC40Uk;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
+  int *fr;
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  ps = CPU_PROFILE_STATE (cpu);
+  dual_ACC40Sk = DUAL_REG (out_ACC40Sk);
+  dual_ACC40Uk = DUAL_REG (out_ACC40Uk);
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  if (use_is_media (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (in_FRj != in_FRi)
+    {
+      if (use_is_media (cpu, in_FRj))
+	{
+	  busy_adjustment[1] = 2;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+    }
+  if (out_ACC40Sk >= 0)
+    {
+      busy_adjustment[2] = 1;
+      decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
+    }
+  if (dual_ACC40Sk >= 0)
+    {
+      busy_adjustment[3] = 1;
+      decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]);
+    }
+  if (out_ACC40Uk >= 0)
+    {
+      busy_adjustment[4] = 1;
+      decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
+    }
+  if (dual_ACC40Uk >= 0)
+    {
+      busy_adjustment[5] = 1;
+      decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, dual_ACC40Sk);
+  post_wait_for_ACC (cpu, out_ACC40Uk);
+  post_wait_for_ACC (cpu, dual_ACC40Uk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  acc = ps->acc_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  fr[in_FRj] += busy_adjustment[1];
+  if (out_ACC40Sk >= 0)
+    acc[out_ACC40Sk] += busy_adjustment[2];
+  if (dual_ACC40Sk >= 0)
+    acc[dual_ACC40Sk] += busy_adjustment[3];
+  if (out_ACC40Uk >= 0)
+    acc[out_ACC40Uk] += busy_adjustment[4];
+  if (dual_ACC40Uk >= 0)
+    acc[dual_ACC40Uk] += busy_adjustment[5];
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_ACC40Sk >= 0)
+    update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+  if (dual_ACC40Sk >= 0)
+    update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1);
+  if (out_ACC40Uk >= 0)
+    update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
+  if (dual_ACC40Uk >= 0)
+    update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc,
+				    int unit_num, int referenced,
+				    INT in_FRi, INT in_FRj,
+				    INT out_ACC40Sk, INT out_ACC40Uk)
+{
+  int cycles;
+  INT FRi_1;
+  INT FRj_1;
+  INT ACC40Sk_1;
+  INT ACC40Sk_2;
+  INT ACC40Sk_3;
+  INT ACC40Uk_1;
+  INT ACC40Uk_2;
+  INT ACC40Uk_3;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0};
+  int *fr;
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  FRi_1 = DUAL_REG (in_FRi);
+  FRj_1 = DUAL_REG (in_FRj);
+  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+  ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
+  ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
+  ACC40Uk_1 = DUAL_REG (out_ACC40Uk);
+  ACC40Uk_2 = DUAL_REG (ACC40Uk_1);
+  ACC40Uk_3 = DUAL_REG (ACC40Uk_2);
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_media (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (FRi_1 >= 0)
+    {
+      if (use_is_media (cpu, FRi_1))
+	{
+	  busy_adjustment[1] = 2;
+	  decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, FRi_1);
+    }
+  if (in_FRj != in_FRi)
+    {
+      if (use_is_media (cpu, in_FRj))
+	{
+	  busy_adjustment[2] = 2;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+      if (FRj_1 >= 0)
+	{
+	  if (use_is_media (cpu, FRj_1))
+	    {
+	      busy_adjustment[3] = 2;
+	      decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRj_1);
+	}
+    }
+  if (out_ACC40Sk >= 0)
+    {
+      busy_adjustment[4] = 1;
+      decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
+
+      if (ACC40Sk_1 >= 0)
+	{
+	  busy_adjustment[5] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
+	}
+      if (ACC40Sk_2 >= 0)
+	{
+	  busy_adjustment[6] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
+	}
+      if (ACC40Sk_3 >= 0)
+	{
+	  busy_adjustment[7] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
+	}
+    }
+  else if (out_ACC40Uk >= 0)
+    {
+      busy_adjustment[4] = 1;
+      decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
+
+      if (ACC40Uk_1 >= 0)
+	{
+	  busy_adjustment[5] = 1;
+	  decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]);
+	}
+      if (ACC40Uk_2 >= 0)
+	{
+	  busy_adjustment[6] = 1;
+	  decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]);
+	}
+      if (ACC40Uk_3 >= 0)
+	{
+	  busy_adjustment[7] = 1;
+	  decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, FRi_1);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, FRj_1);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, ACC40Sk_1);
+  post_wait_for_ACC (cpu, ACC40Sk_2);
+  post_wait_for_ACC (cpu, ACC40Sk_3);
+  post_wait_for_ACC (cpu, out_ACC40Uk);
+  post_wait_for_ACC (cpu, ACC40Uk_1);
+  post_wait_for_ACC (cpu, ACC40Uk_2);
+  post_wait_for_ACC (cpu, ACC40Uk_3);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  acc = ps->acc_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  if (FRi_1 >= 0)
+    fr[FRi_1] += busy_adjustment[1];
+  fr[in_FRj] += busy_adjustment[2];
+  if (FRj_1 > 0)
+    fr[FRj_1] += busy_adjustment[3];
+  if (out_ACC40Sk >= 0)
+    {
+      acc[out_ACC40Sk] += busy_adjustment[4];
+      if (ACC40Sk_1 >= 0)
+	acc[ACC40Sk_1] += busy_adjustment[5];
+      if (ACC40Sk_2 >= 0)
+	acc[ACC40Sk_2] += busy_adjustment[6];
+      if (ACC40Sk_3 >= 0)
+	acc[ACC40Sk_3] += busy_adjustment[7];
+    }
+  else if (out_ACC40Uk >= 0)
+    {
+      acc[out_ACC40Uk] += busy_adjustment[4];
+      if (ACC40Uk_1 >= 0)
+	acc[ACC40Uk_1] += busy_adjustment[5];
+      if (ACC40Uk_2 >= 0)
+	acc[ACC40Uk_2] += busy_adjustment[6];
+      if (ACC40Uk_3 >= 0)
+	acc[ACC40Uk_3] += busy_adjustment[7];
+    }
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_ACC40Sk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+      if (ACC40Sk_1 >= 0)
+	update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+      if (ACC40Sk_2 >= 0)
+	update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
+      if (ACC40Sk_3 >= 0)
+	update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
+    }
+  else if (out_ACC40Uk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
+      if (ACC40Uk_1 >= 0)
+	update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);
+      if (ACC40Uk_2 >= 0)
+	update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);
+      if (ACC40Uk_3 >= 0)
+	update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc,
+					int unit_num, int referenced,
+					INT in_FRi, INT in_FRj,
+					INT out_ACC40Sk)
+{
+  int cycles;
+  INT FRi_1;
+  INT FRj_1;
+  INT ACC40Sk_1;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
+  int *fr;
+  int *acc;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  FRi_1 = DUAL_REG (in_FRi);
+  FRj_1 = DUAL_REG (in_FRj);
+  ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_media (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (FRi_1 >= 0)
+    {
+      if (use_is_media (cpu, FRi_1))
+	{
+	  busy_adjustment[1] = 2;
+	  decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, FRi_1);
+    }
+  if (in_FRj != in_FRi)
+    {
+      if (use_is_media (cpu, in_FRj))
+	{
+	  busy_adjustment[2] = 2;
+	  decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, in_FRj);
+      if (FRj_1 >= 0)
+	{
+	  if (use_is_media (cpu, FRj_1))
+	    {
+	      busy_adjustment[3] = 2;
+	      decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRj_1);
+	}
+    }
+  if (out_ACC40Sk >= 0)
+    {
+      busy_adjustment[4] = 1;
+      decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
+
+      if (ACC40Sk_1 >= 0)
+	{
+	  busy_adjustment[5] = 1;
+	  decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, FRi_1);
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, FRj_1);
+  post_wait_for_ACC (cpu, out_ACC40Sk);
+  post_wait_for_ACC (cpu, ACC40Sk_1);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  acc = ps->acc_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  if (FRi_1 >= 0)
+    fr[FRi_1] += busy_adjustment[1];
+  fr[in_FRj] += busy_adjustment[2];
+  if (FRj_1 > 0)
+    fr[FRj_1] += busy_adjustment[3];
+  if (out_ACC40Sk >= 0)
+    {
+      acc[out_ACC40Sk] += busy_adjustment[4];
+      if (ACC40Sk_1 >= 0)
+	acc[ACC40Sk_1] += busy_adjustment[5];
+    }
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 1 cycle.  */
+  if (out_ACC40Sk >= 0)
+    {
+      update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+      if (ACC40Sk_1 >= 0)
+	update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
+				       int unit_num, int referenced,
+				       INT in_FRi,
+				       INT out_FRk)
+{
+  int cycles;
+  INT dual_FRk;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  dual_FRk = DUAL_REG (out_FRk);
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_media (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (out_FRk != in_FRi)
+    {
+      if (use_is_media (cpu, out_FRk))
+	{
+	  busy_adjustment[1] = 2;
+	  decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, out_FRk);
+    }
+  if (dual_FRk >= 0 && dual_FRk != in_FRi)
+    {
+      if (use_is_media (cpu, dual_FRk))
+	{
+	  busy_adjustment[2] = 2;
+	  decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, dual_FRk);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, dual_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  fr[out_FRk] += busy_adjustment[1];
+  if (dual_FRk >= 0)
+    fr[dual_FRk] += busy_adjustment[2];
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 3 cycles.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_ptime (cpu, out_FRk, 3);
+
+  /* Mark this use of the register as a media op.  */
+  set_use_is_media (cpu, out_FRk);
+  if (dual_FRk >= 0)
+    {
+      update_FR_latency (cpu, dual_FRk, ps->post_wait);
+      update_FR_ptime (cpu, dual_FRk, 3);
+
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, dual_FRk);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc,
+				       int unit_num, int referenced,
+				       INT in_FRi,
+				       INT out_FRk)
+{
+  int cycles;
+  INT FRi_1;
+  INT FRk_1;
+  INT FRk_2;
+  INT FRk_3;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  FRi_1 = DUAL_REG (in_FRi);
+  FRk_1 = DUAL_REG (out_FRk);
+  FRk_2 = DUAL_REG (FRk_1);
+  FRk_3 = DUAL_REG (FRk_2);
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_media (cpu, in_FRi))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRi);
+  if (FRi_1 >= 0 && use_is_media (cpu, FRi_1))
+    {
+      busy_adjustment[1] = 2;
+      decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
+    }
+  else
+    enforce_full_fr_latency (cpu, FRi_1);
+  if (out_FRk != in_FRi)
+    {
+      if (use_is_media (cpu, out_FRk))
+	{
+	  busy_adjustment[2] = 2;
+	  decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, out_FRk);
+      if (FRk_1 >= 0 && FRk_1 != in_FRi)
+	{
+	  if (use_is_media (cpu, FRk_1))
+	    {
+	      busy_adjustment[3] = 2;
+	      decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRk_1);
+	}
+      if (FRk_2 >= 0 && FRk_2 != in_FRi)
+	{
+	  if (use_is_media (cpu, FRk_2))
+	    {
+	      busy_adjustment[4] = 2;
+	      decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRk_2);
+	}
+      if (FRk_3 >= 0 && FRk_3 != in_FRi)
+	{
+	  if (use_is_media (cpu, FRk_3))
+	    {
+	      busy_adjustment[5] = 2;
+	      decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRk_3);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRi);
+  post_wait_for_FR (cpu, FRi_1);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, FRk_1);
+  post_wait_for_FR (cpu, FRk_2);
+  post_wait_for_FR (cpu, FRk_3);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRi] += busy_adjustment[0];
+  if (FRi_1 >= 0)
+    fr[FRi_1] += busy_adjustment[1];
+  fr[out_FRk] += busy_adjustment[2];
+  if (FRk_1 >= 0)
+    fr[FRk_1] += busy_adjustment[3];
+  if (FRk_2 >= 0)
+    fr[FRk_2] += busy_adjustment[4];
+  if (FRk_3 >= 0)
+    fr[FRk_3] += busy_adjustment[5];
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 3 cycles.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_ptime (cpu, out_FRk, 3);
+
+  /* Mark this use of the register as a media op.  */
+  set_use_is_media (cpu, out_FRk);
+  if (FRk_1 >= 0)
+    {
+      update_FR_latency (cpu, FRk_1, ps->post_wait);
+      update_FR_ptime (cpu, FRk_1, 3);
+
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, FRk_1);
+    }
+  if (FRk_2 >= 0)
+    {
+      update_FR_latency (cpu, FRk_2, ps->post_wait);
+      update_FR_ptime (cpu, FRk_2, 3);
+
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, FRk_2);
+    }
+  if (FRk_3 >= 0)
+    {
+      update_FR_latency (cpu, FRk_3, ps->post_wait);
+      update_FR_ptime (cpu, FRk_3, 3);
+
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, FRk_3);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc,
+				     int unit_num, int referenced,
+				     INT in_FRj,
+				     INT out_FRk)
+{
+  return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num,
+						referenced, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
+				     int unit_num, int referenced,
+				     INT in_FRj,
+				     INT out_FRk)
+{
+  int cycles;
+  INT dual_FRj;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  dual_FRj = DUAL_REG (in_FRj);
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_media (cpu, in_FRj))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRj);
+  if (dual_FRj >= 0)
+    {
+      if (use_is_media (cpu, dual_FRj))
+	{
+	  busy_adjustment[1] = 2;
+	  decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, dual_FRj);
+    }
+  if (out_FRk != in_FRj)
+    {
+      if (use_is_media (cpu, out_FRk))
+	{
+	  busy_adjustment[2] = 2;
+	  decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
+	}
+      else
+	enforce_full_fr_latency (cpu, out_FRk);
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, dual_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRj] += busy_adjustment[0];
+  if (dual_FRj >= 0)
+    fr[dual_FRj] += busy_adjustment[1];
+  fr[out_FRk] += busy_adjustment[2];
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+
+  /* Once initiated, post-processing will take 3 cycles.  */
+  update_FR_ptime (cpu, out_FRk, 3);
+
+  /* Mark this use of the register as a media op.  */
+  set_use_is_media (cpu, out_FRk);
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc,
+				      int unit_num, int referenced,
+				      INT in_FRj,
+				      INT out_FRk)
+{
+  int cycles;
+  INT FRk_1;
+  INT FRk_2;
+  INT FRk_3;
+  FRV_PROFILE_STATE *ps;
+  int busy_adjustment[] = {0, 0, 0, 0, 0};
+  int *fr;
+
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    return 0;
+
+  /* The preprocessing can execute right away.  */
+  cycles = idesc->timing->units[unit_num].done;
+
+  FRk_1 = DUAL_REG (out_FRk);
+  FRk_2 = DUAL_REG (FRk_1);
+  FRk_3 = DUAL_REG (FRk_2);
+
+  /* If the previous use of the registers was a media op,
+     then their latency will be less than previously recorded.
+     See Table 13-13 in the LSI.  */
+  ps = CPU_PROFILE_STATE (cpu);
+  if (use_is_media (cpu, in_FRj))
+    {
+      busy_adjustment[0] = 2;
+      decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
+    }
+  else
+    enforce_full_fr_latency (cpu, in_FRj);
+  if (out_FRk != in_FRj)
+    {
+      if (use_is_media (cpu, out_FRk))
+	{
+	  busy_adjustment[1] = 2;
+	  decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
+	}
+      else
+	enforce_full_fr_latency (cpu, out_FRk);
+      if (FRk_1 >= 0 && FRk_1 != in_FRj)
+	{
+	  if (use_is_media (cpu, FRk_1))
+	    {
+	      busy_adjustment[2] = 2;
+	      decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRk_1);
+	}
+      if (FRk_2 >= 0 && FRk_2 != in_FRj)
+	{
+	  if (use_is_media (cpu, FRk_2))
+	    {
+	      busy_adjustment[3] = 2;
+	      decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRk_2);
+	}
+      if (FRk_3 >= 0 && FRk_3 != in_FRj)
+	{
+	  if (use_is_media (cpu, FRk_3))
+	    {
+	      busy_adjustment[4] = 2;
+	      decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]);
+	    }
+	  else
+	    enforce_full_fr_latency (cpu, FRk_3);
+	}
+    }
+
+  /* The post processing must wait if there is a dependency on a FR
+     which is not ready yet.  */
+  ps->post_wait = cycles;
+  post_wait_for_FR (cpu, in_FRj);
+  post_wait_for_FR (cpu, out_FRk);
+  post_wait_for_FR (cpu, FRk_1);
+  post_wait_for_FR (cpu, FRk_2);
+  post_wait_for_FR (cpu, FRk_3);
+
+  /* Restore the busy cycles of the registers we used.  */
+  fr = ps->fr_busy;
+  fr[in_FRj] += busy_adjustment[0];
+  fr[out_FRk] += busy_adjustment[1];
+  if (FRk_1 >= 0)
+    fr[FRk_1] += busy_adjustment[2];
+  if (FRk_2 >= 0)
+    fr[FRk_2] += busy_adjustment[3];
+  if (FRk_3 >= 0)
+    fr[FRk_3] += busy_adjustment[4];
+
+  /* The latency of tht output register will be at least the latency of the
+     other inputs.  Once initiated, post-processing will take 3 cycles.  */
+  update_FR_latency (cpu, out_FRk, ps->post_wait);
+  update_FR_ptime (cpu, out_FRk, 3);
+
+  /* Mark this use of the register as a media op.  */
+  set_use_is_media (cpu, out_FRk);
+  if (FRk_1 >= 0)
+    {
+      update_FR_latency (cpu, FRk_1, ps->post_wait);
+      update_FR_ptime (cpu, FRk_1, 3);
+
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, FRk_1);
+    }
+  if (FRk_2 >= 0)
+    {
+      update_FR_latency (cpu, FRk_2, ps->post_wait);
+      update_FR_ptime (cpu, FRk_2, 3);
+
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, FRk_2);
+    }
+  if (FRk_3 >= 0)
+    {
+      update_FR_latency (cpu, FRk_3, ps->post_wait);
+      update_FR_ptime (cpu, FRk_3, 3);
+
+      /* Mark this use of the register as a media op.  */
+      set_use_is_media (cpu, FRk_3);
+    }
+
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced)
+{
+  int cycles;
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      int i;
+      /* Wait for ALL resources.  */
+      for (i = 0; i < 64; ++i)
+	{
+	  enforce_full_fr_latency (cpu, i);
+	  vliw_wait_for_GR (cpu, i);
+	  vliw_wait_for_FR (cpu, i);
+	  vliw_wait_for_ACC (cpu, i);
+	}
+      for (i = 0; i < 8; ++i)
+	vliw_wait_for_CCR (cpu, i);
+      for (i = 0; i < 2; ++i)
+	{
+	  vliw_wait_for_idiv_resource (cpu, i);
+	  vliw_wait_for_fdiv_resource (cpu, i);
+	  vliw_wait_for_fsqrt_resource (cpu, i);
+	}
+      handle_resource_wait (cpu);
+      for (i = 0; i < 64; ++i)
+	{
+	  load_wait_for_GR (cpu, i);
+	  load_wait_for_FR (cpu, i);
+	}
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  return cycles;
+}
+
+int
+frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced)
+{
+  int cycles;
+  if (model_insn == FRV_INSN_MODEL_PASS_1)
+    {
+      int i;
+      /* Wait for ALL resources, except GR and ICC.  */
+      for (i = 0; i < 64; ++i)
+	{
+	  enforce_full_fr_latency (cpu, i);
+	  vliw_wait_for_FR (cpu, i);
+	  vliw_wait_for_ACC (cpu, i);
+	}
+      for (i = 0; i < 4; ++i)
+	vliw_wait_for_CCR (cpu, i);
+      for (i = 0; i < 2; ++i)
+	{
+	  vliw_wait_for_idiv_resource (cpu, i);
+	  vliw_wait_for_fdiv_resource (cpu, i);
+	  vliw_wait_for_fsqrt_resource (cpu, i);
+	}
+      handle_resource_wait (cpu);
+      for (i = 0; i < 64; ++i)
+	{
+	  load_wait_for_FR (cpu, i);
+	}
+      trace_vliw_wait_cycles (cpu);
+      return 0;
+    }
+
+  cycles = idesc->timing->units[unit_num].done;
+  return cycles;
+}
+
+/* The frv machine is a fictional implementation of the fr500 which implements
+   all frv architectural features.  */
+int
+frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+/* The simple machine is a fictional implementation of the fr500 which
+   implements limited frv architectural features.  */
+int
+frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+/* The tomcat machine is models a prototype fr500 machine which had a few
+   bugs and restrictions to work around.  */
+int
+frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/frv/profile-fr500.h b/sim/frv/profile-fr500.h
new file mode 100644
index 00000000000..6b3c6293d57
--- /dev/null
+++ b/sim/frv/profile-fr500.h
@@ -0,0 +1,30 @@
+/* Profiling definitions for the fr500 model of the FRV simulator
+   Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef PROFILE_FR500_H
+#define PROFILE_FR500_H
+
+void fr500_model_insn_before (SIM_CPU *, int);
+void fr500_model_insn_after (SIM_CPU *, int, int);
+
+void fr500_reset_fr_flags (SIM_CPU *, INT);
+void fr500_reset_cc_flags (SIM_CPU *, INT);
+
+#endif /* PROFILE_FR500_H */
diff --git a/sim/frv/profile.c b/sim/frv/profile.c
new file mode 100644
index 00000000000..1a59e4a89a7
--- /dev/null
+++ b/sim/frv/profile.c
@@ -0,0 +1,1807 @@
+/* frv simulator machine independent profiling code.
+
+   Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+#if WITH_PROFILE_MODEL_P
+
+#include "profile.h"
+#include "profile-fr400.h"
+#include "profile-fr500.h"
+
+static void
+reset_gr_flags (SIM_CPU *cpu, INT gr)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    fr400_reset_gr_flags (cpu, gr);
+  /* Other machines have no gr flags right now.  */
+}
+
+static void
+reset_fr_flags (SIM_CPU *cpu, INT fr)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    fr400_reset_fr_flags (cpu, fr);
+  else if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500)
+    fr500_reset_fr_flags (cpu, fr);
+}
+
+static void
+reset_acc_flags (SIM_CPU *cpu, INT acc)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    fr400_reset_acc_flags (cpu, acc);
+  /* Other machines have no acc flags right now.  */
+}
+
+static void
+reset_cc_flags (SIM_CPU *cpu, INT cc)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500)
+    fr500_reset_cc_flags (cpu, cc);
+  /* Other machines have no cc flags.  */
+}
+
+void
+set_use_is_gr_complex (SIM_CPU *cpu, INT gr)
+{
+  if (gr != -1)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      reset_gr_flags (cpu, gr);
+      ps->cur_gr_complex |= (((DI)1) << gr);
+    }
+}
+
+void
+set_use_not_gr_complex (SIM_CPU *cpu, INT gr)
+{
+  if (gr != -1)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      ps->cur_gr_complex &= ~(((DI)1) << gr);
+    }
+}
+
+int
+use_is_gr_complex (SIM_CPU *cpu, INT gr)
+{
+  if (gr != -1)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      return ps->cur_gr_complex & (((DI)1) << gr);
+    }
+  return 0;
+}
+
+/* Globals flag indicates whether this insn is being modeled.  */
+enum FRV_INSN_MODELING model_insn = FRV_INSN_NO_MODELING;
+
+/* static buffer for the name of the currently most restrictive hazard.  */
+static char hazard_name[100] = "";
+
+/* Print information about the wait applied to an entire VLIW insn.  */
+FRV_INSN_FETCH_BUFFER frv_insn_fetch_buffer[]
+= {
+  {1, NO_REQNO}, {1, NO_REQNO} /* init with impossible address.  */
+};
+
+enum cache_request
+{
+  cache_load,
+  cache_invalidate,
+  cache_flush,
+  cache_preload,
+  cache_unlock
+};
+
+/* A queue of load requests from the data cache. Use to keep track of loads
+   which are still pending.  */
+/* TODO -- some of these are mutually exclusive and can use a union.  */
+typedef struct
+{
+  FRV_CACHE *cache;
+  unsigned reqno;
+  SI address;
+  int length;
+  int is_signed;
+  int regnum;
+  int cycles;
+  int regtype;
+  int lock;
+  int all;
+  int slot;
+  int active;
+  enum cache_request request;
+} CACHE_QUEUE_ELEMENT;
+
+#define CACHE_QUEUE_SIZE 64 /* TODO -- make queue dynamic */
+struct
+{
+  unsigned reqno;
+  int ix;
+  CACHE_QUEUE_ELEMENT q[CACHE_QUEUE_SIZE];
+} cache_queue = {0, 0};
+
+/* Queue a request for a load from the cache. The load will be queued as
+   'inactive' and will be requested after the given number
+   of cycles have passed from the point the load is activated.  */
+void
+request_cache_load (SIM_CPU *cpu, INT regnum, int regtype, int cycles)
+{
+  CACHE_QUEUE_ELEMENT *q;
+  FRV_VLIW *vliw;
+  int slot;
+
+  /* For a conditional load which was not executed, CPU_LOAD_LENGTH will be
+     zero.  */
+  if (CPU_LOAD_LENGTH (cpu) == 0)
+    return;
+
+  if (cache_queue.ix >= CACHE_QUEUE_SIZE)
+    abort (); /* TODO: Make the queue dynamic */
+
+  q = & cache_queue.q[cache_queue.ix];
+  ++cache_queue.ix;
+
+  q->reqno = cache_queue.reqno++;
+  q->request = cache_load;
+  q->cache = CPU_DATA_CACHE (cpu);
+  q->address = CPU_LOAD_ADDRESS (cpu);
+  q->length = CPU_LOAD_LENGTH (cpu);
+  q->is_signed = CPU_LOAD_SIGNED (cpu);
+  q->regnum = regnum;
+  q->regtype = regtype;
+  q->cycles = cycles;
+  q->active = 0;
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  q->slot = (*vliw->current_vliw)[slot];
+
+  CPU_LOAD_LENGTH (cpu) = 0;
+}
+
+/* Queue a request to flush the cache. The request will be queued as
+   'inactive' and will be requested after the given number
+   of cycles have passed from the point the request is activated.  */
+void
+request_cache_flush (SIM_CPU *cpu, FRV_CACHE *cache, int cycles)
+{
+  CACHE_QUEUE_ELEMENT *q;
+  FRV_VLIW *vliw;
+  int slot;
+
+  if (cache_queue.ix >= CACHE_QUEUE_SIZE)
+    abort (); /* TODO: Make the queue dynamic */
+
+  q = & cache_queue.q[cache_queue.ix];
+  ++cache_queue.ix;
+
+  q->reqno = cache_queue.reqno++;
+  q->request = cache_flush;
+  q->cache = cache;
+  q->address = CPU_LOAD_ADDRESS (cpu);
+  q->all = CPU_PROFILE_STATE (cpu)->all_cache_entries;
+  q->cycles = cycles;
+  q->active = 0;
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  q->slot = (*vliw->current_vliw)[slot];
+}
+
+/* Queue a request to invalidate the cache. The request will be queued as
+   'inactive' and will be requested after the given number
+   of cycles have passed from the point the request is activated.  */
+void
+request_cache_invalidate (SIM_CPU *cpu, FRV_CACHE *cache, int cycles)
+{
+  CACHE_QUEUE_ELEMENT *q;
+  FRV_VLIW *vliw;
+  int slot;
+
+  if (cache_queue.ix >= CACHE_QUEUE_SIZE)
+    abort (); /* TODO: Make the queue dynamic */
+
+  q = & cache_queue.q[cache_queue.ix];
+  ++cache_queue.ix;
+
+  q->reqno = cache_queue.reqno++;
+  q->request = cache_invalidate;
+  q->cache = cache;
+  q->address = CPU_LOAD_ADDRESS (cpu);
+  q->all = CPU_PROFILE_STATE (cpu)->all_cache_entries;
+  q->cycles = cycles;
+  q->active = 0;
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  q->slot = (*vliw->current_vliw)[slot];
+}
+
+/* Queue a request to preload the cache. The request will be queued as
+   'inactive' and will be requested after the given number
+   of cycles have passed from the point the request is activated.  */
+void
+request_cache_preload (SIM_CPU *cpu, FRV_CACHE *cache, int cycles)
+{
+  CACHE_QUEUE_ELEMENT *q;
+  FRV_VLIW *vliw;
+  int slot;
+
+  if (cache_queue.ix >= CACHE_QUEUE_SIZE)
+    abort (); /* TODO: Make the queue dynamic */
+
+  q = & cache_queue.q[cache_queue.ix];
+  ++cache_queue.ix;
+
+  q->reqno = cache_queue.reqno++;
+  q->request = cache_preload;
+  q->cache = cache;
+  q->address = CPU_LOAD_ADDRESS (cpu);
+  q->length = CPU_LOAD_LENGTH (cpu);
+  q->lock = CPU_LOAD_LOCK (cpu);
+  q->cycles = cycles;
+  q->active = 0;
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  q->slot = (*vliw->current_vliw)[slot];
+
+  CPU_LOAD_LENGTH (cpu) = 0;
+}
+
+/* Queue a request to unlock the cache. The request will be queued as
+   'inactive' and will be requested after the given number
+   of cycles have passed from the point the request is activated.  */
+void
+request_cache_unlock (SIM_CPU *cpu, FRV_CACHE *cache, int cycles)
+{
+  CACHE_QUEUE_ELEMENT *q;
+  FRV_VLIW *vliw;
+  int slot;
+
+  if (cache_queue.ix >= CACHE_QUEUE_SIZE)
+    abort (); /* TODO: Make the queue dynamic */
+
+  q = & cache_queue.q[cache_queue.ix];
+  ++cache_queue.ix;
+
+  q->reqno = cache_queue.reqno++;
+  q->request = cache_unlock;
+  q->cache = cache;
+  q->address = CPU_LOAD_ADDRESS (cpu);
+  q->cycles = cycles;
+  q->active = 0;
+
+  vliw = CPU_VLIW (cpu);
+  slot = vliw->next_slot - 1;
+  q->slot = (*vliw->current_vliw)[slot];
+}
+
+static void
+submit_cache_request (CACHE_QUEUE_ELEMENT *q)
+{
+  switch (q->request)
+    {
+    case cache_load:
+      frv_cache_request_load (q->cache, q->reqno, q->address, q->slot);
+      break;
+    case cache_flush:
+      frv_cache_request_invalidate (q->cache, q->reqno, q->address, q->slot,
+				    q->all, 1/*flush*/);
+      break;
+    case cache_invalidate:
+      frv_cache_request_invalidate (q->cache, q->reqno, q->address, q->slot,
+				   q->all, 0/*flush*/);
+      break;
+    case cache_preload:
+      frv_cache_request_preload (q->cache, q->address, q->slot,
+				 q->length, q->lock);
+      break;
+    case cache_unlock:
+      frv_cache_request_unlock (q->cache, q->address, q->slot);
+      break;
+    default:
+      abort ();
+    }
+}
+
+/* Activate all inactive load requests.  */
+static void
+activate_cache_requests (SIM_CPU *cpu)
+{
+  int i;
+  for (i = 0; i < cache_queue.ix; ++i)
+    {
+      CACHE_QUEUE_ELEMENT *q = & cache_queue.q[i];
+      if (! q->active)
+	{
+	  q->active = 1;
+	  /* Submit the request now if the cycle count is zero.  */
+	  if (q->cycles == 0)
+	    submit_cache_request (q);
+	}
+    }
+}
+
+/* Check to see if a load is pending which affects the given register(s).
+ */
+int
+load_pending_for_register (SIM_CPU *cpu, int regnum, int words, int regtype)
+{
+  int i;
+  for (i = 0; i < cache_queue.ix; ++i)
+    {
+      CACHE_QUEUE_ELEMENT *q = & cache_queue.q[i];
+
+      /* Must be the same kind of register.  */
+      if (! q->active || q->request != cache_load || q->regtype != regtype)
+	continue;
+
+      /* If the registers numbers are equal, then we have a match.  */
+      if (q->regnum == regnum)
+	return 1; /* load pending */
+
+      /* Check for overlap of a load with a multi-word register.  */
+      if (regnum < q->regnum)
+	{
+	  if (regnum + words > q->regnum)
+	    return 1;
+	}
+      /* Check for overlap of a multi-word load with the register.  */
+      else
+	{
+	  int data_words = (q->length + sizeof (SI) - 1) / sizeof (SI);
+	  if (q->regnum + data_words > regnum)
+	    return 1;
+	}
+    }
+
+  return 0; /* no load pending */
+}
+
+/* Check to see if a cache flush pending which affects the given address.  */
+static int
+flush_pending_for_address (SIM_CPU *cpu, SI address)
+{
+  int line_mask = ~(CPU_DATA_CACHE (cpu)->line_size - 1);
+  int i;
+  for (i = 0; i < cache_queue.ix; ++i)
+    {
+      CACHE_QUEUE_ELEMENT *q = & cache_queue.q[i];
+
+      /* Must be the same kind of request and active.  */
+      if (! q->active || q->request != cache_flush)
+	continue;
+
+      /* If the addresses are equal, then we have a match.  */
+      if ((q->address & line_mask) == (address & line_mask))
+	return 1; /* flush pending */
+    }
+
+  return 0; /* no flush pending */
+}
+
+static void
+remove_cache_queue_element (SIM_CPU *cpu, int i)
+{
+  /* If we are removing the load of a FR register, then remember which one(s).
+   */
+  CACHE_QUEUE_ELEMENT q = cache_queue.q[i];
+
+  for (--cache_queue.ix; i < cache_queue.ix; ++i)
+    cache_queue.q[i] = cache_queue.q[i + 1];
+
+  /* If we removed a load of a FR register, check to see if any other loads
+     of that register is still queued. If not, then apply the queued post
+     processing time of that register to its latency.  Also apply
+     1 extra cycle of latency to the register since it was a floating point
+     load.  */
+  if (q.request == cache_load && q.regtype != REGTYPE_NONE)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int data_words = (q.length + sizeof (SI) - 1) / sizeof (SI);
+      int j;
+      for (j = 0; j < data_words; ++j)
+	{
+	  int regnum = q.regnum + j;
+	  if (! load_pending_for_register (cpu, regnum, 1, q.regtype))
+	    {
+	      if (q.regtype == REGTYPE_FR)
+		{
+		  int *fr = ps->fr_busy;
+		  fr[regnum] += 1 + ps->fr_ptime[regnum];
+		  ps->fr_ptime[regnum] = 0;
+		}
+	    }
+	}
+    }
+}
+
+/* Copy data from the cache buffer to the target register(s).  */
+static void
+copy_load_data (SIM_CPU *current_cpu, FRV_CACHE *cache, int slot,
+		CACHE_QUEUE_ELEMENT *q)
+{
+  switch (q->length)
+    {
+    case 1:
+      if (q->regtype == REGTYPE_FR)
+	{
+	  if (q->is_signed)
+	    {
+	      QI value = CACHE_RETURN_DATA (cache, slot, q->address, QI, 1);
+	      SET_H_FR (q->regnum, value);
+	    }
+	  else
+	    {
+	      UQI value = CACHE_RETURN_DATA (cache, slot, q->address, UQI, 1);
+	      SET_H_FR (q->regnum, value);
+	    }
+	}
+      else
+	{
+	  if (q->is_signed)
+	    {
+	      QI value = CACHE_RETURN_DATA (cache, slot, q->address, QI, 1);
+	      SET_H_GR (q->regnum, value);
+	    }
+	  else
+	    {
+	      UQI value = CACHE_RETURN_DATA (cache, slot, q->address, UQI, 1);
+	      SET_H_GR (q->regnum, value);
+	    }
+	}
+      break;
+    case 2:
+      if (q->regtype == REGTYPE_FR)
+	{
+	  if (q->is_signed)
+	    {
+	      HI value = CACHE_RETURN_DATA (cache, slot, q->address, HI, 2);
+	      SET_H_FR (q->regnum, value);
+	    }
+	  else
+	    {
+	      UHI value = CACHE_RETURN_DATA (cache, slot, q->address, UHI, 2);
+	      SET_H_FR (q->regnum, value);
+	    }
+	}
+      else
+	{
+	  if (q->is_signed)
+	    {
+	      HI value = CACHE_RETURN_DATA (cache, slot, q->address, HI, 2);
+	      SET_H_GR (q->regnum, value);
+	    }
+	  else
+	    {
+	      UHI value = CACHE_RETURN_DATA (cache, slot, q->address, UHI, 2);
+	      SET_H_GR (q->regnum, value);
+	    }
+	}
+      break;
+    case 4:
+      if (q->regtype == REGTYPE_FR)
+	{
+	  SET_H_FR (q->regnum,
+		    CACHE_RETURN_DATA (cache, slot, q->address, SF, 4));
+	}
+      else
+	{
+	  SET_H_GR (q->regnum,
+		    CACHE_RETURN_DATA (cache, slot, q->address, SI, 4));
+	}
+      break;
+    case 8:
+      if (q->regtype == REGTYPE_FR)
+	{
+	  SET_H_FR_DOUBLE (q->regnum,
+			   CACHE_RETURN_DATA (cache, slot, q->address, DF, 8));
+	}
+      else
+	{
+	  SET_H_GR_DOUBLE (q->regnum,
+			   CACHE_RETURN_DATA (cache, slot, q->address, DI, 8));
+	}
+      break;
+    case 16:
+      if (q->regtype == REGTYPE_FR)
+	frvbf_h_fr_quad_set_handler (current_cpu, q->regnum,
+				     CACHE_RETURN_DATA_ADDRESS (cache, slot,
+								q->address,
+								16));
+      else
+	frvbf_h_gr_quad_set_handler (current_cpu, q->regnum,
+				     CACHE_RETURN_DATA_ADDRESS (cache, slot,
+								q->address,
+								16));
+      break;
+    default:
+      abort ();
+    }
+}
+
+static int
+request_complete (SIM_CPU *cpu, CACHE_QUEUE_ELEMENT *q)
+{
+  FRV_CACHE* cache;
+  if (! q->active || q->cycles > 0)
+    return 0;
+
+  cache = CPU_DATA_CACHE (cpu);
+  switch (q->request)
+    {
+    case cache_load:
+      /* For loads, we must wait until the data is returned from the cache.  */
+      if (frv_cache_data_in_buffer (cache, 0, q->address, q->reqno))
+	{
+	  copy_load_data (cpu, cache, 0, q);
+	  return 1;
+	}
+      if (frv_cache_data_in_buffer (cache, 1, q->address, q->reqno))
+	{
+	  copy_load_data (cpu, cache, 1, q);
+	  return 1;
+	}
+      break;
+
+    case cache_flush:
+      /* We must wait until the data is flushed.  */
+      if (frv_cache_data_flushed (cache, 0, q->address, q->reqno))
+	return 1;
+      if (frv_cache_data_flushed (cache, 1, q->address, q->reqno))
+	return 1;
+      break;
+
+    default:
+      /* All other requests are complete once they've been made.  */
+      return 1;
+    }
+
+  return 0;
+}
+
+/* Run the insn and data caches through the given number of cycles, taking
+   note of load requests which are fullfilled as a result.  */
+static void
+run_caches (SIM_CPU *cpu, int cycles)
+{
+  FRV_CACHE* data_cache = CPU_DATA_CACHE (cpu);
+  FRV_CACHE* insn_cache = CPU_INSN_CACHE (cpu);
+  int i;
+  /* For each cycle, run the caches, noting which requests have been fullfilled
+     and submitting new requests on their designated cycles.  */
+  for (i = 0; i < cycles; ++i)
+    {
+      int j;
+      /* Run the caches through 1 cycle.  */
+      frv_cache_run (data_cache, 1);
+      frv_cache_run (insn_cache, 1);
+
+      /* Note whether prefetched insn data has been loaded yet.  */
+      for (j = LS; j < FRV_CACHE_PIPELINES; ++j)
+	{
+	  if (frv_insn_fetch_buffer[j].reqno != NO_REQNO
+	      && frv_cache_data_in_buffer (insn_cache, j,
+					   frv_insn_fetch_buffer[j].address,
+					   frv_insn_fetch_buffer[j].reqno))
+	    frv_insn_fetch_buffer[j].reqno = NO_REQNO;
+	}
+
+      /* Check to see which requests have been satisfied and which should
+	 be submitted now.  */
+      for (j = 0; j < cache_queue.ix; ++j)
+	{
+	  CACHE_QUEUE_ELEMENT *q = & cache_queue.q[j];
+	  if (! q->active)
+	    continue;
+
+	  /* If a load has been satisfied, complete the operation and remove it
+	     from the queue.  */
+	  if (request_complete (cpu, q))
+	    {
+	      remove_cache_queue_element (cpu, j);
+	      --j;
+	      continue;
+	    }
+
+	  /* Decrease the cycle count of each queued request.
+	     Submit a request for each queued request whose cycle count has
+	     become zero.  */
+	  --q->cycles;
+	  if (q->cycles == 0)
+	    submit_cache_request (q);
+	}
+    }
+}
+
+static void
+apply_latency_adjustments (SIM_CPU *cpu)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int i;
+  /* update the latencies of the registers.  */
+  int *fr  = ps->fr_busy;
+  int *acc = ps->acc_busy;
+  for (i = 0; i < 64; ++i)
+    {
+      if (ps->fr_busy_adjust[i] > 0)
+	*fr -= ps->fr_busy_adjust[i]; /* OK if it goes negative.  */
+      if (ps->acc_busy_adjust[i] > 0)
+	*acc -= ps->acc_busy_adjust[i]; /* OK if it goes negative.  */
+      ++fr;
+      ++acc;
+    }
+}
+
+/* Account for the number of cycles which have just passed in the latency of
+   various system elements.  Works for negative cycles too so that latency
+   can be extended in the case of insn fetch latency.
+   If negative or zero, then no adjustment is necessary.  */
+static void
+update_latencies (SIM_CPU *cpu, int cycles)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int i;
+  /* update the latencies of the registers.  */
+  int *fdiv;
+  int *fsqrt;
+  int *idiv;
+  int *ccr;
+  int *gr  = ps->gr_busy;
+  int *fr  = ps->fr_busy;
+  int *acc = ps->acc_busy;
+  /* This loop handles GR, FR and ACC registers.  */
+  for (i = 0; i < 64; ++i)
+    {
+      if (*gr <= cycles)
+	{
+	  *gr = 0;
+	  reset_gr_flags (cpu, i);
+	}
+      else
+	*gr -= cycles;
+      /* If the busy drops to 0, then mark the register as
+	 "not in use".  */
+      if (*fr <= cycles)
+	{
+	  int *fr_lat = ps->fr_latency + i;
+	  *fr = 0;
+	  ps->fr_busy_adjust[i] = 0;
+	  /* Only clear flags if this register has no target latency.  */
+	  if (*fr_lat == 0)
+	    reset_fr_flags (cpu, i);
+	}
+      else
+	*fr -= cycles;
+      /* If the busy drops to 0, then mark the register as
+	 "not in use".  */
+      if (*acc <= cycles)
+	{
+	  int *acc_lat = ps->acc_latency + i;
+	  *acc = 0;
+	  ps->acc_busy_adjust[i] = 0;
+	  /* Only clear flags if this register has no target latency.  */
+	  if (*acc_lat == 0)
+	    reset_acc_flags (cpu, i);
+	}
+      else
+	*acc -= cycles;
+      ++gr;
+      ++fr;
+      ++acc;
+    }
+  /* This loop handles CCR registers.  */
+  ccr = ps->ccr_busy;
+  for (i = 0; i < 8; ++i)
+    {
+      if (*ccr <= cycles)
+	{
+	  *ccr = 0;
+	  reset_cc_flags (cpu, i);
+	}
+      else
+	*ccr -= cycles;
+      ++ccr;
+    }
+  /* This loop handles resources.  */
+  idiv = ps->idiv_busy;
+  fdiv = ps->fdiv_busy;
+  fsqrt = ps->fsqrt_busy;
+  for (i = 0; i < 2; ++i)
+    {
+      *idiv = (*idiv <= cycles) ? 0 : (*idiv - cycles);
+      *fdiv = (*fdiv <= cycles) ? 0 : (*fdiv - cycles);
+      *fsqrt = (*fsqrt <= cycles) ? 0 : (*fsqrt - cycles);
+      ++idiv;
+      ++fdiv;
+      ++fsqrt;
+    }
+}
+
+/* Print information about the wait for the given number of cycles.  */
+void
+frv_model_trace_wait_cycles (SIM_CPU *cpu, int cycles, const char *hazard_name)
+{
+  if (TRACE_INSN_P (cpu) && cycles > 0)
+    {
+      SIM_DESC sd = CPU_STATE (cpu);
+      trace_printf (sd, cpu, "**** %s wait %d cycles ***\n",
+		    hazard_name, cycles);
+    }
+}
+
+void
+trace_vliw_wait_cycles (SIM_CPU *cpu)
+{
+  if (TRACE_INSN_P (cpu))
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      frv_model_trace_wait_cycles (cpu, ps->vliw_wait, hazard_name);
+    }
+}
+
+/* Wait for the given number of cycles.  */
+void
+frv_model_advance_cycles (SIM_CPU *cpu, int cycles)
+{
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+  update_latencies (cpu, cycles);
+  run_caches (cpu, cycles);
+  PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
+}
+
+void
+handle_resource_wait (SIM_CPU *cpu)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  if (ps->vliw_wait != 0)
+    frv_model_advance_cycles (cpu, ps->vliw_wait);
+  if (ps->vliw_load_stall > ps->vliw_wait)
+    ps->vliw_load_stall -= ps->vliw_wait;
+  else
+    ps->vliw_load_stall = 0;
+}
+
+/* Account for the number of cycles until these resources will be available
+   again.  */
+static void
+update_target_latencies (SIM_CPU *cpu)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int i;
+  /* update the latencies of the registers.  */
+  int *ccr_lat;
+  int *gr_lat  = ps->gr_latency;
+  int *fr_lat  = ps->fr_latency;
+  int *acc_lat = ps->acc_latency;
+  int *ccr;
+  int *gr = ps->gr_busy;
+  int  *fr = ps->fr_busy;
+  int  *acc = ps->acc_busy;
+  /* This loop handles GR, FR and ACC registers.  */
+  for (i = 0; i < 64; ++i)
+    {
+      if (*gr_lat)
+	{
+	  *gr = *gr_lat;
+	  *gr_lat = 0;
+	}
+      if (*fr_lat)
+	{
+	  *fr = *fr_lat;
+	  *fr_lat = 0;
+	}
+      if (*acc_lat)
+	{
+	  *acc = *acc_lat;
+	  *acc_lat = 0;
+	}
+      ++gr; ++gr_lat;
+      ++fr; ++fr_lat;
+      ++acc; ++acc_lat;
+    }
+  /* This loop handles CCR registers.  */
+  ccr = ps->ccr_busy;
+  ccr_lat = ps->ccr_latency;
+  for (i = 0; i < 8; ++i)
+    {
+      if (*ccr_lat)
+	{
+	  *ccr = *ccr_lat;
+	  *ccr_lat = 0;
+	}
+      ++ccr; ++ccr_lat;
+    }
+}
+
+/* Run the caches until all pending cache flushes are complete.  */
+static void
+wait_for_flush (SIM_CPU *cpu)
+{
+  SI address = CPU_LOAD_ADDRESS (cpu);
+  int wait = 0;
+  while (flush_pending_for_address (cpu, address))
+    {
+      frv_model_advance_cycles (cpu, 1);
+      ++wait;
+    }
+  if (TRACE_INSN_P (cpu) && wait)
+    {
+      sprintf (hazard_name, "Data cache flush address %p:", address);
+      frv_model_trace_wait_cycles (cpu, wait, hazard_name);
+    }
+}
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+void
+frvbf_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+
+  ps->vliw_wait = 0;
+  ps->post_wait = 0;
+  memset (ps->fr_busy_adjust, 0, sizeof (ps->fr_busy_adjust));
+  memset (ps->acc_busy_adjust, 0, sizeof (ps->acc_busy_adjust));
+
+  if (first_p)
+    {
+      ps->vliw_insns++;
+      ps->vliw_cycles = 0;
+      ps->vliw_branch_taken = 0;
+      ps->vliw_load_stall = 0;
+    }
+
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      fr400_model_insn_before (cpu, first_p);
+      break;
+    case bfd_mach_fr500:
+      fr500_model_insn_before (cpu, first_p);
+      break;
+    default:
+      break;
+    }
+
+  if (first_p)
+    wait_for_flush (cpu);
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+
+void
+frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
+
+  /* The number of cycles for a VLIW insn is the maximum number of cycles
+     used by any individual insn within it.  */
+  if (cycles > ps->vliw_cycles)
+    ps->vliw_cycles = cycles;
+
+  if (last_p)
+    {
+      /*  This is the last insn in a VLIW insn.  */
+      struct frv_interrupt_timer *timer = & frv_interrupt_state.timer;
+
+      activate_cache_requests (cpu); /* before advancing cycles.  */
+      apply_latency_adjustments (cpu); /* must go first.  */ 
+      update_target_latencies (cpu); /* must go next.  */ 
+      frv_model_advance_cycles (cpu, ps->vliw_cycles);
+
+      PROFILE_MODEL_LOAD_STALL_CYCLES (p) += ps->vliw_load_stall;
+
+      /* Check the interrupt timer.  cycles contains the total cycle count.  */
+      if (timer->enabled)
+	{
+	  cycles = PROFILE_MODEL_TOTAL_CYCLES (p);
+	  if (timer->current % timer->value
+	      + (cycles - timer->current) >= timer->value)
+	    frv_queue_external_interrupt (cpu, timer->interrupt);
+	  timer->current = cycles;
+	}
+
+      ps->past_first_p = 0; /* Next one will be the first in a new VLIW.  */
+      ps->branch_address = -1;
+    }
+  else
+    ps->past_first_p = 1;
+
+  switch (STATE_ARCHITECTURE (sd)->mach)
+    {
+    case bfd_mach_fr400:
+      fr400_model_insn_after (cpu, last_p, cycles);
+      break;
+    case bfd_mach_fr500:
+      fr500_model_insn_after (cpu, last_p, cycles);
+      break;
+    default:
+      break;
+    }
+}
+
+USI
+frvbf_model_branch (SIM_CPU *current_cpu, PCADDR target, int hint)
+{
+  /* Record the hint and branch address for use in profiling.  */
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+  ps->branch_hint = hint;
+  ps->branch_address = target;
+}
+
+/* Top up the latency of the given GR by the given number of cycles.  */
+void
+update_GR_latency (SIM_CPU *cpu, INT out_GR, int cycles)
+{
+  if (out_GR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *gr = ps->gr_latency;
+      if (gr[out_GR] < cycles)
+	gr[out_GR] = cycles;
+    }
+}
+
+void
+decrease_GR_busy (SIM_CPU *cpu, INT in_GR, int cycles)
+{
+  if (in_GR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *gr = ps->gr_busy;
+      gr[in_GR] -= cycles;
+    }
+}
+
+/* Top up the latency of the given double GR by the number of cycles.  */
+void
+update_GRdouble_latency (SIM_CPU *cpu, INT out_GR, int cycles)
+{
+  if (out_GR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *gr = ps->gr_latency;
+      if (gr[out_GR] < cycles)
+	gr[out_GR] = cycles;
+      if (out_GR < 63 && gr[out_GR + 1] < cycles)
+	gr[out_GR + 1] = cycles;
+    }
+}
+
+void
+update_GR_latency_for_load (SIM_CPU *cpu, INT out_GR, int cycles)
+{
+  if (out_GR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *gr = ps->gr_latency;
+
+      /* The latency of the GR will be at least the number of cycles used
+	 by the insn.  */
+      if (gr[out_GR] < cycles)
+	gr[out_GR] = cycles;
+
+      /* The latency will also depend on how long it takes to retrieve the
+	 data from the cache or memory.  Assume that the load is issued
+	 after the last cycle of the insn.  */
+      request_cache_load (cpu, out_GR, REGTYPE_NONE, cycles);
+    }
+}
+
+void
+update_GRdouble_latency_for_load (SIM_CPU *cpu, INT out_GR, int cycles)
+{
+  if (out_GR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *gr = ps->gr_latency;
+
+      /* The latency of the GR will be at least the number of cycles used
+	 by the insn.  */
+      if (gr[out_GR] < cycles)
+	gr[out_GR] = cycles;
+      if (out_GR < 63 && gr[out_GR + 1] < cycles)
+	gr[out_GR + 1] = cycles;
+
+      /* The latency will also depend on how long it takes to retrieve the
+	 data from the cache or memory.  Assume that the load is issued
+	 after the last cycle of the insn.  */
+      request_cache_load (cpu, out_GR, REGTYPE_NONE, cycles);
+    }
+}
+
+void
+update_GR_latency_for_swap (SIM_CPU *cpu, INT out_GR, int cycles)
+{
+  update_GR_latency_for_load (cpu, out_GR, cycles);
+}
+
+/* Top up the latency of the given FR by the given number of cycles.  */
+void
+update_FR_latency (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr = ps->fr_latency;
+      if (fr[out_FR] < cycles)
+	fr[out_FR] = cycles;
+    }
+}
+
+/* Top up the latency of the given double FR by the number of cycles.  */
+void
+update_FRdouble_latency (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr = ps->fr_latency;
+      if (fr[out_FR] < cycles)
+	fr[out_FR] = cycles;
+      if (out_FR < 63 && fr[out_FR + 1] < cycles)
+	fr[out_FR + 1] = cycles;
+    }
+}
+
+void
+update_FR_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr = ps->fr_latency;
+
+      /* The latency of the FR will be at least the number of cycles used
+	 by the insn.  */
+      if (fr[out_FR] < cycles)
+	fr[out_FR] = cycles;
+
+      /* The latency will also depend on how long it takes to retrieve the
+	 data from the cache or memory.  Assume that the load is issued
+	 after the last cycle of the insn.  */
+      request_cache_load (cpu, out_FR, REGTYPE_FR, cycles);
+    }
+}
+
+void
+update_FRdouble_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr = ps->fr_latency;
+	  
+      /* The latency of the FR will be at least the number of cycles used
+	 by the insn.  */
+      if (fr[out_FR] < cycles)
+	fr[out_FR] = cycles;
+      if (out_FR < 63 && fr[out_FR + 1] < cycles)
+	fr[out_FR + 1] = cycles;
+
+      /* The latency will also depend on how long it takes to retrieve the
+	 data from the cache or memory.  Assume that the load is issued
+	 after the last cycle of the insn.  */
+      request_cache_load (cpu, out_FR, REGTYPE_FR, cycles);
+    }
+}
+
+/* Top up the post-processing time of the given FR by the given number of
+   cycles.  */
+void
+update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles)
+{
+  if (out_ACC >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      /* No load can be pending on this register. Apply the cycles
+	 directly to the latency of the register.  */
+      int *acc = ps->acc_latency;
+      acc[out_ACC] += cycles;
+    }
+}
+
+void
+decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
+{
+  if (out_ACC >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *acc = ps->acc_busy;
+      acc[out_ACC] -= cycles;
+      if (ps->acc_busy_adjust[out_ACC] >= 0
+	  && cycles > ps->acc_busy_adjust[out_ACC])
+	ps->acc_busy_adjust[out_ACC] = cycles;
+    }
+}
+
+void
+decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr = ps->fr_busy;
+      fr[out_FR] -= cycles;
+      if (ps->fr_busy_adjust[out_FR] >= 0
+	  && cycles > ps->fr_busy_adjust[out_FR])
+	ps->fr_busy_adjust[out_FR] = cycles;
+    }
+}
+
+void
+increase_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
+{
+  if (out_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr = ps->fr_busy;
+      fr[out_FR] += cycles;
+    }
+}
+
+/* Top up the latency of the given ACC by the given number of cycles.  */
+void
+update_ACC_latency (SIM_CPU *cpu, INT out_ACC, int cycles)
+{
+  if (out_ACC >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *acc = ps->acc_latency;
+      if (acc[out_ACC] < cycles)
+	acc[out_ACC] = cycles;
+    }
+}
+
+/* Top up the latency of the given CCR by the given number of cycles.  */
+void
+update_CCR_latency (SIM_CPU *cpu, INT out_CCR, int cycles)
+{
+  if (out_CCR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *ccr = ps->ccr_latency;
+      if (ccr[out_CCR] < cycles)
+	ccr[out_CCR] = cycles;
+    }
+}
+
+/* Top up the latency of the given integer division resource by the given
+   number of cycles.  */
+void
+update_idiv_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
+{
+  /* operate directly on the busy cycles since each resource can only
+     be used once in a VLIW insn.  */
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *r = ps->idiv_busy;
+  r[in_resource] = cycles;
+}
+
+/* Set the latency of the given resource to the given number of cycles.  */
+void
+update_fdiv_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
+{
+  /* operate directly on the busy cycles since each resource can only
+     be used once in a VLIW insn.  */
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *r = ps->fdiv_busy;
+  r[in_resource] = cycles;
+}
+
+/* Set the latency of the given resource to the given number of cycles.  */
+void
+update_fsqrt_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
+{
+  /* operate directly on the busy cycles since each resource can only
+     be used once in a VLIW insn.  */
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *r = ps->fsqrt_busy;
+  r[in_resource] = cycles;
+}
+
+/* Set the branch penalty to the given number of cycles.  */
+void
+update_branch_penalty (SIM_CPU *cpu, int cycles)
+{
+  /* operate directly on the busy cycles since only one branch can occur
+     in a VLIW insn.  */
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  ps->branch_penalty = cycles;
+}
+
+/* Check the availability of the given GR register and update the number
+   of cycles the current VLIW insn must wait until it is available.  */
+void
+vliw_wait_for_GR (SIM_CPU *cpu, INT in_GR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *gr = ps->gr_busy;
+  /* If the latency of the register is greater than the current wait
+     then update the current wait.  */
+  if (in_GR >= 0 && gr[in_GR] > ps->vliw_wait)
+    {
+      if (TRACE_INSN_P (cpu))
+	sprintf (hazard_name, "Data hazard for gr%d:", in_GR);
+      ps->vliw_wait = gr[in_GR];
+    }
+}
+
+/* Check the availability of the given GR register and update the number
+   of cycles the current VLIW insn must wait until it is available.  */
+void
+vliw_wait_for_GRdouble (SIM_CPU *cpu, INT in_GR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *gr = ps->gr_busy;
+  /* If the latency of the register is greater than the current wait
+     then update the current wait.  */
+  if (in_GR >= 0)
+    {
+      if (gr[in_GR] > ps->vliw_wait)
+	{
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for gr%d:", in_GR);
+	  ps->vliw_wait = gr[in_GR];
+	}
+      if (in_GR < 63 && gr[in_GR + 1] > ps->vliw_wait)
+	{
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for gr%d:", in_GR + 1);
+	  ps->vliw_wait = gr[in_GR + 1];
+	}
+    }
+}
+
+/* Check the availability of the given FR register and update the number
+   of cycles the current VLIW insn must wait until it is available.  */
+void
+vliw_wait_for_FR (SIM_CPU *cpu, INT in_FR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *fr = ps->fr_busy;
+  /* If the latency of the register is greater than the current wait
+     then update the current wait.  */
+  if (in_FR >= 0 && fr[in_FR] > ps->vliw_wait)
+    {
+      if (TRACE_INSN_P (cpu))
+	sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
+      ps->vliw_wait = fr[in_FR];
+    }
+}
+
+/* Check the availability of the given GR register and update the number
+   of cycles the current VLIW insn must wait until it is available.  */
+void
+vliw_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *fr = ps->fr_busy;
+  /* If the latency of the register is greater than the current wait
+     then update the current wait.  */
+  if (in_FR >= 0)
+    {
+      if (fr[in_FR] > ps->vliw_wait)
+	{
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
+	  ps->vliw_wait = fr[in_FR];
+	}
+      if (in_FR < 63 && fr[in_FR + 1] > ps->vliw_wait)
+	{
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR + 1);
+	  ps->vliw_wait = fr[in_FR + 1];
+	}
+    }
+}
+
+/* Check the availability of the given CCR register and update the number
+   of cycles the current VLIW insn must wait until it is available.  */
+void
+vliw_wait_for_CCR (SIM_CPU *cpu, INT in_CCR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *ccr = ps->ccr_busy;
+  /* If the latency of the register is greater than the current wait
+     then update the current wait.  */
+  if (in_CCR >= 0 && ccr[in_CCR] > ps->vliw_wait)
+    {
+      if (TRACE_INSN_P (cpu))
+	{
+	  if (in_CCR > 3)
+	    sprintf (hazard_name, "Data hazard for icc%d:", in_CCR-4);
+	  else
+	    sprintf (hazard_name, "Data hazard for fcc%d:", in_CCR);
+	}
+      ps->vliw_wait = ccr[in_CCR];
+    }
+}
+
+/* Check the availability of the given ACC register and update the number
+   of cycles the current VLIW insn must wait until it is available.  */
+void
+vliw_wait_for_ACC (SIM_CPU *cpu, INT in_ACC)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *acc = ps->acc_busy;
+  /* If the latency of the register is greater than the current wait
+     then update the current wait.  */
+  if (in_ACC >= 0 && acc[in_ACC] > ps->vliw_wait)
+    {
+      if (TRACE_INSN_P (cpu))
+	sprintf (hazard_name, "Data hazard for acc%d:", in_ACC);
+      ps->vliw_wait = acc[in_ACC];
+    }
+}
+
+/* Check the availability of the given integer division resource and update
+   the number of cycles the current VLIW insn must wait until it is available.
+*/
+void
+vliw_wait_for_idiv_resource (SIM_CPU *cpu, INT in_resource)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *r = ps->idiv_busy;
+  /* If the latency of the resource is greater than the current wait
+     then update the current wait.  */
+  if (r[in_resource] > ps->vliw_wait)
+    {
+      if (TRACE_INSN_P (cpu))
+	{
+	  sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource);
+	}
+      ps->vliw_wait = r[in_resource];
+    }
+}
+
+/* Check the availability of the given float division resource and update
+   the number of cycles the current VLIW insn must wait until it is available.
+*/
+void
+vliw_wait_for_fdiv_resource (SIM_CPU *cpu, INT in_resource)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *r = ps->fdiv_busy;
+  /* If the latency of the resource is greater than the current wait
+     then update the current wait.  */
+  if (r[in_resource] > ps->vliw_wait)
+    {
+      if (TRACE_INSN_P (cpu))
+	{
+	  sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource);
+	}
+      ps->vliw_wait = r[in_resource];
+    }
+}
+
+/* Check the availability of the given float square root resource and update
+   the number of cycles the current VLIW insn must wait until it is available.
+*/
+void
+vliw_wait_for_fsqrt_resource (SIM_CPU *cpu, INT in_resource)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *r = ps->fsqrt_busy;
+  /* If the latency of the resource is greater than the current wait
+     then update the current wait.  */
+  if (r[in_resource] > ps->vliw_wait)
+    {
+      if (TRACE_INSN_P (cpu))
+	{
+	  sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource);
+	}
+      ps->vliw_wait = r[in_resource];
+    }
+}
+
+/* Run the caches until all requests for the given register(s) are satisfied. */
+void
+load_wait_for_GR (SIM_CPU *cpu, INT in_GR)
+{
+  if (in_GR >= 0)
+    {
+      int wait = 0;
+      while (load_pending_for_register (cpu, in_GR, 1/*words*/, REGTYPE_NONE))
+	{
+	  frv_model_advance_cycles (cpu, 1);
+	  ++wait;
+	}
+      if (wait)
+	{
+	  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+	  ps->vliw_wait += wait;
+	  ps->vliw_load_stall += wait;
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for gr%d:", in_GR);
+	}
+    }
+}
+
+void
+load_wait_for_FR (SIM_CPU *cpu, INT in_FR)
+{
+  if (in_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr;
+      int wait = 0;
+      while (load_pending_for_register (cpu, in_FR, 1/*words*/, REGTYPE_FR))
+	{
+	  frv_model_advance_cycles (cpu, 1);
+	  ++wait;
+	}
+      /* Post processing time may have been added to the register's
+	 latency after the loads were processed. Account for that too.
+      */
+      fr = ps->fr_busy;
+      if (fr[in_FR])
+	{
+	  wait += fr[in_FR];
+	  frv_model_advance_cycles (cpu, fr[in_FR]);
+	}
+      /* Update the vliw_wait with the number of cycles we waited for the
+	 load and any post-processing.  */
+      if (wait)
+	{
+	  ps->vliw_wait += wait;
+	  ps->vliw_load_stall += wait;
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
+	}
+    }
+}
+
+void
+load_wait_for_GRdouble (SIM_CPU *cpu, INT in_GR)
+{
+  if (in_GR >= 0)
+    {
+      int wait = 0;
+      while (load_pending_for_register (cpu, in_GR, 2/*words*/, REGTYPE_NONE))
+	{
+	  frv_model_advance_cycles (cpu, 1);
+	  ++wait;
+	}
+      if (wait)
+	{
+	  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+	  ps->vliw_wait += wait;
+	  ps->vliw_load_stall += wait;
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for gr%d:", in_GR);
+	}
+    }
+}
+
+void
+load_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR)
+{
+  if (in_FR >= 0)
+    {
+      FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+      int *fr;
+      int wait = 0;
+      while (load_pending_for_register (cpu, in_FR, 2/*words*/, REGTYPE_FR))
+	{
+	  frv_model_advance_cycles (cpu, 1);
+	  ++wait;
+	}
+      /* Post processing time may have been added to the registers'
+	 latencies after the loads were processed. Account for that too.
+      */
+      fr = ps->fr_busy;
+      if (fr[in_FR])
+	{
+	  wait += fr[in_FR];
+	  frv_model_advance_cycles (cpu, fr[in_FR]);
+	}
+      if (in_FR < 63)
+	{
+	  if (fr[in_FR + 1])
+	    {
+	      wait += fr[in_FR + 1];
+	      frv_model_advance_cycles (cpu, fr[in_FR + 1]);
+	    }
+	}
+      /* Update the vliw_wait with the number of cycles we waited for the
+	 load and any post-processing.  */
+      if (wait)
+	{
+	  ps->vliw_wait += wait;
+	  ps->vliw_load_stall += wait;
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
+	}
+    }
+}
+
+void
+enforce_full_fr_latency (SIM_CPU *cpu, INT in_FR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  ps->fr_busy_adjust [in_FR] = -1;
+}
+
+/* Calculate how long the post processing for a floating point insn must
+   wait for resources to become available.  */
+int
+post_wait_for_FR (SIM_CPU *cpu, INT in_FR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *fr = ps->fr_busy;
+
+  if (in_FR >= 0 && fr[in_FR] > ps->post_wait)
+    {
+      ps->post_wait = fr[in_FR];
+      if (TRACE_INSN_P (cpu))
+	sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
+    }
+}
+
+/* Calculate how long the post processing for a floating point insn must
+   wait for resources to become available.  */
+int
+post_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *fr = ps->fr_busy;
+
+  if (in_FR >= 0)
+    {
+      if (fr[in_FR] > ps->post_wait)
+	{
+	  ps->post_wait = fr[in_FR];
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR);
+	}
+      if (in_FR < 63 && fr[in_FR + 1] > ps->post_wait)
+	{
+	  ps->post_wait = fr[in_FR + 1];
+	  if (TRACE_INSN_P (cpu))
+	    sprintf (hazard_name, "Data hazard for fr%d:", in_FR + 1);
+	}
+    }
+}
+
+int
+post_wait_for_ACC (SIM_CPU *cpu, INT in_ACC)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *acc = ps->acc_busy;
+
+  if (in_ACC >= 0 && acc[in_ACC] > ps->post_wait)
+    {
+      ps->post_wait = acc[in_ACC];
+      if (TRACE_INSN_P (cpu))
+	sprintf (hazard_name, "Data hazard for acc%d:", in_ACC);
+    }
+}
+
+int
+post_wait_for_CCR (SIM_CPU *cpu, INT in_CCR)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *ccr = ps->ccr_busy;
+
+  if (in_CCR >= 0 && ccr[in_CCR] > ps->post_wait)
+    {
+      ps->post_wait = ccr[in_CCR];
+      if (TRACE_INSN_P (cpu))
+	{
+	  if (in_CCR > 3)
+	    sprintf (hazard_name, "Data hazard for icc%d:", in_CCR - 4);
+	  else
+	    sprintf (hazard_name, "Data hazard for fcc%d:", in_CCR);
+	}
+    }
+}
+
+int
+post_wait_for_fdiv (SIM_CPU *cpu, INT slot)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *fdiv = ps->fdiv_busy;
+
+  /* Multiple floating point divisions in the same slot need only wait 1
+     extra cycle.  */
+  if (fdiv[slot] > 0 && 1 > ps->post_wait)
+    {
+      ps->post_wait = 1;
+      if (TRACE_INSN_P (cpu))
+	{
+	  sprintf (hazard_name, "Resource hazard for floating point division in slot F%d:", slot);
+	}
+    }
+}
+
+int
+post_wait_for_fsqrt (SIM_CPU *cpu, INT slot)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  int *fsqrt = ps->fsqrt_busy;
+
+  /* Multiple floating point square roots in the same slot need only wait 1
+     extra cycle.  */
+  if (fsqrt[slot] > 0 && 1 > ps->post_wait)
+    {
+      ps->post_wait = 1;
+      if (TRACE_INSN_P (cpu))
+	{
+	  sprintf (hazard_name, "Resource hazard for square root in slot F%d:", slot);
+	}
+    }
+}
+
+/* Print cpu-specific profile information.  */
+#define COMMAS(n) sim_add_commas (comma_buf, sizeof (comma_buf), (n))
+
+static void
+print_cache (SIM_CPU *cpu, FRV_CACHE *cache, const char *cache_name)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (cache != NULL)
+    {
+      char comma_buf[20];
+      unsigned accesses;
+
+      sim_io_printf (sd, "  %s Cache\n\n", cache_name);
+      accesses = cache->statistics.accesses;
+      sim_io_printf (sd, "    Total accesses:  %s\n", COMMAS (accesses));
+      if (accesses != 0)
+	{
+	  float rate;
+	  unsigned hits = cache->statistics.hits;
+	  sim_io_printf (sd, "    Hits:            %s\n", COMMAS (hits));
+	  rate = (float)hits / accesses;
+	  sim_io_printf (sd, "    Hit rate:        %.2f%%\n", rate * 100);
+	}
+    }
+  else
+    sim_io_printf (sd, "  Model %s has no %s cache\n",
+		   MODEL_NAME (CPU_MODEL (cpu)), cache_name);
+
+  sim_io_printf (sd, "\n");
+}
+
+static char *
+slot_names[] =
+{
+  "none",
+  "I0", "I1", "I01",
+  "FM1", "FM1", "FM01",
+  "B0", "B1", "B01",
+  "C"
+};
+
+static void
+print_parallel (SIM_CPU *cpu, int verbose)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+  unsigned total, vliw;
+  char comma_buf[20];
+  float average;
+
+  sim_io_printf (sd, "Model %s Parallelization\n\n",
+		 MODEL_NAME (CPU_MODEL (cpu)));
+
+  total = PROFILE_TOTAL_INSN_COUNT (p);
+  sim_io_printf (sd, "  Total instructions:           %s\n", COMMAS (total));
+  vliw = ps->vliw_insns;
+  sim_io_printf (sd, "  VLIW instructions:            %s\n", COMMAS (vliw));
+  average = (float)total / vliw;
+  sim_io_printf (sd, "  Average VLIW length:          %.2f\n", average);
+  average = (float)PROFILE_MODEL_TOTAL_CYCLES (p) / vliw;
+  sim_io_printf (sd, "  Cycles per VLIW instruction:  %.2f\n", average);
+  average = (float)total / PROFILE_MODEL_TOTAL_CYCLES (p);
+  sim_io_printf (sd, "  Instructions per cycle:       %.2f\n", average);
+
+  if (verbose)
+    {
+      int i;
+      int max_val = 0;
+      int max_name_len = 0;
+      for (i = UNIT_NIL + 1; i < UNIT_NUM_UNITS; ++i)
+	{
+	  int len;
+	  if (INSNS_IN_SLOT (i) > max_val)
+	    max_val = INSNS_IN_SLOT (i);
+	  len = strlen (slot_names[i]);
+	  if (len > max_name_len)
+	    max_name_len = len;
+	}
+      if (max_val > 0)
+	{
+	  sim_io_printf (sd, "\n");
+	  sim_io_printf (sd, "  Instructions per slot:\n");
+	  sim_io_printf (sd, "\n");
+	  for (i = UNIT_NIL + 1; i < UNIT_NUM_UNITS; ++i)
+	    {
+	      if (INSNS_IN_SLOT (i) != 0)
+		{
+		  sim_io_printf (sd, "  %*s: %*s: ",
+				 max_name_len, slot_names[i],
+				 max_val < 10000 ? 5 : 10,
+				 COMMAS (INSNS_IN_SLOT (i)));
+		  sim_profile_print_bar (sd, PROFILE_HISTOGRAM_WIDTH,
+					 INSNS_IN_SLOT (i),
+					 max_val);
+		  sim_io_printf (sd, "\n");
+		}
+	    }
+	} /* details to print */
+    } /* verbose */
+
+  sim_io_printf (sd, "\n");
+}
+
+void
+frv_profile_info (SIM_CPU *cpu, int verbose)
+{
+  /* FIXME: Need to add smp support.  */
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+
+#if WITH_PROFILE_PARALLEL_P
+  if (PROFILE_FLAGS (p) [PROFILE_PARALLEL_IDX])
+    print_parallel (cpu, verbose);
+#endif
+
+#if WITH_PROFILE_CACHE_P
+  if (PROFILE_FLAGS (p) [PROFILE_CACHE_IDX])
+    {
+      SIM_DESC sd = CPU_STATE (cpu);
+      sim_io_printf (sd, "Model %s Cache Statistics\n\n",
+		     MODEL_NAME (CPU_MODEL (cpu)));
+      print_cache (cpu, CPU_INSN_CACHE (cpu), "Instruction");
+      print_cache (cpu, CPU_DATA_CACHE (cpu), "Data");
+    }
+#endif /* WITH_PROFILE_CACHE_P */
+}
+
+/* A hack to get registers referenced for profiling.  */
+SI frv_ref_SI (SI ref) {return ref;}
+#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/frv/profile.h b/sim/frv/profile.h
new file mode 100644
index 00000000000..80cf5835023
--- /dev/null
+++ b/sim/frv/profile.h
@@ -0,0 +1,194 @@
+/* Profiling definitions for the FRV simulator
+   Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef PROFILE_H
+#define PROFILE_H
+
+/* This struct defines the state of profiling.  All fields are of general
+   use to all machines.  */
+typedef struct
+{
+  long vliw_insns; /* total number of VLIW insns.  */
+  long vliw_wait;  /* number of cycles that the current VLIW insn must wait.  */
+  long post_wait;  /* number of cycles that post processing in the current
+                      VLIW insn must wait.  */
+  long vliw_cycles;/* number of cycles used by current VLIW insn.  */
+
+  int  past_first_p; /* Not the first insns in the VLIW */
+
+  /* Register latencies.  Must be signed since they can be temporarily
+     negative.  */
+  int gr_busy[64];       /* Cycles until GR is available.  */
+  int fr_busy[64];       /* Cycles until FR is available.  */
+  int acc_busy[64];      /* Cycles until FR is available.  */
+  int ccr_busy[8];       /* Cycles until ICC/FCC is available.  */
+  int idiv_busy[2];      /* Cycles until integer division unit is available.  */
+  int fdiv_busy[2];      /* Cycles until float division unit is available.  */
+  int fsqrt_busy[2];     /* Cycles until square root unit is available.  */
+  int branch_penalty;    /* Cycles until branch is complete.  */
+
+  int gr_latency[64];    /* Cycles until target GR is available.  */
+  int fr_latency[64];    /* Cycles until target FR is available.  */
+  int acc_latency[64];   /* Cycles until target FR is available.  */
+  int ccr_latency[8];    /* Cycles until target ICC/FCC is available.  */
+
+  /* Some registers are busy for a shorter number of cycles than normal
+     depending on how they are used next. the xxx_busy_adjust arrays keep track
+     of how many cycles to adjust down.
+  */
+  int fr_busy_adjust[64];
+  int acc_busy_adjust[64];
+
+  /* Register flags.  Each bit represents one register.  */
+  DI cur_gr_complex;
+  DI prev_gr_complex;
+
+  /* Keep track of the total queued post-processing time required before a
+     resource is available.  This is applied to the resource's latency once all
+     pending loads for the resource are completed.  */
+  int fr_ptime[64];
+
+  int branch_hint;       /* hint field from branch insn.  */
+  USI branch_address;    /* Address of predicted branch.  */
+  USI insn_fetch_address;/* Address of sequential insns fetched.  */
+
+  /* We need to know when the first branch of a vliw insn is taken, so that
+     we don't consider the remaining branches in the vliw insn.  */
+  int vliw_branch_taken;
+
+  /* Keep track of the maximum load stall for each VLIW insn.  */
+  int vliw_load_stall;
+
+  /* Need to know if all cache entries are affected by various cache
+     operations.  */
+  int all_cache_entries;
+} FRV_PROFILE_STATE;
+
+#define DUAL_REG(reg) ((reg) >= 0 && (reg) < 63 ? (reg) + 1 : -1)
+#define DUAL_DOUBLE(reg) ((reg) >= 0 && (reg) < 61 ? (reg) + 2 : -1)
+
+/* Top up the latency of the given GR by the given number of cycles.  */
+void update_GR_latency (SIM_CPU *, INT, int);
+void update_GRdouble_latency (SIM_CPU *, INT, int);
+void update_GR_latency_for_load (SIM_CPU *, INT, int);
+void update_GRdouble_latency_for_load (SIM_CPU *, INT, int);
+void update_GR_latency_for_swap (SIM_CPU *, INT, int);
+void update_FR_latency (SIM_CPU *, INT, int);
+void update_FRdouble_latency (SIM_CPU *, INT, int);
+void update_FR_latency_for_load (SIM_CPU *, INT, int);
+void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
+void decrease_ACC_busy (SIM_CPU *, INT, int);
+void decrease_FR_busy (SIM_CPU *, INT, int);
+void decrease_GR_busy (SIM_CPU *, INT, int);
+void increase_FR_busy (SIM_CPU *, INT, int);
+void update_ACC_latency (SIM_CPU *, INT, int);
+void update_CCR_latency (SIM_CPU *, INT, int);
+void update_idiv_resource_latency (SIM_CPU *, INT, int);
+void update_fdiv_resource_latency (SIM_CPU *, INT, int);
+void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
+void update_branch_penalty (SIM_CPU *, int);
+void update_ACC_ptime (SIM_CPU *, INT, int);
+void vliw_wait_for_GR (SIM_CPU *, INT);
+void vliw_wait_for_GRdouble (SIM_CPU *, INT);
+void vliw_wait_for_FR (SIM_CPU *, INT);
+void vliw_wait_for_FRdouble (SIM_CPU *, INT);
+void vliw_wait_for_CCR (SIM_CPU *, INT);
+void vliw_wait_for_ACC (SIM_CPU *, INT);
+void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
+void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
+void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
+void load_wait_for_GR (SIM_CPU *, INT);
+void load_wait_for_FR (SIM_CPU *, INT);
+void load_wait_for_GRdouble (SIM_CPU *, INT);
+void load_wait_for_FRdouble (SIM_CPU *, INT);
+void enforce_full_fr_latency (SIM_CPU *, INT);
+int post_wait_for_FR (SIM_CPU *, INT);
+int post_wait_for_FRdouble (SIM_CPU *, INT);
+int post_wait_for_ACC (SIM_CPU *, INT);
+int post_wait_for_CCR (SIM_CPU *, INT);
+int post_wait_for_fdiv (SIM_CPU *, INT);
+int post_wait_for_fsqrt (SIM_CPU *, INT);
+
+void trace_vliw_wait_cycles (SIM_CPU *);
+void handle_resource_wait (SIM_CPU *);
+
+void request_cache_load (SIM_CPU *, INT, int, int);
+void request_cache_flush (SIM_CPU *, FRV_CACHE *, int);
+void request_cache_invalidate (SIM_CPU *, FRV_CACHE *, int);
+void request_cache_preload (SIM_CPU *, FRV_CACHE *, int);
+void request_cache_unlock (SIM_CPU *, FRV_CACHE *, int);
+int  load_pending_for_register (SIM_CPU *, int, int, int);
+
+void set_use_is_gr_complex (SIM_CPU *, INT);
+void set_use_not_gr_complex (SIM_CPU *, INT);
+int  use_is_gr_complex (SIM_CPU *, INT);
+
+typedef struct
+{
+  SI address;
+  unsigned reqno;
+} FRV_INSN_FETCH_BUFFER;
+
+extern FRV_INSN_FETCH_BUFFER frv_insn_fetch_buffer[];
+
+PROFILE_INFO_CPU_CALLBACK_FN frv_profile_info;
+
+enum {
+  /* Simulator specific profile bits begin here.  */
+  /* Profile caches.  */
+  PROFILE_CACHE_IDX = PROFILE_NEXT_IDX,
+  /* Profile parallelization.  */
+  PROFILE_PARALLEL_IDX
+};
+
+/* Masks so WITH_PROFILE can have symbolic values.
+   The case choice here is on purpose.  The lowercase parts are args to
+   --with-profile.  */
+#define PROFILE_cache    (1 << PROFILE_INSN_IDX)
+#define PROFILE_parallel (1 << PROFILE_INSN_IDX)
+
+/* Preprocessor macros to simplify tests of WITH_PROFILE.  */
+#define WITH_PROFILE_CACHE_P    (WITH_PROFILE & PROFILE_insn)
+#define WITH_PROFILE_PARALLEL_P (WITH_PROFILE & PROFILE_insn)
+
+#define FRV_COUNT_CYCLES(cpu, condition) \
+  ((PROFILE_MODEL_P (cpu) && (condition)) || frv_interrupt_state.timer.enabled)
+
+/* Modelling support.  */
+extern int frv_save_profile_model_p;
+
+extern enum FRV_INSN_MODELING {
+  FRV_INSN_NO_MODELING = 0,
+  FRV_INSN_MODEL_PASS_1,
+  FRV_INSN_MODEL_PASS_2,
+  FRV_INSN_MODEL_WRITEBACK
+} model_insn;
+
+void
+frv_model_advance_cycles (SIM_CPU *, int);
+void
+frv_model_trace_wait_cycles (SIM_CPU *, int, const char *);
+
+/* Register types for queued load requests.  */
+#define REGTYPE_NONE 0
+#define REGTYPE_FR   1
+#define REGTYPE_ACC  2
+
+#endif /* PROFILE_H */
diff --git a/sim/frv/registers.c b/sim/frv/registers.c
new file mode 100644
index 00000000000..9ed8112db6c
--- /dev/null
+++ b/sim/frv/registers.c
@@ -0,0 +1,4405 @@
+/* frv simulator support code
+   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+#define IMPL 1 /* Implemented */
+#define SUP  1 /* Supervisor register */
+#define USER 0 /* User register */
+
+#define RESERVED {0x00000000, 0x00000000, 0x00000000, 0xffffffff, ! IMPL, USER}
+
+/* SPR definitions for the general FRV architecture.
+   All registers and all features should be enabled.
+   Initial and reset values are taken from the fr500 LSI.  */
+static FRV_SPR_CONTROL_INFO frv_spr[] =
+{
+  {0x0000107e, 0x0000007c, 0x000060fd, 0xffff9600,   IMPL,   SUP}, /* PSR */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000003,   IMPL,   SUP}, /* PCSR */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000003,   IMPL,   SUP}, /* BPCSR */
+  {0x00000000, 0x00000000, 0x00000000, 0x000007ff,   IMPL,   SUP}, /* TBR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffeffe,   IMPL,   SUP}, /* BPSR */
+
+  /* spr registers 5-15 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED,
+
+  {0x000003c0, 0x00000000, 0xce400000, 0x313fec38,   IMPL,   SUP}, /* HSR0 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR7 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR15 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR23 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR31 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR39 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR47 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR55 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* HSR63 */
+
+  /* spr registers 80-255 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* CCR */
+
+  /* spr registers 257-262 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffff0000,   IMPL,  USER}, /* CCCR */
+
+  /* spr registers 264-271 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x00000003,   IMPL,  USER}, /* LR */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* LCR */
+
+  /* spr registers 274-287 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0xe0000021, 0x20000000, 0xe0000000, 0xffffffc2,   IMPL,  USER}, /* ISR */
+
+  /* spr registers 289-351 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NEEAR0 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NEEAR7 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NEEAR15 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NEEAR23 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NEEAR31 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NESR0 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NESR7 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NESR15 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NESR23 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,  USER}, /* NESR31 */
+
+  {0x0000007f, 0x0000007f, 0x00000000, 0xffffffff,   IMPL,  USER}, /* NECR */
+
+  /* spr registers 417-431 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* GNER0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* GNER1 */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* FNER0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* FNER1 */
+
+  /* spr registers 436-511 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR63 */
+
+  {0x00000100, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR0 */
+  {0x00000026, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR7 */
+  {0x00000200, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000200, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000200, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000200, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000200, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000200, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR63 */
+
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* EIR0 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* EIR7 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* EIR15 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* EIR23 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* EIR31 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESFR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESFR1 */
+
+  /* spr registers 674-767 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,   SUP}, /* SR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,   SUP}, /* SR3 */
+
+  /* spr registers 772-1023 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00800000, 0x00000000, 0x00000000, 0xc0f103ff,   IMPL,  USER}, /* FSR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* FSR63 */
+
+  /* Each FQ register is a pair of 32 bit registers.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* FQ0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* FQ7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* FQ15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* FQ23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* FQ31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+
+  /* spr registers 1152-1271 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* MCILR0 */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000000,   IMPL,   SUP}, /* MCILR1 */
+
+  /* spr registers 1274-1279 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x01e00000, 0x3fff8fc0,   IMPL,  USER}, /* MSR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffc1,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* MSR63 */
+
+  /* Each MQ register is a pair of 32 bit registers.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* MQ0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* MQ7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* MQ15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* MQ23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* MQ31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* Accumulators are read-only by the user except for special
+     insns and side effect of other insns.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC63 */
+
+  /* Accumulator guards are read-only by the user except for special
+     insns and side effect of other insns.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG63 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR63 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR63 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* IAMLR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* IAMLR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMLR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMLR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMLR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMLR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMLR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMLR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMLR63 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP}, /* IAMPR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP}, /* IAMPR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMPR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMPR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMPR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMPR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMPR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMPR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IAMPR63 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* DAMLR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* DAMLR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMLR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMLR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMLR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMLR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMLR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMLR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMLR63 */
+
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP}, /* DAMPR0 */
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP}, /* DAMPR7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMPR15 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMPR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMPR31 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMPR39 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMPR47 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMPR55 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DAMPR63 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* AMCR  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* STBAR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* MMCR */
+
+  /* spr registers 1923-2047 are reserved */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DCR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* BRR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* NMAR */
+
+  RESERVED, /* spr register 2051 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IBAR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IBAR3 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBAR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBAR3 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR00 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR03 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR10 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR13 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR20 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR30 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR33 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR00 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR03 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR10 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR13 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR20 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR23 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR30 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR33 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* CPCFR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* CPCR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* CPSR */
+
+  RESERVED, /* spr register 2095 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* CPESR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* CPESR1 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* CPEMR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* CPEMR1 */
+
+  /* spr registers 2100-2199 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2200-2299 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2300-2399 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2400-2499 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2500-2599 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2600-2699 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2700-2799 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2800-2899 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2900-2999 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3000-3099 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3100-3199 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3200-3299 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3300-3399 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3400-3499 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3500-3599 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3600-3699 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3700-3799 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3800-3847 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0xffffffff, 0xfffffffe,   IMPL,   SUP}, /* IHSR8 */
+
+  /* spr registers 3849-4095 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED
+};
+
+/* SPR definitions for the fr500 machine.
+   See the FR500 LSI for implementation details.  */
+static FRV_SPR_CONTROL_INFO fr500_spr[] =
+{
+  {0x1000107e, 0x1000107c, 0xff0071fd, 0xffff9e00,   IMPL,   SUP}, /* PSR */
+  {0x00000000, 0x00000000, 0x00000003, 0x00000003,   IMPL,   SUP}, /* PCSR */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000003,   IMPL,   SUP}, /* BPCSR */
+  {0x00000000, 0x00000000, 0x0000000f, 0x000007ff,   IMPL,   SUP}, /* TBR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffeffe,   IMPL,   SUP}, /* BPSR */
+
+  /* spr registers 5-15 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED,
+
+  {0x000003c0, 0x00000000, 0xce000c00, 0x313fec38,   IMPL,   SUP}, /* HSR0 */
+
+  /* HSR1-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 80-255 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* CCR */
+
+  /* spr registers 257-262 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffff0000,   IMPL,  USER}, /* CCCR */
+
+  /* spr registers 264-271 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000003, 0x00000003,   IMPL,  USER}, /* LR */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* LCR */
+
+  /* spr registers 274-287 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2,   IMPL,  USER}, /* ISR */
+
+  /* spr registers 289-351 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* NEEAR0-31 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* NESR0-31 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* NECR is unimplemented on the fr500.  */
+  RESERVED,
+
+  /* spr registers 417-431 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* GNER0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* GNER1 */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* FNER0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* FNER1 */
+
+  /* spr registers 436-511 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* EPCR2-7 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR8 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR13 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* EPCR16-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000100, 0x00000100, 0x00000100, 0xffffffff,   IMPL,   SUP}, /* ESR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* ESR2-7 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR8 */
+  {0x00000800, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000800, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000800, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR13 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* ESR16-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* EIR0-31 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* ESFR0 is unimplemented on the fr500.  */
+  RESERVED,
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESFR1 */
+
+  /* spr registers 674-767 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  /* SR0-SR3 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 772-1023 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00800000, 0x00800000, 0x00800000, 0xc0f103ff,   IMPL,  USER}, /* FSR0 */
+
+  /* FSR1-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  /* Each FQ register is a pair of 32 bit registers.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* FQ0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* FQ7 */
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP},
+
+  /* FQ10-31 are unimplemented on the fr500.  */
+  /* Each FQ register is a pair of 32 bit registers.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 1152-1271 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* MCILR0-1 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  /* spr registers 1274-1279 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x01e00000, 0x3fff8fc0,   IMPL,  USER}, /* MSR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffc1,   IMPL,  USER},
+
+  /* MSR2-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* MQ0-31 are unimplemented on the fr500.  */
+  /* Each MQ register is a pair of 32 bit registers.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* Accumulators are read-only by the user except for special
+     insns and side effect of other insns.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC7 */
+
+  /* ACC8-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* Accumulator guards are read-only by the user except for special
+     insns and side effect of other insns.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG7 */
+
+  /* ACCG8-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* EAR0-7 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR8 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR13 */
+
+  /* EAR14-63 are unimplemented on the fr500.  */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* EDR0-1 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR2 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* EDR4-5 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR6 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* EDR8-9 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EDR10 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* EDR12-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* IAMLR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* IAMLR7 */
+
+  /* IAMLR08-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP}, /* IAMPR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP}, /* IAMPR7 */
+
+  /* IAMPR08-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* DAMLR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fffff,   IMPL,   SUP}, /* DAMLR7 */
+
+  /* DAMLR08-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP}, /* DAMPR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff00,   IMPL,   SUP}, /* DAMPR7 */
+
+  /* DAMPR08-63 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000808, 0x00000808, 0x0000ffff, 0xffffffff,   IMPL,   SUP}, /* AMCR  */
+
+  /* STBAR, MMCR not implemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  /* spr registers 1923-2047 are reserved */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DCR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* BRR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* NMAR */
+
+  RESERVED, /* spr register 2051 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IBAR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IBAR3 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBAR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBAR3 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR00 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBDR02-03 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR10 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBDR12-13 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR20 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBDR22-23 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR30 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBDR32-33 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR00 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBMR02-03 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR10 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBMR12-13 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR20 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBMR22-23 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR30 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBMR32-33 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  /* CPCFR, CPCR and CPSR are unimplemented on the fr500.  */
+  RESERVED, RESERVED, RESERVED,
+
+  RESERVED, /* spr register 2095 */
+
+  /* CPESR0-1 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  /* CPEMR0-1 are unimplemented on the fr500.  */
+  RESERVED, RESERVED,
+
+  /* spr registers 2100-2199 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2200-2299 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2300-2399 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2400-2499 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2500-2599 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2600-2699 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2700-2799 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2800-2899 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2900-2999 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3000-3099 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3100-3199 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3200-3299 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3300-3399 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3400-3499 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3500-3599 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3600-3699 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3700-3799 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3800-3847 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xfffffffe,   IMPL,   SUP}, /* IHSR8 */
+
+  /* spr registers 3849-4095 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED
+};
+
+/* SPR definitions for the fr400 machine.
+   See the FR400 LSI for implementation details.  */
+static FRV_SPR_CONTROL_INFO fr400_spr[] =
+{
+  {0x200030fe, 0x200030fc, 0xf00030fd, 0xffffff80,   IMPL,   SUP}, /* PSR */
+  {0x00000000, 0x00000000, 0x00000003, 0x00000003,   IMPL,   SUP}, /* PCSR */
+  {0x00000000, 0x00000000, 0xffffffff, 0x00000003,   IMPL,   SUP}, /* BPCSR */
+  {0x00000000, 0x00000000, 0x0000000f, 0x000007ff,   IMPL,   SUP}, /* TBR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffeffe,   IMPL,   SUP}, /* BPSR */
+
+  /* spr registers 5-15 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED,
+
+  {0x00000d40, 0x00000d40, 0xcc400fc0, 0x317feff8,   IMPL,   SUP}, /* HSR0 */
+
+  /* HSR1-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 80-255 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* CCR */
+
+  /* spr registers 257-262 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffff0000,   IMPL,  USER}, /* CCCR */
+
+  /* spr registers 264-271 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000003, 0x00000003,   IMPL,  USER}, /* LR */
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,   IMPL,  USER}, /* LCR */
+
+  /* spr registers 274-287 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2,   IMPL,  USER}, /* ISR */
+
+  /* spr registers 289-351 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* NEEAR0-31 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* NESR0-31 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* NECR is unimplemented on the fr400.  */
+  RESERVED,
+
+  /* spr registers 417-431 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* GNER0, GNER1, FNER0, FNER1 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 436-511 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EPCR0 */
+
+  /* EPCR1-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000100, 0x00000100, 0x00000100, 0xffffffff,   IMPL,   SUP}, /* ESR0 */
+
+  /* ESR1-13 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESR14 */
+  {0x00000800, 0x00000800, 0x00000800, 0xffffffff,   IMPL,   SUP},
+
+  /* ESR16-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* EIR0-31 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* ESFR0 is unimplemented on the fr400.  */
+  RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* ESFR1 */
+
+  /* spr registers 674-767 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  /* SR0-3 ARE unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 772-1023 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* FSR0-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* FQ0-31 are unimplemented on the fr400.  */
+  /* Each FQ register is a pair of 32 bit registers.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 1152-1271 are reserved */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED,
+
+  /* MCILR0-1 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  /* spr registers 1274-1279 are reserved */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x01c00000, 0x0fff8fc0,   IMPL,  USER}, /* MSR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffcd,   IMPL,  USER},
+
+  /* MSR2-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* MQ0-31 are unimplemented on the fr400.  */
+  /* Each MQ register is a pair of 32 bit registers.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* Accumulators are read-only by the user except for special
+     insns and side effect of other insns.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACC0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+
+  /* ACC4-63 are unimplemented on the fr400.  */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* Accumulator guards are read-only by the user except for special
+     insns and side effect of other insns.  */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER}, /* ACCG0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,  USER},
+
+  /* ACCG4-63 are unimplemented on the fr400.  */
+  RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* EAR0-14 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* EAR15 */
+
+  /* EAR16-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* EDR0-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* IAMLR0-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP}, /* IAMPR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0x000fff02,   IMPL,   SUP}, /* IAMPR7 */
+
+  /* IAMPR08-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* DAMLR0-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP}, /* DAMPR0 */
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000001, 0x000fff00,   IMPL,   SUP}, /* DAMPR7 */
+
+  /* DAMPR08-63 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000808, 0x00000808, 0x00000808, 0xffffffff,   IMPL,   SUP}, /* AMCR  */
+
+  /* STBAR, MMCR not implemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  /* spr registers 1923-2047 are reserved */
+  RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DCR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* BRR */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* NMAR */
+
+  RESERVED, /* spr register 2051 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IBAR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* IBAR3 */
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBAR0 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBAR2-3 not implemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR00 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBDR02-03 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBDR10 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBDR12-13 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  /* DBDR20-23 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* DBDR30-33 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR00 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBMR02-03 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP}, /* DBMR10 */
+  {0x00000000, 0x00000000, 0x00000000, 0xffffffff,   IMPL,   SUP},
+
+  /* DBMR12-13 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  /* DBMR20-23 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* DBMR30-33 are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* CPCFR, CPCR and CPSR are unimplemented on the fr400.  */
+  RESERVED, RESERVED, RESERVED,
+
+  RESERVED, /* spr register 2095 */
+
+  /* CPESR0-1 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  /* CPEMR0-1 are unimplemented on the fr400.  */
+  RESERVED, RESERVED,
+
+  /* spr registers 2100-2199 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2200-2299 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2300-2399 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2400-2499 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2500-2599 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2600-2699 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2700-2799 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2800-2899 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 2900-2999 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3000-3099 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3100-3199 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3200-3299 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3300-3399 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3400-3499 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3500-3599 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3600-3699 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3700-3799 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3800-3899 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 3900-3999 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+  /* spr registers 4000-4095 are reserved */
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+  RESERVED
+};
+
+/* Initialize register control for this cpu */
+void
+frv_register_control_init (SIM_CPU *cpu)
+{
+  FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (cpu);
+  SIM_DESC sd = CPU_STATE (cpu);
+  int mach = STATE_ARCHITECTURE (sd)->mach;
+
+  if (sizeof (fr400_spr) != FRV_MAX_SPR * sizeof (*fr400_spr))
+    abort ();
+  if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr))
+    abort ();
+  if (sizeof (frv_spr) != FRV_MAX_SPR * sizeof (*frv_spr))
+    abort ();
+
+  switch (mach)
+    {
+    case bfd_mach_frvtomcat:
+    case bfd_mach_fr500:
+      control->fr = 1;
+      control->cpr = 0;
+      control->spr = fr500_spr;
+      return;
+    case bfd_mach_fr400:
+      control->fr = 1;
+      control->cpr = 0;
+      control->spr = fr400_spr;
+      return;
+    case bfd_mach_frvsimple:
+      control->fr = 0;
+      control->cpr = 0;
+      control->spr = fr500_spr; /* Use the same spr configuration as fr500.  */
+      return;
+    case bfd_mach_frv:
+      control->fr = 1;
+      control->cpr = 1;
+      control->spr = frv_spr;
+      return;
+    }
+
+  {      
+    IADDR pc = CPU_PC_GET (cpu);
+    sim_engine_abort (sd, cpu, pc,
+		      "Register control not defined for bfd machine %d\n",
+		      mach);
+  }
+}
+
+/* Initialize spr registers.  Used during startup and during hardware reset.  */
+void
+frv_initialize_spr (SIM_CPU *current_cpu)
+{
+  FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
+  FRV_SPR_CONTROL_INFO *spr_control;
+  USI save_mask;
+  int i;
+
+  /* Make sure that PSR.S is set in order to avoid access problems.
+     Set the hardware directly to avoid user/supervisor state change. */
+  CPU (h_psr_s) = 1;
+
+  /* Now initialize each register except PSR.  */
+  for (i = 0; i < FRV_MAX_SPR; ++i)
+    {
+      /* Make sure that the register is implemented and is not PSR.  */
+      spr_control = & control->spr[i];
+      if (spr_control->implemented && i != H_SPR_PSR)
+	{
+	  /* Temporarily disable the read-only mask for this register in order
+	     to initialize read-only fields.  */
+	  save_mask = spr_control->read_only_mask;
+	  spr_control->read_only_mask = 0;
+	  SET_H_SPR (i, spr_control->init_value);
+	  spr_control->read_only_mask = save_mask;
+	}
+    }
+
+  /* Now explicitely set PSR in order to get the correct setting for PSR.S.  */
+  spr_control = & control->spr[H_SPR_PSR];
+  save_mask = spr_control->read_only_mask;
+  spr_control->read_only_mask = 0;
+  SET_H_SPR (H_SPR_PSR, spr_control->init_value);
+  spr_control->read_only_mask = save_mask;
+}
+
+/* Reset spr registers.  Used during software reset.  */
+void
+frv_reset_spr (SIM_CPU *current_cpu)
+{
+  FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
+  FRV_SPR_CONTROL_INFO *spr_control;
+  USI mask;
+  USI new_val;
+  int i;
+  int psr_s;
+
+  /* Save PSR.S so that it can be stored in PSR.PS when initialization is
+     complete.  */
+  psr_s = GET_H_PSR_S ();
+
+  /* Make sure that PSR.S is set in order to avoid access problems.
+     Set the hardware directly to avoid user/supervisor state change. */
+  CPU (h_psr_s) = 1;
+
+  /* Now reset each register except PSR.  */
+  for (i = 0; i < FRV_MAX_SPR; ++i)
+    {
+      /* Make sure that the register is implemented and is not PSR.  */
+      spr_control = & control->spr[i];
+      if (spr_control->implemented && i != H_SPR_PSR)
+	{
+	  mask = spr_control->reset_mask;
+	  new_val = GET_H_SPR (i) & ~mask;
+	  new_val |= spr_control->reset_value & mask;
+	  SET_H_SPR (i, new_val);
+	}
+    }
+
+  /* Now explicitely set PSR in order to get the correct setting for PSR.S.  */
+  spr_control = & control->spr[H_SPR_PSR];
+  mask = spr_control->reset_mask;
+  new_val = GET_H_SPR (H_SPR_PSR) & ~mask;
+  new_val |= spr_control->reset_value & mask;
+  SET_H_SPR (H_SPR_PSR, new_val);
+
+  /* Now set PSR.PS with the previous value of PSR.S.  */
+  SET_H_PSR_PS (psr_s);
+}
+
+/* Check access to spr registers.  */
+void
+frv_check_spr_read_access (SIM_CPU *current_cpu, UINT spr)
+{
+  FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
+
+  if (! control->spr[spr].implemented)
+    {
+      SIM_DESC sd = CPU_STATE (current_cpu);
+      if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+	{
+	  /* On the fr400: if this is an unimplemented accumulator, then
+	     generate an illegal_instruction_interrupt, otherwise no interrupt.
+	  */
+	  if (spr >= H_SPR_ACC0 && spr <= H_SPR_ACC63
+	      || spr >= H_SPR_ACCG0 && spr <= H_SPR_ACCG63)
+	    frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+	}
+      else
+	{
+	  /* On other machines, it's a register_exception.  */
+	  frv_queue_register_exception_interrupt (current_cpu,
+						  FRV_REC_UNIMPLEMENTED);
+	}
+    }
+}
+
+void
+frv_check_spr_write_access (SIM_CPU *current_cpu, UINT spr)
+{
+  /* Both a register exception (unimplemented) and a privileged insn exception
+     are possible. Check for both and the let the priority be resolved by the
+     exception handling code.  */
+  FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
+
+  /* Write access check is a superset of the read access check.  */
+  frv_check_spr_read_access (current_cpu, spr);
+
+  /* Check for write to supervisor register.  */
+  if (control->spr[spr].supervisor && ! GET_H_PSR_S ())
+    frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
+}
+
+void
+frv_fr_registers_available (
+  SIM_CPU *current_cpu, int *hi_available, int *lo_available
+)
+{
+  int all_implemented;
+  SI hsr0 = GET_HSR0 ();
+
+  /* If ! all_implemented, then registers 0-32 are available, otherwise check
+     availability of the hi/lo banks by checking the HSR0 register.  */
+  all_implemented = ! GET_HSR0_FRN (hsr0);
+  *hi_available = all_implemented && GET_HSR0_FRHE (hsr0);
+  *lo_available = (! all_implemented) || GET_HSR0_FRLE (hsr0);
+}
+
+void
+frv_gr_registers_available (
+  SIM_CPU *current_cpu, int *hi_available, int *lo_available
+)
+{
+  int all_implemented;
+  SI hsr0 = GET_HSR0 ();
+
+  /* If ! all_implemented, then registers 0-32 are available, otherwise check
+     availability of the hi/lo banks by checking the HSR0 register.  */
+  all_implemented = ! GET_HSR0_GRN (hsr0);
+  *hi_available = all_implemented && GET_HSR0_GRHE (hsr0);
+  *lo_available = (! all_implemented) || GET_HSR0_GRLE (hsr0);
+}
+
+/* Return 1 if the given register is available, 0 otherwise.  TARGET_INDEX==-1
+   means to check for any register available.  */
+int
+frv_check_register_access (
+  SIM_CPU *current_cpu,
+  SI target_index,
+  int hi_available,
+  int lo_available
+)
+{
+  SIM_DESC sd;
+  if (target_index > 31)
+    {
+      if (hi_available)
+	return 1;
+    }
+  else
+    {
+      if (lo_available)
+	return 1;
+
+      if (target_index == -1 && hi_available)
+	return 1;
+    }
+
+  /* The register is not available. Generate an exception.  */
+  sd = CPU_STATE (current_cpu);
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    {
+      /* On the fr400 this generates an illegal_instruction interrupt.  */
+      frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+    }
+  else
+    {
+      /* On other machines, it's a register_exception.  */
+      frv_queue_register_exception_interrupt (current_cpu,
+					      FRV_REC_UNIMPLEMENTED);
+    }
+  return 0;
+}
+
+/* Return 1 if the given register is available, 0 otherwise.  TARGET_INDEX==-1
+   means to check for any register available.  */
+int
+frv_check_gr_access (SIM_CPU *current_cpu, SI target_index)
+{
+  int hi_available;
+  int lo_available;
+
+  frv_gr_registers_available (current_cpu, & hi_available, & lo_available);
+  return frv_check_register_access (current_cpu, target_index,
+				    hi_available, lo_available);
+}
+
+/* Return 1 if the given register is available, 0 otherwise.  TARGET_INDEX==-1
+   means to check for any register available.  */
+int
+frv_check_fr_access (SIM_CPU *current_cpu, SI target_index)
+{
+  int hi_available;
+  int lo_available;
+
+  frv_fr_registers_available (current_cpu, & hi_available, & lo_available);
+  return frv_check_register_access (current_cpu, target_index,
+				    hi_available, lo_available);
+}
diff --git a/sim/frv/registers.h b/sim/frv/registers.h
new file mode 100644
index 00000000000..dba4d9659bc
--- /dev/null
+++ b/sim/frv/registers.h
@@ -0,0 +1,59 @@
+/* Register definitions for the FRV simulator
+   Copyright (C) 2000 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#define FRV_MAX_GR  64
+#define FRV_MAX_FR  64
+#define FRV_MAX_CPR 64
+#define FRV_MAX_SPR 4096
+
+/* Register init, reset values and read_only masks.  */
+typedef struct
+{
+  USI init_value;     /* initial value */
+  USI reset_value;    /* value for software reset */
+  USI reset_mask;     /* bits which are reset */
+  USI read_only_mask; /* bits which are read-only */
+  char implemented;   /* 1==register is implemented */
+  char supervisor;    /* 1==register is supervisor-only */
+} FRV_SPR_CONTROL_INFO;
+
+typedef struct
+{
+  int fr;                    /* FR registers implemented */
+  int cpr;                   /* coprocessor registers implemented */
+  FRV_SPR_CONTROL_INFO *spr; /* SPR implementation details */
+} FRV_REGISTER_CONTROL;
+
+void frv_register_control_init (SIM_CPU *);
+void frv_initialize_spr (SIM_CPU *);
+void frv_reset_spr (SIM_CPU *);
+
+void frv_check_spr_access (SIM_CPU *, UINT);
+
+void frv_fr_registers_available (SIM_CPU *, int *, int *);
+void frv_gr_registers_available (SIM_CPU *, int *, int *);
+int  frv_check_register_access (SIM_CPU *, SI, int, int);
+int  frv_check_gr_access (SIM_CPU *, SI);
+int  frv_check_fr_access (SIM_CPU *, SI);
+
+#endif /* REGISTERS_H */
diff --git a/sim/frv/reset.c b/sim/frv/reset.c
new file mode 100644
index 00000000000..51c29fe754e
--- /dev/null
+++ b/sim/frv/reset.c
@@ -0,0 +1,151 @@
+/* frv simulator support code
+   Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+/* Initialize the frv simulator.  */
+void
+frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd)
+{
+  FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+  PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);
+  FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu);
+  FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu);
+  int insn_cache_enabled = CACHE_INITIALIZED (insn_cache);
+  int data_cache_enabled = CACHE_INITIALIZED (data_cache);
+  USI hsr0;
+
+  /* We need to ensure that the caches are initialized even if they are not
+     initially enabled (via commandline) because they can be enabled by
+     software.  */
+  if (! insn_cache_enabled)
+    frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu));
+  if (! data_cache_enabled)
+    frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu));
+
+  /* Set the default cpu frequency if it has not been set on the command
+     line.  */
+  if (PROFILE_CPU_FREQ (p) == 0)
+    PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */
+
+  /* Allocate one cache line of memory containing the address of the reset
+     register Use the largest of the insn cache line size and the data cache
+     line size.  */
+  {
+    int addr = RSTR_ADDRESS;
+    void *aligned_buffer;
+    int bytes;
+
+    if (CPU_INSN_CACHE (current_cpu)->line_size
+	> CPU_DATA_CACHE (current_cpu)->line_size)
+      bytes = CPU_INSN_CACHE (current_cpu)->line_size;
+    else
+      bytes = CPU_DATA_CACHE (current_cpu)->line_size;
+
+    /* 'bytes' is a power of 2. Calculate the starting address of the
+       cache line.  */
+    addr &= ~(bytes - 1);
+    aligned_buffer = zalloc (bytes); /* clear */
+    sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes,
+		     0, NULL, aligned_buffer);
+  }
+
+  PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info;
+  ps->insn_fetch_address = -1;
+  ps->branch_address = -1;
+
+  cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu),
+			  frvbf_fpu_error);
+
+  /* Initialize the register control information.  */
+  frv_register_control_init (current_cpu);
+
+  /* Now perform power-on reset.  */
+  frv_power_on_reset (current_cpu);
+
+  /* Make sure that HSR0.ICE and HSR0.DCE are set properly.  */
+  hsr0 = GET_HSR0 ();
+  if (insn_cache_enabled)
+    SET_HSR0_ICE (hsr0);
+  else
+    CLEAR_HSR0_ICE (hsr0);
+  if (data_cache_enabled)
+    SET_HSR0_DCE (hsr0);
+  else
+    CLEAR_HSR0_DCE (hsr0);
+  SET_HSR0 (hsr0);
+}
+
+/* Initialize the frv simulator.  */
+void
+frv_term (SIM_DESC sd)
+{
+  /* If the timer is enabled, and model profiling was not originally enabled,
+     then turn it off again.  This is the only place we can currently gain
+     control to do this.  */
+  if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
+    sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0");
+}
+
+/* Perform a power on reset.  */
+void
+frv_power_on_reset (SIM_CPU *cpu)
+{
+  /* GR, FR and CPR registers are undefined at initialization time.  */
+  frv_initialize_spr (cpu);
+  /* Initialize the RSTR register (in memory).  */
+  if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
+    frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE);
+  else
+    SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE);
+}
+
+/* Perform a hardware reset.  */
+void
+frv_hardware_reset (SIM_CPU *cpu)
+{
+  /* GR, FR and CPR registers are undefined at hardware reset.  */
+  frv_initialize_spr (cpu);
+  /* Reset the RSTR register (in memory).  */
+  if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
+    frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET);
+  else
+    SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET);
+  /* Reset the insn and data caches.  */
+  frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */);
+  frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */);
+}
+
+/* Perform a software reset.  */
+void
+frv_software_reset (SIM_CPU *cpu)
+{
+  /* GR, FR and CPR registers are undefined at software reset.  */
+  frv_reset_spr (cpu);
+  /* Reset the RSTR register (in memory).  */
+  if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
+    frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET);
+  else
+    SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET);
+}
diff --git a/sim/frv/sem.c b/sim/frv/sem.c
new file mode 100644
index 00000000000..ea27277f99c
--- /dev/null
+++ b/sim/frv/sem.c
@@ -0,0 +1,28578 @@
+/* Simulator instruction semantics for frvbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+/* This is used so that we can compile two copies of the semantic code,
+   one with full feature support and one without that runs fast(er).
+   FAST_P, when desired, is defined on the command line, -DFAST_P=1.  */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+    /* Update the recorded pc in the cpu state struct.
+       Only necessary for WITH_SCACHE case, but to avoid the
+       conditional compilation ....  */
+    SET_H_PC (pc);
+    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
+       using the default-insn-bitsize spec.  When executing insns in parallel
+       we may want to queue the fault and continue execution.  */
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FRVBF
+    frvbf_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FRVBF
+    frvbf_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FRVBF
+#ifdef DEFINE_SWITCH
+    vpc = frvbf_pbb_cti_chain (current_cpu, sem_arg,
+			       pbb_br_type, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = frvbf_pbb_cti_chain (current_cpu, sem_arg,
+			       CPU_PBB_BR_TYPE (current_cpu),
+			       CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FRVBF
+    vpc = frvbf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_FRVBF
+#if defined DEFINE_SWITCH || defined FAST_P
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = frvbf_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
+    vpc = frvbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+    vpc = frvbf_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* add: add$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sub: sub$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* and: and$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* or: or$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* xor: xor$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* not: not$pack $GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sdiv: sdiv$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nsdiv: nsdiv$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nsdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 1);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* udiv: udiv$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,udiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nudiv: nudiv$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nudiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 1);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* smul: smul$pack $GRi,$GRj,$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,smul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* umul: umul$pack $GRi,$GRj,$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,umul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DI opval = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sll: sll$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* srl: srl$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sra: sra$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* scan: scan$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,scan) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp1;
+  SI tmp_tmp2;
+  tmp_tmp1 = GET_H_GR (FLD (f_GRi));
+  tmp_tmp2 = SRASI (GET_H_GR (FLD (f_GRj)), 1);
+  {
+    SI opval = frvbf_scan_result (current_cpu, XORSI (tmp_tmp1, tmp_tmp2));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cadd: cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csub: csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cand: cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cand) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cor: cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cxor: cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cxor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cnot: cnot$pack $GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = INVSI (GET_H_GR (FLD (f_GRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csmul: csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csmul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csdiv: csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0);
+; /*clobber*/
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cudiv: cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cudiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_GRk), 0);
+; /*clobber*/
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csll: csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = SLLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csrl: csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csrl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = SRLSI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csra: csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = SRASI (GET_H_GR (FLD (f_GRi)), ANDSI (GET_H_GR (FLD (f_GRj)), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cscan: cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cscan) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_tmp1;
+  SI tmp_tmp2;
+  tmp_tmp1 = GET_H_GR (FLD (f_GRi));
+  tmp_tmp2 = SRASI (GET_H_GR (FLD (f_GRj)), 1);
+  {
+    SI opval = frvbf_scan_result (current_cpu, XORSI (tmp_tmp1, tmp_tmp2));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* addcc: addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_tmp;
+  QI tmp_cc;
+  SI tmp_result;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+  tmp_tmp = ADDCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  tmp_result = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+if (EQSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_result;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* subcc: subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_tmp;
+  QI tmp_cc;
+  SI tmp_result;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+  tmp_tmp = SUBCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  tmp_result = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+if (EQSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_result;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* andcc: andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,andcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  tmp_tmp = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* orcc: orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,orcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  tmp_tmp = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* xorcc: xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,xorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  tmp_tmp = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* sllcc: sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sllcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31);
+  tmp_cc = frvbf_set_icc_for_shift_left (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)]));
+  tmp_tmp = SLLSI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* srlcc: srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,srlcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31);
+  tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)]));
+  tmp_tmp = SRLSI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* sracc: sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sracc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31);
+  tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)]));
+  tmp_tmp = SRASI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* smulcc: smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,smulcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  DI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))));
+if (EQDI (SRLDI (tmp_tmp, 63), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 7);
+} else {
+  tmp_cc = ORQI (tmp_cc, 8);
+}
+if (EQBI (EQDI (tmp_tmp, 0), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 11);
+} else {
+  tmp_cc = ORQI (tmp_cc, 4);
+}
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* umulcc: umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,umulcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  DI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (GET_H_GR (FLD (f_GRj))));
+if (EQDI (SRLDI (tmp_tmp, 63), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 7);
+} else {
+  tmp_cc = ORQI (tmp_cc, 8);
+}
+if (EQBI (EQDI (tmp_tmp, 0), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 11);
+} else {
+  tmp_cc = ORQI (tmp_cc, 4);
+}
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* caddcc: caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,caddcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  BI tmp_tmp;
+  QI tmp_cc;
+  SI tmp_result;
+  tmp_cc = CPU (h_iccr[((FLD (f_CCi)) & (3))]);
+  tmp_tmp = ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+  tmp_tmp = ADDCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  tmp_result = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+if (EQSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_result;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csubcc: csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csubcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  BI tmp_tmp;
+  QI tmp_cc;
+  SI tmp_result;
+  tmp_cc = CPU (h_iccr[((FLD (f_CCi)) & (3))]);
+  tmp_tmp = SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+  tmp_tmp = SUBCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  tmp_result = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+if (EQSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_result;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csmulcc: csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csmulcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  DI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[((FLD (f_CCi)) & (3))]);
+  tmp_tmp = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))));
+if (EQDI (SRLDI (tmp_tmp, 63), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 7);
+} else {
+  tmp_cc = ORQI (tmp_cc, 8);
+}
+if (EQBI (EQDI (tmp_tmp, 0), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 11);
+} else {
+  tmp_cc = ORQI (tmp_cc, 4);
+}
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* candcc: candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,candcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_tmp;
+  tmp_tmp = ANDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* corcc: corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,corcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_tmp;
+  tmp_tmp = ORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cxorcc: cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cxorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_tmp;
+  tmp_tmp = XORSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[((FLD (f_CCi)) & (3))]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csllcc: csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csllcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31);
+  tmp_cc = frvbf_set_icc_for_shift_left (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[((FLD (f_CCi)) & (3))]));
+  tmp_tmp = SLLSI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csrlcc: csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csrlcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31);
+  tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[((FLD (f_CCi)) & (3))]));
+  tmp_tmp = SRLSI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csracc: csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csracc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (GET_H_GR (FLD (f_GRj)), 31);
+  tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[((FLD (f_CCi)) & (3))]));
+  tmp_tmp = SRASI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[((FLD (f_CCi)) & (3))]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* addx: addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* subx: subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addxcc: addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = ADDCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1)));
+if (EQSI (ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+if (EQSI (ADDCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* subxcc: subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = SUBCSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1)));
+if (EQSI (SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+if (EQSI (SUBCFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* addi: addi$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* subi: subi$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* andi: andi$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ori: ori$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* xori: xori$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sdivi: sdivi$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sdivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 0);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nsdivi: nsdivi$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nsdivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_signed_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 1);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* udivi: udivi$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,udivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 0);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nudivi: nudivi$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nudivi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_unsigned_integer_divide (current_cpu, GET_H_GR (FLD (f_GRi)), FLD (f_d12), FLD (f_GRk), 1);
+; /*clobber*/
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* smuli: smuli$pack $GRi,$s12,$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,smuli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (FLD (f_d12)));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* umuli: umuli$pack $GRi,$s12,$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,umuli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DI opval = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (FLD (f_d12)));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* slli: slli$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (GET_H_GR (FLD (f_GRi)), ANDSI (FLD (f_d12), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* srli: srli$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (GET_H_GR (FLD (f_GRi)), ANDSI (FLD (f_d12), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* srai: srai$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (GET_H_GR (FLD (f_GRi)), ANDSI (FLD (f_d12), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* scani: scani$pack $GRi,$s12,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,scani) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp1;
+  SI tmp_tmp2;
+  tmp_tmp1 = GET_H_GR (FLD (f_GRi));
+  tmp_tmp2 = SRASI (FLD (f_d12), 1);
+  {
+    SI opval = frvbf_scan_result (current_cpu, XORSI (tmp_tmp1, tmp_tmp2));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* addicc: addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_tmp;
+  QI tmp_cc;
+  SI tmp_result;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = ADDOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+  tmp_tmp = ADDCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  tmp_result = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10));
+if (EQSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_result;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* subicc: subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_tmp;
+  QI tmp_cc;
+  SI tmp_result;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = SUBOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+  tmp_tmp = SUBCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), 0);
+if (EQBI (tmp_tmp, 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  tmp_result = SUBSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10));
+if (EQSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_result, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_result;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* andicc: andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,andicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  tmp_tmp = ANDSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* oricc: oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,oricc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  tmp_tmp = ORSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* xoricc: xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,xoricc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  tmp_tmp = XORSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10));
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 7), 4);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  {
+    UQI opval = ORQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 11), 8);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 3);
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* smulicc: smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,smulicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  DI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (FLD (f_s10)));
+if (EQDI (SRLDI (tmp_tmp, 63), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 7);
+} else {
+  tmp_cc = ORQI (tmp_cc, 8);
+}
+if (EQBI (EQDI (tmp_tmp, 0), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 11);
+} else {
+  tmp_cc = ORQI (tmp_cc, 4);
+}
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* umulicc: umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,umulicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  DI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = MULDI (ZEXTSIDI (GET_H_GR (FLD (f_GRi))), ZEXTSIDI (FLD (f_s10)));
+if (EQDI (SRLDI (tmp_tmp, 63), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 7);
+} else {
+  tmp_cc = ORQI (tmp_cc, 8);
+}
+if (EQBI (EQDI (tmp_tmp, 0), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 11);
+} else {
+  tmp_cc = ORQI (tmp_cc, 4);
+}
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* sllicc: sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sllicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (FLD (f_s10), 31);
+  tmp_cc = frvbf_set_icc_for_shift_left (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)]));
+  tmp_tmp = SLLSI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* srlicc: srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,srlicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (FLD (f_s10), 31);
+  tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)]));
+  tmp_tmp = SRLSI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* sraicc: sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sraicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_shift;
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_shift = ANDSI (FLD (f_s10), 31);
+  tmp_cc = frvbf_set_icc_for_shift_right (current_cpu, GET_H_GR (FLD (f_GRi)), tmp_shift, CPU (h_iccr[FLD (f_ICCi_1)]));
+  tmp_tmp = SRASI (GET_H_GR (FLD (f_GRi)), tmp_shift);
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* addxi: addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addxi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* subxi: subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subxi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SUBCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_1)]), 1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* addxicc: addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addxicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = ADDCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1)));
+if (EQSI (ADDOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+if (EQSI (ADDCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* subxicc: subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subxicc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  QI tmp_cc;
+  tmp_cc = CPU (h_iccr[FLD (f_ICCi_1)]);
+  tmp_tmp = SUBCSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1)));
+if (EQSI (SUBOFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+if (EQSI (SUBCFSI (GET_H_GR (FLD (f_GRi)), FLD (f_s10), TRUNCQIBI (ANDQI (tmp_cc, 1))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+if (EQSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 7), 4);
+} else {
+if (LTSI (tmp_tmp, 0)) {
+  tmp_cc = ORQI (ANDQI (tmp_cc, 11), 8);
+} else {
+  tmp_cc = ANDQI (tmp_cc, 3);
+}
+}
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpb: cmpb$pack $GRi,$GRj,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmpb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  QI tmp_cc;
+if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 0xff000000), ANDSI (GET_H_GR (FLD (f_GRj)), 0xff000000)), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 7);
+} else {
+  tmp_cc = ORQI (tmp_cc, 8);
+}
+if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 16711680), ANDSI (GET_H_GR (FLD (f_GRj)), 16711680)), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 11);
+} else {
+  tmp_cc = ORQI (tmp_cc, 4);
+}
+if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 65280), ANDSI (GET_H_GR (FLD (f_GRj)), 65280)), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 13);
+} else {
+  tmp_cc = ORQI (tmp_cc, 2);
+}
+if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 255), ANDSI (GET_H_GR (FLD (f_GRj)), 255)), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cmpba: cmpba$pack $GRi,$GRj,$ICCi_1 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmpba) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  QI tmp_cc;
+  tmp_cc = 0;
+if (EQBI (ORIF (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 0xff000000), ANDSI (GET_H_GR (FLD (f_GRj)), 0xff000000)), ORIF (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 16711680), ANDSI (GET_H_GR (FLD (f_GRj)), 16711680)), ORIF (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 65280), ANDSI (GET_H_GR (FLD (f_GRj)), 65280)), EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 255), ANDSI (GET_H_GR (FLD (f_GRj)), 255))))), 0)) {
+  tmp_cc = ANDQI (tmp_cc, 14);
+} else {
+  tmp_cc = ORQI (tmp_cc, 1);
+}
+  {
+    UQI opval = tmp_cc;
+    sim_queue_qi_write (current_cpu, & CPU (h_iccr[FLD (f_ICCi_1)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "iccr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* setlo: setlo$pack $ulo16,$GRklo */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,setlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UHI opval = FLD (f_u16);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_gr_lo_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_lo", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* sethi: sethi$pack $uhi16,$GRkhi */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sethi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UHI opval = FLD (f_u16);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_gr_hi_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr_hi", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* setlos: setlos$pack $slo16,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,setlos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_s16);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldsb: ldsb$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldub: ldub$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldsh: ldsh$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lduh: lduh$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ld: ld$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldbf: ldbf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldhf: ldhf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldhf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldf: ldf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldc: ldc$pack @($GRi,$GRj),$CPRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_si_write (current_cpu, & CPU (h_cpr[FLD (f_CPRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cpr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nldsb: nldsb$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 1, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldub: nldub$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 0, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldsh: nldsh$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 3, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nlduh: nlduh$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 2, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nld: nld$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 4, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldbf: nldbf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 0, 1);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldhf: nldhf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldhf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 2, 1);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldf: nldf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 4, 1);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldd: ldd$pack @($GRi,$GRj),$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lddf: lddf$pack @($GRi,$GRj),$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lddf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* lddc: lddc$pack @($GRi,$GRj),$CPRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lddc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_cpr_double_set, FLD (f_CPRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "cpr_double", 'D', opval);
+  }
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nldd: nldd$pack @($GRi,$GRj),$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 5, 0);
+if (tmp_do_op) {
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nlddf: nlddf$pack @($GRi,$GRj),$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlddf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 5, 1);
+if (tmp_do_op) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldq: ldq$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldqf: ldqf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldqc: ldqc$pack @($GRi,$GRj),$CPRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldqc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nldq: nldq$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 6, 0);
+if (tmp_do_op) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nldqf: nldqf$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 6, 1);
+if (tmp_do_op) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldsbu: ldsbu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldsbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldubu: ldubu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldubu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldshu: ldshu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldshu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lduhu: lduhu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lduhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldu: ldu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldsbu: nldsbu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldsbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 1, 0);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldubu: nldubu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldubu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 0, 0);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldshu: nldshu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldshu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 3, 0);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nlduhu: nlduhu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlduhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 2, 0);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldu: nldu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 4, 0);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldbfu: ldbfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldhfu: ldhfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldhfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldfu: ldfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldcu: ldcu$pack @($GRi,$GRj),$CPRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address);
+    sim_queue_si_write (current_cpu, & CPU (h_cpr[FLD (f_CPRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cpr", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nldbfu: nldbfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 0, 1);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldhfu: nldhfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldhfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 2, 1);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldfu: nldfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 4, 1);
+if (tmp_do_op) {
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lddu: lddu$pack @($GRi,$GRj),$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nlddu: nlddu$pack @($GRi,$GRj),$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 5, 0);
+if (tmp_do_op) {
+{
+  SI tmp_address;
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lddfu: lddfu$pack @($GRi,$GRj),$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lddfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* lddcu: lddcu$pack @($GRi,$GRj),$CPRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lddcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_cpr_double_set, FLD (f_CPRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "cpr_double", 'D', opval);
+  }
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nlddfu: nlddfu$pack @($GRi,$GRj),$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlddfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 5, 1);
+if (tmp_do_op) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldqu: ldqu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldqu: nldqu$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_GRk), 0, 6, 0);
+if (tmp_do_op) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+{
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldqfu: ldqfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldqfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldqcu: ldqcu$pack @($GRi,$GRj),$CPRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldqcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nldqfu: nldqfu$pack @($GRi,$GRj),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldqfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), FLD (f_GRj), FLD (f_FRk), 0, 6, 1);
+if (tmp_do_op) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_force_update (current_cpu);
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldsbi: ldsbi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldsbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldshi: ldshi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldshi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldi: ldi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldubi: ldubi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldubi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* lduhi: lduhi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lduhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldbfi: ldbfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldbfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldhfi: ldhfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldhfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ldfi: ldfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nldsbi: nldsbi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldsbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 1, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldubi: nldubi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldubi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 0, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldshi: nldshi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldshi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 3, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nlduhi: nlduhi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlduhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 2, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldi: nldi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 4, 0);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldbfi: nldbfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldbfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 0, 1);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldhfi: nldhfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldhfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 2, 1);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nldfi: nldfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 4, 1);
+if (tmp_do_op) {
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lddi: lddi$pack @($GRi,$d12),$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lddi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* lddfi: lddfi$pack @($GRi,$d12),$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lddfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nlddi: nlddi$pack @($GRi,$d12),$GRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlddi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 5, 0);
+if (tmp_do_op) {
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nlddfi: nlddfi$pack @($GRi,$d12),$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nlddfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 5, 1);
+if (tmp_do_op) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ldqi: ldqi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* ldqfi: ldqfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ldqfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nldqi: nldqi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 6, 0);
+if (tmp_do_op) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nldqfi: nldqfi$pack @($GRi,$d12),$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nldqfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  BI tmp_do_op;
+  tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_FRk), FLD (f_d12), 6, 1);
+if (tmp_do_op) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stb: stb$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* sth: sth$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* st: st$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* stbf: stbf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* sthf: sthf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* stf: stf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* stc: stc$pack $CPRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), CPU (h_cpr[FLD (f_CPRk)]));
+
+  return vpc;
+#undef FLD
+}
+
+/* rstb: rstb$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 1, 0);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rsth: rsth$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 2, 0);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rst: rst$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 4, 0);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rstbf: rstbf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 1, 1);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rsthf: rsthf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rsthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 2, 1);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rstf: rstf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 4, 1);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* std: std$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,std) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stdf: stdf$pack $FRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stdc: stdc$pack $CPRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stdc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk)));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rstd: rstd$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
+}
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 8, 0);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rstdf: rstdf$pack $FRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
+}
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 8, 1);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stq: stq$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stqf: stqf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stqc: stqc$pack $CPRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stqc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rstq: rstq$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 16, 0);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rstqf: rstqf$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rstqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 16, 1);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stbu: stbu$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* sthu: sthu$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sthu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stu: stu$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_WI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stbfu: stbfu$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* sthfu: sthfu$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sthfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stfu: stfu$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stcu: stcu$pack $CPRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  USI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_SI (current_cpu, pc, tmp_address, CPU (h_cpr[FLD (f_CPRk)]));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stdu: stdu$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stdu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stdfu: stdfu$pack $FRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stdfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stdcu: stdcu$pack $CPRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stdcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk)));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stqu: stqu$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stqfu: stqfu$pack $FRintk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stqfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stqcu: stqcu$pack $CPRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stqcu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cldsb: cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldub: cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldsh: cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* clduh: clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cld: cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldbf: cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldhf: cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldhf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldf: cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldd: cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* clddf: clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clddf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldq: cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cldsbu: cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldsbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_QI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldubu: cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldubu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldshu: cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldshu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_HI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* clduhu: clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clduhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldu: cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldbfu: cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UQI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldhfu: cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldhfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_UHI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldfu: cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_SI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* clddu: clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+if (NESI (FLD (f_GRk), 0)) {
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DI opval = frvbf_read_mem_DI (current_cpu, pc, tmp_address);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_gr_double_set, FLD (f_GRk), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr_double", 'D', opval);
+  }
+}
+}
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* clddfu: clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clddfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    DF opval = frvbf_read_mem_DF (current_cpu, pc, tmp_address);
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cldqu: cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cldqu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+if (NESI (FLD (f_GRi), FLD (f_GRk))) {
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cstb: cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk)));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* csth: csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk)));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cst: cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_GR (FLD (f_GRk)));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cstbf: cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk)));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* csthf: csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk)));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cstf: cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), GET_H_FR_INT (FLD (f_FRk)));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cstd: cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cstdf: cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cstq: cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cstbu: cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csthu: csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csthu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cstu: cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cstbfu: cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstbfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* csthfu: csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,csthfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cstfu: cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cstdu: cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstdu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cstdfu: cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cstdfu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
+}
+  {
+    SI opval = tmp_address;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* stbi: stbi$pack $GRk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_GR (FLD (f_GRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* sthi: sthi$pack $GRk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sthi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_GR (FLD (f_GRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* sti: sti$pack $GRk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sti) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_GR (FLD (f_GRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* stbfi: stbfi$pack $FRintk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stbfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_QI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_FR_INT (FLD (f_FRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* sthfi: sthfi$pack $FRintk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,sthfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_HI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_FR_INT (FLD (f_FRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* stfi: stfi$pack $FRintk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), GET_H_FR_INT (FLD (f_FRk)));
+
+  return vpc;
+#undef FLD
+}
+
+/* stdi: stdi$pack $GRk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stdi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stdfi: stdfi$pack $FRk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stdfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stqi: stqi$pack $GRk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* stqfi: stqfi$pack $FRintk,@($GRi,$d12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,stqfi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_address;
+{
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* swap: swap$pack @($GRi,$GRj),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,swap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  SI tmp_address;
+  tmp_tmp = GET_H_GR (FLD (f_GRk));
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_write_mem_WI (current_cpu, pc, tmp_address, tmp_tmp);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* swapi: swapi$pack @($GRi,$d12),$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,swapi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  SI tmp_address;
+  tmp_tmp = GET_H_GR (FLD (f_GRk));
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+  {
+    SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_write_mem_WI (current_cpu, pc, tmp_address, tmp_tmp);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cswap: cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cswap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  SI tmp_tmp;
+  SI tmp_address;
+  tmp_tmp = GET_H_GR (FLD (f_GRk));
+  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+  {
+    SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address);
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+frvbf_write_mem_WI (current_cpu, pc, tmp_address, tmp_tmp);
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* movgf: movgf$pack $GRj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movgf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GET_H_GR (FLD (f_GRj));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* movfg: movfg$pack $FRintk,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GET_H_FR_INT (FLD (f_FRk));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* movgfd: movgfd$pack $GRj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movgfd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_GRj), 0)) {
+{
+  {
+    SI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+} else {
+{
+  {
+    SI opval = GET_H_GR (FLD (f_GRj));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = GET_H_GR (((FLD (f_GRj)) + (1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* movfgd: movfgd$pack $FRintk,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movfgd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (FLD (f_GRj), 0)) {
+{
+  {
+    SI opval = GET_H_FR_INT (FLD (f_FRk));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (1)), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* movgfq: movgfq$pack $GRj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movgfq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_GRj), 0)) {
+{
+  {
+    SI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (3)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+} else {
+{
+  {
+    SI opval = GET_H_GR (FLD (f_GRj));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = GET_H_GR (((FLD (f_GRj)) + (1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = GET_H_GR (((FLD (f_GRj)) + (2)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = GET_H_GR (((FLD (f_GRj)) + (3)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (3)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* movfgq: movfgq$pack $FRintk,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movfgq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (FLD (f_GRj), 0)) {
+{
+  {
+    SI opval = GET_H_FR_INT (FLD (f_FRk));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (2)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (2)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (3)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (3)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmovgf: cmovgf$pack $GRj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmovgf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = GET_H_GR (FLD (f_GRj));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmovfg: cmovfg$pack $FRintk,$GRj,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmovfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = GET_H_FR_INT (FLD (f_FRk));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmovgfd: cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmovgfd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (EQSI (FLD (f_GRj), 0)) {
+{
+  {
+    SI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = 0;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+} else {
+{
+  {
+    SI opval = GET_H_GR (FLD (f_GRj));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = GET_H_GR (((FLD (f_GRj)) + (1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmovfgd: cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmovfgd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDIF (NESI (FLD (f_GRj), 0), EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2)))) {
+{
+  {
+    SI opval = GET_H_FR_INT (FLD (f_FRk));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = GET_H_FR_INT (((FLD (f_FRk)) + (1)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, ((FLD (f_GRj)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* movgs: movgs$pack $GRj,$spr */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movgs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = GET_H_GR (FLD (f_GRj));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, FLD (f_spr), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* movsg: movsg$pack $spr,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,movsg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GET_H_SPR (FLD (f_spr));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* bra: bra$pack $hint_taken$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* bno: bno$pack$hint_not_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+
+  return vpc;
+#undef FLD
+}
+
+/* beq: beq$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bne: bne$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ble: ble$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bgt: bgt$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* blt: blt$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,blt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bge: bge$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bls: bls$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bhi: bhi$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bc: bc$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bnc: bnc$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bn: bn$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bp: bp$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bv: bv$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bnv: bnv$pack $ICCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bnv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbra: fbra$pack $hint_taken$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fbno: fbno$pack$hint_not_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+
+  return vpc;
+#undef FLD
+}
+
+/* fbne: fbne$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbeq: fbeq$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fblg: fblg$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fblg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbue: fbue$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbue) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbul: fbul$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbge: fbge$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fblt: fblt$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fblt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbuge: fbuge$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbug: fbug$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbug) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fble: fble$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbgt: fbgt$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbule: fbule$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbule) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbu: fbu$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbo: fbo$pack $FCCi_2,$hint,$label16 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, FLD (i_label16), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) {
+  {
+    USI opval = FLD (i_label16);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bctrlr: bctrlr$pack $ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bctrlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bralr: bralr$pack$hint_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* bnolr: bnolr$pack$hint_not_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+
+  return vpc;
+#undef FLD
+}
+
+/* beqlr: beqlr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,beqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bnelr: bnelr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* blelr: blelr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,blelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bgtlr: bgtlr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bltlr: bltlr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bgelr: bgelr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* blslr: blslr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,blslr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bhilr: bhilr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bhilr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bclr: bclr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bnclr: bnclr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bnclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bnlr: bnlr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bnlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bplr: bplr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bplr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bvlr: bvlr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bnvlr: bnvlr$pack $ICCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bnvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbralr: fbralr$pack$hint_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fbnolr: fbnolr$pack$hint_not_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+
+  return vpc;
+#undef FLD
+}
+
+/* fbeqlr: fbeqlr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbeqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbnelr: fbnelr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fblglr: fblglr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fblglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbuelr: fbuelr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbuelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbullr: fbullr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbullr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbgelr: fbgelr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbltlr: fbltlr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbugelr: fbugelr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbugelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbuglr: fbuglr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbuglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fblelr: fblelr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fblelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbgtlr: fbgtlr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbulelr: fbulelr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbulelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbulr: fbulr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbulr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fbolr: fbolr$pack $FCCi_2,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fbolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcralr: bcralr$pack $ccond$hint_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcnolr: bcnolr$pack$hint_not_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+((void) 0); /*nop*/
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* bceqlr: bceqlr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bceqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcnelr: bcnelr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bclelr: bclelr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bclelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcgtlr: bcgtlr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcltlr: bcltlr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcgelr: bcgelr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bclslr: bclslr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bclslr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bchilr: bchilr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bchilr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcclr: bcclr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcnclr: bcnclr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcnclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcnlr: bcnlr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcnlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcplr: bcplr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcplr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcvlr: bcvlr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* bcnvlr: bcnvlr$pack $ICCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bcnvlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbralr: fcbralr$pack $ccond$hint_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbralr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbnolr: fcbnolr$pack$hint_not_taken */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbnolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+((void) 0); /*nop*/
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fcbeqlr: fcbeqlr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbeqlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbnelr: fcbnelr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbnelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcblglr: fcblglr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcblglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbuelr: fcbuelr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbuelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbullr: fcbullr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbullr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbgelr: fcbgelr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbgelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbltlr: fcbltlr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbltlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbugelr: fcbugelr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbugelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbuglr: fcbuglr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbuglr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcblelr: fcblelr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcblelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbgtlr: fcbgtlr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbgtlr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbulelr: fcbulelr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbulelr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbulr: fcbulr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbulr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcbolr: fcbolr$pack $FCCi_2,$ccond,$hint */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcbolr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_model_branch (current_cpu, GET_H_SPR (((UINT) 272)), FLD (f_hint));
+{
+  SI tmp_tmp;
+  tmp_tmp = SUBSI (GET_H_SPR (((UINT) 273)), 1);
+  {
+    USI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, ((UINT) 273), opval);
+    TRACE_RESULT (current_cpu, abuf, "spr", 'x', opval);
+  }
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) {
+if (EQSI (FLD (f_ccond), 0)) {
+if (NESI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+} else {
+if (EQSI (tmp_tmp, 0)) {
+  {
+    USI opval = GET_H_SPR (((UINT) 272));
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* jmpl: jmpl$pack @($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,jmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (EQSI (FLD (f_LI), 1)) {
+frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1);
+}
+  {
+    USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc);
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* calll: calll$pack @($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,calll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (EQSI (FLD (f_LI), 1)) {
+frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1);
+}
+  {
+    USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc);
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* jmpil: jmpil$pack @($GRi,$s12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,jmpil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (EQSI (FLD (f_LI), 1)) {
+frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1);
+}
+  {
+    USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), 0xfffffffc);
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* callil: callil$pack @($GRi,$s12) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,callil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (EQSI (FLD (f_LI), 1)) {
+frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1);
+}
+  {
+    USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)), 0xfffffffc);
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* call: call$pack $label24 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1);
+  {
+    USI opval = FLD (i_label24);
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rett: rett$pack $debug */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rett) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    USI opval = frv_rett (current_cpu, pc, FLD (f_debug));
+    sim_queue_pc_write (current_cpu, opval);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* rei: rei$pack $eir */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,rei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* tra: tra$pack $GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tno: tno$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* teq: teq$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,teq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tne: tne$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tle: tle$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tgt: tgt$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tlt: tlt$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tlt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tge: tge$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tls: tls$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* thi: thi$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,thi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tc: tc$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tnc: tnc$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tn: tn$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tn) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tp: tp$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tv: tv$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tnv: tnv$pack $ICCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tnv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftra: ftra$pack $GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftno: ftno$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* ftne: ftne$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fteq: fteq$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fteq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftlg: ftlg$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftlg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftue: ftue$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftue) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftul: ftul$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftge: ftge$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftlt: ftlt$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftlt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftuge: ftuge$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftug: ftug$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftug) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftle: ftle$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftgt: ftgt$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftule: ftule$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftule) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftu: ftu$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fto: fto$pack $FCCi_2,$GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fto) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tira: tira$pack $GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tira) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tino: tino$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tino) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* tieq: tieq$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tieq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tine: tine$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tine) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tile: tile$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tigt: tigt$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tigt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tilt: tilt$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tilt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tige: tige$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tige) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tils: tils$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tils) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tihi: tihi$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tihi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 4), 2))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tic: tic$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tic) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tinc: tinc$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tinc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tin: tin$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tip: tip$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tip) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 8), 3)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tiv: tiv$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* tinv: tinv$pack $ICCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tinv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftira: ftira$pack $GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftira) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftino: ftino$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftino) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* ftine: ftine$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftine) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftieq: ftieq$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftieq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftilg: ftilg$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftilg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftiue: ftiue$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftiue) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftiul: ftiul$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftiul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftige: ftige$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftige) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftilt: ftilt$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftilt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftiuge: ftiuge$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftiuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftiug: ftiug$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftiug) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftile: ftile$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftigt: ftigt$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftigt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftiule: ftiule$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftiule) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftiu: ftiu$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 1))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ftio: ftio$pack $FCCi_2,$GRi,$s12 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ftio) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_2)]), 2), 1))))) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+if (NEBI (CPU (h_psr_esr), 0)) {
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+}
+}
+frv_itrap (current_cpu, pc, GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* break: break$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,break) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+; /*clobber*/
+frv_break (current_cpu);
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mtrap: mtrap$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mtrap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frv_mtrap (current_cpu);
+
+  return vpc;
+#undef FLD
+}
+
+/* andcr: andcr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,andcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 0, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* orcr: orcr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,orcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 1, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* xorcr: xorcr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,xorcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 2, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nandcr: nandcr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nandcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 3, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* norcr: norcr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,norcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 4, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* andncr: andncr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,andncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 5, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* orncr: orncr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,orncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 6, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* nandncr: nandncr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nandncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 7, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* norncr: norncr$pack $CRi,$CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,norncr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = frvbf_cr_logic (current_cpu, 8, CPU (h_cccr[FLD (f_CRi)]), CPU (h_cccr[FLD (f_CRj)]));
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* notcr: notcr$pack $CRj,$CRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,notcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = XORQI (CPU (h_cccr[FLD (f_CRj)]), 1);
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRk)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ckra: ckra$pack $CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ckno: ckno$pack $CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* ckeq: ckeq$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckne: ckne$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckle: ckle$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckgt: ckgt$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cklt: cklt$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckge: ckge$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckls: ckls$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckhi: ckhi$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckc: ckc$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cknc: cknc$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cknc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckn: ckn$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckn) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckp: ckp$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ckv: ckv$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ckv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cknv: cknv$pack $ICCi_3,$CRj_int */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cknv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckra: fckra$pack $CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fckno: fckno$pack $CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fckne: fckne$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckeq: fckeq$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcklg: fcklg$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcklg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckue: fckue$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckue) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckul: fckul$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckge: fckge$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcklt: fcklt$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckuge: fckuge$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckug: fckug$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckug) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckle: fckle$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckgt: fckgt$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fckule: fckule$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fckule) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcku: fcku$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcku) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcko: fcko$pack $FCCi_3,$CRj_float */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcko) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 1);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckra: cckra$pack $CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckno: cckno$pack $CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckeq: cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckne: cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckle: cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckgt: cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (NOTBI (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)), XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ccklt: ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ccklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckge: cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (NOTBI (XORBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckls: cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckhi: cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (NOTBI (ORIF (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 4), 2))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckc: cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ccknc: ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ccknc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (NOTBI (TRUNCQIBI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckn: cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckn) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckp: cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 8), 3)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cckv: cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cckv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ccknv: ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ccknv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (NOTBI (TRUNCQIBI (SRLQI (ANDQI (CPU (h_iccr[FLD (f_ICCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_int)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckra: cfckra$pack $CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckno: cfckno$pack $CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckno) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckne: cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckeq: cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfcklg: cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfcklg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckue: cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckue) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckul: cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckge: cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfcklt: cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfcklt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckuge: cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckuge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckug: cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckug) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckle: cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckgt: cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfckule: cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfckule) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfcku: cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfcku) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (TRUNCQIBI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 1))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfcko: cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfcko) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 8), 3)), ORIF (TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 4), 2)), TRUNCQIBI (SRLQI (ANDQI (CPU (h_fccr[FLD (f_FCCi_3)]), 2), 1))))) {
+  {
+    UQI opval = 3;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+} else {
+  {
+    UQI opval = 0;
+    sim_queue_qi_write (current_cpu, & CPU (h_cccr[FLD (f_CRj_float)]), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "cccr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cjmpl: cjmpl$pack @($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cjmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+if (EQSI (FLD (f_LI), 1)) {
+frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1);
+}
+  {
+    USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ccalll: ccalll$pack @($GRi,$GRj),$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ccalll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+if (EQSI (FLD (f_LI), 1)) {
+frvbf_set_write_next_vliw_addr_to_LR (current_cpu, 1);
+}
+  {
+    USI opval = ANDSI (ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0xfffffffc);
+    sim_queue_pc_write (current_cpu, opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+frvbf_model_branch (current_cpu, pc, 2);
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* ici: ici$pack @($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,ici) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_insn_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dci: dci$pack @($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,dci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_data_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0);
+
+  return vpc;
+#undef FLD
+}
+
+/* icei: icei$pack @($GRi,$GRj),$ae */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,icei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_ae), 0)) {
+frvbf_insn_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), -1);
+} else {
+frvbf_insn_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), FLD (f_ae));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* dcei: dcei$pack @($GRi,$GRj),$ae */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,dcei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_ae), 0)) {
+frvbf_data_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), -1);
+} else {
+frvbf_data_cache_invalidate (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), FLD (f_ae));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* dcf: dcf$pack @($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,dcf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_data_cache_flush (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), 0);
+
+  return vpc;
+#undef FLD
+}
+
+/* dcef: dcef$pack @($GRi,$GRj),$ae */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,dcef) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (FLD (f_ae), 0)) {
+frvbf_data_cache_flush (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), -1);
+} else {
+frvbf_data_cache_flush (current_cpu, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))), FLD (f_ae));
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* witlb: witlb$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,witlb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* wdtlb: wdtlb$pack $GRk,@($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,wdtlb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* itlbi: itlbi$pack @($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,itlbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* dtlbi: dtlbi$pack @($GRi,$GRj) */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,dtlbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* icpl: icpl$pack $GRi,$GRj,$lock */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,icpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_insn_cache_preload (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_lock));
+
+  return vpc;
+#undef FLD
+}
+
+/* dcpl: dcpl$pack $GRi,$GRj,$lock */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,dcpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_data_cache_preload (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), FLD (f_lock));
+
+  return vpc;
+#undef FLD
+}
+
+/* icul: icul$pack $GRi */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,icul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_insn_cache_unlock (current_cpu, GET_H_GR (FLD (f_GRi)));
+
+  return vpc;
+#undef FLD
+}
+
+/* dcul: dcul$pack $GRi */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,dcul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_data_cache_unlock (current_cpu, GET_H_GR (FLD (f_GRi)));
+
+  return vpc;
+#undef FLD
+}
+
+/* bar: bar$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,bar) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* membar: membar$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,membar) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* cop1: cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cop1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* cop2: cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cop2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* clrgr: clrgr$pack $GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clrgr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_clear_ne_flags (current_cpu, FLD (f_GRk), 0);
+
+  return vpc;
+#undef FLD
+}
+
+/* clrfr: clrfr$pack $FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clrfr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_clear_ne_flags (current_cpu, FLD (f_FRk), 1);
+
+  return vpc;
+#undef FLD
+}
+
+/* clrga: clrga$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clrga) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_clear_ne_flags (current_cpu, -1, 0);
+
+  return vpc;
+#undef FLD
+}
+
+/* clrfa: clrfa$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,clrfa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_clear_ne_flags (current_cpu, -1, 1);
+
+  return vpc;
+#undef FLD
+}
+
+/* commitgr: commitgr$pack $GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,commitgr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_commit (current_cpu, FLD (f_GRk), 0);
+
+  return vpc;
+#undef FLD
+}
+
+/* commitfr: commitfr$pack $FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,commitfr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_commit (current_cpu, FLD (f_FRk), 1);
+
+  return vpc;
+#undef FLD
+}
+
+/* commitga: commitga$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,commitga) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_commit (current_cpu, -1, 0);
+
+  return vpc;
+#undef FLD
+}
+
+/* commitfa: commitfa$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,commitfa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_commit (current_cpu, -1, 1);
+
+  return vpc;
+#undef FLD
+}
+
+/* fitos: fitos$pack $FRintj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fstoi: fstoi$pack $FRj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fitod: fitod$pack $FRintj,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fitod) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsidf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdtoi: fdtoi$pack $FRdoublej,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdtoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixdfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fditos: fditos$pack $FRintj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fditos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdstoi: fdstoi$pack $FRj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfditos: nfditos$pack $FRintj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfditos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdstoi: nfdstoi$pack $FRj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    USI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cfitos: cfitos$pack $FRintj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfstoi: cfstoi$pack $FRj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nfitos: nfitos$pack $FRintj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfstoi: nfstoi$pack $FRj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fmovs: fmovs$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = GET_H_FR (FLD (f_FRj));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fmovd: fmovd$pack $FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmovd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = GET_H_FR_DOUBLE (FLD (f_FRj));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdmovs: fdmovs$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = GET_H_FR (FLD (f_FRj));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = GET_H_FR (((FLD (f_FRj)) + (1)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cfmovs: cfmovs$pack $FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = GET_H_FR (FLD (f_FRj));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fnegs: fnegs$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fnegd: fnegd$pack $FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fnegd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdnegs: fdnegs$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cfnegs: cfnegs$pack $FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fabss: fabss$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fabsd: fabsd$pack $FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fabsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->absdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdabss: fdabss$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cfabss: cfabss$pack $FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fsqrts: fsqrts$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdsqrts: fdsqrts$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdsqrts: nfdsqrts$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fsqrtd: fsqrtd$pack $FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fsqrtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cfsqrts: cfsqrts$pack $FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nfsqrts: nfsqrts$pack $FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fadds: fadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fsubs: fsubs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fmuls: fmuls$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdivs: fdivs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* faddd: faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,faddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fsubd: fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fmuld: fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmuld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdivd: fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdivd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cfadds: cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfsubs: cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfmuls: cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfdivs: cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nfadds: nfadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfsubs: nfsubs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfmuls: nfmuls$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdivs: nfdivs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fcmps: fcmps$pack $FRi,$FRj,$FCCi_2 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fcmpd: fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fcmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if ((* CGEN_CPU_FPU (current_cpu)->ops->gtdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->eqdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->ltdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfcmps: cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fdcmps: fdcmps$pack $FRi,$FRj,$FCCi_2 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fmadds: fmadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fmsubs: fmsubs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fmaddd: fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmaddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fmsubd: fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk)));
+    sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* fdmadds: fdmadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdmadds: nfdmadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cfmadds: cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfmsubs: cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* nfmadds: nfmadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfmsubs: nfmsubs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fmas: fmas$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fmss: fmss$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdmas: fdmas$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdmss: fdmss$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdmas: nfdmas$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 2));
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 3));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdmss: nfdmss$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 2));
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 3));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cfmas: cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cfmss: cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cfmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* fmad: fmad$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmad) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fmsd: fmsd$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fmsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfmas: nfmas$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfmss: nfmss$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdadds: fdadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdsubs: fdsubs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdmuls: fdmuls$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fddivs: fddivs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fddivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdsads: fdsads$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdsads) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* fdmulcs: fdmulcs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fdmulcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdmulcs: nfdmulcs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdmulcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdadds: nfdadds$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdsubs: nfdsubs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdmuls: nfdmuls$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfddivs: nfddivs$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfddivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdsads: nfdsads$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdsads) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+  {
+    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* nfdcmps: nfdcmps$pack $FRi,$FRj,$FCCi_2 */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,nfdcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+frvbf_set_ne_index (current_cpu, FLD (f_FRk));
+if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
+if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mhsetlos: mhsetlos$pack $u12,$FRklo */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mhsetlos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UHI opval = FLD (f_u12);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mhsethis: mhsethis$pack $u12,$FRkhi */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mhsethis) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    UHI opval = FLD (f_u12);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mhdsets: mhdsets$pack $u12,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mhdsets) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    UHI opval = FLD (f_u12);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = FLD (f_u12);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mhsetloh: mhsetloh$pack $s5,$FRklo */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mhsetloh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_tmp;
+  tmp_tmp = GET_H_FR_LO (FLD (f_FRk));
+  tmp_tmp = ANDHI (tmp_tmp, 2047);
+  tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11));
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mhsethih: mhsethih$pack $s5,$FRkhi */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mhsethih) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_tmp;
+  tmp_tmp = GET_H_FR_HI (FLD (f_FRk));
+  tmp_tmp = ANDHI (tmp_tmp, 2047);
+  tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11));
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mhdseth: mhdseth$pack $s5,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mhdseth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  HI tmp_tmp;
+  tmp_tmp = GET_H_FR_HI (((FLD (f_FRk)) + (0)));
+  tmp_tmp = ANDHI (tmp_tmp, 2047);
+  tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11));
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+{
+  HI tmp_tmp;
+  tmp_tmp = GET_H_FR_LO (((FLD (f_FRk)) + (0)));
+  tmp_tmp = ANDHI (tmp_tmp, 2047);
+  tmp_tmp = ORHI (tmp_tmp, SLLSI (ANDSI (FLD (f_s5), 31), 11));
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mand: mand$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mand) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mor: mor$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mxor: mxor$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mxor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmand: cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmand) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = ANDSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmor: cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = ORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmxor: cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmxor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = XORSI (GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mnot: mnot$pack $FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = INVSI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* cmnot: cmnot$pack $FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+  {
+    SI opval = INVSI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mrotli: mrotli$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mrotli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ROLSI (GET_H_FR_INT (FLD (f_FRi)), ANDSI (FLD (f_u6), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mrotri: mrotri$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mrotri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = RORSI (GET_H_FR_INT (FLD (f_FRi)), ANDSI (FLD (f_u6), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mwcut: mwcut$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mwcut) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_cut (current_cpu, GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (((FLD (f_FRi)) + (1))), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mwcuti: mwcuti$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mwcuti) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_cut (current_cpu, GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (((FLD (f_FRi)) + (1))), FLD (f_u6));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mcut: mcut$pack $ACC40Si,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcut) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_media_cut (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mcuti: mcuti$pack $ACC40Si,$s6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcuti) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_media_cut (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), FLD (f_s6));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mcutss: mcutss$pack $ACC40Si,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcutss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mcutssi: mcutssi$pack $ACC40Si,$s6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcutssi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), FLD (f_s6));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mdcutssi: mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mdcutssi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    SI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (FLD (f_ACC40Si)), FLD (f_s6));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = frvbf_media_cut_ss (current_cpu, GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))), FLD (f_s6));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* maveh: maveh$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,maveh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = frvbf_media_average (current_cpu, GET_H_FR_INT (FLD (f_FRi)), GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* msllhi: msllhi$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msllhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* msrlhi: msrlhi$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msrlhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    UHI opval = SRLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = SRLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* msrahi: msrahi$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msrahi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mdrotli: mdrotli$pack $FRintieven,$s6,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mdrotli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    SI opval = ROLSI (GET_H_FR_INT (FLD (f_FRi)), ANDSI (FLD (f_s6), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    USI opval = ROLSI (GET_H_FR_INT (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_s6), 31));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mcplhi: mcplhi$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcplhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_arg1;
+  HI tmp_arg2;
+  HI tmp_shift;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  tmp_shift = ANDSI (FLD (f_u6), 15);
+  tmp_arg1 = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), tmp_shift);
+if (NEHI (tmp_shift, 0)) {
+{
+  tmp_arg2 = GET_H_FR_HI (((FLD (f_FRi)) + (1)));
+  tmp_arg2 = SRLHI (SLLHI (tmp_arg2, SUBSI (15, tmp_shift)), SUBSI (15, tmp_shift));
+  tmp_arg1 = ORHI (tmp_arg1, tmp_arg2);
+}
+}
+  {
+    UHI opval = tmp_arg1;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mcpli: mcpli$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcpli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI tmp_tmp;
+  SI tmp_shift;
+  tmp_shift = ANDSI (FLD (f_u6), 31);
+  tmp_tmp = SLLSI (GET_H_FR_INT (FLD (f_FRi)), tmp_shift);
+if (NESI (tmp_shift, 0)) {
+{
+  SI tmp_tmp1;
+  tmp_tmp1 = SRLSI (SLLSI (GET_H_FR_INT (((FLD (f_FRi)) + (1))), SUBSI (31, tmp_shift)), SUBSI (31, tmp_shift));
+  tmp_tmp = ORSI (tmp_tmp, tmp_tmp1);
+}
+}
+  {
+    SI opval = tmp_tmp;
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* msaths: msaths$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msaths) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+if (GTHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UHI opval = tmp_argjhi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argihi, INVHI (tmp_argjhi))) {
+  {
+    UHI opval = INVHI (tmp_argjhi);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argihi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+if (GTHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UHI opval = tmp_argjlo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argilo, INVHI (tmp_argjlo))) {
+  {
+    UHI opval = INVHI (tmp_argjlo);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argilo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqsaths: mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqsaths) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+if (GTHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UHI opval = tmp_argjhi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argihi, INVHI (tmp_argjhi))) {
+  {
+    UHI opval = INVHI (tmp_argjhi);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argihi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+if (GTHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UHI opval = tmp_argjlo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argilo, INVHI (tmp_argjlo))) {
+  {
+    UHI opval = INVHI (tmp_argjlo);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argilo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+if (GTHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UHI opval = tmp_argjhi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argihi, INVHI (tmp_argjhi))) {
+  {
+    UHI opval = INVHI (tmp_argjhi);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argihi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+if (GTHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UHI opval = tmp_argjlo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argilo, INVHI (tmp_argjlo))) {
+  {
+    UHI opval = INVHI (tmp_argjlo);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argilo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* msathu: msathu$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msathu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+if (GTUHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UHI opval = tmp_argjhi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argihi;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+if (GTUHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UHI opval = tmp_argjlo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+} else {
+  {
+    UHI opval = tmp_argilo;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mcmpsh: mcmpsh$pack $FRinti,$FRintj,$FCCk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcmpsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_FCCk), SUBSI (2, 1))) {
+frvbf_media_cr_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+if (GTHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (EQHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+if (GTHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (EQHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (LTHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mcmpuh: mcmpuh$pack $FRinti,$FRintj,$FCCk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcmpuh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_FCCk), SUBSI (2, 1))) {
+frvbf_media_cr_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+if (GTUHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (EQHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (LTUHI (tmp_argihi, tmp_argjhi)) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCk)]), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+if (GTUHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UQI opval = 2;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (EQHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UQI opval = 8;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+if (LTUHI (tmp_argilo, tmp_argjlo)) {
+  {
+    UQI opval = 4;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+} else {
+  {
+    UQI opval = 1;
+    sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCk)) + (1))]), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mabshs: mabshs$pack $FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mabshs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_arghi;
+  HI tmp_arglo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  tmp_arghi = GET_H_FR_HI (((FLD (f_FRj)) + (0)));
+  tmp_arglo = GET_H_FR_LO (((FLD (f_FRj)) + (0)));
+if (GTDI (ABSHI (tmp_arghi), 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (ABSHI (tmp_arghi), -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = ABSHI (tmp_arghi);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+if (GTDI (ABSHI (tmp_arglo), 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (ABSHI (tmp_arglo), -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = ABSHI (tmp_arglo);
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* maddhss: maddhss$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,maddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* maddhus: maddhus$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,maddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* msubhss: msubhss$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* msubhus: msubhus$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmaddhss: cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmaddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmaddhus: cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmaddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmsubhss: cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmsubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmsubhus: cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmsubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqaddhss: mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqaddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqaddhus: mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqaddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqsubhss: mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqsubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqsubhus: mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqsubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqaddhss: cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqaddhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqaddhus: cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqaddhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqsubhss: cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqsubhss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 32767)) {
+{
+  {
+    UHI opval = 32767;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, -32768)) {
+{
+  {
+    UHI opval = -32768;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqsubhus: cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqsubhus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argihi, tmp_argjhi);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBHI (tmp_argilo, tmp_argjlo);
+if (GTDI (tmp_tmp, 65535)) {
+{
+  {
+    UHI opval = 65535;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, 0)) {
+{
+  {
+    UHI opval = 0;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* maddaccs: maddaccs$pack $ACC40Si,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,maddaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* msubaccs: msubaccs$pack $ACC40Si,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,msubaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mdaddaccs: mdaddaccs$pack $ACC40Si,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mdaddaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mdsubaccs: mdsubaccs$pack $ACC40Si,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mdsubaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* masaccs: masaccs$pack $ACC40Si,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,masaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 5);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mdasaccs: mdasaccs$pack $ACC40Si,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mdasaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
+if (GTDI (tmp_tmp, 549755813887)) {
+{
+  {
+    DI opval = 549755813887;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, INVDI (549755813887))) {
+{
+  {
+    DI opval = INVDI (549755813887);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmulhs: mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmulhu: mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmulxhs: mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmulxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmulxhu: mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmulxhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmmulhs: cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmmulhu: cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqmulhs: mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqmulhu: mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqmulxhs: mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqmulxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqmulxhu: mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqmulxhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqmulhs: cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqmulhu: cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+  {
+    DI opval = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmachs: mmachs$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmachu: mmachu$pack $FRinti,$FRintj,$ACC40Uk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmrdhs: mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmrdhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mmrdhu: mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mmrdhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = SUBDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmmachs: cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmmachu: cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqmachs: mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqmachu: mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Uk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (2))), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (3))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqmachs: cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 21);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 21);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 21);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 22);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 22);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 22);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmqmachu: cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmqmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Uk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (FLD (f_ACC40Uk)), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, FLD (f_ACC40Uk), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (1))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (1)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (2))), MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval);
+    written |= (1 << 21);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval);
+    written |= (1 << 21);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (2)), opval);
+    written |= (1 << 21);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40U (((FLD (f_ACC40Uk)) + (3))), MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    UDI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval);
+    written |= (1 << 22);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0, 0))) {
+{
+  {
+    UDI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval);
+    written |= (1 << 22);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    UDI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40U_set, ((FLD (f_ACC40Uk)) + (3)), opval);
+    written |= (1 << 22);
+    TRACE_RESULT (current_cpu, abuf, "acc40U", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqxmachs: mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqxmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqxmacxhs: mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqxmacxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqmacxhs: mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqmacxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (1))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (2))), MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 2);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  DI tmp_tmp;
+  tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Sk)) + (3))), MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi)));
+if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+if (LTDI (tmp_tmp, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 1);
+}
+} else {
+  {
+    DI opval = tmp_tmp;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
+    written |= (1 << 20);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mcpxrs: mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mcpxru: mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mcpxis: mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mcpxiu: mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmcpxrs: cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmcpxru: cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmcpxis: cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmcpxiu: cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqcpxrs: mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqcpxru: mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp1 = SUBDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqcpxis: mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  HI tmp_argihi;
+  HI tmp_argilo;
+  HI tmp_argjhi;
+  HI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (EXTHIDI (tmp_argihi), EXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (EXTHIDI (tmp_argilo), EXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (127, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
+{
+  {
+    DI opval = MAKEDI (0xffffff80, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mqcpxiu: mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
+frvbf_media_acc_not_aligned (current_cpu);
+} else {
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRj), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_argihi;
+  UHI tmp_argilo;
+  UHI tmp_argjhi;
+  UHI tmp_argjlo;
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 8);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+{
+  tmp_argihi = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argilo = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+  tmp_argjhi = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+  tmp_argjlo = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+  DI tmp_tmp1;
+  DI tmp_tmp2;
+  tmp_tmp1 = MULDI (ZEXTHIDI (tmp_argihi), ZEXTHIDI (tmp_argjlo));
+  tmp_tmp2 = MULDI (ZEXTHIDI (tmp_argilo), ZEXTHIDI (tmp_argjhi));
+  tmp_tmp1 = ADDDI (tmp_tmp1, tmp_tmp2);
+if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
+{
+  {
+    DI opval = MAKEDI (255, 0xffffffff);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
+{
+  {
+    DI opval = MAKEDI (0, 0);
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+frvbf_media_overflow (current_cpu, 4);
+}
+} else {
+  {
+    DI opval = tmp_tmp1;
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+}
+}
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mexpdhw: mexpdhw$pack $FRinti,$u6,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mexpdhw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  UHI tmp_tmp;
+if (ANDSI (FLD (f_u6), 1)) {
+  tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+} else {
+  tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+}
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* cmexpdhw: cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmexpdhw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_tmp;
+if (ANDSI (FLD (f_u6), 1)) {
+  tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+} else {
+  tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+}
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mexpdhd: mexpdhd$pack $FRinti,$u6,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mexpdhd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  UHI tmp_tmp;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_u6), 1)) {
+  tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+} else {
+  tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+}
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmexpdhd: cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmexpdhd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  UHI tmp_tmp;
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_u6), 1)) {
+  tmp_tmp = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+} else {
+  tmp_tmp = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+}
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = tmp_tmp;
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mpackh: mpackh$pack $FRinti,$FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+
+  return vpc;
+#undef FLD
+}
+
+/* mdpackh: mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mdpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+{
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* munpackh: munpackh$pack $FRinti,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,munpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+    written |= (1 << 6);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 7);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mdunpackh: mdunpackh$pack $FRintieven,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mdunpackh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (4, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+    written |= (1 << 8);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    written |= (1 << 9);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+{
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (ADDSI (0, 1))), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+{
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRi)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (ADDSI (2, 1))), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRi)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (ADDSI (2, 1))), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mbtoh: mbtoh$pack $FRintj,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mbtoh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmbtoh: cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmbtoh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_FRk), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  {
+    UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mhtob: mhtob$pack $FRintjeven,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mhtob) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_FRj), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_3_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_3", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_2_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_2", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_1_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_1", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_0_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_0", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmhtob: cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmhtob) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_FRj), SUBSI (2, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_3_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_3", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_2_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_2", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_HI (((FLD (f_FRj)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_1_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_1", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_LO (((FLD (f_FRj)) + (1)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_0_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_0", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mbtohe: mbtohe$pack $FRintj,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mbtohe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_FRk), SUBSI (4, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+  {
+    UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 10);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 11);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (3)), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (3)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* cmbtohe: cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,cmbtohe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRj)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRj), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+  {
+    SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+if (ANDSI (FLD (f_FRk), SUBSI (4, 1))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+{
+  {
+    UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 12);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_3 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+    written |= (1 << 16);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 13);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_2 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+    written |= (1 << 17);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 14);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_1 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (2)), opval);
+    written |= (1 << 18);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (3)), opval);
+    written |= (1 << 15);
+    TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+  }
+  {
+    UHI opval = GET_H_FR_0 (((FLD (f_FRj)) + (0)));
+    sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (3)), opval);
+    written |= (1 << 19);
+    TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+  }
+}
+}
+}
+}
+
+  abuf->written = written;
+  return vpc;
+#undef FLD
+}
+
+/* mclracc: mclracc$pack $ACC40Sk,$A */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mclracc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mclracc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_clear_accumulators (current_cpu, FLD (f_ACC40Sk), FLD (f_A));
+
+  return vpc;
+#undef FLD
+}
+
+/* mrdacc: mrdacc$pack $ACC40Si,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mrdacc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GET_H_ACC40S (FLD (f_ACC40Si));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mrdaccg: mrdaccg$pack $ACCGi,$FRintk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mrdaccg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GET_H_ACCG (FLD (f_ACCGi));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+    TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mwtacc: mwtacc$pack $FRinti,$ACC40Sk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mwtacc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    DI opval = ORDI (ANDDI (GET_H_ACC40S (FLD (f_ACC40Sk)), MAKEDI (0xffffffff, 0)), GET_H_FR_INT (FLD (f_FRi)));
+    sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
+    TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mwtaccg: mwtaccg$pack $FRinti,$ACCGk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mwtaccg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = GET_H_FR_INT (FLD (f_FRi));
+    sim_queue_fn_si_write (current_cpu, frvbf_h_accg_set, FLD (f_ACCGk), opval);
+    TRACE_RESULT (current_cpu, abuf, "accg", 'x', opval);
+  }
+
+  return vpc;
+#undef FLD
+}
+
+/* mcop1: mcop1$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcop1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_media_cop (current_cpu, 1);
+
+  return vpc;
+#undef FLD
+}
+
+/* mcop2: mcop2$pack $FRi,$FRj,$FRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mcop2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+frvbf_media_cop (current_cpu, 2);
+
+  return vpc;
+#undef FLD
+}
+
+/* fnop: fnop$pack */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,fnop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+  return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns.  */
+
+static const struct sem_fn_desc sem_fns[] = {
+  { FRVBF_INSN_X_INVALID, SEM_FN_NAME (frvbf,x_invalid) },
+  { FRVBF_INSN_X_AFTER, SEM_FN_NAME (frvbf,x_after) },
+  { FRVBF_INSN_X_BEFORE, SEM_FN_NAME (frvbf,x_before) },
+  { FRVBF_INSN_X_CTI_CHAIN, SEM_FN_NAME (frvbf,x_cti_chain) },
+  { FRVBF_INSN_X_CHAIN, SEM_FN_NAME (frvbf,x_chain) },
+  { FRVBF_INSN_X_BEGIN, SEM_FN_NAME (frvbf,x_begin) },
+  { FRVBF_INSN_ADD, SEM_FN_NAME (frvbf,add) },
+  { FRVBF_INSN_SUB, SEM_FN_NAME (frvbf,sub) },
+  { FRVBF_INSN_AND, SEM_FN_NAME (frvbf,and) },
+  { FRVBF_INSN_OR, SEM_FN_NAME (frvbf,or) },
+  { FRVBF_INSN_XOR, SEM_FN_NAME (frvbf,xor) },
+  { FRVBF_INSN_NOT, SEM_FN_NAME (frvbf,not) },
+  { FRVBF_INSN_SDIV, SEM_FN_NAME (frvbf,sdiv) },
+  { FRVBF_INSN_NSDIV, SEM_FN_NAME (frvbf,nsdiv) },
+  { FRVBF_INSN_UDIV, SEM_FN_NAME (frvbf,udiv) },
+  { FRVBF_INSN_NUDIV, SEM_FN_NAME (frvbf,nudiv) },
+  { FRVBF_INSN_SMUL, SEM_FN_NAME (frvbf,smul) },
+  { FRVBF_INSN_UMUL, SEM_FN_NAME (frvbf,umul) },
+  { FRVBF_INSN_SLL, SEM_FN_NAME (frvbf,sll) },
+  { FRVBF_INSN_SRL, SEM_FN_NAME (frvbf,srl) },
+  { FRVBF_INSN_SRA, SEM_FN_NAME (frvbf,sra) },
+  { FRVBF_INSN_SCAN, SEM_FN_NAME (frvbf,scan) },
+  { FRVBF_INSN_CADD, SEM_FN_NAME (frvbf,cadd) },
+  { FRVBF_INSN_CSUB, SEM_FN_NAME (frvbf,csub) },
+  { FRVBF_INSN_CAND, SEM_FN_NAME (frvbf,cand) },
+  { FRVBF_INSN_COR, SEM_FN_NAME (frvbf,cor) },
+  { FRVBF_INSN_CXOR, SEM_FN_NAME (frvbf,cxor) },
+  { FRVBF_INSN_CNOT, SEM_FN_NAME (frvbf,cnot) },
+  { FRVBF_INSN_CSMUL, SEM_FN_NAME (frvbf,csmul) },
+  { FRVBF_INSN_CSDIV, SEM_FN_NAME (frvbf,csdiv) },
+  { FRVBF_INSN_CUDIV, SEM_FN_NAME (frvbf,cudiv) },
+  { FRVBF_INSN_CSLL, SEM_FN_NAME (frvbf,csll) },
+  { FRVBF_INSN_CSRL, SEM_FN_NAME (frvbf,csrl) },
+  { FRVBF_INSN_CSRA, SEM_FN_NAME (frvbf,csra) },
+  { FRVBF_INSN_CSCAN, SEM_FN_NAME (frvbf,cscan) },
+  { FRVBF_INSN_ADDCC, SEM_FN_NAME (frvbf,addcc) },
+  { FRVBF_INSN_SUBCC, SEM_FN_NAME (frvbf,subcc) },
+  { FRVBF_INSN_ANDCC, SEM_FN_NAME (frvbf,andcc) },
+  { FRVBF_INSN_ORCC, SEM_FN_NAME (frvbf,orcc) },
+  { FRVBF_INSN_XORCC, SEM_FN_NAME (frvbf,xorcc) },
+  { FRVBF_INSN_SLLCC, SEM_FN_NAME (frvbf,sllcc) },
+  { FRVBF_INSN_SRLCC, SEM_FN_NAME (frvbf,srlcc) },
+  { FRVBF_INSN_SRACC, SEM_FN_NAME (frvbf,sracc) },
+  { FRVBF_INSN_SMULCC, SEM_FN_NAME (frvbf,smulcc) },
+  { FRVBF_INSN_UMULCC, SEM_FN_NAME (frvbf,umulcc) },
+  { FRVBF_INSN_CADDCC, SEM_FN_NAME (frvbf,caddcc) },
+  { FRVBF_INSN_CSUBCC, SEM_FN_NAME (frvbf,csubcc) },
+  { FRVBF_INSN_CSMULCC, SEM_FN_NAME (frvbf,csmulcc) },
+  { FRVBF_INSN_CANDCC, SEM_FN_NAME (frvbf,candcc) },
+  { FRVBF_INSN_CORCC, SEM_FN_NAME (frvbf,corcc) },
+  { FRVBF_INSN_CXORCC, SEM_FN_NAME (frvbf,cxorcc) },
+  { FRVBF_INSN_CSLLCC, SEM_FN_NAME (frvbf,csllcc) },
+  { FRVBF_INSN_CSRLCC, SEM_FN_NAME (frvbf,csrlcc) },
+  { FRVBF_INSN_CSRACC, SEM_FN_NAME (frvbf,csracc) },
+  { FRVBF_INSN_ADDX, SEM_FN_NAME (frvbf,addx) },
+  { FRVBF_INSN_SUBX, SEM_FN_NAME (frvbf,subx) },
+  { FRVBF_INSN_ADDXCC, SEM_FN_NAME (frvbf,addxcc) },
+  { FRVBF_INSN_SUBXCC, SEM_FN_NAME (frvbf,subxcc) },
+  { FRVBF_INSN_ADDI, SEM_FN_NAME (frvbf,addi) },
+  { FRVBF_INSN_SUBI, SEM_FN_NAME (frvbf,subi) },
+  { FRVBF_INSN_ANDI, SEM_FN_NAME (frvbf,andi) },
+  { FRVBF_INSN_ORI, SEM_FN_NAME (frvbf,ori) },
+  { FRVBF_INSN_XORI, SEM_FN_NAME (frvbf,xori) },
+  { FRVBF_INSN_SDIVI, SEM_FN_NAME (frvbf,sdivi) },
+  { FRVBF_INSN_NSDIVI, SEM_FN_NAME (frvbf,nsdivi) },
+  { FRVBF_INSN_UDIVI, SEM_FN_NAME (frvbf,udivi) },
+  { FRVBF_INSN_NUDIVI, SEM_FN_NAME (frvbf,nudivi) },
+  { FRVBF_INSN_SMULI, SEM_FN_NAME (frvbf,smuli) },
+  { FRVBF_INSN_UMULI, SEM_FN_NAME (frvbf,umuli) },
+  { FRVBF_INSN_SLLI, SEM_FN_NAME (frvbf,slli) },
+  { FRVBF_INSN_SRLI, SEM_FN_NAME (frvbf,srli) },
+  { FRVBF_INSN_SRAI, SEM_FN_NAME (frvbf,srai) },
+  { FRVBF_INSN_SCANI, SEM_FN_NAME (frvbf,scani) },
+  { FRVBF_INSN_ADDICC, SEM_FN_NAME (frvbf,addicc) },
+  { FRVBF_INSN_SUBICC, SEM_FN_NAME (frvbf,subicc) },
+  { FRVBF_INSN_ANDICC, SEM_FN_NAME (frvbf,andicc) },
+  { FRVBF_INSN_ORICC, SEM_FN_NAME (frvbf,oricc) },
+  { FRVBF_INSN_XORICC, SEM_FN_NAME (frvbf,xoricc) },
+  { FRVBF_INSN_SMULICC, SEM_FN_NAME (frvbf,smulicc) },
+  { FRVBF_INSN_UMULICC, SEM_FN_NAME (frvbf,umulicc) },
+  { FRVBF_INSN_SLLICC, SEM_FN_NAME (frvbf,sllicc) },
+  { FRVBF_INSN_SRLICC, SEM_FN_NAME (frvbf,srlicc) },
+  { FRVBF_INSN_SRAICC, SEM_FN_NAME (frvbf,sraicc) },
+  { FRVBF_INSN_ADDXI, SEM_FN_NAME (frvbf,addxi) },
+  { FRVBF_INSN_SUBXI, SEM_FN_NAME (frvbf,subxi) },
+  { FRVBF_INSN_ADDXICC, SEM_FN_NAME (frvbf,addxicc) },
+  { FRVBF_INSN_SUBXICC, SEM_FN_NAME (frvbf,subxicc) },
+  { FRVBF_INSN_CMPB, SEM_FN_NAME (frvbf,cmpb) },
+  { FRVBF_INSN_CMPBA, SEM_FN_NAME (frvbf,cmpba) },
+  { FRVBF_INSN_SETLO, SEM_FN_NAME (frvbf,setlo) },
+  { FRVBF_INSN_SETHI, SEM_FN_NAME (frvbf,sethi) },
+  { FRVBF_INSN_SETLOS, SEM_FN_NAME (frvbf,setlos) },
+  { FRVBF_INSN_LDSB, SEM_FN_NAME (frvbf,ldsb) },
+  { FRVBF_INSN_LDUB, SEM_FN_NAME (frvbf,ldub) },
+  { FRVBF_INSN_LDSH, SEM_FN_NAME (frvbf,ldsh) },
+  { FRVBF_INSN_LDUH, SEM_FN_NAME (frvbf,lduh) },
+  { FRVBF_INSN_LD, SEM_FN_NAME (frvbf,ld) },
+  { FRVBF_INSN_LDBF, SEM_FN_NAME (frvbf,ldbf) },
+  { FRVBF_INSN_LDHF, SEM_FN_NAME (frvbf,ldhf) },
+  { FRVBF_INSN_LDF, SEM_FN_NAME (frvbf,ldf) },
+  { FRVBF_INSN_LDC, SEM_FN_NAME (frvbf,ldc) },
+  { FRVBF_INSN_NLDSB, SEM_FN_NAME (frvbf,nldsb) },
+  { FRVBF_INSN_NLDUB, SEM_FN_NAME (frvbf,nldub) },
+  { FRVBF_INSN_NLDSH, SEM_FN_NAME (frvbf,nldsh) },
+  { FRVBF_INSN_NLDUH, SEM_FN_NAME (frvbf,nlduh) },
+  { FRVBF_INSN_NLD, SEM_FN_NAME (frvbf,nld) },
+  { FRVBF_INSN_NLDBF, SEM_FN_NAME (frvbf,nldbf) },
+  { FRVBF_INSN_NLDHF, SEM_FN_NAME (frvbf,nldhf) },
+  { FRVBF_INSN_NLDF, SEM_FN_NAME (frvbf,nldf) },
+  { FRVBF_INSN_LDD, SEM_FN_NAME (frvbf,ldd) },
+  { FRVBF_INSN_LDDF, SEM_FN_NAME (frvbf,lddf) },
+  { FRVBF_INSN_LDDC, SEM_FN_NAME (frvbf,lddc) },
+  { FRVBF_INSN_NLDD, SEM_FN_NAME (frvbf,nldd) },
+  { FRVBF_INSN_NLDDF, SEM_FN_NAME (frvbf,nlddf) },
+  { FRVBF_INSN_LDQ, SEM_FN_NAME (frvbf,ldq) },
+  { FRVBF_INSN_LDQF, SEM_FN_NAME (frvbf,ldqf) },
+  { FRVBF_INSN_LDQC, SEM_FN_NAME (frvbf,ldqc) },
+  { FRVBF_INSN_NLDQ, SEM_FN_NAME (frvbf,nldq) },
+  { FRVBF_INSN_NLDQF, SEM_FN_NAME (frvbf,nldqf) },
+  { FRVBF_INSN_LDSBU, SEM_FN_NAME (frvbf,ldsbu) },
+  { FRVBF_INSN_LDUBU, SEM_FN_NAME (frvbf,ldubu) },
+  { FRVBF_INSN_LDSHU, SEM_FN_NAME (frvbf,ldshu) },
+  { FRVBF_INSN_LDUHU, SEM_FN_NAME (frvbf,lduhu) },
+  { FRVBF_INSN_LDU, SEM_FN_NAME (frvbf,ldu) },
+  { FRVBF_INSN_NLDSBU, SEM_FN_NAME (frvbf,nldsbu) },
+  { FRVBF_INSN_NLDUBU, SEM_FN_NAME (frvbf,nldubu) },
+  { FRVBF_INSN_NLDSHU, SEM_FN_NAME (frvbf,nldshu) },
+  { FRVBF_INSN_NLDUHU, SEM_FN_NAME (frvbf,nlduhu) },
+  { FRVBF_INSN_NLDU, SEM_FN_NAME (frvbf,nldu) },
+  { FRVBF_INSN_LDBFU, SEM_FN_NAME (frvbf,ldbfu) },
+  { FRVBF_INSN_LDHFU, SEM_FN_NAME (frvbf,ldhfu) },
+  { FRVBF_INSN_LDFU, SEM_FN_NAME (frvbf,ldfu) },
+  { FRVBF_INSN_LDCU, SEM_FN_NAME (frvbf,ldcu) },
+  { FRVBF_INSN_NLDBFU, SEM_FN_NAME (frvbf,nldbfu) },
+  { FRVBF_INSN_NLDHFU, SEM_FN_NAME (frvbf,nldhfu) },
+  { FRVBF_INSN_NLDFU, SEM_FN_NAME (frvbf,nldfu) },
+  { FRVBF_INSN_LDDU, SEM_FN_NAME (frvbf,lddu) },
+  { FRVBF_INSN_NLDDU, SEM_FN_NAME (frvbf,nlddu) },
+  { FRVBF_INSN_LDDFU, SEM_FN_NAME (frvbf,lddfu) },
+  { FRVBF_INSN_LDDCU, SEM_FN_NAME (frvbf,lddcu) },
+  { FRVBF_INSN_NLDDFU, SEM_FN_NAME (frvbf,nlddfu) },
+  { FRVBF_INSN_LDQU, SEM_FN_NAME (frvbf,ldqu) },
+  { FRVBF_INSN_NLDQU, SEM_FN_NAME (frvbf,nldqu) },
+  { FRVBF_INSN_LDQFU, SEM_FN_NAME (frvbf,ldqfu) },
+  { FRVBF_INSN_LDQCU, SEM_FN_NAME (frvbf,ldqcu) },
+  { FRVBF_INSN_NLDQFU, SEM_FN_NAME (frvbf,nldqfu) },
+  { FRVBF_INSN_LDSBI, SEM_FN_NAME (frvbf,ldsbi) },
+  { FRVBF_INSN_LDSHI, SEM_FN_NAME (frvbf,ldshi) },
+  { FRVBF_INSN_LDI, SEM_FN_NAME (frvbf,ldi) },
+  { FRVBF_INSN_LDUBI, SEM_FN_NAME (frvbf,ldubi) },
+  { FRVBF_INSN_LDUHI, SEM_FN_NAME (frvbf,lduhi) },
+  { FRVBF_INSN_LDBFI, SEM_FN_NAME (frvbf,ldbfi) },
+  { FRVBF_INSN_LDHFI, SEM_FN_NAME (frvbf,ldhfi) },
+  { FRVBF_INSN_LDFI, SEM_FN_NAME (frvbf,ldfi) },
+  { FRVBF_INSN_NLDSBI, SEM_FN_NAME (frvbf,nldsbi) },
+  { FRVBF_INSN_NLDUBI, SEM_FN_NAME (frvbf,nldubi) },
+  { FRVBF_INSN_NLDSHI, SEM_FN_NAME (frvbf,nldshi) },
+  { FRVBF_INSN_NLDUHI, SEM_FN_NAME (frvbf,nlduhi) },
+  { FRVBF_INSN_NLDI, SEM_FN_NAME (frvbf,nldi) },
+  { FRVBF_INSN_NLDBFI, SEM_FN_NAME (frvbf,nldbfi) },
+  { FRVBF_INSN_NLDHFI, SEM_FN_NAME (frvbf,nldhfi) },
+  { FRVBF_INSN_NLDFI, SEM_FN_NAME (frvbf,nldfi) },
+  { FRVBF_INSN_LDDI, SEM_FN_NAME (frvbf,lddi) },
+  { FRVBF_INSN_LDDFI, SEM_FN_NAME (frvbf,lddfi) },
+  { FRVBF_INSN_NLDDI, SEM_FN_NAME (frvbf,nlddi) },
+  { FRVBF_INSN_NLDDFI, SEM_FN_NAME (frvbf,nlddfi) },
+  { FRVBF_INSN_LDQI, SEM_FN_NAME (frvbf,ldqi) },
+  { FRVBF_INSN_LDQFI, SEM_FN_NAME (frvbf,ldqfi) },
+  { FRVBF_INSN_NLDQI, SEM_FN_NAME (frvbf,nldqi) },
+  { FRVBF_INSN_NLDQFI, SEM_FN_NAME (frvbf,nldqfi) },
+  { FRVBF_INSN_STB, SEM_FN_NAME (frvbf,stb) },
+  { FRVBF_INSN_STH, SEM_FN_NAME (frvbf,sth) },
+  { FRVBF_INSN_ST, SEM_FN_NAME (frvbf,st) },
+  { FRVBF_INSN_STBF, SEM_FN_NAME (frvbf,stbf) },
+  { FRVBF_INSN_STHF, SEM_FN_NAME (frvbf,sthf) },
+  { FRVBF_INSN_STF, SEM_FN_NAME (frvbf,stf) },
+  { FRVBF_INSN_STC, SEM_FN_NAME (frvbf,stc) },
+  { FRVBF_INSN_RSTB, SEM_FN_NAME (frvbf,rstb) },
+  { FRVBF_INSN_RSTH, SEM_FN_NAME (frvbf,rsth) },
+  { FRVBF_INSN_RST, SEM_FN_NAME (frvbf,rst) },
+  { FRVBF_INSN_RSTBF, SEM_FN_NAME (frvbf,rstbf) },
+  { FRVBF_INSN_RSTHF, SEM_FN_NAME (frvbf,rsthf) },
+  { FRVBF_INSN_RSTF, SEM_FN_NAME (frvbf,rstf) },
+  { FRVBF_INSN_STD, SEM_FN_NAME (frvbf,std) },
+  { FRVBF_INSN_STDF, SEM_FN_NAME (frvbf,stdf) },
+  { FRVBF_INSN_STDC, SEM_FN_NAME (frvbf,stdc) },
+  { FRVBF_INSN_RSTD, SEM_FN_NAME (frvbf,rstd) },
+  { FRVBF_INSN_RSTDF, SEM_FN_NAME (frvbf,rstdf) },
+  { FRVBF_INSN_STQ, SEM_FN_NAME (frvbf,stq) },
+  { FRVBF_INSN_STQF, SEM_FN_NAME (frvbf,stqf) },
+  { FRVBF_INSN_STQC, SEM_FN_NAME (frvbf,stqc) },
+  { FRVBF_INSN_RSTQ, SEM_FN_NAME (frvbf,rstq) },
+  { FRVBF_INSN_RSTQF, SEM_FN_NAME (frvbf,rstqf) },
+  { FRVBF_INSN_STBU, SEM_FN_NAME (frvbf,stbu) },
+  { FRVBF_INSN_STHU, SEM_FN_NAME (frvbf,sthu) },
+  { FRVBF_INSN_STU, SEM_FN_NAME (frvbf,stu) },
+  { FRVBF_INSN_STBFU, SEM_FN_NAME (frvbf,stbfu) },
+  { FRVBF_INSN_STHFU, SEM_FN_NAME (frvbf,sthfu) },
+  { FRVBF_INSN_STFU, SEM_FN_NAME (frvbf,stfu) },
+  { FRVBF_INSN_STCU, SEM_FN_NAME (frvbf,stcu) },
+  { FRVBF_INSN_STDU, SEM_FN_NAME (frvbf,stdu) },
+  { FRVBF_INSN_STDFU, SEM_FN_NAME (frvbf,stdfu) },
+  { FRVBF_INSN_STDCU, SEM_FN_NAME (frvbf,stdcu) },
+  { FRVBF_INSN_STQU, SEM_FN_NAME (frvbf,stqu) },
+  { FRVBF_INSN_STQFU, SEM_FN_NAME (frvbf,stqfu) },
+  { FRVBF_INSN_STQCU, SEM_FN_NAME (frvbf,stqcu) },
+  { FRVBF_INSN_CLDSB, SEM_FN_NAME (frvbf,cldsb) },
+  { FRVBF_INSN_CLDUB, SEM_FN_NAME (frvbf,cldub) },
+  { FRVBF_INSN_CLDSH, SEM_FN_NAME (frvbf,cldsh) },
+  { FRVBF_INSN_CLDUH, SEM_FN_NAME (frvbf,clduh) },
+  { FRVBF_INSN_CLD, SEM_FN_NAME (frvbf,cld) },
+  { FRVBF_INSN_CLDBF, SEM_FN_NAME (frvbf,cldbf) },
+  { FRVBF_INSN_CLDHF, SEM_FN_NAME (frvbf,cldhf) },
+  { FRVBF_INSN_CLDF, SEM_FN_NAME (frvbf,cldf) },
+  { FRVBF_INSN_CLDD, SEM_FN_NAME (frvbf,cldd) },
+  { FRVBF_INSN_CLDDF, SEM_FN_NAME (frvbf,clddf) },
+  { FRVBF_INSN_CLDQ, SEM_FN_NAME (frvbf,cldq) },
+  { FRVBF_INSN_CLDSBU, SEM_FN_NAME (frvbf,cldsbu) },
+  { FRVBF_INSN_CLDUBU, SEM_FN_NAME (frvbf,cldubu) },
+  { FRVBF_INSN_CLDSHU, SEM_FN_NAME (frvbf,cldshu) },
+  { FRVBF_INSN_CLDUHU, SEM_FN_NAME (frvbf,clduhu) },
+  { FRVBF_INSN_CLDU, SEM_FN_NAME (frvbf,cldu) },
+  { FRVBF_INSN_CLDBFU, SEM_FN_NAME (frvbf,cldbfu) },
+  { FRVBF_INSN_CLDHFU, SEM_FN_NAME (frvbf,cldhfu) },
+  { FRVBF_INSN_CLDFU, SEM_FN_NAME (frvbf,cldfu) },
+  { FRVBF_INSN_CLDDU, SEM_FN_NAME (frvbf,clddu) },
+  { FRVBF_INSN_CLDDFU, SEM_FN_NAME (frvbf,clddfu) },
+  { FRVBF_INSN_CLDQU, SEM_FN_NAME (frvbf,cldqu) },
+  { FRVBF_INSN_CSTB, SEM_FN_NAME (frvbf,cstb) },
+  { FRVBF_INSN_CSTH, SEM_FN_NAME (frvbf,csth) },
+  { FRVBF_INSN_CST, SEM_FN_NAME (frvbf,cst) },
+  { FRVBF_INSN_CSTBF, SEM_FN_NAME (frvbf,cstbf) },
+  { FRVBF_INSN_CSTHF, SEM_FN_NAME (frvbf,csthf) },
+  { FRVBF_INSN_CSTF, SEM_FN_NAME (frvbf,cstf) },
+  { FRVBF_INSN_CSTD, SEM_FN_NAME (frvbf,cstd) },
+  { FRVBF_INSN_CSTDF, SEM_FN_NAME (frvbf,cstdf) },
+  { FRVBF_INSN_CSTQ, SEM_FN_NAME (frvbf,cstq) },
+  { FRVBF_INSN_CSTBU, SEM_FN_NAME (frvbf,cstbu) },
+  { FRVBF_INSN_CSTHU, SEM_FN_NAME (frvbf,csthu) },
+  { FRVBF_INSN_CSTU, SEM_FN_NAME (frvbf,cstu) },
+  { FRVBF_INSN_CSTBFU, SEM_FN_NAME (frvbf,cstbfu) },
+  { FRVBF_INSN_CSTHFU, SEM_FN_NAME (frvbf,csthfu) },
+  { FRVBF_INSN_CSTFU, SEM_FN_NAME (frvbf,cstfu) },
+  { FRVBF_INSN_CSTDU, SEM_FN_NAME (frvbf,cstdu) },
+  { FRVBF_INSN_CSTDFU, SEM_FN_NAME (frvbf,cstdfu) },
+  { FRVBF_INSN_STBI, SEM_FN_NAME (frvbf,stbi) },
+  { FRVBF_INSN_STHI, SEM_FN_NAME (frvbf,sthi) },
+  { FRVBF_INSN_STI, SEM_FN_NAME (frvbf,sti) },
+  { FRVBF_INSN_STBFI, SEM_FN_NAME (frvbf,stbfi) },
+  { FRVBF_INSN_STHFI, SEM_FN_NAME (frvbf,sthfi) },
+  { FRVBF_INSN_STFI, SEM_FN_NAME (frvbf,stfi) },
+  { FRVBF_INSN_STDI, SEM_FN_NAME (frvbf,stdi) },
+  { FRVBF_INSN_STDFI, SEM_FN_NAME (frvbf,stdfi) },
+  { FRVBF_INSN_STQI, SEM_FN_NAME (frvbf,stqi) },
+  { FRVBF_INSN_STQFI, SEM_FN_NAME (frvbf,stqfi) },
+  { FRVBF_INSN_SWAP, SEM_FN_NAME (frvbf,swap) },
+  { FRVBF_INSN_SWAPI, SEM_FN_NAME (frvbf,swapi) },
+  { FRVBF_INSN_CSWAP, SEM_FN_NAME (frvbf,cswap) },
+  { FRVBF_INSN_MOVGF, SEM_FN_NAME (frvbf,movgf) },
+  { FRVBF_INSN_MOVFG, SEM_FN_NAME (frvbf,movfg) },
+  { FRVBF_INSN_MOVGFD, SEM_FN_NAME (frvbf,movgfd) },
+  { FRVBF_INSN_MOVFGD, SEM_FN_NAME (frvbf,movfgd) },
+  { FRVBF_INSN_MOVGFQ, SEM_FN_NAME (frvbf,movgfq) },
+  { FRVBF_INSN_MOVFGQ, SEM_FN_NAME (frvbf,movfgq) },
+  { FRVBF_INSN_CMOVGF, SEM_FN_NAME (frvbf,cmovgf) },
+  { FRVBF_INSN_CMOVFG, SEM_FN_NAME (frvbf,cmovfg) },
+  { FRVBF_INSN_CMOVGFD, SEM_FN_NAME (frvbf,cmovgfd) },
+  { FRVBF_INSN_CMOVFGD, SEM_FN_NAME (frvbf,cmovfgd) },
+  { FRVBF_INSN_MOVGS, SEM_FN_NAME (frvbf,movgs) },
+  { FRVBF_INSN_MOVSG, SEM_FN_NAME (frvbf,movsg) },
+  { FRVBF_INSN_BRA, SEM_FN_NAME (frvbf,bra) },
+  { FRVBF_INSN_BNO, SEM_FN_NAME (frvbf,bno) },
+  { FRVBF_INSN_BEQ, SEM_FN_NAME (frvbf,beq) },
+  { FRVBF_INSN_BNE, SEM_FN_NAME (frvbf,bne) },
+  { FRVBF_INSN_BLE, SEM_FN_NAME (frvbf,ble) },
+  { FRVBF_INSN_BGT, SEM_FN_NAME (frvbf,bgt) },
+  { FRVBF_INSN_BLT, SEM_FN_NAME (frvbf,blt) },
+  { FRVBF_INSN_BGE, SEM_FN_NAME (frvbf,bge) },
+  { FRVBF_INSN_BLS, SEM_FN_NAME (frvbf,bls) },
+  { FRVBF_INSN_BHI, SEM_FN_NAME (frvbf,bhi) },
+  { FRVBF_INSN_BC, SEM_FN_NAME (frvbf,bc) },
+  { FRVBF_INSN_BNC, SEM_FN_NAME (frvbf,bnc) },
+  { FRVBF_INSN_BN, SEM_FN_NAME (frvbf,bn) },
+  { FRVBF_INSN_BP, SEM_FN_NAME (frvbf,bp) },
+  { FRVBF_INSN_BV, SEM_FN_NAME (frvbf,bv) },
+  { FRVBF_INSN_BNV, SEM_FN_NAME (frvbf,bnv) },
+  { FRVBF_INSN_FBRA, SEM_FN_NAME (frvbf,fbra) },
+  { FRVBF_INSN_FBNO, SEM_FN_NAME (frvbf,fbno) },
+  { FRVBF_INSN_FBNE, SEM_FN_NAME (frvbf,fbne) },
+  { FRVBF_INSN_FBEQ, SEM_FN_NAME (frvbf,fbeq) },
+  { FRVBF_INSN_FBLG, SEM_FN_NAME (frvbf,fblg) },
+  { FRVBF_INSN_FBUE, SEM_FN_NAME (frvbf,fbue) },
+  { FRVBF_INSN_FBUL, SEM_FN_NAME (frvbf,fbul) },
+  { FRVBF_INSN_FBGE, SEM_FN_NAME (frvbf,fbge) },
+  { FRVBF_INSN_FBLT, SEM_FN_NAME (frvbf,fblt) },
+  { FRVBF_INSN_FBUGE, SEM_FN_NAME (frvbf,fbuge) },
+  { FRVBF_INSN_FBUG, SEM_FN_NAME (frvbf,fbug) },
+  { FRVBF_INSN_FBLE, SEM_FN_NAME (frvbf,fble) },
+  { FRVBF_INSN_FBGT, SEM_FN_NAME (frvbf,fbgt) },
+  { FRVBF_INSN_FBULE, SEM_FN_NAME (frvbf,fbule) },
+  { FRVBF_INSN_FBU, SEM_FN_NAME (frvbf,fbu) },
+  { FRVBF_INSN_FBO, SEM_FN_NAME (frvbf,fbo) },
+  { FRVBF_INSN_BCTRLR, SEM_FN_NAME (frvbf,bctrlr) },
+  { FRVBF_INSN_BRALR, SEM_FN_NAME (frvbf,bralr) },
+  { FRVBF_INSN_BNOLR, SEM_FN_NAME (frvbf,bnolr) },
+  { FRVBF_INSN_BEQLR, SEM_FN_NAME (frvbf,beqlr) },
+  { FRVBF_INSN_BNELR, SEM_FN_NAME (frvbf,bnelr) },
+  { FRVBF_INSN_BLELR, SEM_FN_NAME (frvbf,blelr) },
+  { FRVBF_INSN_BGTLR, SEM_FN_NAME (frvbf,bgtlr) },
+  { FRVBF_INSN_BLTLR, SEM_FN_NAME (frvbf,bltlr) },
+  { FRVBF_INSN_BGELR, SEM_FN_NAME (frvbf,bgelr) },
+  { FRVBF_INSN_BLSLR, SEM_FN_NAME (frvbf,blslr) },
+  { FRVBF_INSN_BHILR, SEM_FN_NAME (frvbf,bhilr) },
+  { FRVBF_INSN_BCLR, SEM_FN_NAME (frvbf,bclr) },
+  { FRVBF_INSN_BNCLR, SEM_FN_NAME (frvbf,bnclr) },
+  { FRVBF_INSN_BNLR, SEM_FN_NAME (frvbf,bnlr) },
+  { FRVBF_INSN_BPLR, SEM_FN_NAME (frvbf,bplr) },
+  { FRVBF_INSN_BVLR, SEM_FN_NAME (frvbf,bvlr) },
+  { FRVBF_INSN_BNVLR, SEM_FN_NAME (frvbf,bnvlr) },
+  { FRVBF_INSN_FBRALR, SEM_FN_NAME (frvbf,fbralr) },
+  { FRVBF_INSN_FBNOLR, SEM_FN_NAME (frvbf,fbnolr) },
+  { FRVBF_INSN_FBEQLR, SEM_FN_NAME (frvbf,fbeqlr) },
+  { FRVBF_INSN_FBNELR, SEM_FN_NAME (frvbf,fbnelr) },
+  { FRVBF_INSN_FBLGLR, SEM_FN_NAME (frvbf,fblglr) },
+  { FRVBF_INSN_FBUELR, SEM_FN_NAME (frvbf,fbuelr) },
+  { FRVBF_INSN_FBULLR, SEM_FN_NAME (frvbf,fbullr) },
+  { FRVBF_INSN_FBGELR, SEM_FN_NAME (frvbf,fbgelr) },
+  { FRVBF_INSN_FBLTLR, SEM_FN_NAME (frvbf,fbltlr) },
+  { FRVBF_INSN_FBUGELR, SEM_FN_NAME (frvbf,fbugelr) },
+  { FRVBF_INSN_FBUGLR, SEM_FN_NAME (frvbf,fbuglr) },
+  { FRVBF_INSN_FBLELR, SEM_FN_NAME (frvbf,fblelr) },
+  { FRVBF_INSN_FBGTLR, SEM_FN_NAME (frvbf,fbgtlr) },
+  { FRVBF_INSN_FBULELR, SEM_FN_NAME (frvbf,fbulelr) },
+  { FRVBF_INSN_FBULR, SEM_FN_NAME (frvbf,fbulr) },
+  { FRVBF_INSN_FBOLR, SEM_FN_NAME (frvbf,fbolr) },
+  { FRVBF_INSN_BCRALR, SEM_FN_NAME (frvbf,bcralr) },
+  { FRVBF_INSN_BCNOLR, SEM_FN_NAME (frvbf,bcnolr) },
+  { FRVBF_INSN_BCEQLR, SEM_FN_NAME (frvbf,bceqlr) },
+  { FRVBF_INSN_BCNELR, SEM_FN_NAME (frvbf,bcnelr) },
+  { FRVBF_INSN_BCLELR, SEM_FN_NAME (frvbf,bclelr) },
+  { FRVBF_INSN_BCGTLR, SEM_FN_NAME (frvbf,bcgtlr) },
+  { FRVBF_INSN_BCLTLR, SEM_FN_NAME (frvbf,bcltlr) },
+  { FRVBF_INSN_BCGELR, SEM_FN_NAME (frvbf,bcgelr) },
+  { FRVBF_INSN_BCLSLR, SEM_FN_NAME (frvbf,bclslr) },
+  { FRVBF_INSN_BCHILR, SEM_FN_NAME (frvbf,bchilr) },
+  { FRVBF_INSN_BCCLR, SEM_FN_NAME (frvbf,bcclr) },
+  { FRVBF_INSN_BCNCLR, SEM_FN_NAME (frvbf,bcnclr) },
+  { FRVBF_INSN_BCNLR, SEM_FN_NAME (frvbf,bcnlr) },
+  { FRVBF_INSN_BCPLR, SEM_FN_NAME (frvbf,bcplr) },
+  { FRVBF_INSN_BCVLR, SEM_FN_NAME (frvbf,bcvlr) },
+  { FRVBF_INSN_BCNVLR, SEM_FN_NAME (frvbf,bcnvlr) },
+  { FRVBF_INSN_FCBRALR, SEM_FN_NAME (frvbf,fcbralr) },
+  { FRVBF_INSN_FCBNOLR, SEM_FN_NAME (frvbf,fcbnolr) },
+  { FRVBF_INSN_FCBEQLR, SEM_FN_NAME (frvbf,fcbeqlr) },
+  { FRVBF_INSN_FCBNELR, SEM_FN_NAME (frvbf,fcbnelr) },
+  { FRVBF_INSN_FCBLGLR, SEM_FN_NAME (frvbf,fcblglr) },
+  { FRVBF_INSN_FCBUELR, SEM_FN_NAME (frvbf,fcbuelr) },
+  { FRVBF_INSN_FCBULLR, SEM_FN_NAME (frvbf,fcbullr) },
+  { FRVBF_INSN_FCBGELR, SEM_FN_NAME (frvbf,fcbgelr) },
+  { FRVBF_INSN_FCBLTLR, SEM_FN_NAME (frvbf,fcbltlr) },
+  { FRVBF_INSN_FCBUGELR, SEM_FN_NAME (frvbf,fcbugelr) },
+  { FRVBF_INSN_FCBUGLR, SEM_FN_NAME (frvbf,fcbuglr) },
+  { FRVBF_INSN_FCBLELR, SEM_FN_NAME (frvbf,fcblelr) },
+  { FRVBF_INSN_FCBGTLR, SEM_FN_NAME (frvbf,fcbgtlr) },
+  { FRVBF_INSN_FCBULELR, SEM_FN_NAME (frvbf,fcbulelr) },
+  { FRVBF_INSN_FCBULR, SEM_FN_NAME (frvbf,fcbulr) },
+  { FRVBF_INSN_FCBOLR, SEM_FN_NAME (frvbf,fcbolr) },
+  { FRVBF_INSN_JMPL, SEM_FN_NAME (frvbf,jmpl) },
+  { FRVBF_INSN_CALLL, SEM_FN_NAME (frvbf,calll) },
+  { FRVBF_INSN_JMPIL, SEM_FN_NAME (frvbf,jmpil) },
+  { FRVBF_INSN_CALLIL, SEM_FN_NAME (frvbf,callil) },
+  { FRVBF_INSN_CALL, SEM_FN_NAME (frvbf,call) },
+  { FRVBF_INSN_RETT, SEM_FN_NAME (frvbf,rett) },
+  { FRVBF_INSN_REI, SEM_FN_NAME (frvbf,rei) },
+  { FRVBF_INSN_TRA, SEM_FN_NAME (frvbf,tra) },
+  { FRVBF_INSN_TNO, SEM_FN_NAME (frvbf,tno) },
+  { FRVBF_INSN_TEQ, SEM_FN_NAME (frvbf,teq) },
+  { FRVBF_INSN_TNE, SEM_FN_NAME (frvbf,tne) },
+  { FRVBF_INSN_TLE, SEM_FN_NAME (frvbf,tle) },
+  { FRVBF_INSN_TGT, SEM_FN_NAME (frvbf,tgt) },
+  { FRVBF_INSN_TLT, SEM_FN_NAME (frvbf,tlt) },
+  { FRVBF_INSN_TGE, SEM_FN_NAME (frvbf,tge) },
+  { FRVBF_INSN_TLS, SEM_FN_NAME (frvbf,tls) },
+  { FRVBF_INSN_THI, SEM_FN_NAME (frvbf,thi) },
+  { FRVBF_INSN_TC, SEM_FN_NAME (frvbf,tc) },
+  { FRVBF_INSN_TNC, SEM_FN_NAME (frvbf,tnc) },
+  { FRVBF_INSN_TN, SEM_FN_NAME (frvbf,tn) },
+  { FRVBF_INSN_TP, SEM_FN_NAME (frvbf,tp) },
+  { FRVBF_INSN_TV, SEM_FN_NAME (frvbf,tv) },
+  { FRVBF_INSN_TNV, SEM_FN_NAME (frvbf,tnv) },
+  { FRVBF_INSN_FTRA, SEM_FN_NAME (frvbf,ftra) },
+  { FRVBF_INSN_FTNO, SEM_FN_NAME (frvbf,ftno) },
+  { FRVBF_INSN_FTNE, SEM_FN_NAME (frvbf,ftne) },
+  { FRVBF_INSN_FTEQ, SEM_FN_NAME (frvbf,fteq) },
+  { FRVBF_INSN_FTLG, SEM_FN_NAME (frvbf,ftlg) },
+  { FRVBF_INSN_FTUE, SEM_FN_NAME (frvbf,ftue) },
+  { FRVBF_INSN_FTUL, SEM_FN_NAME (frvbf,ftul) },
+  { FRVBF_INSN_FTGE, SEM_FN_NAME (frvbf,ftge) },
+  { FRVBF_INSN_FTLT, SEM_FN_NAME (frvbf,ftlt) },
+  { FRVBF_INSN_FTUGE, SEM_FN_NAME (frvbf,ftuge) },
+  { FRVBF_INSN_FTUG, SEM_FN_NAME (frvbf,ftug) },
+  { FRVBF_INSN_FTLE, SEM_FN_NAME (frvbf,ftle) },
+  { FRVBF_INSN_FTGT, SEM_FN_NAME (frvbf,ftgt) },
+  { FRVBF_INSN_FTULE, SEM_FN_NAME (frvbf,ftule) },
+  { FRVBF_INSN_FTU, SEM_FN_NAME (frvbf,ftu) },
+  { FRVBF_INSN_FTO, SEM_FN_NAME (frvbf,fto) },
+  { FRVBF_INSN_TIRA, SEM_FN_NAME (frvbf,tira) },
+  { FRVBF_INSN_TINO, SEM_FN_NAME (frvbf,tino) },
+  { FRVBF_INSN_TIEQ, SEM_FN_NAME (frvbf,tieq) },
+  { FRVBF_INSN_TINE, SEM_FN_NAME (frvbf,tine) },
+  { FRVBF_INSN_TILE, SEM_FN_NAME (frvbf,tile) },
+  { FRVBF_INSN_TIGT, SEM_FN_NAME (frvbf,tigt) },
+  { FRVBF_INSN_TILT, SEM_FN_NAME (frvbf,tilt) },
+  { FRVBF_INSN_TIGE, SEM_FN_NAME (frvbf,tige) },
+  { FRVBF_INSN_TILS, SEM_FN_NAME (frvbf,tils) },
+  { FRVBF_INSN_TIHI, SEM_FN_NAME (frvbf,tihi) },
+  { FRVBF_INSN_TIC, SEM_FN_NAME (frvbf,tic) },
+  { FRVBF_INSN_TINC, SEM_FN_NAME (frvbf,tinc) },
+  { FRVBF_INSN_TIN, SEM_FN_NAME (frvbf,tin) },
+  { FRVBF_INSN_TIP, SEM_FN_NAME (frvbf,tip) },
+  { FRVBF_INSN_TIV, SEM_FN_NAME (frvbf,tiv) },
+  { FRVBF_INSN_TINV, SEM_FN_NAME (frvbf,tinv) },
+  { FRVBF_INSN_FTIRA, SEM_FN_NAME (frvbf,ftira) },
+  { FRVBF_INSN_FTINO, SEM_FN_NAME (frvbf,ftino) },
+  { FRVBF_INSN_FTINE, SEM_FN_NAME (frvbf,ftine) },
+  { FRVBF_INSN_FTIEQ, SEM_FN_NAME (frvbf,ftieq) },
+  { FRVBF_INSN_FTILG, SEM_FN_NAME (frvbf,ftilg) },
+  { FRVBF_INSN_FTIUE, SEM_FN_NAME (frvbf,ftiue) },
+  { FRVBF_INSN_FTIUL, SEM_FN_NAME (frvbf,ftiul) },
+  { FRVBF_INSN_FTIGE, SEM_FN_NAME (frvbf,ftige) },
+  { FRVBF_INSN_FTILT, SEM_FN_NAME (frvbf,ftilt) },
+  { FRVBF_INSN_FTIUGE, SEM_FN_NAME (frvbf,ftiuge) },
+  { FRVBF_INSN_FTIUG, SEM_FN_NAME (frvbf,ftiug) },
+  { FRVBF_INSN_FTILE, SEM_FN_NAME (frvbf,ftile) },
+  { FRVBF_INSN_FTIGT, SEM_FN_NAME (frvbf,ftigt) },
+  { FRVBF_INSN_FTIULE, SEM_FN_NAME (frvbf,ftiule) },
+  { FRVBF_INSN_FTIU, SEM_FN_NAME (frvbf,ftiu) },
+  { FRVBF_INSN_FTIO, SEM_FN_NAME (frvbf,ftio) },
+  { FRVBF_INSN_BREAK, SEM_FN_NAME (frvbf,break) },
+  { FRVBF_INSN_MTRAP, SEM_FN_NAME (frvbf,mtrap) },
+  { FRVBF_INSN_ANDCR, SEM_FN_NAME (frvbf,andcr) },
+  { FRVBF_INSN_ORCR, SEM_FN_NAME (frvbf,orcr) },
+  { FRVBF_INSN_XORCR, SEM_FN_NAME (frvbf,xorcr) },
+  { FRVBF_INSN_NANDCR, SEM_FN_NAME (frvbf,nandcr) },
+  { FRVBF_INSN_NORCR, SEM_FN_NAME (frvbf,norcr) },
+  { FRVBF_INSN_ANDNCR, SEM_FN_NAME (frvbf,andncr) },
+  { FRVBF_INSN_ORNCR, SEM_FN_NAME (frvbf,orncr) },
+  { FRVBF_INSN_NANDNCR, SEM_FN_NAME (frvbf,nandncr) },
+  { FRVBF_INSN_NORNCR, SEM_FN_NAME (frvbf,norncr) },
+  { FRVBF_INSN_NOTCR, SEM_FN_NAME (frvbf,notcr) },
+  { FRVBF_INSN_CKRA, SEM_FN_NAME (frvbf,ckra) },
+  { FRVBF_INSN_CKNO, SEM_FN_NAME (frvbf,ckno) },
+  { FRVBF_INSN_CKEQ, SEM_FN_NAME (frvbf,ckeq) },
+  { FRVBF_INSN_CKNE, SEM_FN_NAME (frvbf,ckne) },
+  { FRVBF_INSN_CKLE, SEM_FN_NAME (frvbf,ckle) },
+  { FRVBF_INSN_CKGT, SEM_FN_NAME (frvbf,ckgt) },
+  { FRVBF_INSN_CKLT, SEM_FN_NAME (frvbf,cklt) },
+  { FRVBF_INSN_CKGE, SEM_FN_NAME (frvbf,ckge) },
+  { FRVBF_INSN_CKLS, SEM_FN_NAME (frvbf,ckls) },
+  { FRVBF_INSN_CKHI, SEM_FN_NAME (frvbf,ckhi) },
+  { FRVBF_INSN_CKC, SEM_FN_NAME (frvbf,ckc) },
+  { FRVBF_INSN_CKNC, SEM_FN_NAME (frvbf,cknc) },
+  { FRVBF_INSN_CKN, SEM_FN_NAME (frvbf,ckn) },
+  { FRVBF_INSN_CKP, SEM_FN_NAME (frvbf,ckp) },
+  { FRVBF_INSN_CKV, SEM_FN_NAME (frvbf,ckv) },
+  { FRVBF_INSN_CKNV, SEM_FN_NAME (frvbf,cknv) },
+  { FRVBF_INSN_FCKRA, SEM_FN_NAME (frvbf,fckra) },
+  { FRVBF_INSN_FCKNO, SEM_FN_NAME (frvbf,fckno) },
+  { FRVBF_INSN_FCKNE, SEM_FN_NAME (frvbf,fckne) },
+  { FRVBF_INSN_FCKEQ, SEM_FN_NAME (frvbf,fckeq) },
+  { FRVBF_INSN_FCKLG, SEM_FN_NAME (frvbf,fcklg) },
+  { FRVBF_INSN_FCKUE, SEM_FN_NAME (frvbf,fckue) },
+  { FRVBF_INSN_FCKUL, SEM_FN_NAME (frvbf,fckul) },
+  { FRVBF_INSN_FCKGE, SEM_FN_NAME (frvbf,fckge) },
+  { FRVBF_INSN_FCKLT, SEM_FN_NAME (frvbf,fcklt) },
+  { FRVBF_INSN_FCKUGE, SEM_FN_NAME (frvbf,fckuge) },
+  { FRVBF_INSN_FCKUG, SEM_FN_NAME (frvbf,fckug) },
+  { FRVBF_INSN_FCKLE, SEM_FN_NAME (frvbf,fckle) },
+  { FRVBF_INSN_FCKGT, SEM_FN_NAME (frvbf,fckgt) },
+  { FRVBF_INSN_FCKULE, SEM_FN_NAME (frvbf,fckule) },
+  { FRVBF_INSN_FCKU, SEM_FN_NAME (frvbf,fcku) },
+  { FRVBF_INSN_FCKO, SEM_FN_NAME (frvbf,fcko) },
+  { FRVBF_INSN_CCKRA, SEM_FN_NAME (frvbf,cckra) },
+  { FRVBF_INSN_CCKNO, SEM_FN_NAME (frvbf,cckno) },
+  { FRVBF_INSN_CCKEQ, SEM_FN_NAME (frvbf,cckeq) },
+  { FRVBF_INSN_CCKNE, SEM_FN_NAME (frvbf,cckne) },
+  { FRVBF_INSN_CCKLE, SEM_FN_NAME (frvbf,cckle) },
+  { FRVBF_INSN_CCKGT, SEM_FN_NAME (frvbf,cckgt) },
+  { FRVBF_INSN_CCKLT, SEM_FN_NAME (frvbf,ccklt) },
+  { FRVBF_INSN_CCKGE, SEM_FN_NAME (frvbf,cckge) },
+  { FRVBF_INSN_CCKLS, SEM_FN_NAME (frvbf,cckls) },
+  { FRVBF_INSN_CCKHI, SEM_FN_NAME (frvbf,cckhi) },
+  { FRVBF_INSN_CCKC, SEM_FN_NAME (frvbf,cckc) },
+  { FRVBF_INSN_CCKNC, SEM_FN_NAME (frvbf,ccknc) },
+  { FRVBF_INSN_CCKN, SEM_FN_NAME (frvbf,cckn) },
+  { FRVBF_INSN_CCKP, SEM_FN_NAME (frvbf,cckp) },
+  { FRVBF_INSN_CCKV, SEM_FN_NAME (frvbf,cckv) },
+  { FRVBF_INSN_CCKNV, SEM_FN_NAME (frvbf,ccknv) },
+  { FRVBF_INSN_CFCKRA, SEM_FN_NAME (frvbf,cfckra) },
+  { FRVBF_INSN_CFCKNO, SEM_FN_NAME (frvbf,cfckno) },
+  { FRVBF_INSN_CFCKNE, SEM_FN_NAME (frvbf,cfckne) },
+  { FRVBF_INSN_CFCKEQ, SEM_FN_NAME (frvbf,cfckeq) },
+  { FRVBF_INSN_CFCKLG, SEM_FN_NAME (frvbf,cfcklg) },
+  { FRVBF_INSN_CFCKUE, SEM_FN_NAME (frvbf,cfckue) },
+  { FRVBF_INSN_CFCKUL, SEM_FN_NAME (frvbf,cfckul) },
+  { FRVBF_INSN_CFCKGE, SEM_FN_NAME (frvbf,cfckge) },
+  { FRVBF_INSN_CFCKLT, SEM_FN_NAME (frvbf,cfcklt) },
+  { FRVBF_INSN_CFCKUGE, SEM_FN_NAME (frvbf,cfckuge) },
+  { FRVBF_INSN_CFCKUG, SEM_FN_NAME (frvbf,cfckug) },
+  { FRVBF_INSN_CFCKLE, SEM_FN_NAME (frvbf,cfckle) },
+  { FRVBF_INSN_CFCKGT, SEM_FN_NAME (frvbf,cfckgt) },
+  { FRVBF_INSN_CFCKULE, SEM_FN_NAME (frvbf,cfckule) },
+  { FRVBF_INSN_CFCKU, SEM_FN_NAME (frvbf,cfcku) },
+  { FRVBF_INSN_CFCKO, SEM_FN_NAME (frvbf,cfcko) },
+  { FRVBF_INSN_CJMPL, SEM_FN_NAME (frvbf,cjmpl) },
+  { FRVBF_INSN_CCALLL, SEM_FN_NAME (frvbf,ccalll) },
+  { FRVBF_INSN_ICI, SEM_FN_NAME (frvbf,ici) },
+  { FRVBF_INSN_DCI, SEM_FN_NAME (frvbf,dci) },
+  { FRVBF_INSN_ICEI, SEM_FN_NAME (frvbf,icei) },
+  { FRVBF_INSN_DCEI, SEM_FN_NAME (frvbf,dcei) },
+  { FRVBF_INSN_DCF, SEM_FN_NAME (frvbf,dcf) },
+  { FRVBF_INSN_DCEF, SEM_FN_NAME (frvbf,dcef) },
+  { FRVBF_INSN_WITLB, SEM_FN_NAME (frvbf,witlb) },
+  { FRVBF_INSN_WDTLB, SEM_FN_NAME (frvbf,wdtlb) },
+  { FRVBF_INSN_ITLBI, SEM_FN_NAME (frvbf,itlbi) },
+  { FRVBF_INSN_DTLBI, SEM_FN_NAME (frvbf,dtlbi) },
+  { FRVBF_INSN_ICPL, SEM_FN_NAME (frvbf,icpl) },
+  { FRVBF_INSN_DCPL, SEM_FN_NAME (frvbf,dcpl) },
+  { FRVBF_INSN_ICUL, SEM_FN_NAME (frvbf,icul) },
+  { FRVBF_INSN_DCUL, SEM_FN_NAME (frvbf,dcul) },
+  { FRVBF_INSN_BAR, SEM_FN_NAME (frvbf,bar) },
+  { FRVBF_INSN_MEMBAR, SEM_FN_NAME (frvbf,membar) },
+  { FRVBF_INSN_COP1, SEM_FN_NAME (frvbf,cop1) },
+  { FRVBF_INSN_COP2, SEM_FN_NAME (frvbf,cop2) },
+  { FRVBF_INSN_CLRGR, SEM_FN_NAME (frvbf,clrgr) },
+  { FRVBF_INSN_CLRFR, SEM_FN_NAME (frvbf,clrfr) },
+  { FRVBF_INSN_CLRGA, SEM_FN_NAME (frvbf,clrga) },
+  { FRVBF_INSN_CLRFA, SEM_FN_NAME (frvbf,clrfa) },
+  { FRVBF_INSN_COMMITGR, SEM_FN_NAME (frvbf,commitgr) },
+  { FRVBF_INSN_COMMITFR, SEM_FN_NAME (frvbf,commitfr) },
+  { FRVBF_INSN_COMMITGA, SEM_FN_NAME (frvbf,commitga) },
+  { FRVBF_INSN_COMMITFA, SEM_FN_NAME (frvbf,commitfa) },
+  { FRVBF_INSN_FITOS, SEM_FN_NAME (frvbf,fitos) },
+  { FRVBF_INSN_FSTOI, SEM_FN_NAME (frvbf,fstoi) },
+  { FRVBF_INSN_FITOD, SEM_FN_NAME (frvbf,fitod) },
+  { FRVBF_INSN_FDTOI, SEM_FN_NAME (frvbf,fdtoi) },
+  { FRVBF_INSN_FDITOS, SEM_FN_NAME (frvbf,fditos) },
+  { FRVBF_INSN_FDSTOI, SEM_FN_NAME (frvbf,fdstoi) },
+  { FRVBF_INSN_NFDITOS, SEM_FN_NAME (frvbf,nfditos) },
+  { FRVBF_INSN_NFDSTOI, SEM_FN_NAME (frvbf,nfdstoi) },
+  { FRVBF_INSN_CFITOS, SEM_FN_NAME (frvbf,cfitos) },
+  { FRVBF_INSN_CFSTOI, SEM_FN_NAME (frvbf,cfstoi) },
+  { FRVBF_INSN_NFITOS, SEM_FN_NAME (frvbf,nfitos) },
+  { FRVBF_INSN_NFSTOI, SEM_FN_NAME (frvbf,nfstoi) },
+  { FRVBF_INSN_FMOVS, SEM_FN_NAME (frvbf,fmovs) },
+  { FRVBF_INSN_FMOVD, SEM_FN_NAME (frvbf,fmovd) },
+  { FRVBF_INSN_FDMOVS, SEM_FN_NAME (frvbf,fdmovs) },
+  { FRVBF_INSN_CFMOVS, SEM_FN_NAME (frvbf,cfmovs) },
+  { FRVBF_INSN_FNEGS, SEM_FN_NAME (frvbf,fnegs) },
+  { FRVBF_INSN_FNEGD, SEM_FN_NAME (frvbf,fnegd) },
+  { FRVBF_INSN_FDNEGS, SEM_FN_NAME (frvbf,fdnegs) },
+  { FRVBF_INSN_CFNEGS, SEM_FN_NAME (frvbf,cfnegs) },
+  { FRVBF_INSN_FABSS, SEM_FN_NAME (frvbf,fabss) },
+  { FRVBF_INSN_FABSD, SEM_FN_NAME (frvbf,fabsd) },
+  { FRVBF_INSN_FDABSS, SEM_FN_NAME (frvbf,fdabss) },
+  { FRVBF_INSN_CFABSS, SEM_FN_NAME (frvbf,cfabss) },
+  { FRVBF_INSN_FSQRTS, SEM_FN_NAME (frvbf,fsqrts) },
+  { FRVBF_INSN_FDSQRTS, SEM_FN_NAME (frvbf,fdsqrts) },
+  { FRVBF_INSN_NFDSQRTS, SEM_FN_NAME (frvbf,nfdsqrts) },
+  { FRVBF_INSN_FSQRTD, SEM_FN_NAME (frvbf,fsqrtd) },
+  { FRVBF_INSN_CFSQRTS, SEM_FN_NAME (frvbf,cfsqrts) },
+  { FRVBF_INSN_NFSQRTS, SEM_FN_NAME (frvbf,nfsqrts) },
+  { FRVBF_INSN_FADDS, SEM_FN_NAME (frvbf,fadds) },
+  { FRVBF_INSN_FSUBS, SEM_FN_NAME (frvbf,fsubs) },
+  { FRVBF_INSN_FMULS, SEM_FN_NAME (frvbf,fmuls) },
+  { FRVBF_INSN_FDIVS, SEM_FN_NAME (frvbf,fdivs) },
+  { FRVBF_INSN_FADDD, SEM_FN_NAME (frvbf,faddd) },
+  { FRVBF_INSN_FSUBD, SEM_FN_NAME (frvbf,fsubd) },
+  { FRVBF_INSN_FMULD, SEM_FN_NAME (frvbf,fmuld) },
+  { FRVBF_INSN_FDIVD, SEM_FN_NAME (frvbf,fdivd) },
+  { FRVBF_INSN_CFADDS, SEM_FN_NAME (frvbf,cfadds) },
+  { FRVBF_INSN_CFSUBS, SEM_FN_NAME (frvbf,cfsubs) },
+  { FRVBF_INSN_CFMULS, SEM_FN_NAME (frvbf,cfmuls) },
+  { FRVBF_INSN_CFDIVS, SEM_FN_NAME (frvbf,cfdivs) },
+  { FRVBF_INSN_NFADDS, SEM_FN_NAME (frvbf,nfadds) },
+  { FRVBF_INSN_NFSUBS, SEM_FN_NAME (frvbf,nfsubs) },
+  { FRVBF_INSN_NFMULS, SEM_FN_NAME (frvbf,nfmuls) },
+  { FRVBF_INSN_NFDIVS, SEM_FN_NAME (frvbf,nfdivs) },
+  { FRVBF_INSN_FCMPS, SEM_FN_NAME (frvbf,fcmps) },
+  { FRVBF_INSN_FCMPD, SEM_FN_NAME (frvbf,fcmpd) },
+  { FRVBF_INSN_CFCMPS, SEM_FN_NAME (frvbf,cfcmps) },
+  { FRVBF_INSN_FDCMPS, SEM_FN_NAME (frvbf,fdcmps) },
+  { FRVBF_INSN_FMADDS, SEM_FN_NAME (frvbf,fmadds) },
+  { FRVBF_INSN_FMSUBS, SEM_FN_NAME (frvbf,fmsubs) },
+  { FRVBF_INSN_FMADDD, SEM_FN_NAME (frvbf,fmaddd) },
+  { FRVBF_INSN_FMSUBD, SEM_FN_NAME (frvbf,fmsubd) },
+  { FRVBF_INSN_FDMADDS, SEM_FN_NAME (frvbf,fdmadds) },
+  { FRVBF_INSN_NFDMADDS, SEM_FN_NAME (frvbf,nfdmadds) },
+  { FRVBF_INSN_CFMADDS, SEM_FN_NAME (frvbf,cfmadds) },
+  { FRVBF_INSN_CFMSUBS, SEM_FN_NAME (frvbf,cfmsubs) },
+  { FRVBF_INSN_NFMADDS, SEM_FN_NAME (frvbf,nfmadds) },
+  { FRVBF_INSN_NFMSUBS, SEM_FN_NAME (frvbf,nfmsubs) },
+  { FRVBF_INSN_FMAS, SEM_FN_NAME (frvbf,fmas) },
+  { FRVBF_INSN_FMSS, SEM_FN_NAME (frvbf,fmss) },
+  { FRVBF_INSN_FDMAS, SEM_FN_NAME (frvbf,fdmas) },
+  { FRVBF_INSN_FDMSS, SEM_FN_NAME (frvbf,fdmss) },
+  { FRVBF_INSN_NFDMAS, SEM_FN_NAME (frvbf,nfdmas) },
+  { FRVBF_INSN_NFDMSS, SEM_FN_NAME (frvbf,nfdmss) },
+  { FRVBF_INSN_CFMAS, SEM_FN_NAME (frvbf,cfmas) },
+  { FRVBF_INSN_CFMSS, SEM_FN_NAME (frvbf,cfmss) },
+  { FRVBF_INSN_FMAD, SEM_FN_NAME (frvbf,fmad) },
+  { FRVBF_INSN_FMSD, SEM_FN_NAME (frvbf,fmsd) },
+  { FRVBF_INSN_NFMAS, SEM_FN_NAME (frvbf,nfmas) },
+  { FRVBF_INSN_NFMSS, SEM_FN_NAME (frvbf,nfmss) },
+  { FRVBF_INSN_FDADDS, SEM_FN_NAME (frvbf,fdadds) },
+  { FRVBF_INSN_FDSUBS, SEM_FN_NAME (frvbf,fdsubs) },
+  { FRVBF_INSN_FDMULS, SEM_FN_NAME (frvbf,fdmuls) },
+  { FRVBF_INSN_FDDIVS, SEM_FN_NAME (frvbf,fddivs) },
+  { FRVBF_INSN_FDSADS, SEM_FN_NAME (frvbf,fdsads) },
+  { FRVBF_INSN_FDMULCS, SEM_FN_NAME (frvbf,fdmulcs) },
+  { FRVBF_INSN_NFDMULCS, SEM_FN_NAME (frvbf,nfdmulcs) },
+  { FRVBF_INSN_NFDADDS, SEM_FN_NAME (frvbf,nfdadds) },
+  { FRVBF_INSN_NFDSUBS, SEM_FN_NAME (frvbf,nfdsubs) },
+  { FRVBF_INSN_NFDMULS, SEM_FN_NAME (frvbf,nfdmuls) },
+  { FRVBF_INSN_NFDDIVS, SEM_FN_NAME (frvbf,nfddivs) },
+  { FRVBF_INSN_NFDSADS, SEM_FN_NAME (frvbf,nfdsads) },
+  { FRVBF_INSN_NFDCMPS, SEM_FN_NAME (frvbf,nfdcmps) },
+  { FRVBF_INSN_MHSETLOS, SEM_FN_NAME (frvbf,mhsetlos) },
+  { FRVBF_INSN_MHSETHIS, SEM_FN_NAME (frvbf,mhsethis) },
+  { FRVBF_INSN_MHDSETS, SEM_FN_NAME (frvbf,mhdsets) },
+  { FRVBF_INSN_MHSETLOH, SEM_FN_NAME (frvbf,mhsetloh) },
+  { FRVBF_INSN_MHSETHIH, SEM_FN_NAME (frvbf,mhsethih) },
+  { FRVBF_INSN_MHDSETH, SEM_FN_NAME (frvbf,mhdseth) },
+  { FRVBF_INSN_MAND, SEM_FN_NAME (frvbf,mand) },
+  { FRVBF_INSN_MOR, SEM_FN_NAME (frvbf,mor) },
+  { FRVBF_INSN_MXOR, SEM_FN_NAME (frvbf,mxor) },
+  { FRVBF_INSN_CMAND, SEM_FN_NAME (frvbf,cmand) },
+  { FRVBF_INSN_CMOR, SEM_FN_NAME (frvbf,cmor) },
+  { FRVBF_INSN_CMXOR, SEM_FN_NAME (frvbf,cmxor) },
+  { FRVBF_INSN_MNOT, SEM_FN_NAME (frvbf,mnot) },
+  { FRVBF_INSN_CMNOT, SEM_FN_NAME (frvbf,cmnot) },
+  { FRVBF_INSN_MROTLI, SEM_FN_NAME (frvbf,mrotli) },
+  { FRVBF_INSN_MROTRI, SEM_FN_NAME (frvbf,mrotri) },
+  { FRVBF_INSN_MWCUT, SEM_FN_NAME (frvbf,mwcut) },
+  { FRVBF_INSN_MWCUTI, SEM_FN_NAME (frvbf,mwcuti) },
+  { FRVBF_INSN_MCUT, SEM_FN_NAME (frvbf,mcut) },
+  { FRVBF_INSN_MCUTI, SEM_FN_NAME (frvbf,mcuti) },
+  { FRVBF_INSN_MCUTSS, SEM_FN_NAME (frvbf,mcutss) },
+  { FRVBF_INSN_MCUTSSI, SEM_FN_NAME (frvbf,mcutssi) },
+  { FRVBF_INSN_MDCUTSSI, SEM_FN_NAME (frvbf,mdcutssi) },
+  { FRVBF_INSN_MAVEH, SEM_FN_NAME (frvbf,maveh) },
+  { FRVBF_INSN_MSLLHI, SEM_FN_NAME (frvbf,msllhi) },
+  { FRVBF_INSN_MSRLHI, SEM_FN_NAME (frvbf,msrlhi) },
+  { FRVBF_INSN_MSRAHI, SEM_FN_NAME (frvbf,msrahi) },
+  { FRVBF_INSN_MDROTLI, SEM_FN_NAME (frvbf,mdrotli) },
+  { FRVBF_INSN_MCPLHI, SEM_FN_NAME (frvbf,mcplhi) },
+  { FRVBF_INSN_MCPLI, SEM_FN_NAME (frvbf,mcpli) },
+  { FRVBF_INSN_MSATHS, SEM_FN_NAME (frvbf,msaths) },
+  { FRVBF_INSN_MQSATHS, SEM_FN_NAME (frvbf,mqsaths) },
+  { FRVBF_INSN_MSATHU, SEM_FN_NAME (frvbf,msathu) },
+  { FRVBF_INSN_MCMPSH, SEM_FN_NAME (frvbf,mcmpsh) },
+  { FRVBF_INSN_MCMPUH, SEM_FN_NAME (frvbf,mcmpuh) },
+  { FRVBF_INSN_MABSHS, SEM_FN_NAME (frvbf,mabshs) },
+  { FRVBF_INSN_MADDHSS, SEM_FN_NAME (frvbf,maddhss) },
+  { FRVBF_INSN_MADDHUS, SEM_FN_NAME (frvbf,maddhus) },
+  { FRVBF_INSN_MSUBHSS, SEM_FN_NAME (frvbf,msubhss) },
+  { FRVBF_INSN_MSUBHUS, SEM_FN_NAME (frvbf,msubhus) },
+  { FRVBF_INSN_CMADDHSS, SEM_FN_NAME (frvbf,cmaddhss) },
+  { FRVBF_INSN_CMADDHUS, SEM_FN_NAME (frvbf,cmaddhus) },
+  { FRVBF_INSN_CMSUBHSS, SEM_FN_NAME (frvbf,cmsubhss) },
+  { FRVBF_INSN_CMSUBHUS, SEM_FN_NAME (frvbf,cmsubhus) },
+  { FRVBF_INSN_MQADDHSS, SEM_FN_NAME (frvbf,mqaddhss) },
+  { FRVBF_INSN_MQADDHUS, SEM_FN_NAME (frvbf,mqaddhus) },
+  { FRVBF_INSN_MQSUBHSS, SEM_FN_NAME (frvbf,mqsubhss) },
+  { FRVBF_INSN_MQSUBHUS, SEM_FN_NAME (frvbf,mqsubhus) },
+  { FRVBF_INSN_CMQADDHSS, SEM_FN_NAME (frvbf,cmqaddhss) },
+  { FRVBF_INSN_CMQADDHUS, SEM_FN_NAME (frvbf,cmqaddhus) },
+  { FRVBF_INSN_CMQSUBHSS, SEM_FN_NAME (frvbf,cmqsubhss) },
+  { FRVBF_INSN_CMQSUBHUS, SEM_FN_NAME (frvbf,cmqsubhus) },
+  { FRVBF_INSN_MADDACCS, SEM_FN_NAME (frvbf,maddaccs) },
+  { FRVBF_INSN_MSUBACCS, SEM_FN_NAME (frvbf,msubaccs) },
+  { FRVBF_INSN_MDADDACCS, SEM_FN_NAME (frvbf,mdaddaccs) },
+  { FRVBF_INSN_MDSUBACCS, SEM_FN_NAME (frvbf,mdsubaccs) },
+  { FRVBF_INSN_MASACCS, SEM_FN_NAME (frvbf,masaccs) },
+  { FRVBF_INSN_MDASACCS, SEM_FN_NAME (frvbf,mdasaccs) },
+  { FRVBF_INSN_MMULHS, SEM_FN_NAME (frvbf,mmulhs) },
+  { FRVBF_INSN_MMULHU, SEM_FN_NAME (frvbf,mmulhu) },
+  { FRVBF_INSN_MMULXHS, SEM_FN_NAME (frvbf,mmulxhs) },
+  { FRVBF_INSN_MMULXHU, SEM_FN_NAME (frvbf,mmulxhu) },
+  { FRVBF_INSN_CMMULHS, SEM_FN_NAME (frvbf,cmmulhs) },
+  { FRVBF_INSN_CMMULHU, SEM_FN_NAME (frvbf,cmmulhu) },
+  { FRVBF_INSN_MQMULHS, SEM_FN_NAME (frvbf,mqmulhs) },
+  { FRVBF_INSN_MQMULHU, SEM_FN_NAME (frvbf,mqmulhu) },
+  { FRVBF_INSN_MQMULXHS, SEM_FN_NAME (frvbf,mqmulxhs) },
+  { FRVBF_INSN_MQMULXHU, SEM_FN_NAME (frvbf,mqmulxhu) },
+  { FRVBF_INSN_CMQMULHS, SEM_FN_NAME (frvbf,cmqmulhs) },
+  { FRVBF_INSN_CMQMULHU, SEM_FN_NAME (frvbf,cmqmulhu) },
+  { FRVBF_INSN_MMACHS, SEM_FN_NAME (frvbf,mmachs) },
+  { FRVBF_INSN_MMACHU, SEM_FN_NAME (frvbf,mmachu) },
+  { FRVBF_INSN_MMRDHS, SEM_FN_NAME (frvbf,mmrdhs) },
+  { FRVBF_INSN_MMRDHU, SEM_FN_NAME (frvbf,mmrdhu) },
+  { FRVBF_INSN_CMMACHS, SEM_FN_NAME (frvbf,cmmachs) },
+  { FRVBF_INSN_CMMACHU, SEM_FN_NAME (frvbf,cmmachu) },
+  { FRVBF_INSN_MQMACHS, SEM_FN_NAME (frvbf,mqmachs) },
+  { FRVBF_INSN_MQMACHU, SEM_FN_NAME (frvbf,mqmachu) },
+  { FRVBF_INSN_CMQMACHS, SEM_FN_NAME (frvbf,cmqmachs) },
+  { FRVBF_INSN_CMQMACHU, SEM_FN_NAME (frvbf,cmqmachu) },
+  { FRVBF_INSN_MQXMACHS, SEM_FN_NAME (frvbf,mqxmachs) },
+  { FRVBF_INSN_MQXMACXHS, SEM_FN_NAME (frvbf,mqxmacxhs) },
+  { FRVBF_INSN_MQMACXHS, SEM_FN_NAME (frvbf,mqmacxhs) },
+  { FRVBF_INSN_MCPXRS, SEM_FN_NAME (frvbf,mcpxrs) },
+  { FRVBF_INSN_MCPXRU, SEM_FN_NAME (frvbf,mcpxru) },
+  { FRVBF_INSN_MCPXIS, SEM_FN_NAME (frvbf,mcpxis) },
+  { FRVBF_INSN_MCPXIU, SEM_FN_NAME (frvbf,mcpxiu) },
+  { FRVBF_INSN_CMCPXRS, SEM_FN_NAME (frvbf,cmcpxrs) },
+  { FRVBF_INSN_CMCPXRU, SEM_FN_NAME (frvbf,cmcpxru) },
+  { FRVBF_INSN_CMCPXIS, SEM_FN_NAME (frvbf,cmcpxis) },
+  { FRVBF_INSN_CMCPXIU, SEM_FN_NAME (frvbf,cmcpxiu) },
+  { FRVBF_INSN_MQCPXRS, SEM_FN_NAME (frvbf,mqcpxrs) },
+  { FRVBF_INSN_MQCPXRU, SEM_FN_NAME (frvbf,mqcpxru) },
+  { FRVBF_INSN_MQCPXIS, SEM_FN_NAME (frvbf,mqcpxis) },
+  { FRVBF_INSN_MQCPXIU, SEM_FN_NAME (frvbf,mqcpxiu) },
+  { FRVBF_INSN_MEXPDHW, SEM_FN_NAME (frvbf,mexpdhw) },
+  { FRVBF_INSN_CMEXPDHW, SEM_FN_NAME (frvbf,cmexpdhw) },
+  { FRVBF_INSN_MEXPDHD, SEM_FN_NAME (frvbf,mexpdhd) },
+  { FRVBF_INSN_CMEXPDHD, SEM_FN_NAME (frvbf,cmexpdhd) },
+  { FRVBF_INSN_MPACKH, SEM_FN_NAME (frvbf,mpackh) },
+  { FRVBF_INSN_MDPACKH, SEM_FN_NAME (frvbf,mdpackh) },
+  { FRVBF_INSN_MUNPACKH, SEM_FN_NAME (frvbf,munpackh) },
+  { FRVBF_INSN_MDUNPACKH, SEM_FN_NAME (frvbf,mdunpackh) },
+  { FRVBF_INSN_MBTOH, SEM_FN_NAME (frvbf,mbtoh) },
+  { FRVBF_INSN_CMBTOH, SEM_FN_NAME (frvbf,cmbtoh) },
+  { FRVBF_INSN_MHTOB, SEM_FN_NAME (frvbf,mhtob) },
+  { FRVBF_INSN_CMHTOB, SEM_FN_NAME (frvbf,cmhtob) },
+  { FRVBF_INSN_MBTOHE, SEM_FN_NAME (frvbf,mbtohe) },
+  { FRVBF_INSN_CMBTOHE, SEM_FN_NAME (frvbf,cmbtohe) },
+  { FRVBF_INSN_MCLRACC, SEM_FN_NAME (frvbf,mclracc) },
+  { FRVBF_INSN_MRDACC, SEM_FN_NAME (frvbf,mrdacc) },
+  { FRVBF_INSN_MRDACCG, SEM_FN_NAME (frvbf,mrdaccg) },
+  { FRVBF_INSN_MWTACC, SEM_FN_NAME (frvbf,mwtacc) },
+  { FRVBF_INSN_MWTACCG, SEM_FN_NAME (frvbf,mwtaccg) },
+  { FRVBF_INSN_MCOP1, SEM_FN_NAME (frvbf,mcop1) },
+  { FRVBF_INSN_MCOP2, SEM_FN_NAME (frvbf,mcop2) },
+  { FRVBF_INSN_FNOP, SEM_FN_NAME (frvbf,fnop) },
+  { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE.  */
+
+void
+SEM_FN_NAME (frvbf,init_idesc_table) (SIM_CPU *current_cpu)
+{
+  IDESC *idesc_table = CPU_IDESC (current_cpu);
+  const struct sem_fn_desc *sf;
+  int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+  for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+    {
+      const CGEN_INSN *insn = idesc_table[sf->index].idata;
+      int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+		     || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+      if (valid_p)
+	idesc_table[sf->index].sem_fast = sf->fn;
+      else
+	idesc_table[sf->index].sem_fast = SEM_FN_NAME (frvbf,x_invalid);
+#else
+      if (valid_p)
+	idesc_table[sf->index].sem_full = sf->fn;
+      else
+	idesc_table[sf->index].sem_full = SEM_FN_NAME (frvbf,x_invalid);
+#endif
+    }
+}
+
diff --git a/sim/frv/sim-if.c b/sim/frv/sim-if.c
new file mode 100644
index 00000000000..f3ffbcc7b0d
--- /dev/null
+++ b/sim/frv/sim-if.c
@@ -0,0 +1,251 @@
+/* Main simulator entry points specific to the FRV.
+   Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+#include "sim-main.h"
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "sim-options.h"
+#include "libiberty.h"
+#include "bfd.h"
+#include "elf-bfd.h"
+
+static void free_state (SIM_DESC);
+static void print_frv_misc_cpu (SIM_CPU *cpu, int verbose);
+
+/* Records simulator descriptor so utilities like frv_dump_regs can be
+   called from gdb.  */
+SIM_DESC current_state;
+
+/* Cover function of sim_state_free to free the cpu buffers as well.  */
+
+static void
+free_state (SIM_DESC sd)
+{
+  if (STATE_MODULES (sd) != NULL)
+    sim_module_uninstall (sd);
+  sim_cpu_free_all (sd);
+  sim_state_free (sd);
+}
+
+/* Create an instance of the simulator.  */
+
+SIM_DESC
+sim_open (kind, callback, abfd, argv)
+     SIM_OPEN_KIND kind;
+     host_callback *callback;
+     bfd *abfd;
+     char **argv;
+{
+  char c;
+  int i;
+  unsigned long elf_flags = 0;
+  SIM_DESC sd = sim_state_alloc (kind, callback);
+
+  /* The cpu data is kept in a separately allocated chunk of memory.  */
+  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: pc is in mach-specific struct */
+  /* FIXME: watchpoints code shouldn't need this */
+  {
+    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+    STATE_WATCHPOINTS (sd)->pc = &(PC);
+    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+  }
+#endif
+
+  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* These options override any module options.
+     Obviously ambiguity should be avoided, however the caller may wish to
+     augment the meaning of an option.  */
+  sim_add_option_table (sd, NULL, frv_options);
+
+  /* getopt will print the error message so we just have to exit if this fails.
+     FIXME: Hmmm...  in the case of gdb we need getopt to call
+     print_filtered.  */
+  if (sim_parse_args (sd, argv) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0
+  /* Allocate a handler for the control registers and other devices
+     if no memory for that range has been allocated by the user.
+     All are allocated in one chunk to keep things from being
+     unnecessarily complicated.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, FRV_DEVICE_ADDR, 1) == 0)
+    sim_core_attach (sd, NULL,
+		     0 /*level*/,
+		     access_read_write,
+		     0 /*space ???*/,
+		     FRV_DEVICE_ADDR, FRV_DEVICE_LEN /*nr_bytes*/,
+		     0 /*modulo*/,
+		     &frv_devices,
+		     NULL /*buffer*/);
+#endif
+
+  /* Allocate core managed memory if none specified by user.
+     Use address 4 here in case the user wanted address 0 unmapped.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
+    sim_do_commandf (sd, "memory region 0,0x%lx", FRV_DEFAULT_MEM_SIZE);
+
+  /* check for/establish the reference program image */
+  if (sim_analyze_program (sd,
+			   (STATE_PROG_ARGV (sd) != NULL
+			    ? *STATE_PROG_ARGV (sd)
+			    : NULL),
+			   abfd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* set machine and architecture correctly instead of defaulting to frv */
+  {
+    bfd *prog_bfd = STATE_PROG_BFD (sd);
+    if (prog_bfd != NULL)
+      {
+	struct elf_backend_data *backend_data;
+
+	if (bfd_get_arch (prog_bfd) != bfd_arch_frv)
+	  {
+	    sim_io_eprintf (sd, "%s: \"%s\" is not a FRV object file\n",
+			    STATE_MY_NAME (sd),
+			    bfd_get_filename (prog_bfd));
+	    free_state (sd);
+	    return 0;
+	  }
+
+	backend_data = get_elf_backend_data (prog_bfd);
+
+	if (backend_data != NULL)
+	  backend_data->elf_backend_object_p (prog_bfd);
+
+	elf_flags = elf_elfheader (prog_bfd)->e_flags;
+      }
+  }
+
+  /* Establish any remaining configuration options.  */
+  if (sim_config (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  if (sim_post_argv_init (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Open a copy of the cpu descriptor table.  */
+  {
+    CGEN_CPU_DESC cd = frv_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+					     CGEN_ENDIAN_BIG);
+    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+      {
+	SIM_CPU *cpu = STATE_CPU (sd, i);
+	CPU_CPU_DESC (cpu) = cd;
+	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
+	CPU_ELF_FLAGS (cpu) = elf_flags;
+      }
+    frv_cgen_init_dis (cd);
+  }
+
+  /* Initialize various cgen things not done by common framework.
+     Must be done after frv_cgen_cpu_open.  */
+  cgen_init (sd);
+
+  /* CPU specific initialization.  */
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+    {
+      SIM_CPU* cpu = STATE_CPU (sd, i);
+      frv_initialize (cpu, sd);
+    }
+
+  /* Store in a global so things like sparc32_dump_regs can be invoked
+     from the gdb command line.  */
+  current_state = sd;
+
+  return sd;
+}
+
+void
+sim_close (sd, quitting)
+     SIM_DESC sd;
+     int quitting;
+{
+  int i;
+  /* Terminate cache support.  */
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+    {
+      SIM_CPU* cpu = STATE_CPU (sd, i);
+      frv_cache_term (CPU_INSN_CACHE (cpu));
+      frv_cache_term (CPU_DATA_CACHE (cpu));
+    }
+
+  frv_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+  sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_create_inferior (sd, abfd, argv, envp)
+     SIM_DESC sd;
+     bfd *abfd;
+     char **argv;
+     char **envp;
+{
+  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+  SIM_ADDR addr;
+
+  if (abfd != NULL)
+    addr = bfd_get_start_address (abfd);
+  else
+    addr = 0;
+  sim_pc_set (current_cpu, addr);
+
+#if 0
+  STATE_ARGV (sd) = sim_copy_argv (argv);
+  STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+
+  return SIM_RC_OK;
+}
+
+void
+sim_do_command (sd, cmd)
+     SIM_DESC sd;
+     char *cmd;
+{ 
+  if (sim_args_command (sd, cmd) != SIM_RC_OK)
+    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+}
diff --git a/sim/frv/sim-main.h b/sim/frv/sim-main.h
new file mode 100644
index 00000000000..927685af029
--- /dev/null
+++ b/sim/frv/sim-main.h
@@ -0,0 +1,139 @@
+/* frv simulator support code
+   Copyright (C) 1998, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* Main header for the frv.  */
+
+#define USING_SIM_BASE_H /* FIXME: quick hack */
+
+struct _sim_cpu; /* FIXME: should be in sim-basics.h */
+typedef struct _sim_cpu SIM_CPU;
+
+/* Set the mask of unsupported traces.  */
+#define WITH_TRACE \
+  (~(TRACE_alu | TRACE_decode | TRACE_memory | TRACE_model | TRACE_fpu \
+     | TRACE_branch | TRACE_debug))
+
+/* sim-basics.h includes config.h but cgen-types.h must be included before
+   sim-basics.h and cgen-types.h needs config.h.  */
+#include "config.h"
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "frv-desc.h"
+#include "frv-opc.h"
+#include "arch.h"
+
+/* These must be defined before sim-base.h.  */
+typedef USI sim_cia;
+
+#define CIA_GET(cpu)     CPU_PC_GET (cpu)
+#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
+
+void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
+#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
+  frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
+
+#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "frv-sim.h"
+#include "cache.h"
+#include "registers.h"
+#include "profile.h"
+
+/* The _sim_cpu struct.  */
+
+struct _sim_cpu {
+  /* sim/common cpu base.  */
+  sim_cpu_base base;
+
+  /* Static parts of cgen.  */
+  CGEN_CPU cgen_cpu;
+
+  /* CPU specific parts go here.
+     Note that in files that don't need to access these pieces WANT_CPU_FOO
+     won't be defined and thus these parts won't appear.  This is ok in the
+     sense that things work.  It is a source of bugs though.
+     One has to of course be careful to not take the size of this
+     struct and no structure members accessed in non-cpu specific files can
+     go after here.  Oh for a better language.  */
+#if defined (WANT_CPU_FRVBF)
+  FRVBF_CPU_DATA cpu_data;
+
+  /* Control information for registers */
+  FRV_REGISTER_CONTROL register_control;
+#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
+
+  FRV_VLIW vliw;
+#define CPU_VLIW(cpu) (& (cpu)->vliw)
+
+  FRV_CACHE insn_cache;
+#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
+
+  FRV_CACHE data_cache;
+#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
+
+  FRV_PROFILE_STATE profile_state;
+#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
+
+  int debug_state;
+#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
+
+  SI load_address;
+#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
+
+  SI load_length;
+#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
+
+  SI load_flag;
+#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
+#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
+
+  SI store_flag;
+#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
+
+  unsigned long elf_flags;
+#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
+#endif /* defined (WANT_CPU_FRVBF) */
+};
+
+/* The sim_state struct.  */
+
+struct sim_state {
+  sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+  CGEN_STATE cgen_state;
+
+  sim_state_base base;
+};
+
+/* Misc.  */
+
+/* Catch address exceptions.  */
+extern SIM_CORE_SIGNAL_FN frv_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+		  (TRANSFER), (ERROR))
+
+/* Default memory size.  */
+#define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */
diff --git a/sim/frv/tconfig.in b/sim/frv/tconfig.in
new file mode 100644
index 00000000000..a53ad23727c
--- /dev/null
+++ b/sim/frv/tconfig.in
@@ -0,0 +1,42 @@
+/* FRV target configuration file.  -*- C -*- */
+
+/* Define this if the simulator can vary the size of memory.
+   See the xxx simulator for an example.
+   This enables the `-m size' option.
+   The memory size is stored in STATE_MEM_SIZE.  */
+/* Not used for FRV since we use the memory module. TODO -- check this  */
+/* #define SIM_HAVE_MEM_SIZE */
+
+/* See sim-hload.c.  We properly handle LMA. -- TODO: check this */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support.  FIXME: revisit.  */
+#define WITH_DEVICES 1
+
+/* FIXME: Revisit.  */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+#endif
+
+#if 0
+/* Enable watchpoints.  */
+#define WITH_WATCHPOINTS 1
+#endif
+
+/* ??? Temporary hack until model support unified.  */
+#define SIM_HAVE_MODEL
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially
+   duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 0
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0x10, 0xf1 }
+#define SIM_BREAKPOINT_SIZE 2
+#endif
+
+/* This is a global setting.  Different cpu families can't mix-n-match -scache
+   and -pbb.  However some cpu families may use -simple while others use
+   one of -scache/-pbb. ???? */
+#define WITH_SCACHE_PBB 0
diff --git a/sim/frv/traps.c b/sim/frv/traps.c
new file mode 100644
index 00000000000..6ab8a2ca8aa
--- /dev/null
+++ b/sim/frv/traps.c
@@ -0,0 +1,931 @@
+/* frv trap support
+   Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU frvbf
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "targ-vals.h"
+#include "cgen-engine.h"
+#include "cgen-par.h"
+#include "sim-fpu.h"
+
+#include "bfd.h"
+#include "libiberty.h"
+
+/* The semantic code invokes this for invalid (unrecognized) instructions.  */
+
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
+{
+  frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+  return vpc;
+}
+
+/* Process an address exception.  */
+
+void
+frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+		  unsigned int map, int nr_bytes, address_word addr,
+		  transfer_type transfer, sim_core_signals sig)
+{
+  if (sig == sim_core_unaligned_signal)
+    {
+      if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+	frv_queue_data_access_error_interrupt (current_cpu, addr);
+      else
+	frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr);
+    }
+
+  frv_term (sd);
+  sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, transfer, sig);
+}
+
+void
+frv_sim_engine_halt_hook (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia)
+{
+  int i;
+  if (current_cpu != NULL)
+    CIA_SET (current_cpu, cia);
+
+  /* Invalidate the insn and data caches of all cpus.  */
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+    {
+      current_cpu = STATE_CPU (sd, i);
+      frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu), 0);
+      frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu), 1);
+    }
+  frv_term (sd);
+}
+
+/* Read/write functions for system call interface.  */
+
+static int
+syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
+		  unsigned long taddr, char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1);
+  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
+}
+
+static int
+syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
+		   unsigned long taddr, const char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0);
+  frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1);
+  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
+}
+
+/* Handle TRA and TIRA insns.  */
+void
+frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  host_callback *cb = STATE_CALLBACK (sd);
+  USI num = ((base + offset) & 0x7f) + 0x80;
+
+#ifdef SIM_HAVE_BREAKPOINTS
+  /* Check for breakpoints "owned" by the simulator first, regardless
+     of --environment.  */
+  if (num == TRAP_BREAKPOINT)
+    {
+      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
+	 it doesn't return.  Otherwise it returns and let's us try.  */
+      sim_handle_breakpoint (sd, current_cpu, pc);
+      /* Fall through.  */
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      frv_queue_software_interrupt (current_cpu, num);
+      return;
+    }
+
+  switch (num)
+    {
+    case TRAP_SYSCALL :
+      {
+	CB_SYSCALL s;
+	CB_SYSCALL_INIT (&s);
+	s.func = GET_H_GR (7);
+	s.arg1 = GET_H_GR (8);
+	s.arg2 = GET_H_GR (9);
+	s.arg3 = GET_H_GR (10);
+
+	if (s.func == TARGET_SYS_exit)
+	  {
+	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
+	  }
+
+	s.p1 = (PTR) sd;
+	s.p2 = (PTR) current_cpu;
+	s.read_mem = syscall_read_mem;
+	s.write_mem = syscall_write_mem;
+	cb_syscall (cb, &s);
+	SET_H_GR (8, s.result);
+	SET_H_GR (9, s.result2);
+	SET_H_GR (10, s.errcode);
+	break;
+      }
+
+    case TRAP_BREAKPOINT:
+      sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+      break;
+
+      /* Add support for dumping registers, either at fixed traps, or all
+	 unknown traps if configured with --enable-sim-trapdump.  */
+    default:
+#if !TRAPDUMP
+      frv_queue_software_interrupt (current_cpu, num);
+      return;
+#endif
+
+#ifdef TRAP_REGDUMP1
+    case TRAP_REGDUMP1:
+#endif
+
+#ifdef TRAP_REGDUMP2
+    case TRAP_REGDUMP2:
+#endif
+
+#if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
+      {
+	char buf[256];
+	int i, j;
+
+	buf[0] = 0;
+	if (STATE_TEXT_SECTION (sd)
+	    && pc >= STATE_TEXT_START (sd)
+	    && pc < STATE_TEXT_END (sd))
+	  {
+	    const char *pc_filename = (const char *)0;
+	    const char *pc_function = (const char *)0;
+	    unsigned int pc_linenum = 0;
+
+	    if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
+				       STATE_TEXT_SECTION (sd),
+				       (struct symbol_cache_entry **) 0,
+				       pc - STATE_TEXT_START (sd),
+				       &pc_filename, &pc_function, &pc_linenum)
+		&& (pc_function || pc_filename))
+	      {
+		char *p = buf+2;
+		buf[0] = ' ';
+		buf[1] = '(';
+		if (pc_function)
+		  {
+		    strcpy (p, pc_function);
+		    p += strlen (p);
+		  }
+		else
+		  {
+		    char *q = (char *) strrchr (pc_filename, '/');
+		    strcpy (p, (q) ? q+1 : pc_filename);
+		    p += strlen (p);
+		  }
+
+		if (pc_linenum)
+		  {
+		    sprintf (p, " line %d", pc_linenum);
+		    p += strlen (p);
+		  }
+
+		p[0] = ')';
+		p[1] = '\0';
+		if ((p+1) - buf > sizeof (buf))
+		  abort ();
+	      }
+	  }
+
+	sim_io_printf (sd,
+		       "\nRegister dump,    pc = 0x%.8x%s, base = %u, offset = %d\n",
+		       (unsigned)pc, buf, (unsigned)base, (int)offset);
+
+	for (i = 0; i < 64; i += 8)
+	  {
+	    long g0 = (long)GET_H_GR (i);
+	    long g1 = (long)GET_H_GR (i+1);
+	    long g2 = (long)GET_H_GR (i+2);
+	    long g3 = (long)GET_H_GR (i+3);
+	    long g4 = (long)GET_H_GR (i+4);
+	    long g5 = (long)GET_H_GR (i+5);
+	    long g6 = (long)GET_H_GR (i+6);
+	    long g7 = (long)GET_H_GR (i+7);
+
+	    if ((g0 | g1 | g2 | g3 | g4 | g5 | g6 | g7) != 0)
+	      sim_io_printf (sd,
+			     "\tgr%02d - gr%02d:   0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
+			     i, i+7, g0, g1, g2, g3, g4, g5, g6, g7);
+	  }
+
+	for (i = 0; i < 64; i += 8)
+	  {
+	    long f0 = (long)GET_H_FR (i);
+	    long f1 = (long)GET_H_FR (i+1);
+	    long f2 = (long)GET_H_FR (i+2);
+	    long f3 = (long)GET_H_FR (i+3);
+	    long f4 = (long)GET_H_FR (i+4);
+	    long f5 = (long)GET_H_FR (i+5);
+	    long f6 = (long)GET_H_FR (i+6);
+	    long f7 = (long)GET_H_FR (i+7);
+
+	    if ((f0 | f1 | f2 | f3 | f4 | f5 | f6 | f7) != 0)
+	      sim_io_printf (sd,
+			     "\tfr%02d - fr%02d:   0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
+			     i, i+7, f0, f1, f2, f3, f4, f5, f6, f7);
+	  }
+
+	sim_io_printf (sd,
+		       "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
+		       (long)GET_H_SPR (272),
+		       (long)GET_H_SPR (273),
+		       (long)GET_H_SPR (256),
+		       (long)GET_H_SPR (263));
+      }
+      break;
+#endif
+    }
+}
+
+/* Handle the MTRAP insn.  */
+void
+frv_mtrap (SIM_CPU *current_cpu)
+{
+  /* Check the status of media exceptions in MSR0.  */
+  SI msr = GET_MSR (0);
+  if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr))
+    frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
+}
+
+/* Handle the BREAK insn.  */
+void
+frv_break (SIM_CPU *current_cpu)
+{
+  IADDR pc;
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+#ifdef SIM_HAVE_BREAKPOINTS
+  /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
+     it doesn't return.  Otherwise it returns and let's us try.  */
+  pc = GET_H_PC ();
+  sim_handle_breakpoint (sd, current_cpu, pc);
+  /* Fall through.  */
+#endif
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    {
+      /* Invalidate the insn cache because the debugger will presumably
+	 replace the breakpoint insn with the real one.  */
+#ifndef SIM_HAVE_BREAKPOINTS
+      pc = GET_H_PC ();
+#endif
+      sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+    }
+
+  frv_queue_break_interrupt (current_cpu);
+}
+
+/* Return from trap.  */
+USI
+frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field)
+{
+  USI new_pc;
+  /* if (normal running mode and debug_field==0
+       PC=PCSR
+       PSR.ET=1
+       PSR.S=PSR.PS
+     else if (debug running mode and debug_field==1)
+       PC=(BPCSR)
+       PSR.ET=BPSR.BET
+       PSR.S=BPSR.BS
+       change to normal running mode
+  */
+  int psr_s = GET_H_PSR_S ();
+  int psr_et = GET_H_PSR_ET ();
+
+  /* Check for exceptions in the priority order listed in the FRV Architecture
+     Volume 2.  */
+  if (! psr_s)
+    {
+      /* Halt if PSR.ET is not set.  See chapter 6 of the LSI.  */
+      if (! psr_et)
+	{
+	  SIM_DESC sd = CPU_STATE (current_cpu);
+	  sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+	}
+
+      /* privileged_instruction interrupt will have already been queued by
+	 frv_detect_insn_access_interrupts.  */
+      new_pc = pc + 4;
+    }
+  else if (psr_et)
+    {
+      /* Halt if PSR.S is set.  See chapter 6 of the LSI.  */
+      if (psr_s)
+	{
+	  SIM_DESC sd = CPU_STATE (current_cpu);
+	  sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+	}
+
+      frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+      new_pc = pc + 4;
+    }
+  else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0)
+    {
+      USI psr = GET_PSR ();
+      /* Return from normal running state.  */
+      new_pc = GET_H_SPR (H_SPR_PCSR);
+      SET_PSR_ET (psr, 1);
+      SET_PSR_S (psr, GET_PSR_PS (psr));
+      sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr);
+    }
+  else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1)
+    {
+      USI psr = GET_PSR ();
+      /* Return from debug state.  */
+      new_pc = GET_H_SPR (H_SPR_BPCSR);
+      SET_PSR_ET (psr, GET_H_BPSR_BET ());
+      SET_PSR_S (psr, GET_H_BPSR_BS ());
+      sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr);
+      CPU_DEBUG_STATE (current_cpu) = 0;
+    }
+  else
+    new_pc = pc + 4;
+
+  return new_pc;
+}
+
+/* Functions for handling non-excepting instruction side effects.  */
+static SI next_available_nesr (SIM_CPU *current_cpu, SI current_index)
+{
+  FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
+  if (control->spr[H_SPR_NECR].implemented)
+    {
+      int limit;
+      USI necr = GET_NECR ();
+
+      /* See if any NESRs are implemented. First need to check the validity of
+	 the NECR.  */
+      if (! GET_NECR_VALID (necr))
+	return NO_NESR;
+
+      limit = GET_NECR_NEN (necr);
+      for (++current_index; current_index < limit; ++current_index)
+	{
+	  SI nesr = GET_NESR (current_index);
+	  if (! GET_NESR_VALID (nesr))
+	    return current_index;
+	}
+    }
+  return NO_NESR;
+}
+
+static SI next_valid_nesr (SIM_CPU *current_cpu, SI current_index)
+{
+  FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
+  if (control->spr[H_SPR_NECR].implemented)
+    {
+      int limit;
+      USI necr = GET_NECR ();
+
+      /* See if any NESRs are implemented. First need to check the validity of
+	 the NECR.  */
+      if (! GET_NECR_VALID (necr))
+	return NO_NESR;
+
+      limit = GET_NECR_NEN (necr);
+      for (++current_index; current_index < limit; ++current_index)
+	{
+	  SI nesr = GET_NESR (current_index);
+	  if (GET_NESR_VALID (nesr))
+	    return current_index;
+	}
+    }
+  return NO_NESR;
+}
+
+BI
+frvbf_check_non_excepting_load (
+  SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index,
+  SI immediate_disp, QI data_size, BI is_float
+)
+{
+  BI rc = 1; /* perform the load.  */
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  int daec = 0;
+  int rec  = 0;
+  int ec   = 0;
+  USI necr;
+  int do_elos;
+  SI NE_flags[2];
+  SI NE_base;
+  SI nesr;
+  SI ne_index;
+  FRV_REGISTER_CONTROL *control;
+
+  SI address = GET_H_GR (base_index);
+  if (disp_index >= 0)
+    address += GET_H_GR (disp_index);
+  else
+    address += immediate_disp;
+
+  /* Check for interrupt factors.  */
+  switch (data_size)
+    {
+    case NESR_UQI_SIZE:
+    case NESR_QI_SIZE:
+      break;
+    case NESR_UHI_SIZE:
+    case NESR_HI_SIZE:
+      if (address & 1)
+	ec = 1;
+      break;
+    case NESR_SI_SIZE:
+      if (address & 3)
+	ec = 1;
+      break;
+    case NESR_DI_SIZE:
+      if (address & 7)
+	ec = 1;
+      if (target_index & 1)
+	rec = 1;
+      break;
+    case NESR_XI_SIZE:
+      if (address & 0xf)
+	ec = 1;
+      if (target_index & 3)
+	rec = 1;
+      break;
+    default:
+      {
+	IADDR pc = GET_H_PC ();
+	sim_engine_abort (sd, current_cpu, pc, 
+			  "check_non_excepting_load: Incorrect data_size\n");
+	break;
+      }
+    }
+
+  control = CPU_REGISTER_CONTROL (current_cpu);
+  if (control->spr[H_SPR_NECR].implemented)
+    {
+      necr = GET_NECR ();
+      do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr);
+    }
+  else
+    do_elos = 0;
+
+  /* NECR, NESR, NEEAR are only implemented for the full frv machine.  */
+  if (do_elos)
+    {
+      ne_index = next_available_nesr (current_cpu, NO_NESR);
+      if (ne_index == NO_NESR)
+	{
+	  IADDR pc = GET_H_PC ();
+	  sim_engine_abort (sd, current_cpu, pc, 
+			    "No available NESR register\n");
+	}
+
+      /* Fill in the basic fields of the NESR.  */
+      nesr = GET_NESR (ne_index);
+      SET_NESR_VALID (nesr);
+      SET_NESR_EAV (nesr);
+      SET_NESR_DRN (nesr, target_index);
+      SET_NESR_SIZE (nesr, data_size);
+      SET_NESR_NEAN (nesr, ne_index);
+      if (is_float)
+	SET_NESR_FR (nesr);
+      else
+	CLEAR_NESR_FR (nesr);
+
+      /* Set the corresponding NEEAR.  */
+      SET_NEEAR (ne_index, address);
+  
+      SET_NESR_DAEC (nesr, 0);
+      SET_NESR_REC (nesr, 0);
+      SET_NESR_EC (nesr, 0);
+    }
+
+  /* Set the NE flag corresponding to the target register if an interrupt
+     factor was detected. 
+     daec is not checked here yet, but is declared for future reference.  */
+  if (is_float)
+    NE_base = H_SPR_FNER0;
+  else
+    NE_base = H_SPR_GNER0;
+
+  GET_NE_FLAGS (NE_flags, NE_base);
+  if (rec)
+    {
+      SET_NE_FLAG (NE_flags, target_index);
+      if (do_elos)
+	SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED);
+    }
+
+  if (ec)
+    {
+      SET_NE_FLAG (NE_flags, target_index);
+      if (do_elos)
+	SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED);
+    }
+
+  if (do_elos)
+    SET_NESR (ne_index, nesr);
+
+  /* If no interrupt factor was detected then set the NE flag on the
+     target register if the NE flag on one of the input registers
+     is already set.  */
+  if (! rec && ! ec && ! daec)
+    {
+      BI ne_flag = GET_NE_FLAG (NE_flags, base_index);
+      if (disp_index >= 0)
+	ne_flag |= GET_NE_FLAG (NE_flags, disp_index);
+      if (ne_flag)
+	{
+	  SET_NE_FLAG (NE_flags, target_index);
+	  rc = 0; /* Do not perform the load.  */
+	}
+      else
+	CLEAR_NE_FLAG (NE_flags, target_index);
+    }
+
+  SET_NE_FLAGS (NE_base, NE_flags);
+
+  return rc; /* perform the load?  */
+}
+
+/* Record state for media exception: media_cr_not_aligned.  */
+void
+frvbf_media_cr_not_aligned (SIM_CPU *current_cpu)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+  /* On the fr400 this generates an illegal_instruction interrupt.  */
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+  else
+    frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
+}
+
+/* Record state for media exception: media_acc_not_aligned.  */
+void
+frvbf_media_acc_not_aligned (SIM_CPU *current_cpu)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+  /* On the fr400 this generates an illegal_instruction interrupt.  */
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+  else
+    frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0);
+}
+
+/* Record state for media exception: media_register_not_aligned.  */
+void
+frvbf_media_register_not_aligned (SIM_CPU *current_cpu)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+  /* On the fr400 this generates an illegal_instruction interrupt.  */
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+    frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+  else
+    frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
+}
+
+/* Record state for media exception: media_overflow.  */
+void
+frvbf_media_overflow (SIM_CPU *current_cpu, int sie)
+{
+  frv_set_mp_exception_registers (current_cpu, MTT_OVERFLOW, sie);
+}
+
+/* Queue a division exception.  */
+enum frv_dtt
+frvbf_division_exception (SIM_CPU *current_cpu, enum frv_dtt dtt,
+			  int target_index, int non_excepting)
+{
+  /* If there was an overflow and it is masked, then record it in
+     ISR.AEXC.  */
+  USI isr = GET_ISR ();
+  if ((dtt & FRV_DTT_OVERFLOW) && GET_ISR_EDE (isr))
+    {
+      dtt &= ~FRV_DTT_OVERFLOW;
+      SET_ISR_AEXC (isr);
+      SET_ISR (isr);
+    }
+  if (dtt != FRV_DTT_NO_EXCEPTION)
+    {
+      if (non_excepting)
+	{
+	  /* Non excepting instruction, simply set the NE flag for the target
+	     register.  */
+	  SI NE_flags[2];
+	  GET_NE_FLAGS (NE_flags, H_SPR_GNER0);
+	  SET_NE_FLAG (NE_flags, target_index);
+	  SET_NE_FLAGS (H_SPR_GNER0, NE_flags);
+	}
+      else
+	frv_queue_division_exception_interrupt (current_cpu, dtt);
+    }
+  return dtt;
+}
+
+void
+frvbf_check_recovering_store (
+  SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float
+)
+{
+  FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+  int reg_ix;
+
+  CPU_RSTR_INVALIDATE(current_cpu) = 0;
+
+  for (reg_ix = next_valid_nesr (current_cpu, NO_NESR);
+       reg_ix != NO_NESR;
+       reg_ix = next_valid_nesr (current_cpu, reg_ix))
+    {
+      if (address == GET_H_SPR (H_SPR_NEEAR0 + reg_ix))
+	{
+	  SI nesr = GET_NESR (reg_ix);
+	  int nesr_drn = GET_NESR_DRN (nesr);
+	  BI nesr_fr = GET_NESR_FR (nesr);
+	  SI remain;
+
+	  /* Invalidate cache block containing this address.
+	     If we need to count cycles, then the cache operation will be
+	     initiated from the model profiling functions.
+	     See frvbf_model_....  */
+	  if (model_insn)
+	    {
+	      CPU_RSTR_INVALIDATE(current_cpu) = 1;
+	      CPU_LOAD_ADDRESS (current_cpu) = address;
+	    }
+	  else
+	    frv_cache_invalidate (cache, address, 1/* flush */);
+
+	  /* Copy the stored value to the register indicated by NESR.DRN.  */
+	  for (remain = size; remain > 0; remain -= 4)
+	    {
+	      SI value;
+
+	      if (is_float)
+		value = GET_H_FR (regno);
+	      else
+		value = GET_H_GR (regno);
+
+	      switch (size)
+		{
+		case 1:
+		  value &= 0xff;
+		  break;
+		case 2:
+		  value &= 0xffff;
+		  break;
+		default:
+		  break;
+		}
+
+	      if (nesr_fr)
+		sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, nesr_drn,
+				       value);
+	      else
+		sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, nesr_drn,
+				       value);
+
+	      nesr_drn++;
+	      regno++;
+	    }
+	  break; /* Only consider the first matching register.  */
+	}
+    } /* loop over active neear registers.  */
+}
+
+static void
+clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float)
+{
+  int reg_ix;
+
+  /* Only implemented for full frv.  */
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_frv)
+    return;
+
+  /* Clear the appropriate NESR and NEEAR registers.  */
+  for (reg_ix = next_valid_nesr (current_cpu, NO_NESR);
+       reg_ix != NO_NESR;
+       reg_ix = next_valid_nesr (current_cpu, reg_ix))
+    {
+      SI nesr;
+      /* The register is available, now check if it is active.  */
+      nesr = GET_NESR (reg_ix);
+      if (GET_NESR_FR (nesr) == is_float)
+	{
+	  if (target_index < 0 || GET_NESR_DRN (nesr) == target_index)
+	    {
+	      SET_NESR (reg_ix, 0);
+	      SET_NEEAR (reg_ix, 0);
+	    }
+	}
+    }
+}
+
+static void
+clear_ne_flags (
+  SIM_CPU *current_cpu,
+  SI target_index,
+  int hi_available,
+  int lo_available,
+  SI NE_base
+)
+{
+  SI NE_flags[2];
+  int exception;
+
+  GET_NE_FLAGS (NE_flags, NE_base);
+  if (target_index >= 0)
+    CLEAR_NE_FLAG (NE_flags, target_index);
+  else
+    {
+      if (lo_available)
+	NE_flags[1] = 0;
+      if (hi_available)
+	NE_flags[0] = 0;
+    }
+  SET_NE_FLAGS (NE_base, NE_flags);
+}
+
+/* Return 1 if the given register is available, 0 otherwise.  TARGET_INDEX==-1
+   means to check for any register available.  */
+static void
+which_registers_available (
+  SIM_CPU *current_cpu, int *hi_available, int *lo_available, int is_float
+)
+{
+  if (is_float)
+    frv_fr_registers_available (current_cpu, hi_available, lo_available);
+  else
+    frv_gr_registers_available (current_cpu, hi_available, lo_available);
+}
+
+void
+frvbf_clear_ne_flags (SIM_CPU *current_cpu, SI target_index, BI is_float)
+{
+  int hi_available;
+  int lo_available;
+  int exception;
+  SI NE_base;
+  USI necr;
+  FRV_REGISTER_CONTROL *control;
+
+  /* Check for availability of the target register(s).  */
+  which_registers_available (current_cpu, & hi_available, & lo_available,
+			     is_float);
+
+  /* Check to make sure that the target register is available.  */
+  if (! frv_check_register_access (current_cpu, target_index,
+				   hi_available, lo_available))
+    return;
+
+  /* Determine whether we're working with GR or FR registers.  */
+  if (is_float)
+    NE_base = H_SPR_FNER0;
+  else
+    NE_base = H_SPR_GNER0;
+
+  /* Always clear the appropriate NE flags.  */
+  clear_ne_flags (current_cpu, target_index, hi_available, lo_available,
+		  NE_base);
+
+  /* Clear the appropriate NESR and NEEAR registers.  */
+  control = CPU_REGISTER_CONTROL (current_cpu);
+  if (control->spr[H_SPR_NECR].implemented)
+    {
+      necr = GET_NECR ();
+      if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr))
+	clear_nesr_neear (current_cpu, target_index, is_float);
+    }
+}
+
+void
+frvbf_commit (SIM_CPU *current_cpu, SI target_index, BI is_float)
+{
+  SI NE_base;
+  SI NE_flags[2];
+  BI NE_flag;
+  int exception;
+  int hi_available;
+  int lo_available;
+  USI necr;
+  FRV_REGISTER_CONTROL *control;
+
+  /* Check for availability of the target register(s).  */
+  which_registers_available (current_cpu, & hi_available, & lo_available,
+			     is_float);
+
+  /* Check to make sure that the target register is available.  */
+  if (! frv_check_register_access (current_cpu, target_index,
+				   hi_available, lo_available))
+    return;
+
+  /* Determine whether we're working with GR or FR registers.  */
+  if (is_float)
+    NE_base = H_SPR_FNER0;
+  else
+    NE_base = H_SPR_GNER0;
+
+  /* Determine whether a ne exception is pending.  */
+  GET_NE_FLAGS (NE_flags, NE_base);
+  if (target_index >= 0)
+    NE_flag = GET_NE_FLAG (NE_flags, target_index);
+  else
+    {
+      NE_flag =
+	hi_available && NE_flags[0] != 0 || lo_available && NE_flags[1] != 0;
+    }
+
+  /* Always clear the appropriate NE flags.  */
+  clear_ne_flags (current_cpu, target_index, hi_available, lo_available,
+		  NE_base);
+
+  control = CPU_REGISTER_CONTROL (current_cpu);
+  if (control->spr[H_SPR_NECR].implemented)
+    {
+      necr = GET_NECR ();
+      if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr) && NE_flag)
+	{
+	  /* Clear the appropriate NESR and NEEAR registers.  */
+	  clear_nesr_neear (current_cpu, target_index, is_float);
+	  frv_queue_program_interrupt (current_cpu, FRV_COMMIT_EXCEPTION);
+	}
+    }
+}
+
+/* Generate the appropriate fp_exception(s) based on the given status code.  */
+void
+frvbf_fpu_error (CGEN_FPU* fpu, int status)
+{
+  struct frv_fp_exception_info fp_info = {
+    FSR_NO_EXCEPTION, FTT_IEEE_754_EXCEPTION
+  };
+
+  if (status &
+      (sim_fpu_status_invalid_snan |
+       sim_fpu_status_invalid_qnan |
+       sim_fpu_status_invalid_isi |
+       sim_fpu_status_invalid_idi |
+       sim_fpu_status_invalid_zdz |
+       sim_fpu_status_invalid_imz |
+       sim_fpu_status_invalid_cvi |
+       sim_fpu_status_invalid_cmp |
+       sim_fpu_status_invalid_sqrt))
+    fp_info.fsr_mask |= FSR_INVALID_OPERATION;
+
+  if (status & sim_fpu_status_invalid_div0)
+    fp_info.fsr_mask |= FSR_DIVISION_BY_ZERO;
+
+  if (status & sim_fpu_status_inexact)
+    fp_info.fsr_mask |= FSR_INEXACT;
+
+  if (status & sim_fpu_status_overflow)
+    fp_info.fsr_mask |= FSR_OVERFLOW;
+
+  if (status & sim_fpu_status_underflow)
+    fp_info.fsr_mask |= FSR_UNDERFLOW;
+
+  if (status & sim_fpu_status_denorm)
+    {
+      fp_info.fsr_mask |= FSR_DENORMAL_INPUT;
+      fp_info.ftt = FTT_DENORMAL_INPUT;
+    }
+
+  if (fp_info.fsr_mask != FSR_NO_EXCEPTION)
+    {
+      SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner;
+      frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
+    }
+}