im/mips/ChangeLog ]

2004-04-10  Chris Demetriou  <cgd@broadcom.com>

        * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.

[ sim/testsuite/sim/mips/ChangeLog ]
2004-04-10  Chris Demetriou  <cgd@broadcom.com>

        * fpu64-ps-sb1.s: New file.
        * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s
        if appropriate.

5 files changed, 137 insertions, 1 deletions

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 0c4fd8a017e..53dc86c3173 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,7 @@
+2004-04-10  Chris Demetriou  <cgd@broadcom.com>
+
+	* sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
+
 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 
 	* mips.igen (check_fmt): Remove.
diff --git a/sim/mips/sb1.igen b/sim/mips/sb1.igen
index 7a718c736be..b6534cb9bcd 100644
--- a/sim/mips/sb1.igen
+++ b/sim/mips/sb1.igen
@@ -192,3 +192,53 @@
   check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
   StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
 }
+
+
+//  Paired-Single Extension Instructions
+//  ------------------------------------
+//
+//  The SB-1 implements several .PS format instructions that are
+//  extensions to the MIPS64 architecture.
+
+010001,10,3.FMT=6,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.PS
+"div.%s<FMT> f<FD>, f<FS>, f<FT>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
+}
+
+
+010001,10,3.FMT=6,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.PS
+"recip.%s<FMT> f<FD>, f<FS>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
+}
+
+
+010001,10,3.FMT=6,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.PS
+"rsqrt.%s<FMT> f<FD>, f<FS>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
+}
+
+
+010001,10,3.FMT=6,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.PS
+"sqrt.%s<FMT> f<FD>, f<FS>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
+}
diff --git a/sim/testsuite/sim/mips/ChangeLog b/sim/testsuite/sim/mips/ChangeLog
index 3bec86b573a..4712274c2bf 100644
--- a/sim/testsuite/sim/mips/ChangeLog
+++ b/sim/testsuite/sim/mips/ChangeLog
@@ -1,5 +1,11 @@
 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 
+	* fpu64-ps-sb1.s: New file.
+	* basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s
+	if appropriate.
+
+2004-04-10  Chris Demetriou  <cgd@broadcom.com>
+
 	* fpu64-ps.s: New file.
 	* basic.exp: Run fpu64-ps.s.
 
diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp
index ac5d405b3b4..6fb64be5dcc 100644
--- a/sim/testsuite/sim/mips/basic.exp
+++ b/sim/testsuite/sim/mips/basic.exp
@@ -36,7 +36,10 @@ proc run_hilo_test {testfile models nops} {
 # board really is a simulator (sim tests don't work on real HW).
 if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
 
-    if {[istarget mipsisa64*-elf]} {
+    if {[istarget mipsisa64sb1*-elf]} {
+	set models "sb1"
+	set submodels "mips1 mips2 mips3 mips4 mips32 mips64"
+    } elseif {[istarget mipsisa64*-elf]} {
 	set models "mips32 mips64"
 	set submodels "mips1 mips2 mips3 mips4"
     } elseif {[istarget mipsisa32*-elf]} {
@@ -64,4 +67,5 @@ if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
     run_hilo_test hilo-hazard-3.s $models 2
 
     run_sim_test fpu64-ps.s $submodels
+    run_sim_test fpu64-ps-sb1.s $submodels
 }
diff --git a/sim/testsuite/sim/mips/fpu64-ps-sb1.s b/sim/testsuite/sim/mips/fpu64-ps-sb1.s
new file mode 100644
index 00000000000..a39d0799c0d
--- /dev/null
+++ b/sim/testsuite/sim/mips/fpu64-ps-sb1.s
@@ -0,0 +1,72 @@
+# mips test sanity, expected to pass.
+# mach:	 sb1
+# as:		-mabi=eabi
+# ld:		-N -Ttext=0x80010000
+# output:	*\\npass\\n
+
+	.include "testutils.inc"
+
+        .macro check_ps psval, upperval, lowerval
+	.set push
+	.set noreorder
+	cvt.s.pu	$f0, \psval		# upper
+	cvt.s.pl	$f2, \psval		# lower
+	li.s		$f4, \upperval
+	li.s		$f6, \lowerval
+	c.eq.s		$fcc0, $f0, $f4
+	bc1f		$fcc0, _fail
+	 c.eq.s		$fcc0, $f2, $f6
+	bc1f		$fcc0, _fail
+	 nop
+	.set pop
+        .endm
+
+	setup
+
+	.set noreorder
+
+	.ent DIAG
+DIAG:
+
+	# make sure that Status.FR, .CU1, and .SBX are set.
+	mfc0	$2, $12
+	or	$2, $2, (1 << 26) | (1 << 29) | (1 << 16)
+	mtc0	$2, $12
+
+
+	li.s	$f10, 4.0
+	li.s	$f12, 16.0
+	cvt.ps.s $f20, $f10, $f12		# $f20: u=4.0, l=16.0
+
+	li.s	$f10, -1.0
+	li.s	$f12, 2.0
+	cvt.ps.s $f22, $f10, $f12		# $f22: u=-1.0, l=2.0
+
+
+	writemsg "div.ps"
+
+	div.ps $f8, $f20, $f22
+	check_ps $f8, -4.0, 8.0
+
+
+	writemsg "recip.ps"
+
+	recip.ps $f8, $f20
+	check_ps $f8, 0.25, 0.0625
+
+
+	writemsg "rsqrt.ps"
+
+	rsqrt.ps $f8, $f20
+	check_ps $f8, 0.5, 0.25
+
+
+	writemsg "sqrt.ps"
+
+	sqrt.ps $f8, $f20
+	check_ps $f8, 2.0, 4.0
+
+
+	pass
+
+	.end DIAG