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authorMichael Snyder <msnyder@specifix.com>2003-07-23 21:17:33 +0000
committerMichael Snyder <msnyder@specifix.com>2003-07-23 21:17:33 +0000
commit8c78862fc534ad220615e5a1cbb0f8cb08dac0f5 (patch)
tree219d308b7e3e021172d44f5f0344e6bb9aae9b6e /sim
parent99878f41a46997e8159a964f83ee647deecc835f (diff)
downloadgdb-8c78862fc534ad220615e5a1cbb0f8cb08dac0f5.tar.gz
2003-06-27 Michael Snyder <msnyder@redhat.com>
* gencode.c (op movsxy_tab): Fix an error in the bit pattern.
Diffstat (limited to 'sim')
-rw-r--r--sim/sh/ChangeLog1
-rw-r--r--sim/sh/gencode.c2
2 files changed, 2 insertions, 1 deletions
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index 0cd05f52f69..ad4bd8fcfa0 100644
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -4,6 +4,7 @@
2003-06-27 Michael Snyder <msnyder@redhat.com>
+ * gencode.c (op movsxy_tab): Fix an error in the bit pattern.
* gencode.c (gensim_caselist): The movy instructions use
registers R6 and R7 (not R4 and R5 like the movx insns).
diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index e5dee8f987b..e8e780fec9f 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -1259,7 +1259,7 @@ op movsxy_tab[] =
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
"iword &= 0xfd53; goto top;",
},
- { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101000",
+ { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101100",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
"iword &= 0xfd53; goto top;",