diff options
| author | Chris Demetriou <cgd@google.com> | 2002-06-07 16:43:19 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-06-07 16:43:19 +0000 |
| commit | adabc33b577f9475f91d3175055aa33497462c7c (patch) | |
| tree | ada82f3795fd17278e7fd8ba3e30734f5aca8827 /sim | |
| parent | 62e8b8bcdd5eef5e2328bf6e139f6c80793cd9f1 (diff) | |
| download | gdb-adabc33b577f9475f91d3175055aa33497462c7c.tar.gz | |
2002-06-07 Chris Demetriou <cgd@broadcom.com>
* cp1.c: Clean up formatting of a few comments.
(value_fpr): Reformat switch statement.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mips/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/mips/cp1.c | 28 |
2 files changed, 12 insertions, 21 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index dff7b807072..0afcde95552 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,8 @@ +2002-06-07 Chris Demetriou <cgd@broadcom.com> + + * cp1.c: Clean up formatting of a few comments. + (value_fpr): Reformat switch statement. + 2002-06-06 Chris Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c index 3641df7fc95..e4bfba2b028 100644 --- a/sim/mips/cp1.c +++ b/sim/mips/cp1.c @@ -127,25 +127,11 @@ value_fpr (sim_cpu *cpu, /* Set QNaN value: */ switch (fmt) { - case fmt_single: - value = FPQNaN_SINGLE; - break; - - case fmt_double: - value = FPQNaN_DOUBLE; - break; - - case fmt_word: - value = FPQNaN_WORD; - break; - - case fmt_long: - value = FPQNaN_LONG; - break; - - default: - err = -1; - break; + case fmt_single: value = FPQNaN_SINGLE; break; + case fmt_double: value = FPQNaN_DOUBLE; break; + case fmt_word: value = FPQNaN_WORD; break; + case fmt_long: value = FPQNaN_LONG; break; + default: err = -1; break; } } else if (SizeFGR () == 64) @@ -182,7 +168,7 @@ value_fpr (sim_cpu *cpu, case fmt_long: if ((fpr & 1) == 0) { - /* even registers only */ + /* Even registers numbers only. */ #ifdef DEBUG printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n", fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]), @@ -280,7 +266,7 @@ store_fpr (sim_cpu *cpu, case fmt_long: if ((fpr & 1) == 0) { - /* even register number only */ + /* Even register numbers only. */ FGR[fpr+1] = (value >> 32); FGR[fpr] = (value & 0xFFFFFFFF); FPR_STATE[fpr + 1] = fmt; |