Initial revision

2 files changed, 318 insertions, 0 deletions

diff --git a/sim/common/cgen-par.c b/sim/common/cgen-par.c
new file mode 100644
index 00000000000..8b983fbe4c0
--- /dev/null
+++ b/sim/common/cgen-par.c
@@ -0,0 +1,194 @@
+/* Simulator parallel routines for CGEN simulators (and maybe others).
+   Copyright (C) 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU instruction set simulator.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-par.h"
+
+/* Functions required by the cgen interface.  These functions add various
+   kinds of writes to the write queue.  */
+void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_QI_WRITE;
+  element->kinds.qi_write.target = target;
+  element->kinds.qi_write.value  = value;
+}
+
+void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_SI_WRITE;
+  element->kinds.si_write.target = target;
+  element->kinds.si_write.value  = value;
+}
+
+void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_SF_WRITE;
+  element->kinds.sf_write.target = target;
+  element->kinds.sf_write.value  = value;
+}
+
+void sim_queue_pc_write (SIM_CPU *cpu, USI value)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_PC_WRITE;
+  element->kinds.pc_write.value = value;
+}
+
+void sim_queue_fn_si_write (
+  SIM_CPU *cpu,
+  void (*write_function)(SIM_CPU *cpu, UINT, USI),
+  UINT regno,
+  SI value
+)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_FN_SI_WRITE;
+  element->kinds.fn_si_write.function = write_function;
+  element->kinds.fn_si_write.regno = regno;
+  element->kinds.fn_si_write.value = value;
+}
+
+void sim_queue_fn_di_write (
+  SIM_CPU *cpu,
+  void (*write_function)(SIM_CPU *cpu, UINT, DI),
+  UINT regno,
+  DI value
+)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_FN_DI_WRITE;
+  element->kinds.fn_di_write.function = write_function;
+  element->kinds.fn_di_write.regno = regno;
+  element->kinds.fn_di_write.value = value;
+}
+
+void sim_queue_fn_df_write (
+  SIM_CPU *cpu,
+  void (*write_function)(SIM_CPU *cpu, UINT, DI),
+  UINT regno,
+  DF value
+)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_FN_DF_WRITE;
+  element->kinds.fn_df_write.function = write_function;
+  element->kinds.fn_df_write.regno = regno;
+  element->kinds.fn_df_write.value = value;
+}
+
+void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_MEM_QI_WRITE;
+  element->kinds.mem_qi_write.address = address;
+  element->kinds.mem_qi_write.value   = value;
+}
+
+void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_MEM_HI_WRITE;
+  element->kinds.mem_hi_write.address = address;
+  element->kinds.mem_hi_write.value   = value;
+}
+
+void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
+{
+  CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+  CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+  element->kind = CGEN_MEM_SI_WRITE;
+  element->kinds.mem_si_write.address = address;
+  element->kinds.mem_si_write.value   = value;
+}
+
+/* Execute a write stored on the write queue.  */
+void
+cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
+{
+  IADDR pc;
+  switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
+    {
+    case CGEN_QI_WRITE:
+      *item->kinds.qi_write.target = item->kinds.qi_write.value;
+      break;
+    case CGEN_SI_WRITE:
+      *item->kinds.si_write.target = item->kinds.si_write.value;
+      break;
+    case CGEN_SF_WRITE:
+      *item->kinds.sf_write.target = item->kinds.sf_write.value;
+      break;
+    case CGEN_PC_WRITE:
+      CPU_PC_SET (cpu, item->kinds.pc_write.value);
+      break;
+    case CGEN_FN_SI_WRITE:
+      item->kinds.fn_si_write.function (cpu,
+					item->kinds.fn_si_write.regno,
+					item->kinds.fn_si_write.value);
+      break;
+    case CGEN_FN_DI_WRITE:
+      item->kinds.fn_di_write.function (cpu,
+					item->kinds.fn_di_write.regno,
+					item->kinds.fn_di_write.value);
+      break;
+    case CGEN_FN_DF_WRITE:
+      item->kinds.fn_df_write.function (cpu,
+					item->kinds.fn_df_write.regno,
+					item->kinds.fn_df_write.value);
+      break;
+    case CGEN_MEM_QI_WRITE:
+      pc = CPU_PC_GET (cpu);
+      SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
+		item->kinds.mem_qi_write.value);
+      break;
+    case CGEN_MEM_HI_WRITE:
+      pc = CPU_PC_GET (cpu);
+      SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
+		item->kinds.mem_hi_write.value);
+      break;
+    case CGEN_MEM_SI_WRITE:
+      pc = CPU_PC_GET (cpu);
+      SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
+		item->kinds.mem_si_write.value);
+      break;
+    default:
+      break; /* FIXME: for now....print message later.  */
+    }
+}
+
+/* Utilities for the write queue.  */
+CGEN_WRITE_QUEUE_ELEMENT *
+cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
+{
+  abort (); /* FIXME: for now....print message later.  */
+  return 0;
+}
diff --git a/sim/common/cgen-par.h b/sim/common/cgen-par.h
new file mode 100644
index 00000000000..ce4efd59307
--- /dev/null
+++ b/sim/common/cgen-par.h
@@ -0,0 +1,124 @@
+/* Simulator header for cgen parallel support.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU instruction set simulator.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef CGEN_PAR_H
+#define CGEN_PAR_H
+
+/* Kinds of writes stored on the write queue.  */
+enum cgen_write_queue_kind {
+  CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
+  CGEN_PC_WRITE,
+  CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
+  CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
+  CGEN_NUM_WRITE_KINDS
+};
+
+/* Element of the write queue.  */
+typedef struct {
+  enum cgen_write_queue_kind kind; /* Used to select union member below.  */
+  union {
+    struct {
+      UQI *target;
+      QI   value;
+    } qi_write;
+    struct {
+      SI *target;
+      SI  value;
+    } si_write;
+    struct {
+      SI *target;
+      SF  value;
+    } sf_write;
+    struct {
+      USI value;
+    } pc_write;
+    struct {
+      UINT regno;
+      SI   value;
+      void (*function)(SIM_CPU *, UINT, USI);
+    } fn_si_write;
+    struct {
+      UINT regno;
+      DI   value;
+      void (*function)(SIM_CPU *, UINT, DI);
+    } fn_di_write;
+    struct {
+      UINT regno;
+      DI   value;
+      void (*function)(SIM_CPU *, UINT, DI);
+    } fn_df_write;
+    struct {
+      SI   address;
+      QI   value;
+    } mem_qi_write;
+    struct {
+      SI   address;
+      HI   value;
+    } mem_hi_write;
+    struct {
+      SI   address;
+      SI   value;
+    } mem_si_write;
+  } kinds;
+} CGEN_WRITE_QUEUE_ELEMENT;
+
+#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
+
+extern void cgen_write_queue_element_execute (
+  SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
+);
+
+/* Instance of the queue for parallel write-after support.  */
+/* FIXME: Should be dynamic?  */
+#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now.  */
+
+typedef struct {
+  int index;
+  CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
+} CGEN_WRITE_QUEUE;
+
+#define CGEN_WRITE_QUEUE_CLEAR(queue)       ((queue)->index = 0)
+#define CGEN_WRITE_QUEUE_INDEX(queue)       ((queue)->index)
+#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
+
+#define CGEN_WRITE_QUEUE_NEXT(queue) (   \
+  (queue)->index < CGEN_WRITE_QUEUE_SIZE \
+    ? &(queue)->q[(queue)->index++]      \
+    : cgen_write_queue_overflow (queue)  \
+)
+
+extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
+
+/* Functions for queuing writes.  Used by semantic code.  */
+extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
+extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
+extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
+
+extern void sim_queue_pc_write (SIM_CPU *, USI);
+
+extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
+extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
+extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);
+
+extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
+extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
+extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
+
+#endif /* CGEN_PAR_H */