diff options
| -rw-r--r-- | bfd/ChangeLog | 7 | ||||
| -rw-r--r-- | bfd/archures.c | 3 | ||||
| -rw-r--r-- | bfd/bfd-in2.h | 1 | ||||
| -rw-r--r-- | bfd/cpu-sh.c | 19 | ||||
| -rw-r--r-- | bfd/elf32-sh.c | 5 | ||||
| -rw-r--r-- | include/elf/ChangeLog | 4 | ||||
| -rw-r--r-- | include/elf/sh.h | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/sh-dis.c | 9 | ||||
| -rw-r--r-- | opcodes/sh-opc.h | 38 |
10 files changed, 75 insertions, 21 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index ecbeaba7c7b..83c4f4135d6 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,10 @@ +2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com> + + * archures.c: Add bfd_mach_sh4_nommu_nofpu. + * cpu-sh.c: Ditto. + * elf32-sh.c: Ditto. + * bfd-in2.h: Regenerate. + 2004-03-02 Alexandre Oliva <aoliva@redhat.com> * elf32-frv.c (struct frv_pic_relocs_info): Added fixups and diff --git a/bfd/archures.c b/bfd/archures.c index 1f31b5d4fe5..0e2a08b831f 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -1,6 +1,6 @@ /* BFD library support routines for architectures. Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003 + 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Hacked by John Gilmore and Steve Chamberlain of Cygnus Support. @@ -230,6 +230,7 @@ DESCRIPTION .#define bfd_mach_sh3e 0x3e .#define bfd_mach_sh4 0x40 .#define bfd_mach_sh4_nofpu 0x41 +.#define bfd_mach_sh4_nommu_nofpu 0x42 .#define bfd_mach_sh4a 0x4a .#define bfd_mach_sh4a_nofpu 0x4b .#define bfd_mach_sh4al_dsp 0x4d diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index a56a5eee80e..5963bb4e35c 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1662,6 +1662,7 @@ enum bfd_architecture #define bfd_mach_sh3e 0x3e #define bfd_mach_sh4 0x40 #define bfd_mach_sh4_nofpu 0x41 +#define bfd_mach_sh4_nommu_nofpu 0x42 #define bfd_mach_sh4a 0x4a #define bfd_mach_sh4a_nofpu 0x4b #define bfd_mach_sh4al_dsp 0x4d diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c index 2f33240bb07..be359df7090 100644 --- a/bfd/cpu-sh.c +++ b/bfd/cpu-sh.c @@ -1,5 +1,5 @@ /* BFD library support routines for the Renesas / SuperH SH architecture. - Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003 + Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Hacked by Steve Chamberlain of Cygnus Support. @@ -34,7 +34,8 @@ #define SH4A_NEXT &arch_info_struct[8] #define SH4AL_DSP_NEXT &arch_info_struct[9] #define SH4_NOFPU_NEXT &arch_info_struct[10] -#define SH4A_NOFPU_NEXT &arch_info_struct[11] +#define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[11] +#define SH4A_NOFPU_NEXT &arch_info_struct[12] #define SH64_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = @@ -184,6 +185,20 @@ static const bfd_arch_info_type arch_info_struct[] = 32, /* 32 bits in an address */ 8, /* 8 bits in a byte */ bfd_arch_sh, + bfd_mach_sh4_nommu_nofpu, + "sh", /* arch_name */ + "sh4-nommu-nofpu", /* printable name */ + 1, + FALSE, /* not the default */ + bfd_default_compatible, + bfd_default_scan, + SH4_NOMMU_NOFPU_NEXT + }, + { + 32, /* 32 bits in a word */ + 32, /* 32 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_sh, bfd_mach_sh4a_nofpu, "sh", /* arch_name */ "sh4a-nofpu", /* printable name */ diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c index c8a091d53ce..5ab56bcc141 100644 --- a/bfd/elf32-sh.c +++ b/bfd/elf32-sh.c @@ -1,5 +1,5 @@ /* Renesas / SuperH SH specific support for 32-bit ELF - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Ian Lance Taylor, Cygnus Support. @@ -6876,6 +6876,9 @@ sh_elf_set_mach_from_flags (bfd *abfd) case EF_SH4AL_DSP: bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4al_dsp); break; + case EF_SH4_NOMMU_NOFPU: + bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4_nommu_nofpu); + break; default: return FALSE; } diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 707a1ab17bf..6e4d604b2d0 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com> + + * sh.h: Add EF_SH4_NOMMU_NOFPU. + 2004-03-01 Richard Sandiford <rsandifo@redhat.com> * frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define. diff --git a/include/elf/sh.h b/include/elf/sh.h index 15d460d36b4..c46a5ff149f 100644 --- a/include/elf/sh.h +++ b/include/elf/sh.h @@ -1,5 +1,5 @@ /* SH ELF support for BFD. - Copyright 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Copyright 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -39,6 +39,7 @@ #define EF_SH4_NOFPU 0x10 #define EF_SH4A_NOFPU 0x11 +#define EF_SH4_NOMMU_NOFPU 0x12 /* This one can only mix in objects from other EF_SH5 objects. */ #define EF_SH5 10 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ba441c10217..0a1498be757 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com> + + * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in + nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu. + * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions + accordingly. + 2004-03-01 Richard Sandiford <rsandifo@redhat.com> * frv-asm.c: Regenerate. diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c index 2512f966d35..840823e0206 100644 --- a/opcodes/sh-dis.c +++ b/opcodes/sh-dis.c @@ -1,5 +1,5 @@ /* Disassemble SH instructions. - Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003 + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -433,8 +433,10 @@ print_insn_sh (memaddr, info) case bfd_mach_sh3e: target_arch = arch_sh3e; break; - case bfd_mach_sh4: case bfd_mach_sh4_nofpu: + target_arch = arch_sh4_nofpu; + break; + case bfd_mach_sh4: target_arch = arch_sh4; break; case bfd_mach_sh4a: @@ -444,6 +446,9 @@ print_insn_sh (memaddr, info) case bfd_mach_sh4al_dsp: target_arch = arch_sh4al_dsp; break; + case bfd_mach_sh4_nommu_nofpu: + target_arch = arch_sh4_nommu_nofpu; + break; case bfd_mach_sh5: #ifdef INCLUDE_SHMEDIA status = print_insn_sh64 (memaddr, info); diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h index 0ef1fab42a6..a1877b33ae7 100644 --- a/opcodes/sh-opc.h +++ b/opcodes/sh-opc.h @@ -1,5 +1,5 @@ /* Definitions for SH opcodes. - Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003 + Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003, 2004 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -188,12 +188,13 @@ sh_dsp_reg_nums; #define arch_sh4al_dsp 0x0400 #define arch_sh4_nofpu 0x1000 #define arch_sh4a_nofpu 0x2000 +#define arch_sh4_nommu_nofpu 0x4000 /* no mmu nor fpu */ #define arch_sh1_up (arch_sh1 | arch_sh2_up) #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp) #define arch_sh2e_up (arch_sh2e | arch_sh3e_up) #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \ - | arch_sh4_nofp_up) + | arch_sh4_nommu_nofpu_up) #define arch_sh3e_up (arch_sh3e | arch_sh4_up) #define arch_sh4_up (arch_sh4 | arch_sh4a_up) #define arch_sh4a_up (arch_sh4a) @@ -202,9 +203,14 @@ sh_dsp_reg_nums; #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) #define arch_sh4al_dsp_up (arch_sh4al_dsp) +#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) + #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) +#define arch_sh_any_with_mmu (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \ + | arch_sh4_nofp_up) /* arch _sh3_up omitting arch_sh4_nommu_nofpu */ + typedef struct { char *name; @@ -297,6 +303,8 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, +/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, + /* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, /* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, @@ -309,7 +317,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up}, -/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, +/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up}, @@ -319,6 +327,8 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, +/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}, + /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, @@ -329,7 +339,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up}, -/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up}, +/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}, /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up}, @@ -384,7 +394,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, -/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, +/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh_any_with_mmu}, /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, @@ -457,7 +467,7 @@ const sh_opcode_info sh_table[] = /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up}, /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, -/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}, /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up}, /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up}, @@ -482,11 +492,11 @@ const sh_opcode_info sh_table[] = /* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, -/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}, -/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}, -/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}, /* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up}, @@ -495,7 +505,7 @@ const sh_opcode_info sh_table[] = /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, -/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up}, /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, @@ -567,9 +577,9 @@ const sh_opcode_info sh_table[] = /* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up}, -/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up}, +/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, -/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, +/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up}, @@ -589,9 +599,9 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up}, -/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up}, +/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}, -/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up}, +/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}, /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up}, |