diff options
| -rw-r--r-- | bfd/ChangeLog | 19 | ||||
| -rw-r--r-- | bfd/Makefile.am | 8 | ||||
| -rw-r--r-- | bfd/Makefile.in | 8 | ||||
| -rw-r--r-- | bfd/archures.c | 5 | ||||
| -rw-r--r-- | bfd/bfd-in.h | 3 | ||||
| -rw-r--r-- | bfd/bfd-in2.h | 6 | ||||
| -rw-r--r-- | bfd/coff-tic4x.c | 616 | ||||
| -rw-r--r-- | bfd/coffswap.h | 85 | ||||
| -rw-r--r-- | bfd/config.bfd | 7 | ||||
| -rwxr-xr-x | bfd/configure | 34 | ||||
| -rw-r--r-- | bfd/configure.in | 6 | ||||
| -rw-r--r-- | bfd/cpu-tic4x.c | 81 | ||||
| -rw-r--r-- | bfd/targets.c | 6 | ||||
| -rw-r--r-- | bfd/ticoff.h | 130 | ||||
| -rw-r--r-- | include/ChangeLog | 8 | ||||
| -rw-r--r-- | include/coff/internal.h | 4 | ||||
| -rw-r--r-- | include/coff/ti.h | 1 | ||||
| -rw-r--r-- | include/coff/tic4x.h | 46 | ||||
| -rw-r--r-- | include/dis-asm.h | 1 | ||||
| -rw-r--r-- | include/opcode/tic4x.h | 1338 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 13 | ||||
| -rw-r--r-- | opcodes/Makefile.am | 4 | ||||
| -rw-r--r-- | opcodes/Makefile.in | 6 | ||||
| -rwxr-xr-x | opcodes/configure | 1 | ||||
| -rw-r--r-- | opcodes/configure.in | 1 | ||||
| -rw-r--r-- | opcodes/disassemble.c | 6 | ||||
| -rw-r--r-- | opcodes/tic4x-dis.c | 677 |
27 files changed, 3069 insertions, 51 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 2ea53bc9b8f..43a03634e48 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,22 @@ +2002-08-28 Svein E. Seldal <Svein.Seldal@solidas.com> + + * config.bfd: Add tic4x-*-*coff* and c4x-*-*coff* target. + * configure.in: Add tic4x_coff vector files. + * configure: Regenerate. + * Makefile.am: Add tic4x target. + * Makefile.in: Regenerate. + +2002-08-27 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * archures.c: Add the BFD arch type tic4x. + * bfd-in.h: Add BFD_IN_MEMORY flag. + * coff-tic4x.c: New file. + * coffswap.h (coff_swap_sym_out): Add preadjuster. + * cpu-tic4x.c: New file. + * targets.c: Added tic4x- in list of xvecs. + * ticoff.h: New file. + * bfd-in2.h: Regenerate. + 2002-08-27 Adam Nemet <anemet@lnxw.com> * elf32-arm.h (elf32_arm_finish_dynamic_sections): Set the last diff --git a/bfd/Makefile.am b/bfd/Makefile.am index d945dc3d35a..583cb85ed85 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -89,6 +89,7 @@ ALL_MACHINES = \ cpu-sh.lo \ cpu-sparc.lo \ cpu-tic30.lo \ + cpu-tic4x.lo \ cpu-tic54x.lo \ cpu-tic80.lo \ cpu-v850.lo \ @@ -140,6 +141,7 @@ ALL_MACHINES_CFILES = \ cpu-sh.c \ cpu-sparc.c \ cpu-tic30.c \ + cpu-tic4x.c \ cpu-tic54x.c \ cpu-tic80.c \ cpu-v850.c \ @@ -185,6 +187,7 @@ BFD32_BACKENDS = \ coff-stgo32.lo \ coff-svm68k.lo \ coff-tic30.lo \ + coff-tic4x.lo \ coff-tic54x.lo \ coff-tic80.lo \ coff-u68k.lo \ @@ -346,6 +349,7 @@ BFD32_BACKENDS_CFILES = \ coff-stgo32.c \ coff-svm68k.c \ coff-tic30.c \ + coff-tic4x.c \ coff-tic54x.c \ coff-tic80.c \ coff-u68k.c \ @@ -935,6 +939,7 @@ cpu-s390.lo: cpu-s390.c $(INCDIR)/filenames.h cpu-sh.lo: cpu-sh.c $(INCDIR)/filenames.h cpu-sparc.lo: cpu-sparc.c $(INCDIR)/filenames.h cpu-tic30.lo: cpu-tic30.c $(INCDIR)/filenames.h +cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h cpu-tic80.lo: cpu-tic80.c $(INCDIR)/filenames.h cpu-v850.lo: cpu-v850.c $(INCDIR)/filenames.h $(INCDIR)/safe-ctype.h @@ -1053,6 +1058,9 @@ coff-svm68k.lo: coff-svm68k.c coff-m68k.c $(INCDIR)/filenames.h \ coff-tic30.lo: coff-tic30.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \ $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \ libcoff.h coffcode.h coffswap.h +coff-tic4x.lo: coff-tic4x.c $(INCDIR)/filenames.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \ + $(INCDIR)/coff/internal.h libcoff.h coffcode.h coffswap.h coff-tic54x.lo: coff-tic54x.c $(INCDIR)/filenames.h \ $(INCDIR)/bfdlink.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \ $(INCDIR)/coff/internal.h libcoff.h coffcode.h coffswap.h diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 6a137cdbabb..470aade9084 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -215,6 +215,7 @@ ALL_MACHINES = \ cpu-sh.lo \ cpu-sparc.lo \ cpu-tic30.lo \ + cpu-tic4x.lo \ cpu-tic54x.lo \ cpu-tic80.lo \ cpu-v850.lo \ @@ -267,6 +268,7 @@ ALL_MACHINES_CFILES = \ cpu-sh.c \ cpu-sparc.c \ cpu-tic30.c \ + cpu-tic4x.c \ cpu-tic54x.c \ cpu-tic80.c \ cpu-v850.c \ @@ -313,6 +315,7 @@ BFD32_BACKENDS = \ coff-stgo32.lo \ coff-svm68k.lo \ coff-tic30.lo \ + coff-tic4x.lo \ coff-tic54x.lo \ coff-tic80.lo \ coff-u68k.lo \ @@ -475,6 +478,7 @@ BFD32_BACKENDS_CFILES = \ coff-stgo32.c \ coff-svm68k.c \ coff-tic30.c \ + coff-tic4x.c \ coff-tic54x.c \ coff-tic80.c \ coff-u68k.c \ @@ -1465,6 +1469,7 @@ cpu-s390.lo: cpu-s390.c $(INCDIR)/filenames.h cpu-sh.lo: cpu-sh.c $(INCDIR)/filenames.h cpu-sparc.lo: cpu-sparc.c $(INCDIR)/filenames.h cpu-tic30.lo: cpu-tic30.c $(INCDIR)/filenames.h +cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h cpu-tic80.lo: cpu-tic80.c $(INCDIR)/filenames.h cpu-v850.lo: cpu-v850.c $(INCDIR)/filenames.h $(INCDIR)/safe-ctype.h @@ -1583,6 +1588,9 @@ coff-svm68k.lo: coff-svm68k.c coff-m68k.c $(INCDIR)/filenames.h \ coff-tic30.lo: coff-tic30.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \ $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \ libcoff.h coffcode.h coffswap.h +coff-tic4x.lo: coff-tic4x.c $(INCDIR)/filenames.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \ + $(INCDIR)/coff/internal.h libcoff.h coffcode.h coffswap.h coff-tic54x.lo: coff-tic54x.c $(INCDIR)/filenames.h \ $(INCDIR)/bfdlink.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \ $(INCDIR)/coff/internal.h libcoff.h coffcode.h coffswap.h diff --git a/bfd/archures.c b/bfd/archures.c index dd51ec75517..f3ca094bcf2 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -228,6 +228,9 @@ DESCRIPTION . bfd_arch_ns32k, {* National Semiconductors ns32000 *} . bfd_arch_w65, {* WDC 65816 *} . bfd_arch_tic30, {* Texas Instruments TMS320C30 *} +. bfd_arch_tic4x, {* Texas Instruments TMS320C3X/4X *} +.#define bfd_mach_c3x 30 +.#define bfd_mach_c4x 40 . bfd_arch_tic54x, {* Texas Instruments TMS320C54X *} . bfd_arch_tic80, {* TI TMS320c80 (MVP) *} . bfd_arch_v850, {* NEC V850 *} @@ -358,6 +361,7 @@ extern const bfd_arch_info_type bfd_s390_arch; extern const bfd_arch_info_type bfd_sh_arch; extern const bfd_arch_info_type bfd_sparc_arch; extern const bfd_arch_info_type bfd_tic30_arch; +extern const bfd_arch_info_type bfd_tic4x_arch; extern const bfd_arch_info_type bfd_tic54x_arch; extern const bfd_arch_info_type bfd_tic80_arch; extern const bfd_arch_info_type bfd_v850_arch; @@ -412,6 +416,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_sh_arch, &bfd_sparc_arch, &bfd_tic30_arch, + &bfd_tic4x_arch, &bfd_tic54x_arch, &bfd_tic80_arch, &bfd_v850_arch, diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h index 19fd1072084..9017440c2a1 100644 --- a/bfd/bfd-in.h +++ b/bfd/bfd-in.h @@ -267,6 +267,9 @@ bfd_format; /* This flag indicates that the BFD contents are actually cached in memory. If this is set, iostream points to a bfd_in_memory struct. */ #define BFD_IN_MEMORY 0x800 + +/* The sections in this BFD specify a memory page. */ +#define HAS_LOAD_PAGE 0x1000 /* Symbols and relocation. */ diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 1a869f631b8..34fb98ed308 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -273,6 +273,9 @@ bfd_format; /* This flag indicates that the BFD contents are actually cached in memory. If this is set, iostream points to a bfd_in_memory struct. */ #define BFD_IN_MEMORY 0x800 + +/* The sections in this BFD specify a memory page */ +#define HAS_LOAD_PAGE 0x1000 /* Symbols and relocation. */ @@ -1618,6 +1621,9 @@ enum bfd_architecture bfd_arch_ns32k, /* National Semiconductors ns32000 */ bfd_arch_w65, /* WDC 65816 */ bfd_arch_tic30, /* Texas Instruments TMS320C30 */ + bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */ +#define bfd_mach_c3x 30 +#define bfd_mach_c4x 40 bfd_arch_tic54x, /* Texas Instruments TMS320C54X */ bfd_arch_tic80, /* TI TMS320c80 (MVP) */ bfd_arch_v850, /* NEC V850 */ diff --git a/bfd/coff-tic4x.c b/bfd/coff-tic4x.c new file mode 100644 index 00000000000..1669f7cc012 --- /dev/null +++ b/bfd/coff-tic4x.c @@ -0,0 +1,616 @@ +/* BFD back-end for TMS320C4X coff binaries. + Copyright (C) 1996-99, 2000, 2002 Free Software Foundation, Inc. + Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz) + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "bfdlink.h" +#include "coff/tic4x.h" +#include "coff/internal.h" +#include "libcoff.h" + +#undef F_LSYMS +#define F_LSYMS F_LSYMS_TICOFF + +static boolean +ticoff0_bad_format_hook (abfd, filehdr) + bfd *abfd; + PTR filehdr; +{ + struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr; + + if (COFF0_BADMAG (*internal_f)) + return false; + + return true; +} + +static boolean +ticoff1_bad_format_hook (abfd, filehdr) + bfd *abfd ATTRIBUTE_UNUSED; + PTR filehdr; +{ + struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr; + + if (COFF1_BADMAG (*internal_f)) + return false; + + return true; +} + +/* Replace the stock _bfd_coff_is_local_label_name to recognize TI COFF local + labels. */ +static boolean +ticoff_bfd_is_local_label_name (abfd, name) + bfd *abfd ATTRIBUTE_UNUSED; + const char *name; +{ + if (TICOFF_LOCAL_LABEL_P(name)) + return true; + return false; +} + +#define coff_bfd_is_local_label_name ticoff_bfd_is_local_label_name + +static void tic4x_reloc_processing + PARAMS ((arelent *, struct internal_reloc *, asymbol **, bfd *, asection *)); + +#define RELOC_PROCESSING(RELENT,RELOC,SYMS,ABFD,SECT)\ + tic4x_reloc_processing (RELENT,RELOC,SYMS,ABFD,SECT) + +/* Customize coffcode.h; the default coff_ functions are set up to use + COFF2; coff_bad_format_hook uses BADMAG, so set that for COFF2. + The COFF1 and COFF0 vectors use custom _bad_format_hook procs + instead of setting BADMAG. */ +#define BADMAG(x) COFF2_BADMAG(x) +#include "coffcode.h" + +static bfd_reloc_status_type +tic4x_relocation (abfd, reloc_entry, symbol, data, input_section, + output_bfd, error_message) + bfd *abfd ATTRIBUTE_UNUSED; + arelent *reloc_entry; + asymbol *symbol ATTRIBUTE_UNUSED; + PTR data ATTRIBUTE_UNUSED; + asection *input_section; + bfd *output_bfd; + char **error_message ATTRIBUTE_UNUSED; +{ + if (output_bfd != (bfd *) NULL) + { + /* This is a partial relocation, and we want to apply the + relocation to the reloc entry rather than the raw data. + Modify the reloc inplace to reflect what we now know. */ + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + return bfd_reloc_continue; +} + +reloc_howto_type tic4x_howto_table[] = +{ + HOWTO(R_RELWORD, 0, 2, 16, false, 0, complain_overflow_signed, tic4x_relocation, "RELWORD", true, 0x0000ffff, 0x0000ffff, false), + HOWTO(R_REL24, 0, 2, 24, false, 0, complain_overflow_bitfield, tic4x_relocation, "REL24", true, 0x00ffffff, 0x00ffffff, false), + HOWTO(R_RELLONG, 0, 2, 32, false, 0, complain_overflow_dont, tic4x_relocation, "RELLONG", true, 0xffffffff, 0xffffffff, false), + HOWTO(R_PCRWORD, 0, 2, 16, true, 0, complain_overflow_signed, tic4x_relocation, "PCRWORD", true, 0x0000ffff, 0x0000ffff, false), + HOWTO(R_PCR24, 0, 2, 24, true, 0, complain_overflow_signed, tic4x_relocation, "PCR24", true, 0x00ffffff, 0x00ffffff, false), + HOWTO(R_PARTLS16, 0, 2, 16, false, 0, complain_overflow_dont, tic4x_relocation, "PARTLS16", true, 0x0000ffff, 0x0000ffff, false), + HOWTO(R_PARTMS8, 16, 2, 16, false, 0, complain_overflow_dont, tic4x_relocation, "PARTMS8", true, 0x0000ffff, 0x0000ffff, false), + HOWTO(R_RELWORD, 0, 2, 16, false, 0, complain_overflow_signed, tic4x_relocation, "ARELWORD", true, 0x0000ffff, 0x0000ffff, false), + HOWTO(R_REL24, 0, 2, 24, false, 0, complain_overflow_signed, tic4x_relocation, "AREL24", true, 0x00ffffff, 0x00ffffff, false), + HOWTO(R_RELLONG, 0, 2, 32, false, 0, complain_overflow_signed, tic4x_relocation, "ARELLONG", true, 0xffffffff, 0xffffffff, false), + HOWTO(R_PCRWORD, 0, 2, 16, true, 0, complain_overflow_signed, tic4x_relocation, "APCRWORD", true, 0x0000ffff, 0x0000ffff, false), + HOWTO(R_PCR24, 0, 2, 24, true, 0, complain_overflow_signed, tic4x_relocation, "APCR24", true, 0x00ffffff, 0x00ffffff, false), + HOWTO(R_PARTLS16, 0, 2, 16, false, 0, complain_overflow_dont, tic4x_relocation, "APARTLS16", true, 0x0000ffff, 0x0000ffff, false), + HOWTO(R_PARTMS8, 16, 2, 16, false, 0, complain_overflow_dont, tic4x_relocation, "APARTMS8", true, 0x0000ffff, 0x0000ffff, false), +}; +#define HOWTO_SIZE (sizeof(tic4x_howto_table) / sizeof(tic4x_howto_table[0])) + +#undef coff_bfd_reloc_type_lookup +#define coff_bfd_reloc_type_lookup tic4x_coff_reloc_type_lookup + +/* For the case statement use the code values used tc_gen_reloc (defined in + bfd/reloc.c) to map to the howto table entries. */ + +static reloc_howto_type * +tic4x_coff_reloc_type_lookup (abfd, code) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + unsigned int type; + unsigned int i; + + switch (code) + { + case BFD_RELOC_32: type = R_RELLONG; break; + case BFD_RELOC_24: type = R_REL24; break; + case BFD_RELOC_16: type = R_RELWORD; break; + case BFD_RELOC_24_PCREL: type = R_PCR24; break; + case BFD_RELOC_16_PCREL: type = R_PCRWORD; break; + case BFD_RELOC_HI16: type = R_PARTMS8; break; + case BFD_RELOC_LO16: type = R_PARTLS16; break; + default: + return NULL; + } + + for (i = 0; i < HOWTO_SIZE; i++) + { + if (tic4x_howto_table[i].type == type) + return tic4x_howto_table + i; + } + return NULL; +} + + +/* Code to turn a r_type into a howto ptr, uses the above howto table. + Called after some initial checking by the tic4x_rtype_to_howto fn + below. */ +static void +tic4x_lookup_howto (internal, dst) + arelent *internal; + struct internal_reloc *dst; +{ + unsigned int i; + int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; + + for (i = 0; i < HOWTO_SIZE; i++) + { + if (tic4x_howto_table[i].type == dst->r_type) + { + internal->howto = tic4x_howto_table + i + bank; + return; + } + } + + (*_bfd_error_handler) (_("Unrecognized reloc type 0x%x"), + (unsigned int) dst->r_type); + abort(); +} + +#undef coff_rtype_to_howto +#define coff_rtype_to_howto coff_tic4x_rtype_to_howto + +static reloc_howto_type * +coff_tic4x_rtype_to_howto (abfd, sec, rel, h, sym, addendp) + bfd *abfd ATTRIBUTE_UNUSED; + asection *sec; + struct internal_reloc *rel; + struct coff_link_hash_entry *h ATTRIBUTE_UNUSED; + struct internal_syment *sym ATTRIBUTE_UNUSED; + bfd_vma *addendp; +{ + arelent genrel; + + if (rel->r_symndx == -1 && addendp != NULL) + /* This is a TI "internal relocation", which means that the relocation + amount is the amount by which the current section is being relocated + in the output section. */ + *addendp = (sec->output_section->vma + sec->output_offset) - sec->vma; + + tic4x_lookup_howto (&genrel, rel); + + return genrel.howto; +} + + +static void +tic4x_reloc_processing (relent, reloc, symbols, abfd, section) + arelent *relent; + struct internal_reloc *reloc; + asymbol **symbols; + bfd *abfd; + asection *section; +{ + asymbol *ptr; + + relent->address = reloc->r_vaddr; + + if (reloc->r_symndx != -1) + { + if (reloc->r_symndx < 0 || reloc->r_symndx >= obj_conv_table_size (abfd)) + { + (*_bfd_error_handler) + (_("%s: warning: illegal symbol index %ld in relocs"), + bfd_get_filename (abfd), reloc->r_symndx); + relent->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr; + ptr = NULL; + } + else + { + relent->sym_ptr_ptr = (symbols + + obj_convert (abfd)[reloc->r_symndx]); + ptr = *(relent->sym_ptr_ptr); + } + } + else + { + relent->sym_ptr_ptr = section->symbol_ptr_ptr; + ptr = *(relent->sym_ptr_ptr); + } + + /* The symbols definitions that we have read in have been relocated + as if their sections started at 0. But the offsets refering to + the symbols in the raw data have not been modified, so we have to + have a negative addend to compensate. + + Note that symbols which used to be common must be left alone. */ + + /* Calculate any reloc addend by looking at the symbol. */ + CALC_ADDEND (abfd, ptr, *reloc, relent); + + relent->address -= section->vma; + /* !! relent->section = (asection *) NULL; */ + + /* Fill in the relent->howto field from reloc->r_type. */ + tic4x_lookup_howto (relent, reloc); +} + + +static const bfd_coff_backend_data ticoff0_swap_table = +{ + coff_SWAP_aux_in, coff_SWAP_sym_in, coff_SWAP_lineno_in, + coff_SWAP_aux_out, coff_SWAP_sym_out, + coff_SWAP_lineno_out, coff_SWAP_reloc_out, + coff_SWAP_filehdr_out, coff_SWAP_aouthdr_out, + coff_SWAP_scnhdr_out, + FILHSZ_V0, AOUTSZ, SCNHSZ_V01, SYMESZ, AUXESZ, RELSZ_V0, LINESZ, FILNMLEN, +#ifdef COFF_LONG_FILENAMES + true, +#else + false, +#endif +#ifdef COFF_LONG_SECTION_NAMES + true, +#else + false, +#endif +#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS + true, +#else + false, +#endif +#ifdef COFF_DEBUG_STRING_WIDE_PREFIX + 4, +#else + 2, +#endif + COFF_DEFAULT_SECTION_ALIGNMENT_POWER, + coff_SWAP_filehdr_in, coff_SWAP_aouthdr_in, coff_SWAP_scnhdr_in, + coff_SWAP_reloc_in, ticoff0_bad_format_hook, coff_set_arch_mach_hook, + coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook, + coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook, + coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate, + coff_classify_symbol, coff_compute_section_file_positions, + coff_start_final_link, coff_relocate_section, coff_rtype_to_howto, + coff_adjust_symndx, coff_link_add_one_symbol, + coff_link_output_has_begun, coff_final_link_postscript +}; + +/* COFF1 differs in section header size. */ +static const bfd_coff_backend_data ticoff1_swap_table = +{ + coff_SWAP_aux_in, coff_SWAP_sym_in, coff_SWAP_lineno_in, + coff_SWAP_aux_out, coff_SWAP_sym_out, + coff_SWAP_lineno_out, coff_SWAP_reloc_out, + coff_SWAP_filehdr_out, coff_SWAP_aouthdr_out, + coff_SWAP_scnhdr_out, + FILHSZ, AOUTSZ, SCNHSZ_V01, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN, +#ifdef COFF_LONG_FILENAMES + true, +#else + false, +#endif +#ifdef COFF_LONG_SECTION_NAMES + true, +#else + false, +#endif +#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS + true, +#else + false, +#endif +#ifdef COFF_DEBUG_STRING_WIDE_PREFIX + 4, +#else + 2, +#endif + COFF_DEFAULT_SECTION_ALIGNMENT_POWER, + coff_SWAP_filehdr_in, coff_SWAP_aouthdr_in, coff_SWAP_scnhdr_in, + coff_SWAP_reloc_in, ticoff1_bad_format_hook, coff_set_arch_mach_hook, + coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook, + coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook, + coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate, + coff_classify_symbol, coff_compute_section_file_positions, + coff_start_final_link, coff_relocate_section, coff_rtype_to_howto, + coff_adjust_symndx, coff_link_add_one_symbol, + coff_link_output_has_begun, coff_final_link_postscript +}; + + +/* TI COFF v0, DOS tools (little-endian headers). */ +const bfd_target tic4x_coff0_vec = +{ + "coff0-c4x", /* Name. */ + bfd_target_coff_flavour, + BFD_ENDIAN_LITTLE, /* Data byte order is little. */ + BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */ + + (HAS_RELOC | EXEC_P | /* Object flags. */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | WP_TEXT | HAS_LOAD_PAGE ), + + (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */ + '_', /* Leading symbol underscore. */ + '/', /* ar_pad_char. */ + 15, /* ar_max_namelen. */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ + + {_bfd_dummy_target, coff_object_p, /* bfd_check_format */ + bfd_generic_archive_p, _bfd_dummy_target}, + {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ + bfd_false}, + {bfd_false, coff_write_object_contents, /* bfd_write_contents */ + _bfd_write_archive_contents, bfd_false}, + + BFD_JUMP_TABLE_GENERIC (coff), + BFD_JUMP_TABLE_COPY (coff), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), + BFD_JUMP_TABLE_SYMBOLS (coff), + BFD_JUMP_TABLE_RELOCS (coff), + BFD_JUMP_TABLE_WRITE (coff), + BFD_JUMP_TABLE_LINK (coff), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + NULL, + + (PTR)&ticoff0_swap_table +}; + +/* TI COFF v0, SPARC tools (big-endian headers). */ +const bfd_target tic4x_coff0_beh_vec = +{ + "coff0-beh-c4x", /* Name. */ + bfd_target_coff_flavour, + BFD_ENDIAN_LITTLE, /* Data byte order is little. */ + BFD_ENDIAN_BIG, /* Header byte order is big. */ + + (HAS_RELOC | EXEC_P | /* Object flags. */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | WP_TEXT | HAS_LOAD_PAGE ), + + (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */ + '_', /* Leading symbol underscore. */ + '/', /* ar_pad_char */ + 15, /* ar_max_namelen */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ + + {_bfd_dummy_target, coff_object_p, /* bfd_check_format */ + bfd_generic_archive_p, _bfd_dummy_target}, + {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ + bfd_false}, + {bfd_false, coff_write_object_contents, /* bfd_write_contents */ + _bfd_write_archive_contents, bfd_false}, + + BFD_JUMP_TABLE_GENERIC (coff), + BFD_JUMP_TABLE_COPY (coff), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), + BFD_JUMP_TABLE_SYMBOLS (coff), + BFD_JUMP_TABLE_RELOCS (coff), + BFD_JUMP_TABLE_WRITE (coff), + BFD_JUMP_TABLE_LINK (coff), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + &tic4x_coff0_vec, + + (PTR)&ticoff0_swap_table +}; + +/* TI COFF v1, DOS tools (little-endian headers). */ +const bfd_target tic4x_coff1_vec = +{ + "coff1-c4x", /* Name. */ + bfd_target_coff_flavour, + BFD_ENDIAN_LITTLE, /* Data byte order is little. */ + BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */ + + (HAS_RELOC | EXEC_P | /* Object flags. */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | WP_TEXT | HAS_LOAD_PAGE ), + + (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */ + '_', /* Leading symbol underscore. */ + '/', /* ar_pad_char */ + 15, /* ar_max_namelen */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ + + {_bfd_dummy_target, coff_object_p, /* bfd_check_format */ + bfd_generic_archive_p, _bfd_dummy_target}, + {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ + bfd_false}, + {bfd_false, coff_write_object_contents, /* bfd_write_contents */ + _bfd_write_archive_contents, bfd_false}, + + BFD_JUMP_TABLE_GENERIC (coff), + BFD_JUMP_TABLE_COPY (coff), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), + BFD_JUMP_TABLE_SYMBOLS (coff), + BFD_JUMP_TABLE_RELOCS (coff), + BFD_JUMP_TABLE_WRITE (coff), + BFD_JUMP_TABLE_LINK (coff), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + &tic4x_coff0_beh_vec, + + (PTR)&ticoff1_swap_table +}; + +/* TI COFF v1, SPARC tools (big-endian headers). */ +const bfd_target tic4x_coff1_beh_vec = +{ + "coff1-beh-c4x", /* Name. */ + bfd_target_coff_flavour, + BFD_ENDIAN_LITTLE, /* Data byte order is little. */ + BFD_ENDIAN_BIG, /* Header byte order is big. */ + + (HAS_RELOC | EXEC_P | /* Object flags. */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | WP_TEXT | HAS_LOAD_PAGE ), + + (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */ + '_', /* Leading symbol underscore. */ + '/', /* ar_pad_char */ + 15, /* ar_max_namelen */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ + + {_bfd_dummy_target, coff_object_p, /* bfd_check_format */ + bfd_generic_archive_p, _bfd_dummy_target}, + {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ + bfd_false}, + {bfd_false, coff_write_object_contents, /* bfd_write_contents */ + _bfd_write_archive_contents, bfd_false}, + + BFD_JUMP_TABLE_GENERIC (coff), + BFD_JUMP_TABLE_COPY (coff), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), + BFD_JUMP_TABLE_SYMBOLS (coff), + BFD_JUMP_TABLE_RELOCS (coff), + BFD_JUMP_TABLE_WRITE (coff), + BFD_JUMP_TABLE_LINK (coff), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + &tic4x_coff1_vec, + + (PTR)&ticoff1_swap_table +}; + +/* TI COFF v2, TI DOS tools output (little-endian headers). */ +const bfd_target tic4x_coff2_vec = +{ + "coff2-c4x", /* Name. */ + bfd_target_coff_flavour, + BFD_ENDIAN_LITTLE, /* Data byte order is little. */ + BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */ + + (HAS_RELOC | EXEC_P | /* Object flags. */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | WP_TEXT | HAS_LOAD_PAGE ), + + (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */ + '_', /* Leading symbol underscore. */ + '/', /* ar_pad_char */ + 15, /* ar_max_namelen */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ + + {_bfd_dummy_target, coff_object_p, /* bfd_check_format */ + bfd_generic_archive_p, _bfd_dummy_target}, + {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ + bfd_false}, + {bfd_false, coff_write_object_contents, /* bfd_write_contents */ + _bfd_write_archive_contents, bfd_false}, + + BFD_JUMP_TABLE_GENERIC (coff), + BFD_JUMP_TABLE_COPY (coff), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), + BFD_JUMP_TABLE_SYMBOLS (coff), + BFD_JUMP_TABLE_RELOCS (coff), + BFD_JUMP_TABLE_WRITE (coff), + BFD_JUMP_TABLE_LINK (coff), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + &tic4x_coff1_beh_vec, + + COFF_SWAP_TABLE +}; + +/* TI COFF v2, TI SPARC tools output (big-endian headers). */ +const bfd_target tic4x_coff2_beh_vec = +{ + "coff2-beh-c4x", /* Name. */ + bfd_target_coff_flavour, + BFD_ENDIAN_LITTLE, /* Data byte order is little. */ + BFD_ENDIAN_BIG, /* Header byte order is big. */ + + (HAS_RELOC | EXEC_P | /* Object flags. */ + HAS_LINENO | HAS_DEBUG | + HAS_SYMS | HAS_LOCALS | WP_TEXT | HAS_LOAD_PAGE ), + + (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags. */ + '_', /* Leading symbol underscore. */ + '/', /* ar_pad_char */ + 15, /* ar_max_namelen */ + bfd_getl64, bfd_getl_signed_64, bfd_putl64, + bfd_getl32, bfd_getl_signed_32, bfd_putl32, + bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ + bfd_getb64, bfd_getb_signed_64, bfd_putb64, + bfd_getb32, bfd_getb_signed_32, bfd_putb32, + bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ + + {_bfd_dummy_target, coff_object_p, /* bfd_check_format */ + bfd_generic_archive_p, _bfd_dummy_target}, + {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ + bfd_false}, + {bfd_false, coff_write_object_contents, /* bfd_write_contents */ + _bfd_write_archive_contents, bfd_false}, + + BFD_JUMP_TABLE_GENERIC (coff), + BFD_JUMP_TABLE_COPY (coff), + BFD_JUMP_TABLE_CORE (_bfd_nocore), + BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), + BFD_JUMP_TABLE_SYMBOLS (coff), + BFD_JUMP_TABLE_RELOCS (coff), + BFD_JUMP_TABLE_WRITE (coff), + BFD_JUMP_TABLE_LINK (coff), + BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), + + &tic4x_coff2_vec, + + COFF_SWAP_TABLE +}; diff --git a/bfd/coffswap.h b/bfd/coffswap.h index cd147c5bd5f..5f23ecc07b3 100644 --- a/bfd/coffswap.h +++ b/bfd/coffswap.h @@ -1,24 +1,24 @@ /* Generic COFF swapping routines, for BFD. Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, - 2001 + 2001, 2002 Free Software Foundation, Inc. Written by Cygnus Support. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* This file contains routines used to swap COFF data. It is a header file because the details of swapping depend on the details of the @@ -381,7 +381,12 @@ coff_swap_sym_out (abfd, inp, extp) { struct internal_syment *in = (struct internal_syment *) inp; SYMENT *ext =(SYMENT *) extp; - if(in->_n._n_name[0] == 0) + +#ifdef COFF_ADJUST_SYM_OUT_PRE + COFF_ADJUST_SYM_OUT_PRE (abfd, inp, extp); +#endif + + if (in->_n._n_name[0] == 0) { H_PUT_32 (abfd, 0, ext->e.e.e_zeroes); H_PUT_32 (abfd, in->_n._n_n._n_offset, ext->e.e.e_offset); @@ -391,11 +396,13 @@ coff_swap_sym_out (abfd, inp, extp) #if SYMNMLEN != E_SYMNMLEN -> Error, we need to cope with truncating or extending SYMNMLEN!; #else - memcpy(ext->e.e_name, in->_n._n_name, SYMNMLEN); + memcpy (ext->e.e_name, in->_n._n_name, SYMNMLEN); #endif } + H_PUT_32 (abfd, in->n_value, ext->e_value); H_PUT_16 (abfd, in->n_scnum, ext->e_scnum); + if (sizeof (ext->e_type) == 2) { H_PUT_16 (abfd, in->n_type, ext->e_type); @@ -404,11 +411,14 @@ coff_swap_sym_out (abfd, inp, extp) { H_PUT_32 (abfd, in->n_type, ext->e_type); } + H_PUT_8 (abfd, in->n_sclass, ext->e_sclass); H_PUT_8 (abfd, in->n_numaux, ext->e_numaux); + #ifdef COFF_ADJUST_SYM_OUT_POST COFF_ADJUST_SYM_OUT_POST (abfd, inp, extp); #endif + return SYMESZ; } @@ -428,6 +438,7 @@ coff_swap_aux_in (abfd, ext1, type, class, indx, numaux, in1) #ifdef COFF_ADJUST_AUX_IN_PRE COFF_ADJUST_AUX_IN_PRE (abfd, ext1, type, class, indx, numaux, in1); #endif + switch (class) { case C_FILE: @@ -448,9 +459,7 @@ coff_swap_aux_in (abfd, ext1, type, class, indx, numaux, in1) numaux * sizeof (AUXENT)); } else - { - memcpy (in->x_file.x_fname, ext->x_file.x_fname, FILNMLEN); - } + memcpy (in->x_file.x_fname, ext->x_file.x_fname, FILNMLEN); #endif } goto end; @@ -502,7 +511,7 @@ coff_swap_aux_in (abfd, ext1, type, class, indx, numaux, in1) H_GET_16 (abfd, ext->x_sym.x_fcnary.x_ary.x_dimen[3]); } - if (ISFCN(type)) + if (ISFCN (type)) { in->x_sym.x_misc.x_fsize = H_GET_32 (abfd, ext->x_sym.x_misc.x_fsize); } @@ -535,7 +544,9 @@ coff_swap_aux_out (abfd, inp, type, class, indx, numaux, extp) #ifdef COFF_ADJUST_AUX_OUT_PRE COFF_ADJUST_AUX_OUT_PRE (abfd, inp, type, class, indx, numaux, extp); #endif - memset((PTR)ext, 0, AUXESZ); + + memset ((PTR)ext, 0, AUXESZ); + switch (class) { case C_FILE: @@ -681,29 +692,29 @@ coff_swap_aouthdr_in (abfd, aouthdr_ext1, aouthdr_int1) #else aouthdr_int->o_toc = H_GET_32 (abfd, aouthdr_ext->o_toc); #endif - aouthdr_int->o_snentry = H_GET_16 (abfd, aouthdr_ext->o_snentry); - aouthdr_int->o_sntext = H_GET_16 (abfd, aouthdr_ext->o_sntext); - aouthdr_int->o_sndata = H_GET_16 (abfd, aouthdr_ext->o_sndata); - aouthdr_int->o_sntoc = H_GET_16 (abfd, aouthdr_ext->o_sntoc); + aouthdr_int->o_snentry = H_GET_16 (abfd, aouthdr_ext->o_snentry); + aouthdr_int->o_sntext = H_GET_16 (abfd, aouthdr_ext->o_sntext); + aouthdr_int->o_sndata = H_GET_16 (abfd, aouthdr_ext->o_sndata); + aouthdr_int->o_sntoc = H_GET_16 (abfd, aouthdr_ext->o_sntoc); aouthdr_int->o_snloader = H_GET_16 (abfd, aouthdr_ext->o_snloader); - aouthdr_int->o_snbss = H_GET_16 (abfd, aouthdr_ext->o_snbss); + aouthdr_int->o_snbss = H_GET_16 (abfd, aouthdr_ext->o_snbss); aouthdr_int->o_algntext = H_GET_16 (abfd, aouthdr_ext->o_algntext); aouthdr_int->o_algndata = H_GET_16 (abfd, aouthdr_ext->o_algndata); - aouthdr_int->o_modtype = H_GET_16 (abfd, aouthdr_ext->o_modtype); - aouthdr_int->o_cputype = H_GET_16 (abfd, aouthdr_ext->o_cputype); + aouthdr_int->o_modtype = H_GET_16 (abfd, aouthdr_ext->o_modtype); + aouthdr_int->o_cputype = H_GET_16 (abfd, aouthdr_ext->o_cputype); #ifdef XCOFF64 aouthdr_int->o_maxstack = H_GET_64 (abfd, aouthdr_ext->o_maxstack); - aouthdr_int->o_maxdata = H_GET_64 (abfd, aouthdr_ext->o_maxdata); + aouthdr_int->o_maxdata = H_GET_64 (abfd, aouthdr_ext->o_maxdata); #else aouthdr_int->o_maxstack = H_GET_32 (abfd, aouthdr_ext->o_maxstack); - aouthdr_int->o_maxdata = H_GET_32 (abfd, aouthdr_ext->o_maxdata); + aouthdr_int->o_maxdata = H_GET_32 (abfd, aouthdr_ext->o_maxdata); #endif #endif #ifdef MIPSECOFF - aouthdr_int->bss_start = H_GET_32 (abfd, aouthdr_ext->bss_start); - aouthdr_int->gp_value = H_GET_32 (abfd, aouthdr_ext->gp_value); - aouthdr_int->gprmask = H_GET_32 (abfd, aouthdr_ext->gprmask); + aouthdr_int->bss_start = H_GET_32 (abfd, aouthdr_ext->bss_start); + aouthdr_int->gp_value = H_GET_32 (abfd, aouthdr_ext->gp_value); + aouthdr_int->gprmask = H_GET_32 (abfd, aouthdr_ext->gprmask); aouthdr_int->cprmask[0] = H_GET_32 (abfd, aouthdr_ext->cprmask[0]); aouthdr_int->cprmask[1] = H_GET_32 (abfd, aouthdr_ext->cprmask[1]); aouthdr_int->cprmask[2] = H_GET_32 (abfd, aouthdr_ext->cprmask[2]); @@ -712,9 +723,9 @@ coff_swap_aouthdr_in (abfd, aouthdr_ext1, aouthdr_int1) #ifdef ALPHAECOFF aouthdr_int->bss_start = H_GET_64 (abfd, aouthdr_ext->bss_start); - aouthdr_int->gp_value = H_GET_64 (abfd, aouthdr_ext->gp_value); - aouthdr_int->gprmask = H_GET_32 (abfd, aouthdr_ext->gprmask); - aouthdr_int->fprmask = H_GET_32 (abfd, aouthdr_ext->fprmask); + aouthdr_int->gp_value = H_GET_64 (abfd, aouthdr_ext->gp_value); + aouthdr_int->gprmask = H_GET_32 (abfd, aouthdr_ext->gprmask); + aouthdr_int->fprmask = H_GET_32 (abfd, aouthdr_ext->fprmask); #endif } @@ -807,7 +818,8 @@ coff_swap_scnhdr_in (abfd, ext, in) #ifdef COFF_ADJUST_SCNHDR_IN_PRE COFF_ADJUST_SCNHDR_IN_PRE (abfd, ext, in); #endif - memcpy(scnhdr_int->s_name, scnhdr_ext->s_name, sizeof (scnhdr_int->s_name)); + memcpy (scnhdr_int->s_name, scnhdr_ext->s_name, sizeof (scnhdr_int->s_name)); + scnhdr_int->s_vaddr = GET_SCNHDR_VADDR (abfd, scnhdr_ext->s_vaddr); scnhdr_int->s_paddr = GET_SCNHDR_PADDR (abfd, scnhdr_ext->s_paddr); scnhdr_int->s_size = GET_SCNHDR_SIZE (abfd, scnhdr_ext->s_size); @@ -866,6 +878,7 @@ coff_swap_scnhdr_out (abfd, in, out) buf, scnhdr_int->s_nlnno); PUT_SCNHDR_NLNNO (abfd, 0xffff, scnhdr_ext->s_nlnno); } + if (scnhdr_int->s_nreloc <= MAX_SCNHDR_NRELOC) PUT_SCNHDR_NRELOC (abfd, scnhdr_int->s_nreloc, scnhdr_ext->s_nreloc); else diff --git a/bfd/config.bfd b/bfd/config.bfd index 0db37481442..55e2afcf86e 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -34,6 +34,7 @@ case "${targ_cpu}" in alpha*) targ_archs=bfd_alpha_arch ;; arm*) targ_archs=bfd_arm_arch ;; c30*) targ_archs=bfd_tic30_arch ;; +c4x*) targ_archs=bfd_tic4x_arch ;; c54x*) targ_archs=bfd_tic54x_arch ;; dlx*) targ_archs=bfd_dlx_arch ;; hppa*) targ_archs=bfd_hppa_arch ;; @@ -256,6 +257,12 @@ case "${targ}" in targ_defvec=tic30_coff_vec ;; + c4x-*-*coff* | tic4x-*-*coff*) + targ_defvec=tic4x_coff1_vec + targ_selvecs="tic4x_coff1_beh_vec tic4x_coff2_vec tic4x_coff2_beh_vec tic4x_coff0_vec tic4x_coff0_beh_vec" + targ_underscore=yes + ;; + c54x*-*-*coff* | tic54x-*-*coff*) targ_defvec=tic54x_coff1_vec targ_selvecs="tic54x_coff1_beh_vec tic54x_coff2_vec tic54x_coff2_beh_vec tic54x_coff0_vec tic54x_coff0_beh_vec" diff --git a/bfd/configure b/bfd/configure index cd03dd3cae4..d30361eed25 100755 --- a/bfd/configure +++ b/bfd/configure @@ -6240,6 +6240,12 @@ do sunos_big_vec) tb="$tb sunos.lo aout32.lo" ;; tic30_aout_vec) tb="$tb aout-tic30.lo" ;; tic30_coff_vec) tb="$tb coff-tic30.lo" ;; + tic4x_coff0_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff0_beh_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff1_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff1_beh_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff2_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff2_beh_vec) tb="$tb coff-tic4x.lo" ;; tic54x_coff0_beh_vec) tb="$tb coff-tic54x.lo" ;; tic54x_coff0_vec) tb="$tb coff-tic54x.lo" ;; tic54x_coff1_beh_vec) tb="$tb coff-tic54x.lo" ;; @@ -6332,10 +6338,10 @@ case ${host64}-${target64}-${want64} in if test -n "$GCC" ; then bad_64bit_gcc=no; echo $ac_n "checking for gcc version with buggy 64-bit support""... $ac_c" 1>&6 -echo "configure:6336: checking for gcc version with buggy 64-bit support" >&5 +echo "configure:6342: checking for gcc version with buggy 64-bit support" >&5 # Add more tests for gcc versions with non-working 64-bit support here. cat > conftest.$ac_ext <<EOF -#line 6339 "configure" +#line 6345 "configure" #include "confdefs.h" :__GNUC__:__GNUC_MINOR__:__i386__: EOF @@ -6380,17 +6386,17 @@ for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:6384: checking for $ac_hdr" >&5 +echo "configure:6390: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 6389 "configure" +#line 6395 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:6394: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:6400: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -6419,12 +6425,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:6423: checking for $ac_func" >&5 +echo "configure:6429: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 6428 "configure" +#line 6434 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -6447,7 +6453,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:6451: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6457: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -6472,7 +6478,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:6476: checking for working mmap" >&5 +echo "configure:6482: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -6480,7 +6486,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <<EOF -#line 6484 "configure" +#line 6490 "configure" #include "confdefs.h" /* Thanks to Mike Haertel and Jim Avera for this test. @@ -6633,7 +6639,7 @@ main() } EOF -if { (eval echo configure:6637: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:6643: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -6658,12 +6664,12 @@ fi for ac_func in madvise mprotect do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:6662: checking for $ac_func" >&5 +echo "configure:6668: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 6667 "configure" +#line 6673 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -6686,7 +6692,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:6690: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6696: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else diff --git a/bfd/configure.in b/bfd/configure.in index 2f59095714d..1facc24856f 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -741,6 +741,12 @@ do sunos_big_vec) tb="$tb sunos.lo aout32.lo" ;; tic30_aout_vec) tb="$tb aout-tic30.lo" ;; tic30_coff_vec) tb="$tb coff-tic30.lo" ;; + tic4x_coff0_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff0_beh_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff1_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff1_beh_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff2_vec) tb="$tb coff-tic4x.lo" ;; + tic4x_coff2_beh_vec) tb="$tb coff-tic4x.lo" ;; tic54x_coff0_beh_vec) tb="$tb coff-tic54x.lo" ;; tic54x_coff0_vec) tb="$tb coff-tic54x.lo" ;; tic54x_coff1_beh_vec) tb="$tb coff-tic54x.lo" ;; diff --git a/bfd/cpu-tic4x.c b/bfd/cpu-tic4x.c new file mode 100644 index 00000000000..9d90fc62bd7 --- /dev/null +++ b/bfd/cpu-tic4x.c @@ -0,0 +1,81 @@ +/* bfd back-end for TMS320C[34]x support + Copyright (C) 1996, 1997, 2002 Free Software Foundation, Inc. + + Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz) + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +static boolean +c4x_scan (info, string) + const struct bfd_arch_info *info; + const char *string; +{ + /* Allow strings of form [ti][Cc][34][0-9], let's not be too picky + about strange numbered machines in C3x or C4x series. */ + if (string[0] == 't' && string[1] == 'i') + string += 2; + if (*string == 'C' || *string == 'c') + string++; + if (string[1] < '0' && string[1] > '9') + return false; + + if (*string == '3') + return (info->mach == bfd_mach_c3x); + else if (*string == '4') + return info->mach == bfd_mach_c4x; + + return false; +} + + +const bfd_arch_info_type bfd_tic3x_arch = + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 32, /* 32 bits in a byte. */ + bfd_arch_tic4x, + bfd_mach_c3x, /* Machine number. */ + "c3x", /* Architecture name. */ + "tms320c3x", /* Printable name. */ + 0, /* Alignment power. */ + false, /* Not the default architecture. */ + bfd_default_compatible, + c4x_scan, + 0 + }; + +const bfd_arch_info_type bfd_tic4x_arch = + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 32, /* 32 bits in a byte. */ + bfd_arch_tic4x, + bfd_mach_c4x, /* Machine number. */ + "c4x", /* Architecture name. */ + "tms320c4x", /* Printable name. */ + 0, /* Alignment power. */ + true, /* The default architecture. */ + bfd_default_compatible, + c4x_scan, + &bfd_tic3x_arch, + }; + + diff --git a/bfd/targets.c b/bfd/targets.c index 093490cf687..8d893eb2575 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -683,6 +683,12 @@ extern const bfd_target sparcnetbsd_vec; extern const bfd_target sunos_big_vec; extern const bfd_target tic30_aout_vec; extern const bfd_target tic30_coff_vec; +extern const bfd_target tic4x_coff0_beh_vec; +extern const bfd_target tic4x_coff0_vec; +extern const bfd_target tic4x_coff1_beh_vec; +extern const bfd_target tic4x_coff1_vec; +extern const bfd_target tic4x_coff2_beh_vec; +extern const bfd_target tic4x_coff2_vec; extern const bfd_target tic54x_coff0_beh_vec; extern const bfd_target tic54x_coff0_vec; extern const bfd_target tic54x_coff1_beh_vec; diff --git a/bfd/ticoff.h b/bfd/ticoff.h new file mode 100644 index 00000000000..3b3fef02f1b --- /dev/null +++ b/bfd/ticoff.h @@ -0,0 +1,130 @@ +/* Copyright 2002 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#undef F_LSYMS +#define F_LSYMS F_LSYMS_TICOFF + +static boolean +ticoff0_bad_format_hook (abfd, filehdr) + bfd *abfd; + PTR filehdr; +{ + struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr; + + if (COFF0_BADMAG (*internal_f)) + return false; + + return true; +} + +static boolean +ticoff1_bad_format_hook (abfd, filehdr) + bfd *abfd ATTRIBUTE_UNUSED; + PTR filehdr; +{ + struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr; + + if (COFF1_BADMAG (*internal_f)) + return false; + + return true; +} + +/* Replace the stock _bfd_coff_is_local_label_name + to recognize TI COFF local labels. */ +static boolean +ticoff_bfd_is_local_label_name (abfd, name) + bfd *abfd ATTRIBUTE_UNUSED; + const char *name; +{ + if (TICOFF_LOCAL_LABEL_P(name)) + return true; + return false; +} + +#define coff_bfd_is_local_label_name ticoff_bfd_is_local_label_name + +/* Customize coffcode.h; the default coff_ functions are set up to use COFF2; + coff_bad_format_hook uses BADMAG, so set that for COFF2. The COFF1 + and COFF0 vectors use custom _bad_format_hook procs instead of setting + BADMAG. */ +#define BADMAG(x) COFF2_BADMAG(x) +#include "coffcode.h" + +/* COFF0 differs in file/section header size and relocation entry size. */ +static const bfd_coff_backend_data ticoff0_swap_table = +{ + coff_SWAP_aux_in, coff_SWAP_sym_in, coff_SWAP_lineno_in, + coff_SWAP_aux_out, coff_SWAP_sym_out, + coff_SWAP_lineno_out, coff_SWAP_reloc_out, + coff_SWAP_filehdr_out, coff_SWAP_aouthdr_out, + coff_SWAP_scnhdr_out, + FILHSZ_V0, AOUTSZ, SCNHSZ_V01, SYMESZ, AUXESZ, RELSZ_V0, LINESZ, FILNMLEN, +#ifdef COFF_LONG_FILENAMES + true, +#else + false, +#endif +#ifdef COFF_LONG_SECTION_NAMES + true, +#else + false, +#endif + COFF_DEFAULT_SECTION_ALIGNMENT_POWER, + coff_SWAP_filehdr_in, coff_SWAP_aouthdr_in, coff_SWAP_scnhdr_in, + coff_SWAP_reloc_in, ticoff0_bad_format_hook, coff_set_arch_mach_hook, + coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook, + coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook, + coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate, + coff_classify_symbol, coff_compute_section_file_positions, + coff_start_final_link, coff_relocate_section, coff_rtype_to_howto, + coff_adjust_symndx, coff_link_add_one_symbol, + coff_link_output_has_begun, coff_final_link_postscript +}; + +/* COFF1 differs in section header size. */ +static const bfd_coff_backend_data ticoff1_swap_table = +{ + coff_SWAP_aux_in, coff_SWAP_sym_in, coff_SWAP_lineno_in, + coff_SWAP_aux_out, coff_SWAP_sym_out, + coff_SWAP_lineno_out, coff_SWAP_reloc_out, + coff_SWAP_filehdr_out, coff_SWAP_aouthdr_out, + coff_SWAP_scnhdr_out, + FILHSZ, AOUTSZ, SCNHSZ_V01, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN, +#ifdef COFF_LONG_FILENAMES + true, +#else + false, +#endif +#ifdef COFF_LONG_SECTION_NAMES + true, +#else + false, +#endif + COFF_DEFAULT_SECTION_ALIGNMENT_POWER, + coff_SWAP_filehdr_in, coff_SWAP_aouthdr_in, coff_SWAP_scnhdr_in, + coff_SWAP_reloc_in, ticoff1_bad_format_hook, coff_set_arch_mach_hook, + coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook, + coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook, + coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate, + coff_classify_symbol, coff_compute_section_file_positions, + coff_start_final_link, coff_relocate_section, coff_rtype_to_howto, + coff_adjust_symndx, coff_link_add_one_symbol, + coff_link_output_has_begun, coff_final_link_postscript +}; + diff --git a/include/ChangeLog b/include/ChangeLog index 39f18740bd0..e018f1ec506 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,11 @@ +2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * coff/internal.h: Add new relocation types. + * coff/ti.h: Add file-header flags for tic4x code. + * dis-asm.h: Add standard disassembler for tic4x. + * opcode/tic4x.h: New file. + * coff/tic4x.h: New file + 2002-08-07 H.J. Lu <hjl@gnu.org> * bfdlink.h (bfd_link_info): Add allow_undefined_version. diff --git a/include/coff/internal.h b/include/coff/internal.h index 4babbd4de5f..b9b6368f039 100644 --- a/include/coff/internal.h +++ b/include/coff/internal.h @@ -600,6 +600,7 @@ struct internal_reloc }; #define R_DIR16 1 +#define R_REL24 5 #define R_DIR32 6 #define R_IMAGEBASE 7 #define R_RELBYTE 15 @@ -608,12 +609,15 @@ struct internal_reloc #define R_PCRBYTE 18 #define R_PCRWORD 19 #define R_PCRLONG 20 +#define R_PCR24 21 #define R_IPRSHORT 24 #define R_IPRLONG 26 #define R_GETSEG 29 #define R_GETPA 30 #define R_TAGWORD 31 #define R_JUMPTARG 32 /* strange 29k 00xx00xx reloc */ +#define R_PARTLS16 32 +#define R_PARTMS8 33 #define R_PCR16L 128 #define R_PCR26L 129 diff --git a/include/coff/ti.h b/include/coff/ti.h index d98fc89bd1f..0a59b226a32 100644 --- a/include/coff/ti.h +++ b/include/coff/ti.h @@ -118,6 +118,7 @@ struct external_filehdr #define F_RELFLG (0x0001) #define F_EXEC (0x0002) #define F_LNNO (0x0004) +#define F_VERS (0x0010) /* TMS320C4x code */ /* F_LSYMS needs to be redefined in your source file */ #define F_LSYMS_TICOFF (0x0010) /* normal COFF is 0x8 */ diff --git a/include/coff/tic4x.h b/include/coff/tic4x.h new file mode 100644 index 00000000000..03215fb5314 --- /dev/null +++ b/include/coff/tic4x.h @@ -0,0 +1,46 @@ +/* TI COFF information for Texas Instruments TMS320C4X/C3X. + This file customizes the settings in coff/ti.h. + + Copyright 2002 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef COFF_TIC4X_H +#define COFF_TIC4X_H + +#define TIC4X_TARGET_ID 0x0093 +/* Octets per byte, as a power of two. */ +#define TI_TARGET_ID TIC4X_TARGET_ID +#define OCTETS_PER_BYTE_POWER 2 +/* Add to howto to get absolute/sect-relative version. */ +#define HOWTO_BANK 6 +#define TICOFF_TARGET_ARCH bfd_arch_tic4x +/* We use COFF2. */ +#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC + +#define TICOFF_TARGET_MACHINE_GET (FLAGS) \ + (((FLAGS) & F_VERS) ? bfd_mach_c4x : bfd_mach_c3x) + +#define TICOFF_TARGET_MACHINE_SET (FLAGSP, MACHINE) \ + do \ + { \ + if ((MACHINE) == bfd_mach_c4x) \ + *(FLAGSP) = F_VERS; \ + } \ + while (0) + +#include "coff/ti.h" + +#endif /* COFF_TIC4X_H */ diff --git a/include/dis-asm.h b/include/dis-asm.h index 84c436d4f18..0109068f3f8 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -229,6 +229,7 @@ extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_s390 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_tic4x PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic54x PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic80 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); diff --git a/include/opcode/tic4x.h b/include/opcode/tic4x.h new file mode 100644 index 00000000000..68d186d1d0e --- /dev/null +++ b/include/opcode/tic4x.h @@ -0,0 +1,1338 @@ +/* Table of opcodes for the Texas Instruments TMS320C[34]X family. + + Copyright (c) 2002 Free Software Foundation. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* FIXME: Only allow floating point registers for floating point + instructions. Use another field in the instruction table? + This field could also flag which instructions are valid for + which architectures... + e.g., OP_FP | OP_C40 or OP_C40_FP */ + +#define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32) +#define IS_CPU_C4X(v) ((v) == 0 || (v) == 40 || (v) == 44) + +/* Define some bitfield extraction/insertion macros. */ +#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) +#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l)) +#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l)) +#define INSERTU(inst, val, m, l) (inst |= ((val) << (l))) +#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l) + +/* Define register numbers. */ +typedef enum + { + REG_R0, REG_R1, REG_R2, REG_R3, + REG_R4, REG_R5, REG_R6, REG_R7, + REG_AR0, REG_AR1, REG_AR2, REG_AR3, + REG_AR4, REG_AR5, REG_AR6, REG_AR7, + REG_DP, REG_IR0, REG_IR1, REG_BK, + REG_SP, REG_ST, REG_DIE, REG_IIE, + REG_IIF, REG_RS, REG_RE, REG_RC, + REG_R8, REG_R9, REG_R10, REG_R11, + REG_IVTP, REG_TVTP + } +c4x_reg_t; + +/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */ + +#define REG_IE REG_DIE /* C3x only */ +#define REG_IF REG_IIE /* C3x only */ +#define REG_IOF REG_IIF /* C3x only */ + +#define C3X_REG_MAX REG_RC +#define C4X_REG_MAX REG_TVTP + +/* Register table size including C4x expansion regs. */ +#define REG_TABLE_SIZE (C4X_REG_MAX + 1) + +struct c4x_register +{ + char * name; + unsigned long regno; +}; + +typedef struct c4x_register c4x_register_t; + +/* We could store register synonyms here. */ +static const c4x_register_t c3x_registers[] = +{ + {"f0", REG_R0}, + {"r0", REG_R0}, + {"f1", REG_R1}, + {"r1", REG_R1}, + {"f2", REG_R2}, + {"r2", REG_R2}, + {"f3", REG_R3}, + {"r3", REG_R3}, + {"f4", REG_R4}, + {"r4", REG_R4}, + {"f5", REG_R5}, + {"r5", REG_R5}, + {"f6", REG_R6}, + {"r6", REG_R6}, + {"f7", REG_R7}, + {"r7", REG_R7}, + {"ar0", REG_AR0}, + {"ar1", REG_AR1}, + {"ar2", REG_AR2}, + {"ar3", REG_AR3}, + {"ar4", REG_AR4}, + {"ar5", REG_AR5}, + {"ar6", REG_AR6}, + {"ar7", REG_AR7}, + {"dp", REG_DP}, + {"ir0", REG_IR0}, + {"ir1", REG_IR1}, + {"bk", REG_BK}, + {"sp", REG_SP}, + {"st", REG_ST}, + {"ie", REG_IE}, + {"if", REG_IF}, + {"iof", REG_IOF}, + {"rs", REG_RS}, + {"re", REG_RE}, + {"rc", REG_RC}, + {"", 0} +}; + +const unsigned int c3x_num_registers = (((sizeof c3x_registers) / (sizeof c3x_registers[0])) - 1); + +/* Define C4x registers in addition to C3x registers. */ +static const c4x_register_t c4x_registers[] = +{ + {"die", REG_DIE}, /* Clobbers C3x REG_IE */ + {"iie", REG_IIE}, /* Clobbers C3x REG_IF */ + {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */ + {"f8", REG_R8}, + {"r8", REG_R8}, + {"f9", REG_R9}, + {"r9", REG_R9}, + {"f10", REG_R10}, + {"r10", REG_R10}, + {"f11", REG_R11}, + {"r11", REG_R11}, + {"ivtp", REG_IVTP}, + {"tvtp", REG_TVTP}, + {"", 0} +}; + +const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1); + +/* Instruction template. */ +struct c4x_inst +{ + char * name; + unsigned long opcode; + unsigned long opmask; + char * args; +}; + +typedef struct c4x_inst c4x_inst_t; + +/* B condition 16--20 + C condition 23--27 + , required arg follows + ; optional arg follows + General addressing modes + * indirect 0--15 + # direct (for ldp only) 0--15 + @ direct 0--15 + F short float immediate 0--15 + Q register 0--15 + R register 16--20 + S short int immediate 0--15 + D src and dst same reg + Three operand addressing modes + E register 0--7 + G register 8--15 + I indirect(short) 0--7 + J indirect(short) 8--15 + R register 16--20 + W short int (C4x) 0--7 + C indirect(short) (C4x) 0--7 + O indirect(short) (C4x) 8--15 + Parallel instruction addressing modes + E register 0--7 + G register 8--15 + I indirect(short) 0--7 + J indirect(short) 8--15 + K register 19--21 + L register 22--24 + M register (R2,R3) 22--22 + N register (R0,R1) 23--23 + Misc. addressing modes + A address register 22--24 + B unsigned integer 0--23 (absolute on C3x, relative on C4x) + P displacement (PC Rel) 0--15 + U unsigned integer 0--15 + V vector 0--4 (C4x 0--8) + T integer (C4x stik) 16--20 + Y address reg (C4x) 16--20 + X expansion reg (C4x) 0--4 + Z expansion reg (C4x) 16--20. */ + +#define C4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */ +#define C4X_NAME_MAX 16 /* Max number of chars in parallel name. */ + +/* General (two) operand group. */ +#define G_F_r "F,R" +#define G_I_r "S,R" +#define G_L_r "U,R" +#define G_Q_r "*,R" +#define G_T_r "@,R" +#define G_r_r "Q;R" + +/* Three operand group (Type 1 with missing third operand). */ +#define T_rr_ "E,G" +#define T_rS_ "E,J" +#define T_Sr_ "I,G" +#define T_SS_ "I,J" + +/* Three operand group (Type 2 with missing third operand). */ +#define T_Jr_ "W,G" /* C4x only */ +#define T_rJ_ "G,W" /* C4x only (commutative insns only) */ +#define T_Rr_ "C,G" /* C4x only */ +#define T_rR_ "G,C" /* C4x only (commutative insns only) */ +#define T_JR_ "W,O" /* C4x only */ +#define T_RJ_ "O,W" /* C4x only (commutative insns only) */ +#define T_RR_ "C,O" /* C4x only */ + +/* Three operand group (Type 1). */ +#define T_rrr "E,G;R" +#define T_Srr "E,J,R" +#define T_rSr "I,G;R" +#define T_SSr "I,J,R" + +/* Three operand group (Type 2). */ +#define T_Jrr "W,G;R" /* C4x only */ +#define T_rJr "G,W,R" /* C4x only (commutative insns only) */ +#define T_Rrr "C,G;R" /* C4x only */ +#define T_rRr "G,C,R" /* C4x only (commutative insns only) */ +#define T_JRr "W,O,R" /* C4x only */ +#define T_RJr "O,W,R" /* C4x only (commutative insns only) */ +#define T_RRr "C,O,R" /* C4x only */ + +/* Parallel group (store || op). */ +#define Q_rS_rSr "H,J|K,I,L" +#define Q_rS_Sr "H,J|I,L" +#define Q_rS_Srr "H,J|I,K;L" + +/* Parallel group (op || store). */ +#define P_rSr_rS "K,I,L|H,J" +#define P_Srr_rS "I,K;L|H,J" +#define P_rS_rS "L,I|H,J" + +/* Parallel group (load || load). */ +#define P_Sr_Sr "I,L|J,K" +#define Q_Sr_Sr "J,K|I,L" + +/* Parallel group (store || store). */ +#define P_Sr_rS "I,L|H,J" +#define Q_rS_rS "H,J|L,I" + +/* Parallel group (multiply || add/sub). */ +#define P_SSr_rrr "I,J,N|H,K;M" /* 00 (User manual transposes I,J) */ +#define P_Srr_rSr "J,K;N|H,I,M" /* 01 */ +#define P_rSr_rSr "K,J,N|H,I,M" /* 01 */ +#define P_rrr_SSr "H,K;N|I,J,M" /* 10 (User manual transposes H,K) */ +#define P_Srr_Srr "J,K;N|I,H;M" /* 11 */ +#define P_rSr_Srr "K,J,N|I,H;M" /* 11 */ + +#define Q_rrr_SSr "H,K;M|I,J,N" /* 00 (User manual transposes I,J) */ +#define Q_rSr_Srr "H,I,M|J,K;N" /* 01 */ +#define Q_rSr_rSr "H,I,M|K,J,N" /* 01 */ +#define Q_SSr_rrr "I,J,M|H,K;N" /* 10 (User manual transposes H,K) */ +#define Q_Srr_Srr "I,H;M|J,K;N" /* 11 */ +#define Q_Srr_rSr "I,H;M|K,J,N" /* 11 */ + +/* Define c3x opcodes for assembler and disassembler. */ +static const c4x_inst_t c3x_insts[] = +{ + /* Put synonyms after the desired forms in table so that they get + overwritten in the lookup table. The disassembler will thus + print the `proper' mnemonics. Note that the disassembler + only decodes the 11 MSBs, so instructions like ldp @0x500 will + be printed as ldiu 5, dp. Note that with parallel instructions, + the second part is executed before the first part, unless + the sti1||sti2 form is used. We also allow sti2||sti1 + which is equivalent to the default sti||sti form. + + Put most common forms first to speed up assembler. + + FIXME: Add all the other parallel/load forms, like absf1_stf2 + Perhaps I should have used a few macros...especially with + all the bloat after adding the C4x opcodes...too late now! */ + + /* Parallel instructions. */ + { "absf_stf", 0xc8000000, 0xfe000000, P_Sr_rS }, + { "absi_sti", 0xca000000, 0xfe000000, P_Sr_rS }, + { "addf_mpyf", 0x80000000, 0xff000000, Q_rrr_SSr }, + { "addf_mpyf", 0x81000000, 0xff000000, Q_rSr_Srr }, + { "addf_mpyf", 0x81000000, 0xff000000, Q_rSr_rSr }, + { "addf_mpyf", 0x82000000, 0xff000000, Q_SSr_rrr }, + { "addf_mpyf", 0x83000000, 0xff000000, Q_Srr_Srr }, + { "addf_mpyf", 0x83000000, 0xff000000, Q_Srr_rSr }, + { "addf3_mpyf3", 0x80000000, 0xff000000, Q_rrr_SSr }, + { "addf3_mpyf3", 0x81000000, 0xff000000, Q_rSr_Srr }, + { "addf3_mpyf3", 0x81000000, 0xff000000, Q_rSr_rSr }, + { "addf3_mpyf3", 0x82000000, 0xff000000, Q_SSr_rrr }, + { "addf3_mpyf3", 0x83000000, 0xff000000, Q_Srr_Srr }, + { "addf3_mpyf3", 0x83000000, 0xff000000, Q_Srr_rSr }, + { "addf_stf", 0xcc000000, 0xfe000000, P_Srr_rS }, + { "addf_stf", 0xcc000000, 0xfe000000, P_rSr_rS }, + { "addf3_stf", 0xcc000000, 0xfe000000, P_Srr_rS }, + { "addf3_stf", 0xcc000000, 0xfe000000, P_rSr_rS }, + { "addi_mpyi", 0x88000000, 0xff000000, Q_rrr_SSr }, + { "addi_mpyi", 0x89000000, 0xff000000, Q_rSr_Srr }, + { "addi_mpyi", 0x89000000, 0xff000000, Q_rSr_rSr }, + { "addi_mpyi", 0x8a000000, 0xff000000, Q_SSr_rrr }, + { "addi_mpyi", 0x8b000000, 0xff000000, Q_Srr_Srr }, + { "addi3_mpyi3", 0x88000000, 0xff000000, Q_rrr_SSr }, + { "addi3_mpyi3", 0x89000000, 0xff000000, Q_rSr_Srr }, + { "addi3_mpyi3", 0x8a000000, 0xff000000, Q_SSr_rrr }, + { "addi3_mpyi3", 0x8b000000, 0xff000000, Q_Srr_Srr }, + { "addi3_mpyi3", 0x8b000000, 0xff000000, Q_Srr_rSr }, + { "addi_sti", 0xce000000, 0xfe000000, P_Srr_rS }, + { "addi_sti", 0xce000000, 0xfe000000, P_rSr_rS }, + { "addi3_sti", 0xce000000, 0xfe000000, P_Srr_rS }, + { "addi3_sti", 0xce000000, 0xfe000000, P_rSr_rS }, + { "and_sti", 0xd0000000, 0xfe000000, P_Srr_rS }, + { "and_sti", 0xd0000000, 0xfe000000, P_rSr_rS }, + { "and3_sti", 0xd0000000, 0xfe000000, P_Srr_rS }, + { "and3_sti", 0xd0000000, 0xfe000000, P_rSr_rS }, + { "ash_sti", 0xd2000000, 0xfe000000, P_rSr_rS }, + { "ash3_sti", 0xd2000000, 0xfe000000, P_rSr_rS }, + { "fix_sti", 0xd4000000, 0xfe000000, P_Sr_rS }, + { "float_stf", 0xd6000000, 0xfe000000, P_Sr_rS }, + { "ldf_ldf", 0xc4000000, 0xfe000000, P_Sr_Sr }, + { "ldf1_ldf2", 0xc4000000, 0xfe000000, Q_Sr_Sr }, /* synonym */ + { "ldf2_ldf1", 0xc4000000, 0xfe000000, P_Sr_Sr }, /* synonym */ + { "ldf_stf", 0xd8000000, 0xfe000000, P_Sr_rS }, + { "ldi_ldi", 0xc6000000, 0xfe000000, P_Sr_Sr }, + { "ldi1_ldi2", 0xc6000000, 0xfe000000, Q_Sr_Sr }, /* synonym */ + { "ldi2_ldi1", 0xc6000000, 0xfe000000, P_Sr_Sr }, /* synonym */ + { "ldi_sti", 0xda000000, 0xfe000000, P_Sr_rS }, + { "lsh_sti", 0xdc000000, 0xfe000000, P_rSr_rS }, + { "lsh3_sti", 0xdc000000, 0xfe000000, P_rSr_rS }, + { "mpyf_addf", 0x80000000, 0xff000000, P_SSr_rrr }, + { "mpyf_addf", 0x81000000, 0xff000000, P_Srr_rSr }, + { "mpyf_addf", 0x81000000, 0xff000000, P_rSr_rSr }, + { "mpyf_addf", 0x82000000, 0xff000000, P_rrr_SSr }, + { "mpyf_addf", 0x83000000, 0xff000000, P_Srr_Srr }, + { "mpyf_addf", 0x83000000, 0xff000000, P_rSr_Srr }, + { "mpyf3_addf3", 0x80000000, 0xff000000, P_SSr_rrr }, + { "mpyf3_addf3", 0x81000000, 0xff000000, P_Srr_rSr }, + { "mpyf3_addf3", 0x81000000, 0xff000000, P_rSr_rSr }, + { "mpyf3_addf3", 0x82000000, 0xff000000, P_rrr_SSr }, + { "mpyf3_addf3", 0x83000000, 0xff000000, P_Srr_Srr }, + { "mpyf3_addf3", 0x83000000, 0xff000000, P_rSr_Srr }, + { "mpyf_stf", 0xde000000, 0xfe000000, P_Srr_rS }, + { "mpyf_stf", 0xde000000, 0xfe000000, P_rSr_rS }, + { "mpyf3_stf", 0xde000000, 0xfe000000, P_Srr_rS }, + { "mpyf3_stf", 0xde000000, 0xfe000000, P_rSr_rS }, + { "mpyf_subf", 0x84000000, 0xff000000, P_SSr_rrr }, + { "mpyf_subf", 0x85000000, 0xff000000, P_Srr_rSr }, + { "mpyf_subf", 0x85000000, 0xff000000, P_rSr_rSr }, + { "mpyf_subf", 0x86000000, 0xff000000, P_rrr_SSr }, + { "mpyf_subf", 0x87000000, 0xff000000, P_Srr_Srr }, + { "mpyf_subf", 0x87000000, 0xff000000, P_rSr_Srr }, + { "mpyf3_subf3", 0x84000000, 0xff000000, P_SSr_rrr }, + { "mpyf3_subf3", 0x85000000, 0xff000000, P_Srr_rSr }, + { "mpyf3_subf3", 0x85000000, 0xff000000, P_rSr_rSr }, + { "mpyf3_subf3", 0x86000000, 0xff000000, P_rrr_SSr }, + { "mpyf3_subf3", 0x87000000, 0xff000000, P_Srr_Srr }, + { "mpyf3_subf3", 0x87000000, 0xff000000, P_rSr_Srr }, + { "mpyi_addi", 0x88000000, 0xff000000, P_SSr_rrr }, + { "mpyi_addi", 0x89000000, 0xff000000, P_Srr_rSr }, + { "mpyi_addi", 0x89000000, 0xff000000, P_rSr_rSr }, + { "mpyi_addi", 0x8a000000, 0xff000000, P_rrr_SSr }, + { "mpyi_addi", 0x8b000000, 0xff000000, P_Srr_Srr }, + { "mpyi_addi", 0x8b000000, 0xff000000, P_rSr_Srr }, + { "mpyi3_addi3", 0x88000000, 0xff000000, P_SSr_rrr }, + { "mpyi3_addi3", 0x89000000, 0xff000000, P_Srr_rSr }, + { "mpyi3_addi3", 0x89000000, 0xff000000, P_rSr_rSr }, + { "mpyi3_addi3", 0x8a000000, 0xff000000, P_rrr_SSr }, + { "mpyi3_addi3", 0x8b000000, 0xff000000, P_Srr_Srr }, + { "mpyi3_addi3", 0x8b000000, 0xff000000, P_rSr_Srr }, + { "mpyi_sti", 0xe0000000, 0xfe000000, P_Srr_rS }, + { "mpyi_sti", 0xe0000000, 0xfe000000, P_rSr_rS }, + { "mpyi3_sti", 0xe0000000, 0xfe000000, P_Srr_rS }, + { "mpyi3_sti", 0xe0000000, 0xfe000000, P_rSr_rS }, + { "mpyi_subi", 0x8c000000, 0xff000000, P_SSr_rrr }, + { "mpyi_subi", 0x8d000000, 0xff000000, P_Srr_rSr }, + { "mpyi_subi", 0x8d000000, 0xff000000, P_rSr_rSr }, + { "mpyi_subi", 0x8e000000, 0xff000000, P_rrr_SSr }, + { "mpyi_subi", 0x8f000000, 0xff000000, P_Srr_Srr }, + { "mpyi_subi", 0x8f000000, 0xff000000, P_rSr_Srr }, + { "mpyi3_subi3", 0x8c000000, 0xff000000, P_SSr_rrr }, + { "mpyi3_subi3", 0x8d000000, 0xff000000, P_Srr_rSr }, + { "mpyi3_subi3", 0x8d000000, 0xff000000, P_rSr_rSr }, + { "mpyi3_subi3", 0x8e000000, 0xff000000, P_rrr_SSr }, + { "mpyi3_subi3", 0x8f000000, 0xff000000, P_Srr_Srr }, + { "mpyi3_subi3", 0x8f000000, 0xff000000, P_rSr_Srr }, + { "negf_stf", 0xe2000000, 0xfe000000, P_Sr_rS }, + { "negi_sti", 0xe4000000, 0xfe000000, P_Sr_rS }, + { "not_sti", 0xe6000000, 0xfe000000, P_Sr_rS }, + { "or3_sti", 0xe8000000, 0xfe000000, P_Srr_rS }, + { "or3_sti", 0xe8000000, 0xfe000000, P_rSr_rS }, + { "stf_absf", 0xc8000000, 0xfe000000, Q_rS_Sr }, + { "stf_addf", 0xcc000000, 0xfe000000, Q_rS_Srr }, + { "stf_addf", 0xcc000000, 0xfe000000, Q_rS_rSr }, + { "stf_addf3", 0xcc000000, 0xfe000000, Q_rS_Srr }, + { "stf_addf3", 0xcc000000, 0xfe000000, Q_rS_rSr }, + { "stf_float", 0xd6000000, 0xfe000000, Q_rS_Sr }, + { "stf_mpyf", 0xde000000, 0xfe000000, Q_rS_Srr }, + { "stf_mpyf", 0xde000000, 0xfe000000, Q_rS_rSr }, + { "stf_mpyf3", 0xde000000, 0xfe000000, Q_rS_Srr }, + { "stf_mpyf3", 0xde000000, 0xfe000000, Q_rS_rSr }, + { "stf_negf", 0xe2000000, 0xfe000000, Q_rS_Sr }, + { "stf_stf", 0xc0000000, 0xfe000000, P_rS_rS }, + { "stf1_stf2", 0xc0000000, 0xfe000000, Q_rS_rS }, /* synonym */ + { "stf2_stf1", 0xc0000000, 0xfe000000, P_rS_rS }, /* synonym */ + { "stf_subf", 0xea000000, 0xfe000000, Q_rS_rSr }, + { "stf_subf3", 0xea000000, 0xfe000000, Q_rS_rSr }, + { "sti_absi", 0xca000000, 0xfe000000, Q_rS_Sr }, + { "sti_addi", 0xce000000, 0xfe000000, Q_rS_Srr }, + { "sti_addi", 0xce000000, 0xfe000000, Q_rS_rSr }, + { "sti_addi3", 0xce000000, 0xfe000000, Q_rS_Srr }, + { "sti_addi3", 0xce000000, 0xfe000000, Q_rS_rSr }, + { "sti_and", 0xd0000000, 0xfe000000, Q_rS_Srr }, + { "sti_and", 0xd0000000, 0xfe000000, Q_rS_rSr }, + { "sti_and3", 0xd0000000, 0xfe000000, Q_rS_Srr }, + { "sti_and3", 0xd0000000, 0xfe000000, Q_rS_rSr }, + { "sti_ash3", 0xd2000000, 0xfe000000, Q_rS_rSr }, + { "sti_fix", 0xd4000000, 0xfe000000, Q_rS_Sr }, + { "sti_ldi", 0xda000000, 0xfe000000, Q_rS_Sr }, + { "sti_lsh", 0xdc000000, 0xfe000000, Q_rS_rSr }, + { "sti_lsh3", 0xdc000000, 0xfe000000, Q_rS_rSr }, + { "sti_mpyi", 0xe0000000, 0xfe000000, Q_rS_Srr }, + { "sti_mpyi", 0xe0000000, 0xfe000000, Q_rS_rSr }, + { "sti_mpyi3", 0xe0000000, 0xfe000000, Q_rS_Srr }, + { "sti_mpyi3", 0xe0000000, 0xfe000000, Q_rS_rSr }, + { "sti_negi", 0xe4000000, 0xfe000000, Q_rS_Sr }, + { "sti_not", 0xe6000000, 0xfe000000, Q_rS_Sr }, + { "sti_or", 0xe8000000, 0xfe000000, Q_rS_Srr }, + { "sti_or", 0xe8000000, 0xfe000000, Q_rS_rSr }, + { "sti_or3", 0xe8000000, 0xfe000000, Q_rS_Srr }, + { "sti_or3", 0xe8000000, 0xfe000000, Q_rS_rSr }, + { "sti_sti", 0xc2000000, 0xfe000000, P_rS_rS }, + { "sti1_sti2", 0xc2000000, 0xfe000000, Q_rS_rS }, /* synonym */ + { "sti2_sti1", 0xc2000000, 0xfe000000, P_rS_rS }, /* synonym */ + { "sti_subi", 0xec000000, 0xfe000000, Q_rS_rSr }, + { "sti_subi3", 0xec000000, 0xfe000000, Q_rS_rSr }, + { "sti_xor", 0xee000000, 0xfe000000, Q_rS_Srr }, + { "sti_xor", 0xee000000, 0xfe000000, Q_rS_rSr }, + { "sti_xor3", 0xee000000, 0xfe000000, Q_rS_Srr }, + { "sti_xor3", 0xee000000, 0xfe000000, Q_rS_rSr }, + { "subf_mpyf", 0x84000000, 0xff000000, Q_rrr_SSr }, + { "subf_mpyf", 0x85000000, 0xff000000, Q_rSr_Srr }, + { "subf_mpyf", 0x85000000, 0xff000000, Q_rSr_rSr }, + { "subf_mpyf", 0x86000000, 0xff000000, Q_SSr_rrr }, + { "subf_mpyf", 0x87000000, 0xff000000, Q_Srr_Srr }, + { "subf_mpyf", 0x87000000, 0xff000000, Q_Srr_rSr }, + { "subf3_mpyf3", 0x84000000, 0xff000000, Q_rrr_SSr }, + { "subf3_mpyf3", 0x85000000, 0xff000000, Q_rSr_Srr }, + { "subf3_mpyf3", 0x85000000, 0xff000000, Q_rSr_rSr }, + { "subf3_mpyf3", 0x86000000, 0xff000000, Q_SSr_rrr }, + { "subf3_mpyf3", 0x87000000, 0xff000000, Q_Srr_Srr }, + { "subf3_mpyf3", 0x87000000, 0xff000000, Q_Srr_rSr }, + { "subf_stf", 0xea000000, 0xfe000000, P_rSr_rS }, + { "subf3_stf", 0xea000000, 0xfe000000, P_rSr_rS }, + { "subi_mpyi", 0x8c000000, 0xff000000, Q_rrr_SSr }, + { "subi_mpyi", 0x8d000000, 0xff000000, Q_rSr_Srr }, + { "subi_mpyi", 0x8d000000, 0xff000000, Q_rSr_rSr }, + { "subi_mpyi", 0x8e000000, 0xff000000, Q_SSr_rrr }, + { "subi_mpyi", 0x8f000000, 0xff000000, Q_Srr_Srr }, + { "subi_mpyi", 0x8f000000, 0xff000000, Q_Srr_rSr }, + { "subi3_mpyi3", 0x8c000000, 0xff000000, Q_rrr_SSr }, + { "subi3_mpyi3", 0x8d000000, 0xff000000, Q_rSr_Srr }, + { "subi3_mpyi3", 0x8d000000, 0xff000000, Q_rSr_rSr }, + { "subi3_mpyi3", 0x8e000000, 0xff000000, Q_SSr_rrr }, + { "subi3_mpyi3", 0x8f000000, 0xff000000, Q_Srr_Srr }, + { "subi3_mpyi3", 0x8f000000, 0xff000000, Q_Srr_rSr }, + { "subi_sti", 0xec000000, 0xfe000000, P_rSr_rS }, + { "subi3_sti", 0xec000000, 0xfe000000, P_rSr_rS }, + { "xor_sti", 0xee000000, 0xfe000000, P_Srr_rS }, + { "xor_sti", 0xee000000, 0xfe000000, P_rSr_rS }, + { "xor3_sti", 0xee000000, 0xfe000000, P_Srr_rS }, + { "xor3_sti", 0xee000000, 0xfe000000, P_rSr_rS }, + + { "absf", 0x00000000, 0xffe00000, G_r_r }, + { "absf", 0x00200000, 0xffe00000, G_T_r }, + { "absf", 0x00400000, 0xffe00000, G_Q_r }, + { "absf", 0x00600000, 0xffe00000, G_F_r }, + { "absi", 0x00800000, 0xffe00000, G_r_r }, + { "absi", 0x00a00000, 0xffe00000, G_T_r }, + { "absi", 0x00c00000, 0xffe00000, G_Q_r }, + { "absi", 0x00e00000, 0xffe00000, G_I_r }, + { "addc", 0x01000000, 0xffe00000, G_r_r }, + { "addc", 0x01200000, 0xffe00000, G_T_r }, + { "addc", 0x01400000, 0xffe00000, G_Q_r }, + { "addc", 0x01600000, 0xffe00000, G_I_r }, + { "addc", 0x20000000, 0xffe00000, T_rrr }, + { "addc", 0x20200000, 0xffe00000, T_Srr }, + { "addc", 0x20400000, 0xffe00000, T_rSr }, + { "addc", 0x20600000, 0xffe00000, T_SSr }, + { "addc", 0x30000000, 0xffe00000, T_Jrr }, /* C4x */ + { "addc", 0x30000000, 0xffe00000, T_rJr }, /* C4x */ + { "addc", 0x30200000, 0xffe00000, T_rRr }, /* C4x */ + { "addc", 0x30200000, 0xffe00000, T_Rrr }, /* C4x */ + { "addc", 0x30400000, 0xffe00000, T_JRr }, /* C4x */ + { "addc", 0x30400000, 0xffe00000, T_RJr }, /* C4x */ + { "addc", 0x30600000, 0xffe00000, T_RRr }, /* C4x */ + { "addc3", 0x20000000, 0xffe00000, T_rrr }, + { "addc3", 0x20200000, 0xffe00000, T_Srr }, + { "addc3", 0x20400000, 0xffe00000, T_rSr }, + { "addc3", 0x20600000, 0xffe00000, T_SSr }, + { "addc3", 0x30000000, 0xffe00000, T_Jrr }, /* C4x */ + { "addc3", 0x30000000, 0xffe00000, T_rJr }, /* C4x */ + { "addc3", 0x30200000, 0xffe00000, T_rRr }, /* C4x */ + { "addc3", 0x30200000, 0xffe00000, T_Rrr }, /* C4x */ + { "addc3", 0x30400000, 0xffe00000, T_JRr }, /* C4x */ + { "addc3", 0x30400000, 0xffe00000, T_RJr }, /* C4x */ + { "addc3", 0x30600000, 0xffe00000, T_RRr }, /* C4x */ + { "addf", 0x01800000, 0xffe00000, G_r_r }, + { "addf", 0x01a00000, 0xffe00000, G_T_r }, + { "addf", 0x01c00000, 0xffe00000, G_Q_r }, + { "addf", 0x01e00000, 0xffe00000, G_F_r }, + { "addf", 0x20800000, 0xffe00000, T_rrr }, + { "addf", 0x20a00000, 0xffe00000, T_Srr }, + { "addf", 0x20c00000, 0xffe00000, T_rSr }, + { "addf", 0x20e00000, 0xffe00000, T_SSr }, + { "addf", 0x30800000, 0xffe00000, T_Jrr }, /* C4x */ + { "addf", 0x30800000, 0xffe00000, T_rJr }, /* C4x */ + { "addf", 0x30a00000, 0xffe00000, T_rRr }, /* C4x */ + { "addf", 0x30a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "addf", 0x30c00000, 0xffe00000, T_JRr }, /* C4x */ + { "addf", 0x30c00000, 0xffe00000, T_RJr }, /* C4x */ + { "addf", 0x30e00000, 0xffe00000, T_RRr }, /* C4x */ + { "addf3", 0x20800000, 0xffe00000, T_rrr }, + { "addf3", 0x20a00000, 0xffe00000, T_Srr }, + { "addf3", 0x20c00000, 0xffe00000, T_rSr }, + { "addf3", 0x20e00000, 0xffe00000, T_SSr }, + { "addf3", 0x30800000, 0xffe00000, T_Jrr }, /* C4x */ + { "addf3", 0x30800000, 0xffe00000, T_rJr }, /* C4x */ + { "addf3", 0x30a00000, 0xffe00000, T_rRr }, /* C4x */ + { "addf3", 0x30a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "addf3", 0x30c00000, 0xffe00000, T_JRr }, /* C4x */ + { "addf3", 0x30c00000, 0xffe00000, T_RJr }, /* C4x */ + { "addf3", 0x30e00000, 0xffe00000, T_RRr }, /* C4x */ + { "addi", 0x02000000, 0xffe00000, G_r_r }, + { "addi", 0x02200000, 0xffe00000, G_T_r }, + { "addi", 0x02400000, 0xffe00000, G_Q_r }, + { "addi", 0x02600000, 0xffe00000, G_I_r }, + { "addi", 0x21000000, 0xffe00000, T_rrr }, + { "addi", 0x21200000, 0xffe00000, T_Srr }, + { "addi", 0x21400000, 0xffe00000, T_rSr }, + { "addi", 0x21600000, 0xffe00000, T_SSr }, + { "addi", 0x31000000, 0xffe00000, T_Jrr }, /* C4x */ + { "addi", 0x31000000, 0xffe00000, T_rJr }, /* C4x */ + { "addi", 0x31200000, 0xffe00000, T_rRr }, /* C4x */ + { "addi", 0x31200000, 0xffe00000, T_Rrr }, /* C4x */ + { "addi", 0x31400000, 0xffe00000, T_JRr }, /* C4x */ + { "addi", 0x31400000, 0xffe00000, T_RJr }, /* C4x */ + { "addi", 0x31600000, 0xffe00000, T_RRr }, /* C4x */ + { "addi3", 0x21000000, 0xffe00000, T_rrr }, + { "addi3", 0x21200000, 0xffe00000, T_Srr }, + { "addi3", 0x21400000, 0xffe00000, T_rSr }, + { "addi3", 0x21600000, 0xffe00000, T_SSr }, + { "addi3", 0x31000000, 0xffe00000, T_Jrr }, /* C4x */ + { "addi3", 0x31000000, 0xffe00000, T_rJr }, /* C4x */ + { "addi3", 0x31200000, 0xffe00000, T_rRr }, /* C4x */ + { "addi3", 0x31200000, 0xffe00000, T_Rrr }, /* C4x */ + { "addi3", 0x31400000, 0xffe00000, T_JRr }, /* C4x */ + { "addi3", 0x31400000, 0xffe00000, T_RJr }, /* C4x */ + { "addi3", 0x31600000, 0xffe00000, T_RRr }, /* C4x */ + { "and", 0x02800000, 0xffe00000, G_r_r }, + { "and", 0x02a00000, 0xffe00000, G_T_r }, + { "and", 0x02c00000, 0xffe00000, G_Q_r }, + { "and", 0x02e00000, 0xffe00000, G_L_r }, + { "and", 0x21800000, 0xffe00000, T_rrr }, + { "and", 0x21a00000, 0xffe00000, T_Srr }, + { "and", 0x21c00000, 0xffe00000, T_rSr }, + { "and", 0x21e00000, 0xffe00000, T_SSr }, + { "and", 0x31800000, 0xffe00000, T_Jrr }, /* C4x */ + { "and", 0x31800000, 0xffe00000, T_rJr }, /* C4x */ + { "and", 0x31a00000, 0xffe00000, T_rRr }, /* C4x */ + { "and", 0x31a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "and", 0x31c00000, 0xffe00000, T_JRr }, /* C4x */ + { "and", 0x31c00000, 0xffe00000, T_RJr }, /* C4x */ + { "and", 0x31e00000, 0xffe00000, T_RRr }, /* C4x */ + { "and3", 0x21800000, 0xffe00000, T_rrr }, + { "and3", 0x21a00000, 0xffe00000, T_Srr }, + { "and3", 0x21c00000, 0xffe00000, T_rSr }, + { "and3", 0x21e00000, 0xffe00000, T_SSr }, + { "and3", 0x31800000, 0xffe00000, T_Jrr }, /* C4x */ + { "and3", 0x31800000, 0xffe00000, T_rJr }, /* C4x */ + { "and3", 0x31a00000, 0xffe00000, T_rRr }, /* C4x */ + { "and3", 0x31a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "and3", 0x31c00000, 0xffe00000, T_JRr }, /* C4x */ + { "and3", 0x31c00000, 0xffe00000, T_RJr }, /* C4x */ + { "and3", 0x31e00000, 0xffe00000, T_RRr }, /* C4x */ + { "andn", 0x03000000, 0xffe00000, G_r_r }, + { "andn", 0x03200000, 0xffe00000, G_T_r }, + { "andn", 0x03400000, 0xffe00000, G_Q_r }, + { "andn", 0x03600000, 0xffe00000, G_L_r }, + { "andn", 0x22000000, 0xffe00000, T_rrr }, + { "andn", 0x22200000, 0xffe00000, T_Srr }, + { "andn", 0x22400000, 0xffe00000, T_rSr }, + { "andn", 0x22600000, 0xffe00000, T_SSr }, + { "andn", 0x32000000, 0xffe00000, T_Jrr }, /* C4x */ + { "andn", 0x32200000, 0xffe00000, T_Rrr }, /* C4x */ + { "andn", 0x32400000, 0xffe00000, T_JRr }, /* C4x */ + { "andn", 0x32600000, 0xffe00000, T_RRr }, /* C4x */ + { "andn3", 0x22000000, 0xffe00000, T_rrr }, + { "andn3", 0x22200000, 0xffe00000, T_Srr }, + { "andn3", 0x22400000, 0xffe00000, T_rSr }, + { "andn3", 0x22600000, 0xffe00000, T_SSr }, + { "andn3", 0x32000000, 0xffe00000, T_Jrr }, /* C4x */ + { "andn3", 0x32200000, 0xffe00000, T_Rrr }, /* C4x */ + { "andn3", 0x32400000, 0xffe00000, T_JRr }, /* C4x */ + { "andn3", 0x32600000, 0xffe00000, T_RRr }, /* C4x */ + { "ash", 0x03800000, 0xffe00000, G_r_r }, + { "ash", 0x03a00000, 0xffe00000, G_T_r }, + { "ash", 0x03c00000, 0xffe00000, G_Q_r }, + { "ash", 0x03e00000, 0xffe00000, G_I_r }, + { "ash", 0x22800000, 0xffe00000, T_rrr }, + { "ash", 0x22a00000, 0xffe00000, T_Srr }, + { "ash", 0x22c00000, 0xffe00000, T_rSr }, + { "ash", 0x22e00000, 0xffe00000, T_SSr }, + { "ash", 0x32800000, 0xffe00000, T_Jrr }, /* C4x */ + { "ash", 0x32a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "ash", 0x32c00000, 0xffe00000, T_JRr }, /* C4x */ + { "ash", 0x32e00000, 0xffe00000, T_RRr }, /* C4x */ + { "ash3", 0x22800000, 0xffe00000, T_rrr }, + { "ash3", 0x22a00000, 0xffe00000, T_Srr }, + { "ash3", 0x22c00000, 0xffe00000, T_rSr }, + { "ash3", 0x22e00000, 0xffe00000, T_SSr }, + { "ash3", 0x32800000, 0xffe00000, T_Jrr }, /* C4x */ + { "ash3", 0x32a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "ash3", 0x32c00000, 0xffe00000, T_JRr }, /* C4x */ + { "ash3", 0x32e00000, 0xffe00000, T_RRr }, /* C4x */ + { "bB", 0x68000000, 0xffe00000, "Q" }, + { "bB", 0x6a000000, 0xffe00000, "P" }, + { "b", 0x68000000, 0xffe00000, "Q" }, /* synonym for bu */ + { "b", 0x6a000000, 0xffe00000, "P" }, /* synonym for bu */ + { "bBd", 0x68200000, 0xffe00000, "Q" }, + { "bBd", 0x6a200000, 0xffe00000, "P" }, + { "bd", 0x68200000, 0xffe00000, "Q" }, /* synonym for bud */ + { "bd", 0x6a200000, 0xffe00000, "P" }, /* synonym for bud */ + { "br", 0x60000000, 0xff000000, "B" }, + { "brd", 0x61000000, 0xff000000, "B" }, + { "call", 0x62000000, 0xff000000, "B" }, + { "callB", 0x70000000, 0xffe00000, "Q" }, + { "callB", 0x72000000, 0xffe00000, "P" }, + { "cmpf", 0x04000000, 0xffe00000, G_r_r }, + { "cmpf", 0x04200000, 0xffe00000, G_T_r }, + { "cmpf", 0x04400000, 0xffe00000, G_Q_r }, + { "cmpf", 0x04600000, 0xffe00000, G_F_r }, + { "cmpf", 0x23000000, 0xffe00000, T_rr_ }, + { "cmpf", 0x23200000, 0xffe00000, T_rS_ }, + { "cmpf", 0x23400000, 0xffe00000, T_Sr_ }, + { "cmpf", 0x23600000, 0xffe00000, T_SS_ }, + { "cmpf", 0x33200000, 0xffe00000, T_Rr_ }, /* C4x */ + { "cmpf", 0x33600000, 0xffe00000, T_RR_ }, /* C4x */ + { "cmpf3", 0x23000000, 0xffe00000, T_rr_ }, + { "cmpf3", 0x23200000, 0xffe00000, T_rS_ }, + { "cmpf3", 0x23400000, 0xffe00000, T_Sr_ }, + { "cmpf3", 0x23600000, 0xffe00000, T_SS_ }, + { "cmpf3", 0x33200000, 0xffe00000, T_Rr_ }, /* C4x */ + { "cmpf3", 0x33600000, 0xffe00000, T_RR_ }, /* C4x */ + { "cmpi", 0x04800000, 0xffe00000, G_r_r }, + { "cmpi", 0x04a00000, 0xffe00000, G_T_r }, + { "cmpi", 0x04c00000, 0xffe00000, G_Q_r }, + { "cmpi", 0x04e00000, 0xffe00000, G_I_r }, + { "cmpi", 0x23800000, 0xffe00000, T_rr_ }, + { "cmpi", 0x23a00000, 0xffe00000, T_rS_ }, + { "cmpi", 0x23c00000, 0xffe00000, T_Sr_ }, + { "cmpi", 0x23e00000, 0xffe00000, T_SS_ }, + { "cmpi", 0x33800000, 0xffe00000, T_Jr_ }, /* C4x */ + { "cmpi", 0x33a00000, 0xffe00000, T_Rr_ }, /* C4x */ + { "cmpi", 0x33c00000, 0xffe00000, T_JR_ }, /* C4x */ + { "cmpi", 0x33e00000, 0xffe00000, T_RR_ }, /* C4x */ + { "cmpi3", 0x23800000, 0xffe00000, T_rr_ }, + { "cmpi3", 0x23a00000, 0xffe00000, T_rS_ }, + { "cmpi3", 0x23c00000, 0xffe00000, T_Sr_ }, + { "cmpi3", 0x23e00000, 0xffe00000, T_SS_ }, + { "cmpi3", 0x33800000, 0xffe00000, T_Jr_ }, /* C4x */ + { "cmpi3", 0x33a00000, 0xffe00000, T_Rr_ }, /* C4x */ + { "cmpi3", 0x33c00000, 0xffe00000, T_JR_ }, /* C4x */ + { "cmpi3", 0x33e00000, 0xffe00000, T_RR_ }, /* C4x */ + { "dbB", 0x6c000000, 0xfe200000, "A,Q" }, + { "dbB", 0x6e000000, 0xfe200000, "A,P" }, + { "db", 0x6c000000, 0xfe200000, "A,Q" }, /* synonym for dbu */ + { "db", 0x6e000000, 0xfe200000, "A,P" }, /* synonym for dbu */ + { "dbBd", 0x6c200000, 0xfe200000, "A,Q" }, + { "dbBd", 0x6e200000, 0xfe200000, "A,P" }, + { "dbd", 0x6c200000, 0xfe200000, "A,Q" }, /* synonym for dbud */ + { "dbd", 0x6e200000, 0xfe200000, "A,P" }, /* synonym for dbud */ + { "fix", 0x05000000, 0xffe00000, G_r_r }, + { "fix", 0x05200000, 0xffe00000, G_T_r }, + { "fix", 0x05400000, 0xffe00000, G_Q_r }, + { "fix", 0x05600000, 0xffe00000, G_F_r }, + { "float", 0x05800000, 0xffe00000, G_r_r }, + { "float", 0x05a00000, 0xffe00000, G_T_r }, + { "float", 0x05c00000, 0xffe00000, G_Q_r }, + { "float", 0x05e00000, 0xffe00000, G_I_r }, + { "iack", 0x1b200000, 0xffe00000, "@" }, + { "iack", 0x1b400000, 0xffe00000, "*" }, + { "idle", 0x06000000, 0xffffffff, "" }, + { "lde", 0x06800000, 0xffe00000, G_r_r }, + { "lde", 0x06a00000, 0xffe00000, G_T_r }, + { "lde", 0x06c00000, 0xffe00000, G_Q_r }, + { "lde", 0x06e00000, 0xffe00000, G_F_r }, + { "ldf", 0x07000000, 0xffe00000, G_r_r }, + { "ldf", 0x07200000, 0xffe00000, G_T_r }, + { "ldf", 0x07400000, 0xffe00000, G_Q_r }, + { "ldf", 0x07600000, 0xffe00000, G_F_r }, + { "ldfC", 0x40000000, 0xf0600000, G_r_r }, + { "ldfC", 0x40200000, 0xf0600000, G_T_r }, + { "ldfC", 0x40400000, 0xf0600000, G_Q_r }, + { "ldfC", 0x40600000, 0xf0600000, G_F_r }, + { "ldfi", 0x07a00000, 0xffe00000, G_T_r }, + { "ldfi", 0x07c00000, 0xffe00000, G_Q_r }, + { "ldi", 0x08000000, 0xffe00000, G_r_r }, + { "ldi", 0x08200000, 0xffe00000, G_T_r }, + { "ldi", 0x08400000, 0xffe00000, G_Q_r }, + { "ldi", 0x08600000, 0xffe00000, G_I_r }, + { "ldiC", 0x50000000, 0xf0600000, G_r_r }, + { "ldiC", 0x50200000, 0xf0600000, G_T_r }, + { "ldiC", 0x50400000, 0xf0600000, G_Q_r }, + { "ldiC", 0x50600000, 0xf0600000, G_I_r }, + { "ldii", 0x08a00000, 0xffe00000, G_T_r }, + { "ldii", 0x08c00000, 0xffe00000, G_Q_r }, + { "ldp", 0x50700000, 0xffff0000, "#" }, /* synonym for ldiu #,dp */ + { "ldm", 0x09000000, 0xffe00000, G_r_r }, + { "ldm", 0x09200000, 0xffe00000, G_T_r }, + { "ldm", 0x09400000, 0xffe00000, G_Q_r }, + { "ldm", 0x09600000, 0xffe00000, G_F_r }, + { "lsh", 0x09800000, 0xffe00000, G_r_r }, + { "lsh", 0x09a00000, 0xffe00000, G_T_r }, + { "lsh", 0x09c00000, 0xffe00000, G_Q_r }, + { "lsh", 0x09e00000, 0xffe00000, G_I_r }, + { "lsh", 0x24000000, 0xffe00000, T_rrr }, + { "lsh", 0x24200000, 0xffe00000, T_Srr }, + { "lsh", 0x24400000, 0xffe00000, T_rSr }, + { "lsh", 0x24600000, 0xffe00000, T_SSr }, + { "lsh", 0x34000000, 0xffe00000, T_Jrr }, /* C4x */ + { "lsh", 0x34200000, 0xffe00000, T_Rrr }, /* C4x */ + { "lsh", 0x34400000, 0xffe00000, T_JRr }, /* C4x */ + { "lsh", 0x34600000, 0xffe00000, T_RRr }, /* C4x */ + { "lsh3", 0x24000000, 0xffe00000, T_rrr }, + { "lsh3", 0x24200000, 0xffe00000, T_Srr }, + { "lsh3", 0x24400000, 0xffe00000, T_rSr }, + { "lsh3", 0x24600000, 0xffe00000, T_SSr }, + { "lsh3", 0x34000000, 0xffe00000, T_Jrr }, /* C4x */ + { "lsh3", 0x34200000, 0xffe00000, T_Rrr }, /* C4x */ + { "lsh3", 0x34400000, 0xffe00000, T_JRr }, /* C4x */ + { "lsh3", 0x34600000, 0xffe00000, T_RRr }, /* C4x */ + { "mpyf", 0x0a000000, 0xffe00000, G_r_r }, + { "mpyf", 0x0a200000, 0xffe00000, G_T_r }, + { "mpyf", 0x0a400000, 0xffe00000, G_Q_r }, + { "mpyf", 0x0a600000, 0xffe00000, G_F_r }, + { "mpyf", 0x24800000, 0xffe00000, T_rrr }, + { "mpyf", 0x24a00000, 0xffe00000, T_Srr }, + { "mpyf", 0x24c00000, 0xffe00000, T_rSr }, + { "mpyf", 0x24e00000, 0xffe00000, T_SSr }, + { "mpyf", 0x34800000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyf", 0x34800000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyf", 0x34a00000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyf", 0x34a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyf", 0x34c00000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyf", 0x34c00000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyf", 0x34e00000, 0xffe00000, T_RRr }, /* C4x */ + { "mpyf3", 0x24800000, 0xffe00000, T_rrr }, + { "mpyf3", 0x24a00000, 0xffe00000, T_Srr }, + { "mpyf3", 0x24c00000, 0xffe00000, T_rSr }, + { "mpyf3", 0x24e00000, 0xffe00000, T_SSr }, + { "mpyf3", 0x34800000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyf3", 0x34800000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyf3", 0x34a00000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyf3", 0x34a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyf3", 0x34c00000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyf3", 0x34c00000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyf3", 0x34e00000, 0xffe00000, T_RRr }, /* C4x */ + { "mpyi", 0x0a800000, 0xffe00000, G_r_r }, + { "mpyi", 0x0aa00000, 0xffe00000, G_T_r }, + { "mpyi", 0x0ac00000, 0xffe00000, G_Q_r }, + { "mpyi", 0x0ae00000, 0xffe00000, G_I_r }, + { "mpyi", 0x25000000, 0xffe00000, T_rrr }, + { "mpyi", 0x25200000, 0xffe00000, T_Srr }, + { "mpyi", 0x25400000, 0xffe00000, T_rSr }, + { "mpyi", 0x25600000, 0xffe00000, T_SSr }, + { "mpyi", 0x35000000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyi", 0x35000000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyi", 0x35200000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyi", 0x35200000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyi", 0x35400000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyi", 0x35400000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyi", 0x35600000, 0xffe00000, T_RRr }, /* C4x */ + { "mpyi3", 0x25000000, 0xffe00000, T_rrr }, + { "mpyi3", 0x25200000, 0xffe00000, T_Srr }, + { "mpyi3", 0x25400000, 0xffe00000, T_rSr }, + { "mpyi3", 0x25600000, 0xffe00000, T_SSr }, + { "mpyi3", 0x35000000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyi3", 0x35000000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyi3", 0x35200000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyi3", 0x35200000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyi3", 0x35400000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyi3", 0x35400000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyi3", 0x35600000, 0xffe00000, T_RRr }, /* C4x */ + { "negb", 0x0b000000, 0xffe00000, G_r_r }, + { "negb", 0x0b200000, 0xffe00000, G_T_r }, + { "negb", 0x0b400000, 0xffe00000, G_Q_r }, + { "negb", 0x0b600000, 0xffe00000, G_I_r }, + { "negf", 0x0b800000, 0xffe00000, G_r_r }, + { "negf", 0x0ba00000, 0xffe00000, G_T_r }, + { "negf", 0x0bc00000, 0xffe00000, G_Q_r }, + { "negf", 0x0be00000, 0xffe00000, G_F_r }, + { "negi", 0x0c000000, 0xffe00000, G_r_r }, + { "negi", 0x0c200000, 0xffe00000, G_T_r }, + { "negi", 0x0c400000, 0xffe00000, G_Q_r }, + { "negi", 0x0c600000, 0xffe00000, G_I_r }, + { "nop", 0x0c800000, 0xffe00000, "Q" }, + { "nop", 0x0cc00000, 0xffe00000, "*" }, + { "nop", 0x0c800000, 0xffe00000, "" }, + { "norm", 0x0d000000, 0xffe00000, G_r_r }, + { "norm", 0x0d200000, 0xffe00000, G_T_r }, + { "norm", 0x0d400000, 0xffe00000, G_Q_r }, + { "norm", 0x0d600000, 0xffe00000, G_F_r }, + { "not", 0x0d800000, 0xffe00000, G_r_r }, + { "not", 0x0da00000, 0xffe00000, G_T_r }, + { "not", 0x0dc00000, 0xffe00000, G_Q_r }, + { "not", 0x0de00000, 0xffe00000, G_L_r }, + { "or", 0x10000000, 0xffe00000, G_r_r }, + { "or", 0x10200000, 0xffe00000, G_T_r }, + { "or", 0x10400000, 0xffe00000, G_Q_r }, + { "or", 0x10600000, 0xffe00000, G_L_r }, + { "or", 0x25800000, 0xffe00000, T_rrr }, + { "or", 0x25a00000, 0xffe00000, T_Srr }, + { "or", 0x25c00000, 0xffe00000, T_rSr }, + { "or", 0x25e00000, 0xffe00000, T_SSr }, + { "or", 0x35800000, 0xffe00000, T_Jrr }, /* C4x */ + { "or", 0x35800000, 0xffe00000, T_rJr }, /* C4x */ + { "or", 0x35a00000, 0xffe00000, T_rRr }, /* C4x */ + { "or", 0x35a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "or", 0x35c00000, 0xffe00000, T_JRr }, /* C4x */ + { "or", 0x35c00000, 0xffe00000, T_RJr }, /* C4x */ + { "or", 0x35e00000, 0xffe00000, T_RRr }, /* C4x */ + { "or3", 0x25800000, 0xffe00000, T_rrr }, + { "or3", 0x25a00000, 0xffe00000, T_Srr }, + { "or3", 0x25c00000, 0xffe00000, T_rSr }, + { "or3", 0x25e00000, 0xffe00000, T_SSr }, + { "or3", 0x35800000, 0xffe00000, T_Jrr }, /* C4x */ + { "or3", 0x35800000, 0xffe00000, T_rJr }, /* C4x */ + { "or3", 0x35a00000, 0xffe00000, T_rRr }, /* C4x */ + { "or3", 0x35a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "or3", 0x35c00000, 0xffe00000, T_JRr }, /* C4x */ + { "or3", 0x35c00000, 0xffe00000, T_RJr }, /* C4x */ + { "or3", 0x35e00000, 0xffe00000, T_RRr }, /* C4x */ + { "pop", 0x0e200000, 0xffe00000, "R" }, + { "popf", 0x0ea00000, 0xffe00000, "R" }, + { "push", 0x0f200000, 0xffe00000, "R" }, + { "pushf", 0x0fa00000, 0xffe00000, "R" }, + { "retiB", 0x78000000, 0xffe00000, "" }, + { "reti", 0x78000000, 0xffe00000, "" }, /* synonym for reti */ + { "retsB", 0x78800000, 0xffe00000, "" }, + { "rets", 0x78800000, 0xffe00000, "" }, /* synonym for rets */ + { "rnd", 0x11000000, 0xffe00000, G_r_r }, + { "rnd", 0x11200000, 0xffe00000, G_T_r }, + { "rnd", 0x11400000, 0xffe00000, G_Q_r }, + { "rnd", 0x11600000, 0xffe00000, G_F_r }, + { "rol", 0x11e00000, 0xffe00000, "R" }, + { "rolc", 0x12600000, 0xffe00000, "R" }, + { "ror", 0x12e00000, 0xffe00000, "R" }, + { "rorc", 0x13600000, 0xffe00000, "R" }, + { "rptb", 0x64000000, 0xff000000, "B" }, + { "rptb", 0x79000000, 0xff000000, "Q" }, /* C4x */ + { "rpts", 0x139b0000, 0xffff0000, "Q" }, + { "rpts", 0x13bb0000, 0xffff0000, "@" }, + { "rpts", 0x13db0000, 0xffff0000, "*" }, + { "rpts", 0x13fb0000, 0xffff0000, "U" }, + { "sigi", 0x16000000, 0xffe00000, "" }, /* C3x */ + { "sigi", 0x16200000, 0xffe00000, G_T_r }, /* C4x */ + { "sigi", 0x16400000, 0xffe00000, G_Q_r }, /* C4x */ + { "stf", 0x14200000, 0xffe00000, "R,@" }, + { "stf", 0x14400000, 0xffe00000, "R,*" }, + { "stfi", 0x14a00000, 0xffe00000, "R,@" }, + { "stfi", 0x14c00000, 0xffe00000, "R,*" }, + { "sti", 0x15000000, 0xffe00000, "T,@" }, /* C4x only */ + { "sti", 0x15200000, 0xffe00000, "R,@" }, + { "sti", 0x15400000, 0xffe00000, "R,*" }, + { "sti", 0x15600000, 0xffe00000, "T,*" }, /* C4x only */ + { "stii", 0x15a00000, 0xffe00000, "R,@" }, + { "stii", 0x15c00000, 0xffe00000, "R,*" }, + { "subb", 0x16800000, 0xffe00000, G_r_r }, + { "subb", 0x16a00000, 0xffe00000, G_T_r }, + { "subb", 0x16c00000, 0xffe00000, G_Q_r }, + { "subb", 0x16e00000, 0xffe00000, G_I_r }, + { "subb", 0x26000000, 0xffe00000, T_rrr }, + { "subb", 0x26200000, 0xffe00000, T_Srr }, + { "subb", 0x26400000, 0xffe00000, T_rSr }, + { "subb", 0x26600000, 0xffe00000, T_SSr }, + { "subb", 0x36000000, 0xffe00000, T_Jrr }, /* C4x */ + { "subb", 0x36200000, 0xffe00000, T_Rrr }, /* C4x */ + { "subb", 0x36400000, 0xffe00000, T_JRr }, /* C4x */ + { "subb", 0x36600000, 0xffe00000, T_RRr }, /* C4x */ + { "subb3", 0x26000000, 0xffe00000, T_rrr }, + { "subb3", 0x26200000, 0xffe00000, T_Srr }, + { "subb3", 0x26400000, 0xffe00000, T_rSr }, + { "subb3", 0x26600000, 0xffe00000, T_SSr }, + { "subb3", 0x36000000, 0xffe00000, T_Jrr }, /* C4x */ + { "subb3", 0x36200000, 0xffe00000, T_Rrr }, /* C4x */ + { "subb3", 0x36400000, 0xffe00000, T_JRr }, /* C4x */ + { "subb3", 0x36600000, 0xffe00000, T_RRr }, /* C4x */ + { "subc", 0x17000000, 0xffe00000, G_r_r }, + { "subc", 0x17200000, 0xffe00000, G_T_r }, + { "subc", 0x17400000, 0xffe00000, G_Q_r }, + { "subc", 0x17600000, 0xffe00000, G_I_r }, + { "subf", 0x17800000, 0xffe00000, G_r_r }, + { "subf", 0x17a00000, 0xffe00000, G_T_r }, + { "subf", 0x17c00000, 0xffe00000, G_Q_r }, + { "subf", 0x17e00000, 0xffe00000, G_F_r }, + { "subf", 0x26800000, 0xffe00000, T_rrr }, + { "subf", 0x26a00000, 0xffe00000, T_Srr }, + { "subf", 0x26c00000, 0xffe00000, T_rSr }, + { "subf", 0x26e00000, 0xffe00000, T_SSr }, + { "subf", 0x36800000, 0xffe00000, T_Jrr }, /* C4x */ + { "subf", 0x36a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "subf", 0x36c00000, 0xffe00000, T_JRr }, /* C4x */ + { "subf", 0x36e00000, 0xffe00000, T_RRr }, /* C4x */ + { "subf3", 0x26800000, 0xffe00000, T_rrr }, + { "subf3", 0x26a00000, 0xffe00000, T_Srr }, + { "subf3", 0x26c00000, 0xffe00000, T_rSr }, + { "subf3", 0x26e00000, 0xffe00000, T_SSr }, + { "subf3", 0x36800000, 0xffe00000, T_Jrr }, /* C4x */ + { "subf3", 0x36a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "subf3", 0x36c00000, 0xffe00000, T_JRr }, /* C4x */ + { "subf3", 0x36e00000, 0xffe00000, T_RRr }, /* C4x */ + { "subi", 0x18000000, 0xffe00000, G_r_r }, + { "subi", 0x18200000, 0xffe00000, G_T_r }, + { "subi", 0x18400000, 0xffe00000, G_Q_r }, + { "subi", 0x18600000, 0xffe00000, G_I_r }, + { "subi", 0x27000000, 0xffe00000, T_rrr }, + { "subi", 0x27200000, 0xffe00000, T_Srr }, + { "subi", 0x27400000, 0xffe00000, T_rSr }, + { "subi", 0x27600000, 0xffe00000, T_SSr }, + { "subi", 0x37000000, 0xffe00000, T_Jrr }, /* C4x */ + { "subi", 0x37200000, 0xffe00000, T_Rrr }, /* C4x */ + { "subi", 0x37400000, 0xffe00000, T_JRr }, /* C4x */ + { "subi", 0x37600000, 0xffe00000, T_RRr }, /* C4x */ + { "subi3", 0x27000000, 0xffe00000, T_rrr }, + { "subi3", 0x27200000, 0xffe00000, T_Srr }, + { "subi3", 0x27400000, 0xffe00000, T_rSr }, + { "subi3", 0x27600000, 0xffe00000, T_SSr }, + { "subi3", 0x37000000, 0xffe00000, T_Jrr }, /* C4x */ + { "subi3", 0x37200000, 0xffe00000, T_Rrr }, /* C4x */ + { "subi3", 0x37400000, 0xffe00000, T_JRr }, /* C4x */ + { "subi3", 0x37600000, 0xffe00000, T_RRr }, /* C4x */ + { "subrb", 0x18800000, 0xffe00000, G_r_r }, + { "subrb", 0x18a00000, 0xffe00000, G_T_r }, + { "subrb", 0x18c00000, 0xffe00000, G_Q_r }, + { "subrb", 0x18e00000, 0xffe00000, G_I_r }, + { "subrf", 0x19000000, 0xffe00000, G_r_r }, + { "subrf", 0x19200000, 0xffe00000, G_T_r }, + { "subrf", 0x19400000, 0xffe00000, G_Q_r }, + { "subrf", 0x19600000, 0xffe00000, G_F_r }, + { "subri", 0x19800000, 0xffe00000, G_r_r }, + { "subri", 0x19a00000, 0xffe00000, G_T_r }, + { "subri", 0x19c00000, 0xffe00000, G_Q_r }, + { "subri", 0x19e00000, 0xffe00000, G_I_r }, + { "swi", 0x66000000, 0xffffffff, "" }, + { "trapB", 0x74000000, 0xffe00000, "V" }, + { "trap", 0x74000000, 0xffe00000, "V" }, /* synonym for trapu */ + { "tstb", 0x1a000000, 0xffe00000, G_r_r }, + { "tstb", 0x1a200000, 0xffe00000, G_T_r }, + { "tstb", 0x1a400000, 0xffe00000, G_Q_r }, + { "tstb", 0x1a600000, 0xffe00000, G_L_r }, + { "tstb", 0x27800000, 0xffe00000, T_rr_ }, + { "tstb", 0x27a00000, 0xffe00000, T_rS_ }, + { "tstb", 0x27c00000, 0xffe00000, T_Sr_ }, + { "tstb", 0x27e00000, 0xffe00000, T_SS_ }, + { "tstb", 0x37800000, 0xffe00000, T_Jr_ }, /* C4x */ + { "tstb", 0x37800000, 0xffe00000, T_rJ_ }, /* C4x */ + { "tstb", 0x37a00000, 0xffe00000, T_rR_ }, /* C4x */ + { "tstb", 0x37a00000, 0xffe00000, T_Rr_ }, /* C4x */ + { "tstb", 0x37c00000, 0xffe00000, T_JR_ }, /* C4x */ + { "tstb", 0x37c00000, 0xffe00000, T_RJ_ }, /* C4x */ + { "tstb", 0x37e00000, 0xffe00000, T_RR_ }, /* C4x */ + { "tstb3", 0x27800000, 0xffe00000, T_rr_ }, + { "tstb3", 0x27a00000, 0xffe00000, T_rS_ }, + { "tstb3", 0x27c00000, 0xffe00000, T_Sr_ }, + { "tstb3", 0x27e00000, 0xffe00000, T_SS_ }, + { "tstb3", 0x37800000, 0xffe00000, T_Jr_ }, /* C4x */ + { "tstb3", 0x37800000, 0xffe00000, T_rJ_ }, /* C4x */ + { "tstb3", 0x37a00000, 0xffe00000, T_rR_ }, /* C4x */ + { "tstb3", 0x37a00000, 0xffe00000, T_Rr_ }, /* C4x */ + { "tstb3", 0x37c00000, 0xffe00000, T_JR_ }, /* C4x */ + { "tstb3", 0x37c00000, 0xffe00000, T_RJ_ }, /* C4x */ + { "tstb3", 0x37e00000, 0xffe00000, T_RR_ }, /* C4x */ + { "xor", 0x1a800000, 0xffe00000, G_r_r }, + { "xor", 0x1aa00000, 0xffe00000, G_T_r }, + { "xor", 0x1ac00000, 0xffe00000, G_Q_r }, + { "xor", 0x1ae00000, 0xffe00000, G_L_r }, + { "xor", 0x28000000, 0xffe00000, T_rrr }, + { "xor", 0x28200000, 0xffe00000, T_Srr }, + { "xor", 0x28400000, 0xffe00000, T_rSr }, + { "xor", 0x28600000, 0xffe00000, T_SSr }, + { "xor", 0x38000000, 0xffe00000, T_Jrr }, /* C4x */ + { "xor", 0x38000000, 0xffe00000, T_rJr }, /* C4x */ + { "xor", 0x38200000, 0xffe00000, T_rRr }, /* C4x */ + { "xor", 0x38200000, 0xffe00000, T_Rrr }, /* C4x */ + { "xor", 0x3c400000, 0xffe00000, T_JRr }, /* C4x */ + { "xor", 0x3c400000, 0xffe00000, T_RJr }, /* C4x */ + { "xor", 0x3c600000, 0xffe00000, T_RRr }, /* C4x */ + { "xor3", 0x28000000, 0xffe00000, T_rrr }, + { "xor3", 0x28200000, 0xffe00000, T_Srr }, + { "xor3", 0x28400000, 0xffe00000, T_rSr }, + { "xor3", 0x28600000, 0xffe00000, T_SSr }, + { "xor3", 0x38000000, 0xffe00000, T_Jrr }, /* C4x */ + { "xor3", 0x38000000, 0xffe00000, T_rJr }, /* C4x */ + { "xor3", 0x38200000, 0xffe00000, T_rRr }, /* C4x */ + { "xor3", 0x38200000, 0xffe00000, T_Rrr }, /* C4x */ + { "xor3", 0x3c400000, 0xffe00000, T_JRr }, /* C4x */ + { "xor3", 0x3c400000, 0xffe00000, T_RJr }, /* C4x */ + { "xor3", 0x3c600000, 0xffe00000, T_RRr }, /* C4x */ + + /* Dummy entry, not included in c3x_num_insts. This + lets code examine entry i + 1 without checking + if we've run off the end of the table. */ + { "", 0x0, 0x00, "" } +}; + +const unsigned int c3x_num_insts = (((sizeof c3x_insts) / (sizeof c3x_insts[0])) - 1); + +/* Define c4x additional opcodes for assembler and disassembler. */ +static const c4x_inst_t c4x_insts[] = +{ + /* Parallel instructions. */ + { "frieee_stf", 0xf2000000, 0xfe000000, P_Sr_rS }, + { "toieee_stf", 0xf0000000, 0xfe000000, P_Sr_rS }, + + { "bBaf", 0x68a00000, 0xffe00000, "Q" }, + { "bBaf", 0x6aa00000, 0xffe00000, "P" }, + { "baf", 0x68a00000, 0xffe00000, "Q" }, /* synonym for buaf */ + { "baf", 0x6aa00000, 0xffe00000, "P" }, /* synonym for buaf */ + { "bBat", 0x68600000, 0xffe00000, "Q" }, + { "bBat", 0x6a600000, 0xffe00000, "P" }, + { "bat", 0x68600000, 0xffe00000, "Q" }, /* synonym for buat */ + { "bat", 0x6a600000, 0xffe00000, "P" }, /* synonym for buat */ + { "laj", 0x63000000, 0xff000000, "B" }, + { "lajB", 0x70200000, 0xffe00000, "Q" }, + { "lajB", 0x72200000, 0xffe00000, "P" }, + { "latB", 0x74800000, 0xffe00000, "V" }, + + { "frieee", 0x1c000000, 0xffe00000, G_r_r }, + { "frieee", 0x1c200000, 0xffe00000, G_T_r }, + { "frieee", 0x1c400000, 0xffe00000, G_Q_r }, + { "frieee", 0x1c600000, 0xffe00000, G_F_r }, + + { "lb0", 0xb0000000, 0xffe00000, G_r_r }, + { "lb0", 0xb0200000, 0xffe00000, G_T_r }, + { "lb0", 0xb0400000, 0xffe00000, G_Q_r }, + { "lb0", 0xb0600000, 0xffe00000, G_I_r }, + { "lbu0", 0xb2000000, 0xffe00000, G_r_r }, + { "lbu0", 0xb2200000, 0xffe00000, G_T_r }, + { "lbu0", 0xb2400000, 0xffe00000, G_Q_r }, + { "lbu0", 0xb2600000, 0xffe00000, G_L_r }, + { "lb1", 0xb0800000, 0xffe00000, G_r_r }, + { "lb1", 0xb0a00000, 0xffe00000, G_T_r }, + { "lb1", 0xb0c00000, 0xffe00000, G_Q_r }, + { "lb1", 0xb0e00000, 0xffe00000, G_I_r }, + { "lbu1", 0xb2800000, 0xffe00000, G_r_r }, + { "lbu1", 0xb2a00000, 0xffe00000, G_T_r }, + { "lbu1", 0xb2c00000, 0xffe00000, G_Q_r }, + { "lbu1", 0xb2e00000, 0xffe00000, G_L_r }, + { "lb2", 0xb1000000, 0xffe00000, G_r_r }, + { "lb2", 0xb1200000, 0xffe00000, G_T_r }, + { "lb2", 0xb1400000, 0xffe00000, G_Q_r }, + { "lb2", 0xb1600000, 0xffe00000, G_I_r }, + { "lbu2", 0xb3000000, 0xffe00000, G_r_r }, + { "lbu2", 0xb3200000, 0xffe00000, G_T_r }, + { "lbu2", 0xb3400000, 0xffe00000, G_Q_r }, + { "lbu2", 0xb3600000, 0xffe00000, G_L_r }, + { "lb3", 0xb1800000, 0xffe00000, G_r_r }, + { "lb3", 0xb1a00000, 0xffe00000, G_T_r }, + { "lb3", 0xb1c00000, 0xffe00000, G_Q_r }, + { "lb3", 0xb1e00000, 0xffe00000, G_I_r }, + { "lbu3", 0xb3800000, 0xffe00000, G_r_r }, + { "lbu3", 0xb3a00000, 0xffe00000, G_T_r }, + { "lbu3", 0xb3c00000, 0xffe00000, G_Q_r }, + { "lbu3", 0xb3e00000, 0xffe00000, G_L_r }, + { "lda", 0x1e800000, 0xffe00000, "Q,Y" }, + { "lda", 0x1ea00000, 0xffe00000, "@,Y" }, + { "lda", 0x1ec00000, 0xffe00000, "*,Y" }, + { "lda", 0x1ee00000, 0xffe00000, "S,Y" }, + { "ldep", 0x76000000, 0xffe00000, "X,R" }, + { "ldhi", 0x1fe00000, 0xffe00000, G_L_r }, + { "ldhi", 0x1fe00000, 0xffe00000, "#,R" }, + { "ldpe", 0x76800000, 0xffe00000, "Q,Z" }, + { "ldpk", 0x1F700000, 0xffff0000, "#" }, + { "lh0", 0xba000000, 0xffe00000, G_r_r }, + { "lh0", 0xba200000, 0xffe00000, G_T_r }, + { "lh0", 0xba400000, 0xffe00000, G_Q_r }, + { "lh0", 0xba600000, 0xffe00000, G_I_r }, + { "lhu0", 0xbb000000, 0xffe00000, G_r_r }, + { "lhu0", 0xbb200000, 0xffe00000, G_T_r }, + { "lhu0", 0xbb400000, 0xffe00000, G_Q_r }, + { "lhu0", 0xbb600000, 0xffe00000, G_L_r }, + { "lh1", 0xba800000, 0xffe00000, G_r_r }, + { "lh1", 0xbaa00000, 0xffe00000, G_T_r }, + { "lh1", 0xbac00000, 0xffe00000, G_Q_r }, + { "lh1", 0xbae00000, 0xffe00000, G_I_r }, + { "lhu1", 0xbb800000, 0xffe00000, G_r_r }, + { "lhu1", 0xbba00000, 0xffe00000, G_T_r }, + { "lhu1", 0xbbc00000, 0xffe00000, G_Q_r }, + { "lhu1", 0xbbe00000, 0xffe00000, G_L_r }, + { "lwl0", 0xb4000000, 0xffe00000, G_r_r }, + { "lwl0", 0xb4200000, 0xffe00000, G_T_r }, + { "lwl0", 0xb4400000, 0xffe00000, G_Q_r }, + { "lwl0", 0xb4600000, 0xffe00000, G_I_r }, + { "lwl1", 0xb4800000, 0xffe00000, G_r_r }, + { "lwl1", 0xb4a00000, 0xffe00000, G_T_r }, + { "lwl1", 0xb4c00000, 0xffe00000, G_Q_r }, + { "lwl1", 0xb4e00000, 0xffe00000, G_I_r }, + { "lwl2", 0xb5000000, 0xffe00000, G_r_r }, + { "lwl2", 0xb5200000, 0xffe00000, G_T_r }, + { "lwl2", 0xb5400000, 0xffe00000, G_Q_r }, + { "lwl2", 0xb5600000, 0xffe00000, G_I_r }, + { "lwl3", 0xb5800000, 0xffe00000, G_r_r }, + { "lwl3", 0xb5a00000, 0xffe00000, G_T_r }, + { "lwl3", 0xb5c00000, 0xffe00000, G_Q_r }, + { "lwl3", 0xb5e00000, 0xffe00000, G_I_r }, + { "lwr0", 0xb6000000, 0xffe00000, G_r_r }, + { "lwr0", 0xb6200000, 0xffe00000, G_T_r }, + { "lwr0", 0xb6400000, 0xffe00000, G_Q_r }, + { "lwr0", 0xb6600000, 0xffe00000, G_I_r }, + { "lwr1", 0xb6800000, 0xffe00000, G_r_r }, + { "lwr1", 0xb6a00000, 0xffe00000, G_T_r }, + { "lwr1", 0xb6c00000, 0xffe00000, G_Q_r }, + { "lwr1", 0xb6e00000, 0xffe00000, G_I_r }, + { "lwr2", 0xb7000000, 0xffe00000, G_r_r }, + { "lwr2", 0xb7200000, 0xffe00000, G_T_r }, + { "lwr2", 0xb7400000, 0xffe00000, G_Q_r }, + { "lwr2", 0xb7600000, 0xffe00000, G_I_r }, + { "lwr3", 0xb7800000, 0xffe00000, G_r_r }, + { "lwr3", 0xb7a00000, 0xffe00000, G_T_r }, + { "lwr3", 0xb7c00000, 0xffe00000, G_Q_r }, + { "lwr3", 0xb7e00000, 0xffe00000, G_I_r }, + { "mb0", 0xb8000000, 0xffe00000, G_r_r }, + { "mb0", 0xb8200000, 0xffe00000, G_T_r }, + { "mb0", 0xb8400000, 0xffe00000, G_Q_r }, + { "mb0", 0xb8600000, 0xffe00000, G_I_r }, + { "mb1", 0xb8800000, 0xffe00000, G_r_r }, + { "mb1", 0xb8a00000, 0xffe00000, G_T_r }, + { "mb1", 0xb8c00000, 0xffe00000, G_Q_r }, + { "mb1", 0xb8e00000, 0xffe00000, G_I_r }, + { "mb2", 0xb9000000, 0xffe00000, G_r_r }, + { "mb2", 0xb9200000, 0xffe00000, G_T_r }, + { "mb2", 0xb9400000, 0xffe00000, G_Q_r }, + { "mb2", 0xb9600000, 0xffe00000, G_I_r }, + { "mb3", 0xb9800000, 0xffe00000, G_r_r }, + { "mb3", 0xb9a00000, 0xffe00000, G_T_r }, + { "mb3", 0xb9c00000, 0xffe00000, G_Q_r }, + { "mb3", 0xb9e00000, 0xffe00000, G_I_r }, + { "mh0", 0xbc000000, 0xffe00000, G_r_r }, + { "mh0", 0xbc200000, 0xffe00000, G_T_r }, + { "mh0", 0xbc400000, 0xffe00000, G_Q_r }, + { "mh0", 0xbc600000, 0xffe00000, G_I_r }, + { "mh1", 0xbc800000, 0xffe00000, G_r_r }, + { "mh1", 0xbca00000, 0xffe00000, G_T_r }, + { "mh1", 0xbcc00000, 0xffe00000, G_Q_r }, + { "mh1", 0xbce00000, 0xffe00000, G_I_r }, + { "mh2", 0xbd000000, 0xffe00000, G_r_r }, + { "mh2", 0xbd200000, 0xffe00000, G_T_r }, + { "mh2", 0xbd400000, 0xffe00000, G_Q_r }, + { "mh2", 0xbd600000, 0xffe00000, G_I_r }, + { "mh3", 0xbd800000, 0xffe00000, G_r_r }, + { "mh3", 0xbda00000, 0xffe00000, G_T_r }, + { "mh3", 0xbdc00000, 0xffe00000, G_Q_r }, + { "mh3", 0xbde00000, 0xffe00000, G_I_r }, + { "mpyshi", 0x1d800000, 0xffe00000, G_r_r }, + { "mpyshi", 0x1da00000, 0xffe00000, G_T_r }, + { "mpyshi", 0x1dc00000, 0xffe00000, G_Q_r }, + { "mpyshi", 0x1de00000, 0xffe00000, G_I_r }, + { "mpyshi", 0x28800000, 0xffe00000, T_rrr }, + { "mpyshi", 0x28a00000, 0xffe00000, T_Srr }, + { "mpyshi", 0x28c00000, 0xffe00000, T_rSr }, + { "mpyshi", 0x28e00000, 0xffe00000, T_SSr }, + { "mpyshi", 0x38800000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyshi", 0x38800000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyshi", 0x38a00000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyshi", 0x38a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyshi", 0x38c00000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyshi", 0x38c00000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyshi", 0x38e00000, 0xffe00000, T_RRr }, /* C4x */ + { "mpyshi3", 0x28800000, 0xffe00000, T_rrr }, + { "mpyshi3", 0x28a00000, 0xffe00000, T_Srr }, + { "mpyshi3", 0x28c00000, 0xffe00000, T_rSr }, + { "mpyshi3", 0x28e00000, 0xffe00000, T_SSr }, + { "mpyshi3", 0x38800000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyshi3", 0x38800000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyshi3", 0x38a00000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyshi3", 0x38a00000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyshi3", 0x38c00000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyshi3", 0x38c00000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyshi3", 0x38e00000, 0xffe00000, T_RRr }, /* C4x */ + { "mpyuhi", 0x1e000000, 0xffe00000, G_r_r }, + { "mpyuhi", 0x1e200000, 0xffe00000, G_T_r }, + { "mpyuhi", 0x1e400000, 0xffe00000, G_Q_r }, + { "mpyuhi", 0x1e600000, 0xffe00000, G_I_r }, + { "mpyuhi", 0x29000000, 0xffe00000, T_rrr }, + { "mpyuhi", 0x29200000, 0xffe00000, T_Srr }, + { "mpyuhi", 0x29400000, 0xffe00000, T_rSr }, + { "mpyuhi", 0x29600000, 0xffe00000, T_SSr }, + { "mpyuhi", 0x39000000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyuhi", 0x39000000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyuhi", 0x39200000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyuhi", 0x39200000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyuhi", 0x39400000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyuhi", 0x39400000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyuhi", 0x39600000, 0xffe00000, T_RRr }, /* C4x */ + { "mpyuhi3", 0x29000000, 0xffe00000, T_rrr }, + { "mpyuhi3", 0x29200000, 0xffe00000, T_Srr }, + { "mpyuhi3", 0x29400000, 0xffe00000, T_rSr }, + { "mpyuhi3", 0x29600000, 0xffe00000, T_SSr }, + { "mpyuhi3", 0x39000000, 0xffe00000, T_Jrr }, /* C4x */ + { "mpyuhi3", 0x39000000, 0xffe00000, T_rJr }, /* C4x */ + { "mpyuhi3", 0x39200000, 0xffe00000, T_rRr }, /* C4x */ + { "mpyuhi3", 0x39200000, 0xffe00000, T_Rrr }, /* C4x */ + { "mpyuhi3", 0x39400000, 0xffe00000, T_JRr }, /* C4x */ + { "mpyuhi3", 0x39400000, 0xffe00000, T_RJr }, /* C4x */ + { "mpyuhi3", 0x39600000, 0xffe00000, T_RRr }, /* C4x */ + { "rcpf", 0x1d000000, 0xffe00000, G_r_r }, + { "rcpf", 0x1d200000, 0xffe00000, G_T_r }, + { "rcpf", 0x1d400000, 0xffe00000, G_Q_r }, + { "rcpf", 0x1d600000, 0xffe00000, G_F_r }, + { "retiBd", 0x78200000, 0xffe00000, "" }, + { "retid", 0x78200000, 0xffe00000, "" }, /* synonym for retiud */ + { "rptbd", 0x79800000, 0xff000000, "Q" }, + { "rptbd", 0x65000000, 0xff000000, "B" }, + { "rsqrf", 0x1c800000, 0xffe00000, G_r_r }, + { "rsqrf", 0x1ca00000, 0xffe00000, G_T_r }, + { "rsqrf", 0x1cc00000, 0xffe00000, G_Q_r }, + { "rsqrf", 0x1ce00000, 0xffe00000, G_F_r }, + { "stik", 0x15000000, 0xffe00000, "T,@" }, + { "stik", 0x15600000, 0xffe00000, "T,*" }, + { "toieee", 0x1b800000, 0xffe00000, G_r_r }, + { "toieee", 0x1ba00000, 0xffe00000, G_T_r }, + { "toieee", 0x1bc00000, 0xffe00000, G_Q_r }, + { "toieee", 0x1be00000, 0xffe00000, G_F_r }, + { "idle2", 0x06000001, 0xffffffff, "" }, + + /* Dummy entry, not included in num_insts. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0, 0x00, "" } +}; + +const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1); + + +struct c4x_cond +{ + char * name; + unsigned long cond; +}; + +typedef struct c4x_cond c4x_cond_t; + +/* Define conditional branch/load suffixes. Put desired form for + disassembler last. */ +static const c4x_cond_t c4x_conds[] = +{ + { "u", 0x00 }, + { "c", 0x01 }, { "lo", 0x01 }, + { "ls", 0x02 }, + { "hi", 0x03 }, + { "nc", 0x04 }, { "hs", 0x04 }, + { "z", 0x05 }, { "eq", 0x05 }, + { "nz", 0x06 }, { "ne", 0x06 }, + { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 }, + { "le", 0x08 }, + { "p", 0x09 }, { "gt", 0x09 }, + { "nn", 0x0a }, { "ge", 0x0a }, + { "nv", 0x0c }, + { "v", 0x0d }, + { "nuf", 0x0e }, + { "uf", 0x0f }, + { "nlv", 0x10 }, + { "lv", 0x11 }, + { "nluf", 0x12 }, + { "luf", 0x13 }, + { "zuf", 0x14 }, + /* Dummy entry, not included in num_conds. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1); + +struct c4x_indirect +{ + char * name; + unsigned long modn; +}; + +typedef struct c4x_indirect c4x_indirect_t; + +/* Define indirect addressing modes where: + d displacement (signed) + y ir0 + z ir1 */ + +static const c4x_indirect_t c4x_indirects[] = +{ + { "*+a(d)", 0x00 }, + { "*-a(d)", 0x01 }, + { "*++a(d)", 0x02 }, + { "*--a(d)", 0x03 }, + { "*a++(d)", 0x04 }, + { "*a--(d)", 0x05 }, + { "*a++(d)%", 0x06 }, + { "*a--(d)%", 0x07 }, + { "*+a(y)", 0x08 }, + { "*-a(y)", 0x09 }, + { "*++a(y)", 0x0a }, + { "*--a(y)", 0x0b }, + { "*a++(y)", 0x0c }, + { "*a--(y)", 0x0d }, + { "*a++(y)%", 0x0e }, + { "*a--(y)%", 0x0f }, + { "*+a(z)", 0x10 }, + { "*-a(z)", 0x11 }, + { "*++a(z)", 0x12 }, + { "*--a(z)", 0x13 }, + { "*a++(z)", 0x14 }, + { "*a--(z)", 0x15 }, + { "*a++(z)%", 0x16 }, + { "*a--(z)%", 0x17 }, + { "*a", 0x18 }, + { "*a++(y)b", 0x19 }, + /* Dummy entry, not included in num_indirects. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +#define C3X_MODN_MAX 0x19 + +const unsigned int num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8bbcdffb45b..7fd83af1707 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,16 @@ +2002-08-28 Svein E. Seldal <Svein.Seldal@solidas.com> + + * configure.in: Added bfd_tic4x_arch. + * configure: Regenerate. + * Makefile.am: Added tic4x-dis.o target. + * Makefile.in: Regenerate. + +2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * disassemble.c: Added tic4x target and c4x + disassembler routine. + * tic4x-dis.c: New file. + 2002-08-16 Christian Groessler <chris@groessler.org> * z8k-dis.c (unparse_instr): case CLASS_BA: Designate hex diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index d2f043cf7d7..d2c21434f00 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -140,6 +140,7 @@ CFILES = \ sparc-dis.c \ sparc-opc.c \ tic30-dis.c \ + tic4x-dis.c \ tic54x-dis.c \ tic54x-opc.c \ tic80-dis.c \ @@ -243,6 +244,7 @@ ALL_MACHINES = \ sparc-dis.lo \ sparc-opc.lo \ tic30-dis.lo \ + tic4x-dis.lo \ tic54x-dis.lo \ tic54x-opc.lo \ tic80-dis.lo \ @@ -721,6 +723,8 @@ sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h +tic4x-dis.lo: tic4x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic4x.h tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index c2a5c5afc5e..634161834a3 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -251,6 +251,7 @@ CFILES = \ sparc-dis.c \ sparc-opc.c \ tic30-dis.c \ + tic4x-dis.c \ tic54x-dis.c \ tic54x-opc.c \ tic80-dis.c \ @@ -355,6 +356,7 @@ ALL_MACHINES = \ sparc-dis.lo \ sparc-opc.lo \ tic30-dis.lo \ + tic4x-dis.lo \ tic54x-dis.lo \ tic54x-opc.lo \ tic80-dis.lo \ @@ -447,7 +449,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) -TAR = tar +TAR = gtar GZIP_ENV = --best SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES) OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS) @@ -1217,6 +1219,8 @@ sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h +tic4x-dis.lo: tic4x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic4x.h tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h diff --git a/opcodes/configure b/opcodes/configure index 9b6992b1fca..6825a0b020b 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -4654,6 +4654,7 @@ if test x${all_targets} = xfalse ; then bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; bfd_tahoe_arch) ;; bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 3ce5e379218..0e5eb6f5fb4 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -229,6 +229,7 @@ if test x${all_targets} = xfalse ; then bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; bfd_tahoe_arch) ;; bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 88fa63573a6..4d78a73b403 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -60,6 +60,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_sh #define ARCH_sparc #define ARCH_tic30 +#define ARCH_tic4x #define ARCH_tic54x #define ARCH_tic80 #define ARCH_v850 @@ -305,6 +306,11 @@ disassembler (abfd) disassemble = print_insn_tic30; break; #endif +#ifdef ARCH_tic4x + case bfd_arch_tic4x: + disassemble = print_insn_tic4x; + break; +#endif #ifdef ARCH_tic54x case bfd_arch_tic54x: disassemble = print_insn_tic54x; diff --git a/opcodes/tic4x-dis.c b/opcodes/tic4x-dis.c new file mode 100644 index 00000000000..eff4ebb8ff1 --- /dev/null +++ b/opcodes/tic4x-dis.c @@ -0,0 +1,677 @@ +/* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils. + + Copyright 2002 Free Software Foundation, Inc. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include <math.h> +#include "libiberty.h" +#include "dis-asm.h" +#include "opcode/tic4x.h" + +#define C4X_DEBUG 0 + +#define C4X_HASH_SIZE 11 /* 11 and above should give unique entries. */ + +typedef enum + { + IMMED_SINT, + IMMED_SUINT, + IMMED_SFLOAT, + IMMED_INT, + IMMED_UINT, + IMMED_FLOAT + } +immed_t; + +typedef enum + { + INDIRECT_SHORT, + INDIRECT_LONG, + INDIRECT_C4X + } +indirect_t; + +static int c4x_version = 0; +static int c4x_dp = 0; + +static int +c4x_pc_offset (unsigned int op) +{ + /* Determine the PC offset for a C[34]x instruction. + This could be simplified using some boolean algebra + but at the expense of readability. */ + switch (op >> 24) + { + case 0x60: /* br */ + case 0x62: /* call (C4x) */ + case 0x64: /* rptb (C4x) */ + return 1; + case 0x61: /* brd */ + case 0x63: /* laj */ + case 0x65: /* rptbd (C4x) */ + return 3; + case 0x66: /* swi */ + case 0x67: + return 0; + default: + break; + } + + switch ((op & 0xffe00000) >> 20) + { + case 0x6a0: /* bB */ + case 0x720: /* callB */ + case 0x740: /* trapB */ + return 1; + + case 0x6a2: /* bBd */ + case 0x6a6: /* bBat */ + case 0x6aa: /* bBaf */ + case 0x722: /* lajB */ + case 0x748: /* latB */ + case 0x798: /* rptbd */ + return 3; + + default: + break; + } + + switch ((op & 0xfe200000) >> 20) + { + case 0x6e0: /* dbB */ + return 1; + + case 0x6e2: /* dbBd */ + return 3; + + default: + break; + } + + return 0; +} + +static int +c4x_print_char (struct disassemble_info * info, char ch) +{ + if (info != NULL) + (*info->fprintf_func) (info->stream, "%c", ch); + return 1; +} + +static int +c4x_print_str (struct disassemble_info *info, char *str) +{ + if (info != NULL) + (*info->fprintf_func) (info->stream, "%s", str); + return 1; +} + +static int +c4x_print_register (struct disassemble_info *info, + unsigned long regno) +{ + static c4x_register_t **registertable = NULL; + unsigned int i; + + if (registertable == NULL) + { + registertable = (c4x_register_t **) + xmalloc (sizeof (c4x_register_t *) * REG_TABLE_SIZE); + for (i = 0; i < c3x_num_registers; i++) + registertable[c3x_registers[i].regno] = (void *)&c3x_registers[i]; + if (IS_CPU_C4X (c4x_version)) + { + /* Add C4x additional registers, overwriting + any C3x registers if necessary. */ + for (i = 0; i < c4x_num_registers; i++) + registertable[c4x_registers[i].regno] = (void *)&c4x_registers[i]; + } + } + if ((int) regno > (IS_CPU_C4X (c4x_version) ? C4X_REG_MAX : C3X_REG_MAX)) + return 0; + if (info != NULL) + (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name); + return 1; +} + +static int +c4x_print_addr (struct disassemble_info *info, + unsigned long addr) +{ + if (info != NULL) + (*info->print_address_func)(addr, info); + return 1; +} + +static int +c4x_print_relative (struct disassemble_info *info, + unsigned long pc, + long offset, + unsigned long opcode) +{ + return c4x_print_addr (info, pc + offset + c4x_pc_offset (opcode)); +} + +static int +c4x_print_direct (struct disassemble_info *info, + unsigned long arg) +{ + if (info != NULL) + { + (*info->fprintf_func) (info->stream, "@"); + c4x_print_addr (info, arg + (c4x_dp << 16)); + } + return 1; +} + +/* FIXME: make the floating point stuff not rely on host + floating point arithmetic. */ +void +c4x_print_ftoa (unsigned int val, + FILE *stream, + int (*pfunc)()) +{ + int e; + int s; + int f; + double num = 0.0; + + e = EXTRS (val, 31, 24); /* exponent */ + if (e != -128) + { + s = EXTRU (val, 23, 23); /* sign bit */ + f = EXTRU (val, 22, 0); /* mantissa */ + if (s) + f += -2 * (1 << 23); + else + f += (1 << 23); + num = f / (double)(1 << 23); + num = ldexp (num, e); + } + (*pfunc)(stream, "%.9g", num); +} + +static int +c4x_print_immed (struct disassemble_info *info, + immed_t type, + unsigned long arg) +{ + int s; + int f; + int e; + double num = 0.0; + + if (info == NULL) + return 1; + switch (type) + { + case IMMED_SINT: + case IMMED_INT: + (*info->fprintf_func) (info->stream, "%d", (long)arg); + break; + + case IMMED_SUINT: + case IMMED_UINT: + (*info->fprintf_func) (info->stream, "%u", arg); + break; + + case IMMED_SFLOAT: + e = EXTRS (arg, 15, 12); + if (e != -8) + { + s = EXTRU (arg, 11, 11); + f = EXTRU (arg, 10, 0); + if (s) + f += -2 * (1 << 11); + else + f += (1 << 11); + num = f / (double)(1 << 11); + num = ldexp (num, e); + } + (*info->fprintf_func) (info->stream, "%f", num); + break; + case IMMED_FLOAT: + e = EXTRS (arg, 31, 24); + if (e != -128) + { + s = EXTRU (arg, 23, 23); + f = EXTRU (arg, 22, 0); + if (s) + f += -2 * (1 << 23); + else + f += (1 << 23); + num = f / (double)(1 << 23); + num = ldexp (num, e); + } + (*info->fprintf_func) (info->stream, "%f", num); + break; + } + return 1; +} + +static int +c4x_print_cond (struct disassemble_info *info, + unsigned int cond) +{ + static c4x_cond_t **condtable = NULL; + unsigned int i; + + if (condtable == NULL) + { + condtable = (c4x_cond_t **)xmalloc (sizeof (c4x_cond_t *) * 32); + for (i = 0; i < num_conds; i++) + condtable[c4x_conds[i].cond] = (void *)&c4x_conds[i]; + } + if (cond > 31 || condtable[cond] == NULL) + return 0; + if (info != NULL) + (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name); + return 1; +} + +static int +c4x_print_indirect (struct disassemble_info *info, + indirect_t type, + unsigned long arg) +{ + unsigned int aregno; + unsigned int modn; + unsigned int disp; + char *a; + + aregno = 0; + modn = 0; + disp = 1; + switch(type) + { + case INDIRECT_C4X: /* *+ARn(disp) */ + disp = EXTRU (arg, 7, 3); + aregno = EXTRU (arg, 2, 0) + REG_AR0; + modn = 0; + break; + case INDIRECT_SHORT: + disp = 1; + aregno = EXTRU (arg, 2, 0) + REG_AR0; + modn = EXTRU (arg, 7, 3); + break; + case INDIRECT_LONG: + disp = EXTRU (arg, 7, 0); + aregno = EXTRU (arg, 10, 8) + REG_AR0; + modn = EXTRU (arg, 15, 11); + if (modn > 7 && disp != 0) + return 0; + break; + default: + abort (); + } + if (modn > C3X_MODN_MAX) + return 0; + a = c4x_indirects[modn].name; + while (*a) + { + switch (*a) + { + case 'a': + c4x_print_register (info, aregno); + break; + case 'd': + c4x_print_immed (info, IMMED_UINT, disp); + break; + case 'y': + c4x_print_str (info, "ir0"); + break; + case 'z': + c4x_print_str (info, "ir1"); + break; + default: + c4x_print_char (info, *a); + break; + } + a++; + } + return 1; +} + +static int +c4x_print_op (struct disassemble_info *info, + unsigned long instruction, + c4x_inst_t *p, unsigned long pc) +{ + int val; + char *s; + char *parallel = NULL; + + /* Print instruction name. */ + s = p->name; + while (*s && parallel == NULL) + { + switch (*s) + { + case 'B': + if (! c4x_print_cond (info, EXTRU (instruction, 20, 16))) + return 0; + break; + case 'C': + if (! c4x_print_cond (info, EXTRU (instruction, 27, 23))) + return 0; + break; + case '_': + parallel = s + 1; /* Skip past `_' in name */ + break; + default: + c4x_print_char (info, *s); + break; + } + s++; + } + + /* Print arguments. */ + s = p->args; + if (*s) + c4x_print_char (info, ' '); + + while (*s) + { + switch (*s) + { + case '*': /* indirect 0--15 */ + if (! c4x_print_indirect (info, INDIRECT_LONG, + EXTRU (instruction, 15, 0))) + return 0; + break; + + case '#': /* only used for ldp, ldpk */ + c4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); + break; + + case '@': /* direct 0--15 */ + c4x_print_direct (info, EXTRU (instruction, 15, 0)); + break; + + case 'A': /* address register 24--22 */ + if (! c4x_print_register (info, EXTRU (instruction, 24, 22) + + REG_AR0)) + return 0; + break; + + case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb + address 0--23. */ + if (IS_CPU_C4X (c4x_version)) + c4x_print_relative (info, pc, EXTRS (instruction, 23, 0), + p->opcode); + else + c4x_print_addr (info, EXTRU (instruction, 23, 0)); + break; + + case 'C': /* indirect (short C4x) 0--7 */ + if (! IS_CPU_C4X (c4x_version)) + return 0; + if (! c4x_print_indirect (info, INDIRECT_C4X, + EXTRU (instruction, 7, 0))) + return 0; + break; + + case 'D': + /* Cockup if get here... */ + break; + + case 'E': /* register 0--7 */ + if (! c4x_print_register (info, EXTRU (instruction, 7, 0))) + return 0; + break; + + case 'F': /* 16-bit float immediate 0--15 */ + c4x_print_immed (info, IMMED_SFLOAT, + EXTRU (instruction, 15, 0)); + break; + + case 'I': /* indirect (short) 0--7 */ + if (! c4x_print_indirect (info, INDIRECT_SHORT, + EXTRU (instruction, 7, 0))) + return 0; + break; + + case 'J': /* indirect (short) 8--15 */ + if (! c4x_print_indirect (info, INDIRECT_SHORT, + EXTRU (instruction, 15, 8))) + return 0; + break; + + case 'G': /* register 8--15 */ + if (! c4x_print_register (info, EXTRU (instruction, 15, 8))) + return 0; + break; + + case 'H': /* register 16--18 */ + if (! c4x_print_register (info, EXTRU (instruction, 18, 16))) + return 0; + break; + + case 'K': /* register 19--21 */ + if (! c4x_print_register (info, EXTRU (instruction, 21, 19))) + return 0; + break; + + case 'L': /* register 22--24 */ + if (! c4x_print_register (info, EXTRU (instruction, 24, 22))) + return 0; + break; + + case 'M': /* register 22--22 */ + c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2); + break; + + case 'N': /* register 23--23 */ + c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R0); + break; + + case 'O': /* indirect (short C4x) 8--15 */ + if (! IS_CPU_C4X (c4x_version)) + return 0; + if (! c4x_print_indirect (info, INDIRECT_C4X, + EXTRU (instruction, 15, 8))) + return 0; + break; + + case 'P': /* displacement 0--15 (used by Bcond and BcondD) */ + c4x_print_relative (info, pc, EXTRS (instruction, 15, 0), + p->opcode); + break; + + case 'Q': /* register 0--15 */ + if (! c4x_print_register (info, EXTRU (instruction, 15, 0))) + return 0; + break; + + case 'R': /* register 16--20 */ + if (! c4x_print_register (info, EXTRU (instruction, 20, 16))) + return 0; + break; + + case 'S': /* 16-bit signed immediate 0--15 */ + c4x_print_immed (info, IMMED_SINT, + EXTRS (instruction, 15, 0)); + break; + + case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */ + if (! IS_CPU_C4X (c4x_version)) + return 0; + if (! c4x_print_immed (info, IMMED_SUINT, + EXTRU (instruction, 20, 16))) + return 0; + break; + + case 'U': /* 16-bit unsigned int immediate 0--15 */ + c4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0)); + break; + + case 'V': /* 5/9-bit unsigned vector 0--4/8 */ + c4x_print_immed (info, IMMED_SUINT, + IS_CPU_C4X (c4x_version) ? + EXTRU (instruction, 8, 0) : + EXTRU (instruction, 4, 0) & ~0x20); + break; + + case 'W': /* 8-bit signed immediate 0--7 */ + if (! IS_CPU_C4X (c4x_version)) + return 0; + c4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0)); + break; + + case 'X': /* expansion register 4--0 */ + val = EXTRU (instruction, 4, 0) + REG_IVTP; + if (val < REG_IVTP || val > REG_TVTP) + return 0; + if (! c4x_print_register (info, val)) + return 0; + break; + + case 'Y': /* address register 16--20 */ + val = EXTRU (instruction, 20, 16); + if (val < REG_AR0 || val > REG_SP) + return 0; + if (! c4x_print_register (info, val)) + return 0; + break; + + case 'Z': /* expansion register 16--20 */ + val = EXTRU (instruction, 20, 16) + REG_IVTP; + if (val < REG_IVTP || val > REG_TVTP) + return 0; + if (! c4x_print_register (info, val)) + return 0; + break; + + case '|': /* Parallel instruction */ + c4x_print_str (info, " || "); + c4x_print_str (info, parallel); + c4x_print_char (info, ' '); + break; + + case ';': + c4x_print_char (info, ','); + break; + + default: + c4x_print_char (info, *s); + break; + } + s++; + } + return 1; +} + +static void +c4x_hash_opcode (c4x_inst_t **optable, + const c4x_inst_t *inst) +{ + int j; + int opcode = inst->opcode >> (32 - C4X_HASH_SIZE); + int opmask = inst->opmask >> (32 - C4X_HASH_SIZE); + + /* Use a C4X_HASH_SIZE bit index as a hash index. We should + have unique entries so there's no point having a linked list + for each entry? */ + for (j = opcode; j < opmask; j++) + if ((j & opmask) == opcode) + { +#if C4X_DEBUG + /* We should only have collisions for synonyms like + ldp for ldi. */ + if (optable[j] != NULL) + printf("Collision at index %d, %s and %s\n", + j, optable[j]->name, inst->name); +#endif + optable[j] = (void *)inst; + } +} + +/* Disassemble the instruction in 'instruction'. + 'pc' should be the address of this instruction, it will + be used to print the target address if this is a relative jump or call + the disassembled instruction is written to 'info'. + The function returns the length of this instruction in words. */ + +static int +c4x_disassemble (unsigned long pc, + unsigned long instruction, + struct disassemble_info *info) +{ + static c4x_inst_t **optable = NULL; + c4x_inst_t *p; + int i; + + c4x_version = info->mach; + + if (optable == NULL) + { + optable = (c4x_inst_t **) + xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE)); + /* Install opcodes in reverse order so that preferred + forms overwrite synonyms. */ + for (i = c3x_num_insts - 1; i >= 0; i--) + c4x_hash_opcode (optable, &c3x_insts[i]); + if (IS_CPU_C4X (c4x_version)) + { + for (i = c4x_num_insts - 1; i >= 0; i--) + c4x_hash_opcode (optable, &c4x_insts[i]); + } + } + + /* See if we can pick up any loading of the DP register... */ + if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70) + c4x_dp = EXTRU (instruction, 15, 0); + + p = optable[instruction >> (32 - C4X_HASH_SIZE)]; + if (p != NULL && ((instruction & p->opmask) == p->opcode) + && c4x_print_op (NULL, instruction, p, pc)) + c4x_print_op (info, instruction, p, pc); + else + (*info->fprintf_func) (info->stream, "%08x", instruction); + + /* Return size of insn in words. */ + return 1; +} + +/* The entry point from objdump and gdb. */ +int +print_insn_tic4x (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status; + unsigned long pc; + unsigned long op; + bfd_byte buffer[4]; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + pc = memaddr; + op = bfd_getl32 (buffer); + info->bytes_per_line = 4; + info->bytes_per_chunk = 4; + info->octets_per_byte = 4; + info->display_endian = BFD_ENDIAN_LITTLE; + return c4x_disassemble (pc, op, info) * 4; +} |