diff options
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 4 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 22 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 260 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 4 |
5 files changed, 250 insertions, 44 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 6f68432fc35..89a231bcec5 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2002-12-31 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Note that the "+D" operand type name is now used. + 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips.h: Document "+" as the start of two-character operand diff --git a/include/opcode/mips.h b/include/opcode/mips.h index ce6ce0812cf..19f3e21519a 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -257,6 +257,8 @@ struct mips_opcode "e" 5 bit vector register byte specifier (OP_*_VECBYTE) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) see also "k" above + "+D" Combined destination register ("G") and sel ("H") for CP0 ops, + for pretty-printing in disassembly only. Macro instructions: "A" General 32 bit expression @@ -287,7 +289,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: - "ABC" + "ABCD" */ /* These are the bits which may be set in the pinfo field of an diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 98a4b3c70af..f33f75d943b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,25 @@ +2002-12-31 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_cp0sel_name): New structure. + (mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2) + (mips_cp0sel_names_sb1): New arrays. + (mips_arch_choice): New structure members "cp0sel_names" and + "cp0sel_names_len". + (mips_arch_choices): Add references to new cp0sel_names arrays + as appropriate, and make all existing entries reference + appropriate mips_XXX_names_numeric arrays rather than simply + using NULL. + (mips_cp0sel_names, mips_cp0sel_names_len): New variables. + (lookup_mips_cp0sel_name): New function. + (set_default_mips_dis_options): Set mips_cp0sel_names and + mips_cp0sel_names_len as appropriate. Remove now-unnecessary + checks for NULL register name arrays. + (parse_mips_dis_option): Likewise. + (print_insn_arg): Handle "+D" operand type. + * mips-opc.c (mips_builtin_opcodes): Add new "+D" variants + of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register + names symbolically. + 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric) diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 71cf6beacb2..a2f68e96667 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -62,6 +62,12 @@ static void print_mips16_insn_arg /* FIXME: These should be shared with gdb somehow. */ +struct mips_cp0sel_name { + unsigned int cp0reg; + unsigned int sel; + const char * const name; +}; + /* The mips16 register names. */ static const char * const mips16_reg_names[] = { "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" @@ -134,6 +140,38 @@ static const char * const mips_cp0_names_mips3264[32] = { "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", }; +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = { + { 16, 1, "c0_config1" }, + { 16, 2, "c0_config2" }, + { 16, 3, "c0_config3" }, + { 18, 1, "c0_watchlo,1" }, + { 18, 2, "c0_watchlo,2" }, + { 18, 3, "c0_watchlo,3" }, + { 18, 4, "c0_watchlo,4" }, + { 18, 5, "c0_watchlo,5" }, + { 18, 6, "c0_watchlo,6" }, + { 18, 7, "c0_watchlo,7" }, + { 19, 1, "c0_watchhi,1" }, + { 19, 2, "c0_watchhi,2" }, + { 19, 3, "c0_watchhi,3" }, + { 19, 4, "c0_watchhi,4" }, + { 19, 5, "c0_watchhi,5" }, + { 19, 6, "c0_watchhi,6" }, + { 19, 7, "c0_watchhi,7" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 27, 1, "c0_cacheerr,1" }, + { 27, 2, "c0_cacheerr,2" }, + { 27, 3, "c0_cacheerr,3" }, + { 28, 1, "c0_datalo" }, + { 29, 1, "c0_datahi" } +}; + static const char * const mips_cp0_names_mips3264r2[32] = { "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", @@ -145,6 +183,60 @@ static const char * const mips_cp0_names_mips3264r2[32] = { "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", }; +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = { + { 4, 1, "c0_contextconfig" }, + { 5, 1, "c0_pagegrain" }, + { 12, 1, "c0_intctl" }, + { 12, 2, "c0_srsctl" }, + { 12, 3, "c0_srsmap" }, + { 15, 1, "c0_ebase" }, + { 16, 1, "c0_config1" }, + { 16, 2, "c0_config2" }, + { 16, 3, "c0_config3" }, + { 18, 1, "c0_watchlo,1" }, + { 18, 2, "c0_watchlo,2" }, + { 18, 3, "c0_watchlo,3" }, + { 18, 4, "c0_watchlo,4" }, + { 18, 5, "c0_watchlo,5" }, + { 18, 6, "c0_watchlo,6" }, + { 18, 7, "c0_watchlo,7" }, + { 19, 1, "c0_watchhi,1" }, + { 19, 2, "c0_watchhi,2" }, + { 19, 3, "c0_watchhi,3" }, + { 19, 4, "c0_watchhi,4" }, + { 19, 5, "c0_watchhi,5" }, + { 19, 6, "c0_watchhi,6" }, + { 19, 7, "c0_watchhi,7" }, + { 23, 1, "c0_tracecontrol" }, + { 23, 2, "c0_tracecontrol2" }, + { 23, 3, "c0_usertracedata" }, + { 23, 4, "c0_tracebpc" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 27, 1, "c0_cacheerr,1" }, + { 27, 2, "c0_cacheerr,2" }, + { 27, 3, "c0_cacheerr,3" }, + { 28, 1, "c0_datalo" }, + { 28, 2, "c0_taglo1" }, + { 28, 3, "c0_datalo1" }, + { 28, 4, "c0_taglo2" }, + { 28, 5, "c0_datalo2" }, + { 28, 6, "c0_taglo3" }, + { 28, 7, "c0_datalo3" }, + { 29, 1, "c0_datahi" }, + { 29, 2, "c0_taghi1" }, + { 29, 3, "c0_datahi1" }, + { 29, 4, "c0_taghi2" }, + { 29, 5, "c0_datahi2" }, + { 29, 6, "c0_taghi3" }, + { 29, 7, "c0_datahi3" }, +}; + /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ static const char * const mips_cp0_names_sb1[32] = { "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", @@ -157,6 +249,30 @@ static const char * const mips_cp0_names_sb1[32] = { "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", }; +static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = { + { 16, 1, "c0_config1" }, + { 18, 1, "c0_watchlo,1" }, + { 19, 1, "c0_watchhi,1" }, + { 22, 0, "c0_perftrace" }, + { 23, 3, "c0_edebug" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 26, 1, "c0_buserr_pa" }, + { 27, 1, "c0_cacheerr_d" }, + { 27, 3, "c0_cacheerr_d_pa" }, + { 28, 1, "c0_datalo_i" }, + { 28, 2, "c0_taglo_d" }, + { 28, 3, "c0_datalo_d" }, + { 29, 1, "c0_datahi_i" }, + { 29, 2, "c0_taghi_d" }, + { 29, 3, "c0_datahi_d" }, +}; + static const char * const mips_hwr_names_numeric[32] = { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", @@ -192,50 +308,54 @@ struct mips_arch_choice { int processor; int isa; const char * const *cp0_names; + const struct mips_cp0sel_name *cp0sel_names; + unsigned int cp0sel_names_len; const char * const *hwr_names; }; -struct mips_arch_choice mips_arch_choices[] = { +const struct mips_arch_choice mips_arch_choices[] = { { "numeric", 0, 0, 0, 0, - mips_cp0_names_numeric, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. Note that MIPS-3D and MDMX are not applicable to MIPS32. (See _MIPS32 Architecture For Programmers Volume I: Introduction to the @@ -243,22 +363,33 @@ struct mips_arch_choice mips_arch_choices[] = { page 1. */ { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, ISA_MIPS32 | INSN_MIPS16, - mips_cp0_names_mips3264, NULL }, + mips_cp0_names_mips3264, + mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), + mips_hwr_names_numeric }, + { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, ISA_MIPS32R2 | INSN_MIPS16, - mips_cp0_names_mips3264r2, mips_hwr_names_mips3264r2 }, + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, + /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, - mips_cp0_names_mips3264, NULL }, + mips_cp0_names_mips3264, + mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), + mips_hwr_names_numeric }, + { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, - mips_cp0_names_sb1, NULL }, + mips_cp0_names_sb1, + mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), + mips_hwr_names_numeric }, /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, - NULL, NULL }, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, }; /* ISA and processor type to disassemble for, and register names to use. @@ -269,6 +400,8 @@ static int mips_isa; static const char * const *mips_gpr_names; static const char * const *mips_fpr_names; static const char * const *mips_cp0_names; +static const struct mips_cp0sel_name *mips_cp0sel_names; +static int mips_cp0sel_names_len; static const char * const *mips_hwr_names; static const struct mips_abi_choice *choose_abi_by_name @@ -277,6 +410,9 @@ static const struct mips_arch_choice *choose_arch_by_name PARAMS ((const char *, unsigned int)); static const struct mips_arch_choice *choose_arch_by_number PARAMS ((unsigned long)); +static const struct mips_cp0sel_name *lookup_mips_cp0sel_name + PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int, + unsigned int)); static const struct mips_abi_choice * choose_abi_by_name (name, namelen) @@ -354,6 +490,8 @@ set_default_mips_dis_options (info) mips_gpr_names = mips_gpr_names_oldabi; mips_fpr_names = mips_fpr_names_numeric; mips_cp0_names = mips_cp0_names_numeric; + mips_cp0sel_names = NULL; + mips_cp0sel_names_len = 0; mips_hwr_names = mips_hwr_names_numeric; /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ @@ -378,10 +516,10 @@ set_default_mips_dis_options (info) { mips_processor = chosen_arch->processor; mips_isa = chosen_arch->isa; - if (chosen_arch->cp0_names != NULL) - mips_cp0_names = chosen_arch->cp0_names; - if (chosen_arch->hwr_names != NULL) - mips_hwr_names = chosen_arch->hwr_names; + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_hwr_names = chosen_arch->hwr_names; } #endif } @@ -417,7 +555,7 @@ parse_mips_dis_option (option, len) && strlen("gpr-names") == optionlen) { chosen_abi = choose_abi_by_name (val, vallen); - if (chosen_abi != NULL && chosen_abi->gpr_names != NULL) + if (chosen_abi != NULL) mips_gpr_names = chosen_abi->gpr_names; return; } @@ -426,7 +564,7 @@ parse_mips_dis_option (option, len) && strlen("fpr-names") == optionlen) { chosen_abi = choose_abi_by_name (val, vallen); - if (chosen_abi != NULL && chosen_abi->fpr_names != NULL) + if (chosen_abi != NULL) mips_fpr_names = chosen_abi->fpr_names; return; } @@ -435,8 +573,12 @@ parse_mips_dis_option (option, len) && strlen("cp0-names") == optionlen) { chosen_arch = choose_arch_by_name (val, vallen); - if (chosen_arch != NULL && chosen_arch->cp0_names != NULL) - mips_cp0_names = chosen_arch->cp0_names; + if (chosen_arch != NULL) + { + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + } return; } @@ -444,7 +586,7 @@ parse_mips_dis_option (option, len) && strlen("hwr-names") == optionlen) { chosen_arch = choose_arch_by_name (val, vallen); - if (chosen_arch != NULL && chosen_arch->hwr_names != NULL) + if (chosen_arch != NULL) mips_hwr_names = chosen_arch->hwr_names; return; } @@ -459,18 +601,16 @@ parse_mips_dis_option (option, len) chosen_abi = choose_abi_by_name (val, vallen); if (chosen_abi != NULL) { - if (chosen_abi->gpr_names != NULL) - mips_gpr_names = chosen_abi->gpr_names; - if (chosen_abi->fpr_names != NULL) - mips_fpr_names = chosen_abi->fpr_names; + mips_gpr_names = chosen_abi->gpr_names; + mips_fpr_names = chosen_abi->fpr_names; } chosen_arch = choose_arch_by_name (val, vallen); if (chosen_arch != NULL) { - if (chosen_arch->cp0_names != NULL) - mips_cp0_names = chosen_arch->cp0_names; - if (chosen_arch->hwr_names != NULL) - mips_hwr_names = chosen_arch->hwr_names; + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_hwr_names = chosen_arch->hwr_names; } return; } @@ -509,6 +649,18 @@ parse_mips_dis_options (options) } } +static const struct mips_cp0sel_name * +lookup_mips_cp0sel_name(names, len, cp0reg, sel) + const struct mips_cp0sel_name *names; + unsigned int len, cp0reg, sel; +{ + unsigned int i; + + for (i = 0; i < len; i++) + if (names[i].cp0reg == cp0reg && names[i].sel == sel) + return &names[i]; + return NULL; +} /* Print insn arguments for 32/64-bit code. */ @@ -556,6 +708,28 @@ print_insn_arg (d, l, pc, info) + 1)); break; + case 'D': + { + const struct mips_cp0sel_name *n; + unsigned int cp0reg, sel; + + cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; + sel = (l >> OP_SH_SEL) & OP_MASK_SEL; + + /* CP0 register including 'sel' code for mtcN (et al.), to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name(mips_cp0sel_names, + mips_cp0sel_names_len, cp0reg, sel); + if (n != NULL) + (*info->fprintf_func) (info->stream, "%s", n->name); + else + (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); + break; + } + default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index c35aa065ce7..436420ef7fb 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -521,8 +521,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N411 }, {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, +{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, +{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, @@ -714,6 +716,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 }, {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 }, {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, +{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, @@ -777,6 +780,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 }, {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 }, {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, +{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, |