diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 43 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 9 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 10 | ||||
| -rw-r--r-- | opcodes/i386-gen.c | 2 | ||||
| -rw-r--r-- | opcodes/i386-init.h | 6 | ||||
| -rw-r--r-- | opcodes/ppc-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 13 | ||||
| -rw-r--r-- | opcodes/s390-mkopc.c | 5 | ||||
| -rw-r--r-- | opcodes/s390-opc.c | 74 | ||||
| -rw-r--r-- | opcodes/s390-opc.txt | 39 | ||||
| -rw-r--r-- | opcodes/v850-dis.c | 16 |
11 files changed, 170 insertions, 49 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4fe082a615d..398ae6f16b1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,42 @@ +2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and + rmr_el3; remove daifset and daifclr. + +2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64-opc.c (operand_general_constraint_met_p): Change to check + the alignment of addr.offset.imm instead of that of shifter.amount for + operand type AARCH64_OPND_ADDR_UIMM12. + +2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * arm-dis.c: Use preferred form of vrint instruction variants + for disassembly. + +2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com> + + * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS. + * i386-init.h: Regenerated. + +2012-10-05 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2; + * ppc-opc.c (VBA): New define. + (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot, + mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics. + +2012-10-04 Nick Clifton <nickc@redhat.com> + + * v850-dis.c (disassemble): Place square parentheses around second + register operand of clr1, not1, set1 and tst1 instructions. + +2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390-mkopc.c: Support new option zEC12. + * s390-opc.c: Add new instruction formats. + * s390-opc.txt: Add new instructions for zEC12. + 2012-09-27 Anthony Green <green@moxielogic.com> * moxie-dis.c (print_insn_moxie): Print 'bad' instructions. @@ -5,8 +44,8 @@ 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> - * i386-gen.c (cpu_flag_init): Add missing Cpu flags in - CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS + * i386-gen.c (cpu_flag_init): Add missing Cpu flags in + CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-init.h: Regenerated. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 2d66a255e95..b5e0984f6c6 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1426,7 +1426,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, 0, 4095 * size); return 0; } - if (!value_aligned_p (opnd->shifter.amount, size)) + if (!value_aligned_p (opnd->addr.offset.imm, size)) { set_unaligned_error (mismatch_detail, idx, size); return 0; @@ -2771,6 +2771,9 @@ const struct aarch64_name_value_pair aarch64_sys_regs [] = { "rvbar_el1", CPENC(3,0,C12,C0,1) }, /* RO */ { "rvbar_el2", CPENC(3,4,C12,C0,1) }, /* RO */ { "rvbar_el3", CPENC(3,6,C12,C0,1) }, /* RO */ + { "rmr_el1", CPENC(3,0,C12,C0,2) }, + { "rmr_el2", CPENC(3,4,C12,C0,2) }, + { "rmr_el3", CPENC(3,6,C12,C0,2) }, { "isr_el1", CPENC(3,0,C12,C1,0) }, /* RO */ { "contextidr_el1", CPENC(3,0,C13,C0,1) }, { "tpidr_el0", CPENC(3,3,C13,C0,2) }, @@ -2962,10 +2965,6 @@ const struct aarch64_name_value_pair aarch64_sys_regs [] = { "pmevtyper29_el0", CPENC(3,3,C14,C15,5) }, { "pmevtyper30_el0", CPENC(3,3,C14,C15,6) }, { "pmccfiltr_el0", CPENC(3,3,C14,C15,7) }, - - { "daifset", CPENC(0,3,C4,C0,6) }, - { "daifclr", CPENC(0,3,C4,C0,7) }, - { 0, CPENC(0,0,0,0,0) }, }; diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 22bdd829dc8..d140761e004 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -498,10 +498,10 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, - {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32.f32\t%y1, %y0"}, - {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64.f64\t%z1, %z0"}, - {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32.f32\t%y1, %y0"}, - {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64.f64\t%z1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, /* Generic coprocessor instructions. */ { 0, SENTINEL_GENERIC_START, 0, "" }, @@ -584,7 +584,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, /* Two registers, miscellaneous. */ - {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 87254d2df83..600904f1b84 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -92,6 +92,8 @@ static initializer cpu_flag_init[] = "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA4|CpuXOP|CpuLWP|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" }, { "CPU_BDVER2_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" }, + { "CPU_BDVER3_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuXsave|CpuXsaveopt" }, { "CPU_BTVER1_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4a|CpuABM|CpuLM|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME|CpuLZCNT" }, { "CPU_BTVER2_FLAGS", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index 4dbc18a1d61..2e4589b00ba 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -169,6 +169,12 @@ 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \ 0, 0, 0 } } +#define CPU_BDVER3_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \ + 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \ + 0, 0, 0 } } + #define CPU_BTVER1_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \ 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 44310e879d4..03b31604876 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -88,7 +88,7 @@ struct ppc_mopt ppc_opts[] = { | PPC_OPCODE_A2), 0 }, { "altivec", (PPC_OPCODE_PPC), - PPC_OPCODE_ALTIVEC }, + PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, { "any", 0, PPC_OPCODE_ANY }, { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 6ebcc90d660..cbf264b620a 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -156,6 +156,9 @@ const struct powerpc_operand powerpc_operands[] = /* The BB field in an XL form instruction when it must be the same as the BA field in the same instruction. */ #define BBA BB + 1 + /* The VB field in a VX form instruction when it must be the same + as the VA field in the same instruction. */ +#define VBA BBA { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, /* The BD field in a B form instruction. The lower two bits are @@ -3106,6 +3109,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, {"vcfux", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, @@ -3146,6 +3150,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmulesh", VX (4, 840), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3159,11 +3164,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, {"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcfpsxsw", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3234,6 +3241,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, +{"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}}, {"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, @@ -3268,6 +3276,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vnot", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}}, {"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, @@ -4818,6 +4827,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, PPCNONE, {RT}}, +{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, PPCNONE, {RT}}, {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}}, @@ -5121,6 +5132,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}}, {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}}, {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, PPCNONE, {RS}}, +{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, PPCNONE, {RS}}, {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}}, {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}}, {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}}, diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c index b3f13ab5368..a1f0a1295c0 100644 --- a/opcodes/s390-mkopc.c +++ b/opcodes/s390-mkopc.c @@ -39,7 +39,8 @@ enum s390_opcode_cpu_val S390_OPCODE_Z9_109, S390_OPCODE_Z9_EC, S390_OPCODE_Z10, - S390_OPCODE_Z196 + S390_OPCODE_Z196, + S390_OPCODE_ZEC12 }; struct op_struct @@ -365,6 +366,8 @@ main (void) min_cpu = S390_OPCODE_Z10; else if (strcmp (cpu_string, "z196") == 0) min_cpu = S390_OPCODE_Z196; + else if (strcmp (cpu_string, "zEC12") == 0) + min_cpu = S390_OPCODE_ZEC12; else { fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); exit (1); diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 282298b98b6..f421abe0bee 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -171,50 +171,64 @@ const struct s390_operand s390_operands[] = { 8, 8, S390_OPERAND_SIGNED }, #define I8_32 48 /* 8 bit signed value starting at 32 */ { 8, 32, S390_OPERAND_SIGNED }, -#define I16_16 49 /* 16 bit signed value starting at 16 */ +#define I12_12 49 /* 12 bit signed value starting at 12 */ + { 12, 12, S390_OPERAND_SIGNED }, +#define I16_16 50 /* 16 bit signed value starting at 16 */ { 16, 16, S390_OPERAND_SIGNED }, -#define I16_32 50 /* 16 bit signed value starting at 32 */ +#define I16_32 51 /* 16 bit signed value starting at 32 */ { 16, 32, S390_OPERAND_SIGNED }, -#define I32_16 51 /* 32 bit signed value starting at 16 */ +#define I24_24 52 /* 24 bit signed value starting at 24 */ + { 24, 24, S390_OPERAND_SIGNED }, +#define I32_16 53 /* 32 bit signed value starting at 16 */ { 32, 16, S390_OPERAND_SIGNED }, /* Unsigned immediate operands. */ -#define U4_8 52 /* 4 bit unsigned value starting at 8 */ +#define U4_8 54 /* 4 bit unsigned value starting at 8 */ { 4, 8, 0 }, -#define U4_12 53 /* 4 bit unsigned value starting at 12 */ +#define U4_12 55 /* 4 bit unsigned value starting at 12 */ { 4, 12, 0 }, -#define U4_16 54 /* 4 bit unsigned value starting at 16 */ +#define U4_16 56 /* 4 bit unsigned value starting at 16 */ { 4, 16, 0 }, -#define U4_20 55 /* 4 bit unsigned value starting at 20 */ +#define U4_20 57 /* 4 bit unsigned value starting at 20 */ { 4, 20, 0 }, -#define U4_32 56 /* 4 bit unsigned value starting at 32 */ +#define U4_24 58 /* 4 bit unsigned value starting at 24 */ + { 4, 24, 0 }, +#define U4_28 59 /* 4 bit unsigned value starting at 28 */ + { 4, 28, 0 }, +#define U4_32 60 /* 4 bit unsigned value starting at 32 */ { 4, 32, 0 }, -#define U8_8 57 /* 8 bit unsigned value starting at 8 */ +#define U4_36 61 /* 4 bit unsigned value starting at 36 */ + { 4, 36, 0 }, +#define U8_8 62 /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U8_16 58 /* 8 bit unsigned value starting at 16 */ +#define U8_16 63 /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define U8_24 59 /* 8 bit unsigned value starting at 24 */ +#define U8_24 64 /* 8 bit unsigned value starting at 24 */ { 8, 24, 0 }, -#define U8_32 60 /* 8 bit unsigned value starting at 32 */ +#define U8_32 65 /* 8 bit unsigned value starting at 32 */ { 8, 32, 0 }, -#define U16_16 61 /* 16 bit unsigned value starting at 16 */ +#define U16_16 66 /* 16 bit unsigned value starting at 16 */ { 16, 16, 0 }, -#define U16_32 62 /* 16 bit unsigned value starting at 32 */ +#define U16_32 67 /* 16 bit unsigned value starting at 32 */ { 16, 32, 0 }, -#define U32_16 63 /* 32 bit unsigned value starting at 16 */ +#define U32_16 68 /* 32 bit unsigned value starting at 16 */ { 32, 16, 0 }, /* PC-relative address operands. */ -#define J16_16 64 /* PC relative jump offset at 16 */ +#define J12_12 69 /* PC relative offset at 12 */ + { 12, 12, S390_OPERAND_PCREL }, +#define J16_16 70 /* PC relative offset at 16 */ { 16, 16, S390_OPERAND_PCREL }, -#define J32_16 65 /* PC relative long offset at 16 */ +#define J16_32 71 /* PC relative offset at 16 */ + { 16, 32, S390_OPERAND_PCREL }, +#define J32_16 72 /* PC relative offset at 16 */ { 32, 16, S390_OPERAND_PCREL }, /* Conditional mask operands. */ -#define M_16OPT 66 /* 4 bit optional mask starting at 16 */ +#define M_16OPT 73 /* 4 bit optional mask starting at 16 */ { 4, 16, S390_OPERAND_OPTIONAL }, }; @@ -240,13 +254,13 @@ const struct s390_operand s390_operands[] = c - control register d - displacement, 12 bit f - floating pointer register - fe - even numbered floating point register operand + fe - fpr extended operand, a valid floating pointer register pair i - signed integer, 4, 8, 16 or 32 bit l - length, 4 or 8 bit p - pc relative r - general purpose register ro - optional register operand - re - even numbered register operand + re - gpr extended operand, a valid general purpose register pair u - unsigned integer, 4, 8, 16 or 32 bit m - mode field, 4 bit 0 - operand skipped. @@ -267,6 +281,8 @@ const struct s390_operand s390_operands[] = The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ +#define INSTR_MII_UPI 6, { U4_8,J12_12,I24_24 } /* e.g. bprp */ #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ @@ -368,14 +384,16 @@ const struct s390_operand s390_operands[] = #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ +#define INSTR_RSL_LRDFU 6, { F_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cdzt */ +#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cxzt */ #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ #define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ +#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locgt */ #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ -#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ -#define INSTR_RSY_RDRM 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ -#define INSTR_RSY_RDR0 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. loc */ +#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ @@ -407,6 +425,7 @@ const struct s390_operand s390_operands[] = #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ +#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ @@ -422,6 +441,8 @@ const struct s390_operand s390_operands[] = #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_MII_UPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } @@ -521,6 +542,8 @@ const struct s390_operand s390_operands[] = #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -532,10 +555,10 @@ const struct s390_operand s390_operands[] = #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSY_RDRM { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSY_RDR0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } @@ -560,6 +583,7 @@ const struct s390_operand s390_operands[] = #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 58b54d13135..5946a052668 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -1017,14 +1017,14 @@ b9f2 locr RRF_U0RR "load on condition 32 bit" z196 zarch b9f200000000 locr*16 RRF_00RR "load on condition 32 bit" z196 zarch b9e2 locgr RRF_U0RR "load on condition 64 bit" z196 zarch b9e200000000 locgr*16 RRF_00RR "load on condition 64 bit" z196 zarch -eb00000000f2 loc RSY_RDRM "load on condition 32 bit" z196 zarch -eb00000000f2 loc*12 RSY_RDR0 "load on condition 32 bit" z196 zarch -eb00000000e2 locg RSY_RDRM "load on condition 64 bit" z196 zarch -eb00000000e2 locg*12 RSY_RDR0 "load on condition 64 bit" z196 zarch -eb00000000f3 stoc RSY_RDRM "store on condition 32 bit" z196 zarch -eb00000000f3 stoc*12 RSY_RDR0 "store on condition 32 bit" z196 zarch -eb00000000e3 stocg RSY_RDRM "store on condition 64 bit" z196 zarch -eb00000000e3 stocg*12 RSY_RDR0 "store on condition 64 bit" z196 zarch +eb00000000f2 loc RSY_RURD2 "load on condition 32 bit" z196 zarch +eb00000000f2 loc*12 RSY_R0RD "load on condition 32 bit" z196 zarch +eb00000000e2 locg RSY_RURD2 "load on condition 64 bit" z196 zarch +eb00000000e2 locg*12 RSY_R0RD "load on condition 64 bit" z196 zarch +eb00000000f3 stoc RSY_RURD2 "store on condition 32 bit" z196 zarch +eb00000000f3 stoc*12 RSY_R0RD "store on condition 32 bit" z196 zarch +eb00000000e3 stocg RSY_RURD2 "store on condition 64 bit" z196 zarch +eb00000000e3 stocg*12 RSY_R0RD "store on condition 64 bit" z196 zarch b9f8 ark RRF_R0RR2 "add 3 operands 32 bit" z196 zarch b9e8 agrk RRF_R0RR2 "add 3 operands 64 bit" z196 zarch ec00000000d8 ahik RIE_RRI0 "add immediate 3 operands 32 bit" z196 zarch @@ -1104,3 +1104,26 @@ b3d8 mxtra RRF_FEUFEFE2 "multiply extended dfp with rounding mode" z196 zarch b3d3 sdtra RRF_FUFF2 "subtract long dfp with rounding mode" z196 zarch b3db sxtra RRF_FEUFEFE2 "subtract extended dfp with rounding mode" z196 zarch b2b8 srnmb S_RD "set 3 bit bfp rounding mode" z196 zarch +b2ec etnd RRE_R0 "extract transaction nesting depth" zEC12 zarch +e30000000025 ntstg RXY_RRRD "nontransactional store" zEC12 zarch +b2fc tabort S_RD "transaction abort" zEC12 zarch +e560 tbegin SIL_RDU "transaction begin" zEC12 zarch +e561 tbeginc SIL_RDU "constrained transaction begin" zEC12 zarch +b2f8 tend S_00 "transaction end" zEC12 zarch +c7 bpp SMI_U0RDP "branch prediction preload" zEC12 zarch +c5 bprp MII_UPI "branch prediction relative preload" zEC12 zarch +b2fa niai IE_UU "next instruction access intent" zEC12 zarch +e3000000009f lat RXY_RRRD "load and trap 32 bit" zEC12 zarch +e30000000085 lgat RXY_RRRD "load and trap 64 bit" zEC12 zarch +e300000000c8 lfhat RXY_RRRD "load high and trap" zEC12 zarch +e3000000009d llgfat RXY_RRRD "load logical and trap 32>64" zEC12 zarch +e3000000009c llgtat RXY_RRRD "load logical thirty one bits and trap 31>64" zEC12 zarch +eb0000000023 clt RSY_RURD "compare logical and trap 32 bit reg-mem" zEC12 zarch +eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zarch +eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch +eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch +ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch +ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch +ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch +ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch +ed00000000a9 czxt RSL_LRDFEU "convert to zoned extended" zEC12 zarch diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c index 60b452bf79c..5f9d87b8f86 100644 --- a/opcodes/v850-dis.c +++ b/opcodes/v850-dis.c @@ -309,9 +309,11 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns We may need to output a trailing ']' if the last operand in an instruction is the register for a memory address. - The exception (and there's always an exception) is the + The exception (and there's always an exception) are the "jmp" insn which needs square brackets around it's only - register argument. */ + register argument, and the clr1/not1/set1/tst1 insns + which [...] around their second register argument. */ + prefix = ""; if (operand->flags & V850_OPERAND_BANG) { @@ -334,6 +336,16 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns info->fprintf_func (info->stream, "%s[", prefix); square = TRUE; } + else if (opnum == 2 + && ( op->opcode == 0x00e407e0 /* clr1 */ + || op->opcode == 0x00e207e0 /* not1 */ + || op->opcode == 0x00e007e0 /* set1 */ + || op->opcode == 0x00e607e0 /* tst1 */ + )) + { + info->fprintf_func (info->stream, ", %s[", prefix); + square = TRUE; + } else if (opnum > 1) info->fprintf_func (info->stream, ", %s", prefix); |