diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 1229 | ||||
| -rw-r--r-- | opcodes/ChangeLog-2008 | 1204 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 826 | ||||
| -rw-r--r-- | opcodes/i386-opc.h | 7 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 194 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 1384 |
6 files changed, 2191 insertions, 2653 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c6c6d6b799e..e33aa5c1d3e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,1205 +1,66 @@ -2009-01-02 Matthias Klose <doko@ubuntu.com> - - * or32-opc.c (or32_print_register, or32_print_immediate, - disassemble_insn): Don't rely on undefined sprintf behaviour. - -2008-12-30 Martin Schwidefsky <schwidefskyy@de.ibm.com> - - * s390-opc.txt: Add ptff instruction. - -2008-12-24 Jan Kratochvil <jan.kratochvil@redhat.com> - - * Makefile.am (CFILES, ALL_MACHINES): Add LM32 source and object files. - * Makefile.in: Regenerate. - -2008-12-23 Jon Beniston <jon@beniston.com> - - * Makefile.am: Add LM32 object files and dependencies. - * Makefile.in: Regenerate. - * configure.in: Add LM32 target. - * configure: Regenerate. - * disassemble.c: Add LM32 disassembler. - * cgen-asm.in: Update copyright year. - * cgen-dis.in: Update copyright year. - * cgen-ibld.in: Update copyright year. - * lm32-asm.c: New file. - * lm32-desc.c: New file. - * lm32-desc.h: New file. - * lm32-dis.c: New file. - * lm32-ibld.c: New file. - * lm32-opc.c: New file. - * lm32-opc.h: New file. - * lm32-opinst.c: New file. - -2008-12-23 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (EXdS): New. - (EXdVexS): Likewise. - (EXqVexS): Likewise. - (d_swap_mode): Likewise. - (q_mode): Updated. - (prefix_table): Use EXdS on movss and EXqS on movsd. - (vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd. - (intel_operand_size): Handle d_swap_mode. - (OP_EX): Likewise. - - * i386-opc.h (S): Update comments. - - * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd. - * i386-tbl.h: Regenerated. - -2008-12-23 Nick Clifton <nickc@redhat.com> - - * po/ga.po: Updated Irish translation. - -2008-12-20 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (EbS): New. - (EvS): Likewise. - (EMS): Likewise. - (EXqS): Likewise. - (EXxS): Likewise. - (b_swap_mode): Likewise. - (v_swap_mode): Likewise. - (q_swap_mode): Likewise. - (x_swap_mode): Likewise. - (v_mode): Updated. - (w_mode): Likewise. - (t_mode): Likewise. - (xmm_mode): Likewise. - (swap_operand): Likewise. - (dis386): Use EbS on movB. Use EvS on moveS. - (dis386_twobyte): Use EXxS on movapX. - (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa, - vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq. - (vex_table): Use EXxS on vmovapX. - (vex_len_table): Use EXqS on vmovq. - (intel_operand_size): Handle b_swap_mode, v_swap_mode, - q_swap_mode and x_swap_mode. - (OP_E_register): Handle b_swap_mode and v_swap_mode. - (OP_EM): Handle v_swap_mode. - (OP_EX): x_swap_mode and q_swap_mode. - - * i386-gen.c (opcode_modifiers): Add S. - - * i386-opc.h (S): New. - (Modrm): Updated. - (i386_opcode_modifier): Add s. - - * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq, - movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq. - * i386-tbl.h: Regenerated. - -2008-12-18 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (mnemonicendp): New. - (op): Likewise. - (print_insn): Use mnemonicendp. - (OP_3DNowSuffix): Likewise. - (CMP_Fixup): Likewise. - (CMPXCHG8B_Fixup): Likewise. - (CRC32_Fixup): Likewise. - (OP_DREX_FCMP): Likewise. - (OP_DREX_ICMP): Likewise. - (VZERO_Fixup): Likewise. - (VCMP_Fixup): Likewise. - (PCLMUL_Fixup): Likewise. - (VPERMIL2_Fixup): Likewise. - (MOVBE_Fixup): Likewise. - (putop): Update mnemonicendp. - (oappend): Use stpcpy. - (simd_cmp_op): Changed to struct op. - (vex_cmp_op): Likewise. - (pclmul_op): Likewise. - (vpermil2_op): Likewise. - -2008-12-18 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> - - * configure: Regenerate. - -2008-12-15 Richard Earnshaw <rearnsha@arm.com> - - * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using - unified syntax. - -2008-12-08 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD. - -2008-12-08 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (putop): Remove strayed comments. - -2008-12-04 Ben Elliston <bje@au.ibm.com> - - * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE - for -Mbooke. - (print_ppc_disassembler_options): Update usage. - * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove. - (BOOKE64): Remove. - (PPCCHLK64): Likewise. - (powerpc_opcodes): Remove all BOOKE64 instructions. - -2008-11-28 Joshua Kinard <kumba@gentoo.org> - - * mips-dis.c (mips_arch_choices): Add r14000, r16000. - -2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - - * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and - adjusted the mask for 32-bit branch instruction. - -2008-11-27 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (extract_sprg): Correct operand range check. - -2008-11-26 Andreas Schwab <schwab@suse.de> - - * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE) - (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling. - (save_printer, save_print_address): Remove. - (fetch_data): Don't use them. - (match_insn_m68k): Always restore printing functions. - (print_insn_m68k): Don't save/restore printing functions. - -2008-11-25 Nick Clifton <nickc@redhat.com> - - * m68k-dis.c: Rewrite to remove use of setjmp/longjmp. - -2008-11-18 Catherine Moore <clm@codesourcery.com> - - * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt - instructions. - (neon_opcodes): Likewise. - (print_insn_coprocessor): Print 't' or 'b' for vcvt - instructions. - -2008-11-14 Tristan Gingold <gingold@adacore.com> - - * makefile.vms (OBJS): Update list of objects. - (DEFS): Update - (CFLAGS): Update. - -2008-11-06 Chao-ying Fu <fu@mips.com> - - * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these - before sync. - (sync): New instruction with 5-bit sync type. - * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values. - -2008-11-06 Nick Clifton <nickc@redhat.com> - - * avr-dis.c: Replace uses of sprintf without a format string with - calls to strcpy. - -2008-11-03 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Add cmovpe and cmovpo. - * i386-tbl.h: Regenerated. - -2008-10-22 Nick Clifton <nickc@redhat.com> - - PR 6937 - * configure.in (SHARED_LIBADD): Revert previous change. - Add a comment explaining why. - (SHARED_DEPENDENCIES): Revert previous change. - * configure: Regenerate. - -2008-10-10 Nick Clifton <nickc@redhat.com> - - PR 6937 - * configure.in (SHARED_LIBADD): Add libiberty.a. - (SHARED_DEPENDENCIES): Add libiberty.a. - -2008-09-30 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c: Include "hashtab.h". - (next_field): Take a new argument, last. Check last. - (process_i386_cpu_flag): Updated. - (process_i386_opcode_modifier): Likewise. - (process_i386_operand_type): Likewise. - (process_i386_registers): Likewise. - (output_i386_opcode): New. - (opcode_hash_entry): Likewise. - (opcode_hash_table): Likewise. - (opcode_hash_hash): Likewise. - (opcode_hash_eq): Likewise. - (process_i386_opcodes): Use opcode hash table and opcode array. - -2008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> - - * s390-opc.txt (stdy, stey): Fix description - -2008-09-30 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2008-09-29 H.J. Lu <hongjiu.lu@intel.com> - - * aclocal.m4: Regenerated. - * configure: Likewise. - * Makefile.in: Likewise. - -2008-09-29 Nick Clifton <nickc@redhat.com> - - * po/vi.po: Updated Vietnamese translation. - * po/fr.po: Updated French translation. - -2008-09-26 Florian Krohm <fkrohm@us.ibm.com> - - * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF. - (cfxr, cfdr, cfer, clclu): Add esa flag. - (sqd): Instruction added. - (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF. - * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed. - -2008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl> - - * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes. - (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions. - -2008-09-11 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd]. - * i386-tbl.h: Regenerated. - -2008-08-28 Jan Beulich <jbeulich@novell.com> - - * i386-dis.c (dis386): Adjust far return mnemonics. - * i386-opc.tbl: Add retf. - * i386-tbl.h: Re-generate. - -2008-08-28 Jan Beulich <jbeulich@novell.com> - - * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics. - -2008-08-28 H.J. Lu <hongjiu.lu@intel.com> - - * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1. - * ia64-gen.c (lookup_specifier): Likewise. - - * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1. - * ia64-raw.tbl: Likewise. - * ia64-waw.tbl: Likewise. - * ia64-asmtab.c: Regenerated. - -2008-08-27 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Correct fidivr operand size. - - * i386-tbl.h: Regenerated. - -2008-08-24 Alan Modra <amodra@bigpond.net.au> - - * configure.in: Update a number of obsolete autoconf macros. - * aclocal.m4: Regenerate. - -2008-08-20 H.J. Lu <hongjiu.lu@intel.com> - - AVX Programming Reference (August, 2008) - * i386-dis.c (PREFIX_VEX_38DB): New. - (PREFIX_VEX_38DC): Likewise. - (PREFIX_VEX_38DD): Likewise. - (PREFIX_VEX_38DE): Likewise. - (PREFIX_VEX_38DF): Likewise. - (PREFIX_VEX_3ADF): Likewise. - (VEX_LEN_38DB_P_2): Likewise. - (VEX_LEN_38DC_P_2): Likewise. - (VEX_LEN_38DD_P_2): Likewise. - (VEX_LEN_38DE_P_2): Likewise. - (VEX_LEN_38DF_P_2): Likewise. - (VEX_LEN_3ADF_P_2): Likewise. - (PREFIX_VEX_3A04): Updated. - (VEX_LEN_3A06_P_2): Likewise. - (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC, - PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF. - (x86_64_table): Likewise. - (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2, - VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and - VEX_LEN_3ADF_P_2. - - * i386-opc.tbl: Add AES + AVX instructions. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> - - * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format. - * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format. - -2008-08-15 Alan Modra <amodra@bigpond.net.au> - - PR 6526 - * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS. - * Makefile.in: Regenerate. - * aclocal.m4: Regenerate. - * config.in: Regenerate. - * configure: Regenerate. - -2008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de> - - PR 6825 - * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300. - -2008-08-12 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Add syscall and sysret for Cpu64. - - * i386-tbl.h: Regenerated. - -2008-08-04 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am (POTFILES.in): Set LC_ALL=C. - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2008-08-01 Peter Bergner <bergner@vnet.ibm.com> - - * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. - (print_insn_powerpc): Prepend 'vs' when printing VSX registers. - (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. - * ppc-opc.c (insert_xt6): New static function. - (extract_xt6): Likewise. - (insert_xa6): Likewise. - (extract_xa6: Likewise. - (insert_xb6): Likewise. - (extract_xb6): Likewise. - (insert_xb6s): Likewise. - (extract_xb6s): Likewise. - (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, - XX3DM_MASK, PPCVSX): New. - (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", - "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp". - -2008-08-01 Pedro Alves <pedro@codesourcery.com> - - * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation. - * Makefile.in: Regenerate. - -2008-08-01 H.J. Lu <hongjiu.lu@intel.com> - - * i386-reg.tbl: Use Dw2Inval on AVX registers. - * i386-tbl.h: Regenerated. - -2008-07-30 Michael J. Eager <eager@eagercon.com> - - * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields. - * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands. - (insert_sprg, PPC405): Use PPC_OPCODE_405. - (powerpc_opcodes): Add Xilinx APU related opcodes. - -2008-07-30 Alan Modra <amodra@bigpond.net.au> - - * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings. - -2008-07-10 Richard Sandiford <rdsandiford@googlemail.com> - - * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16. - -2008-07-07 Adam Nemet <anemet@caviumnetworks.com> - - * mips-opc.c (CP): New macro. - (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the - membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and - dmtc2 Octeon instructions. - -2008-07-07 Stan Shebs <stan@codesourcery.com> - - * dis-init.c (init_disassemble_info): Init endian_code field. - * arm-dis.c (print_insn): Disassemble code according to - setting of endian_code. - (print_insn_big_arm): Detect when BE8 extension flag has been set. - -2008-06-30 Richard Sandiford <rdsandiford@googlemail.com> - - * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check - for ELF symbols. - -2008-06-25 Peter Bergner <bergner@vnet.ibm.com> - - * ppc-dis.c (powerpc_init_dialect): Handle -M464. - (print_ppc_disassembler_options): Likewise. - * ppc-opc.c (PPC464): Define. - (powerpc_opcodes): Add mfdcrux and mtdcrux. - -2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> - - * configure: Regenerate. - -2008-06-13 Peter Bergner <bergner@vnet.ibm.com> - - * ppc-dis.c (print_insn_powerpc): Update prototye to use new - ppc_cpu_t typedef. - (struct dis_private): New. - (POWERPC_DIALECT): New define. - (powerpc_dialect): Renamed to... - (powerpc_init_dialect): This. Update to use ppc_cpu_t and - struct dis_private. - (print_insn_big_powerpc): Update for using structure in - info->private_data. - (print_insn_little_powerpc): Likewise. - (operand_value_powerpc): Change type of dialect param to ppc_cpu_t. - (skip_optional_operands): Likewise. - (print_insn_powerpc): Likewise. Remove initialization of dialect. - * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp, - extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe, - extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr, - extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm, - insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe, - insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs, - insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect - param to be of type ppc_cpu_t. Update prototype. - -2008-06-12 Adam Nemet <anemet@caviumnetworks.com> - - * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, - +s, +S. - * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions - baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, - syncw, syncws, vm3mulu, vm0 and vmulu. - - * mips-dis.c (print_insn_args): Handle field descriptor +Q. - * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, - seqi, sne and snei. - -2008-05-30 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Add vmovd with 64bit operand. - * i386-tbl.h: Regenerated. - -2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format. - -2008-05-22 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi. - * i386-tbl.h: Regenerated. - -2008-05-22 H.J. Lu <hongjiu.lu@intel.com> - - PR gas/6517 - * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss - into 32bit and 64bit. Remove Reg64|Qword and add - IgnoreSize|No_qSuf on 32bit version. - * i386-tbl.h: Regenerated. - -2008-05-21 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. - * i386-tbl.h: Regenerated. - -2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - - * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond. - -2008-05-14 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2008-05-02 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (MOVBE_Fixup): New. - (Mo): Likewise. - (PREFIX_0F3880): Likewise. - (PREFIX_0F3881): Likewise. - (PREFIX_0F38F0): Updated. - (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update - PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. - (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. - - * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and - CPU_EPT_FLAGS. - (cpu_flags): Add CpuMovbe and CpuEPT. - - * i386-opc.h (CpuMovbe): New. - (CpuEPT): Likewise. - (CpuLM): Updated. - (i386_cpu_flags): Add cpumovbe and cpuept. - - * i386-opc.tbl: Add entries for movbe and EPT instructions. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-04-29 Adam Nemet <anemet@caviumnetworks.com> - - * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for - the two drem and the two dremu macros. - -2008-04-28 Adam Nemet <anemet@caviumnetworks.com> - - * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1 - instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and - cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros - INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D. - -2008-04-25 David S. Miller <davem@davemloft.net> - - * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr - instead of %sys_tick_cmpr, as suggested in architecture manuals. - -2008-04-23 Paolo Bonzini <bonzini@gnu.org> - - * aclocal.m4: Regenerate. - * configure: Regenerate. +2009-01-05 H.J. Lu <hongjiu.lu@intel.com> -2008-04-23 David S. Miller <davem@davemloft.net> - - * sparc-opc.c (asi_table): Add UltraSPARC and Niagara - extended values. - (prefetch_table): Add missing values. - -2008-04-22 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (opcode_modifiers): Add NoAVX. - - * i386-opc.h (NoAVX): New. - (OldGcc): Updated. - (i386_opcode_modifier): Add noavx. - - * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3 - instructions which don't have AVX equivalent. - * i386-tbl.h: Regenerated. - -2008-04-18 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (OP_VEX_FMA): New. - (OP_EX_VexImmW): Likewise. - (VexFMA): Likewise. - (Vex128FMA): Likewise. - (EXVexImmW): Likewise. - (get_vex_imm8): Likewise. - (OP_EX_VexReg): Likewise. - (vex_i4_done): Renamed to ... - (vex_w_done): This. - (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps - and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on - FMA instructions. - (print_insn): Updated. - (OP_EX_VexW): Rewrite to swap register in VEX with EX. - (OP_REG_VexI4): Check invalid high registers. - -2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> - Michael Meissner <michael.meissner@amd.com> - - * i386-opc.tbl: Fix protX to allow memory in the middle operand. - * i386-tbl.h: Regenerate from i386-opc.tbl. - -2008-04-14 Edmar Wienskoski <edmar@freescale.com> - - * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to - accept Power E500MC instructions. - (print_ppc_disassembler_options): Document -Me500mc. - * ppc-opc.c (DUIS, DUI, T): New. - (XRT, XRTRA): Likewise. - (E500MC): Likewise. - (powerpc_opcodes): Add new Power E500MC instructions. - -2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> - - * s390-dis.c (init_disasm): Evaluate disassembler_options. - (print_s390_disassembler_options): New function. - * disassemble.c (disassembler_usage): Invoke - print_s390_disassembler_options. - -2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> - - * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes - of local variables used for mnemonic parsing: prefix, suffix and - number. - -2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> - - * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic - extensions for conditional jumps (o, p, m, nz, z, nm, np, no). - (s390_crb_extensions): New extensions table. - (insertExpandedMnemonic): Handle '$' tag. - * s390-opc.txt: Remove conditional jump variants which can now - be expanded automatically. - Replace '*' tag with '$' in the compare and branch instructions. - -2008-04-07 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (PREFIX_VEX_38XX): Add a tab. - (PREFIX_VEX_3AXX): Likewis. - -2008-04-07 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Remove 4 extra blank lines. - -2008-04-04 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL - with CPU_PCLMUL_FLAGS/CpuPCLMUL. - (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. - * i386-opc.tbl: Likewise. - - * i386-opc.h (CpuCLMUL): Renamed to ... - (CpuPCLMUL): This. - (CpuFMA): Updated. - (i386_cpu_flags): Replace cpuclmul with cpupclmul. - - * i386-init.h: Regenerated. - -2008-04-03 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (OP_E_register): New. - (OP_E_memory): Likewise. - (OP_VEX): Likewise. - (OP_EX_Vex): Likewise. + AVX Programming Reference (December, 2008) + * i386-dis.c (OP_VEX_FMA): Removed. (OP_EX_VexW): Likewise. - (OP_XMM_Vex): Likewise. + (OP_EX_VexImmW): Likewise. (OP_XMM_VexW): Likewise. - (OP_REG_VexI4): Likewise. - (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. - (VZERO_Fixup): Likewise. - (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. - (rex_original): Likewise. - (rex_ignored): Likewise. - (Mxmm): Likewise. - (XMM): Likewise. - (EXxmm): Likewise. - (EXxmmq): Likewise. - (EXymmq): Likewise. - (Vex): Likewise. - (Vex128): Likewise. - (Vex256): Likewise. (VexI4): Likewise. - (EXdVex): Likewise. - (EXqVex): Likewise. + (VexFMA): Likewise. + (Vex128FMA): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. - (XMVex): Likewise. + (EXVexImmW): Likewise. (XMVexW): Likewise. - (XMVexI4): Likewise. - (PCLMUL): Likewise. - (VZERO): Likewise. - (VCMP): Likewise. (VPERMIL2): Likewise. - (xmm_mode): Likewise. - (xmmq_mode): Likewise. - (ymmq_mode): Likewise. - (vex_mode): Likewise. - (vex128_mode): Likewise. - (vex256_mode): Likewise. - (USE_VEX_C4_TABLE): Likewise. - (USE_VEX_C5_TABLE): Likewise. - (USE_VEX_LEN_TABLE): Likewise. - (VEX_C4_TABLE): Likewise. - (VEX_C5_TABLE): Likewise. - (VEX_LEN_TABLE): Likewise. - (REG_VEX_XX): Likewise. - (MOD_VEX_XXX): Likewise. - (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. - (PREFIX_0F3A44): Likewise. - (PREFIX_0F3ADF): Likewise. - (PREFIX_VEX_XXX): Likewise. - (VEX_OF): Likewise. - (VEX_OF38): Likewise. - (VEX_OF3A): Likewise. - (VEX_LEN_XXX): Likewise. - (vex): Likewise. - (need_vex): Likewise. - (need_vex_reg): Likewise. - (vex_i4_done): Likewise. + (PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise. + (PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise. + (PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise. + (PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise. + (VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise. + (VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise. + (get_vex_imm8): Likewise. + (OP_EX_VexReg): Likewise. + vpermil2_op): Likewise. + (EXVexWdq): New. + (vex_w_dq_mode): Likewise. + (PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise. + (PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise. + (PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise. + (es_reg): Updated. + (PREFIX_VEX_38DB): Likewise. + (PREFIX_VEX_3A4A): Likewise. + (PREFIX_VEX_3A60): Likewise. + (PREFIX_VEX_3ADF): Likewise. + (VEX_LEN_3ADF_P_2): Likewise. + (prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A, + PREFIX_VEX_3A5C...PREFIX_VEX_3A5F, + PREFIX_VEX_3A68...PREFIX_VEX_3A6F and + PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add + PREFIX_VEX_3896...PREFIX_VEX_389F, + PREFIX_VEX_38A6...PREFIX_VEX_38AF and + PREFIX_VEX_38B6...PREFIX_VEX_38BF. (vex_table): Likewise. - (vex_len_table): Likewise. - (OP_REG_VexI4): Likewise. - (vex_cmp_op): Likewise. - (pclmul_op): Likewise. - (vpermil2_op): Likewise. - (m_mode): Updated. - (es_reg): Likewise. - (PREFIX_0F38F0): Likewise. - (PREFIX_0F3A60): Likewise. - (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. - (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF - and PREFIX_VEX_XXX entries. - (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. - (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and - PREFIX_0F3ADF. - (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. - Add MOD_VEX_XXX entries. - (ckprefix): Initialize rex_original and rex_ignored. Store the - REX byte in rex_original. - (get_valid_dis386): Handle the implicit prefix in VEX prefix - bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. - (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before - calling get_valid_dis386. Use rex_original and rex_ignored when - printing out REX. - (putop): Handle "XY". - (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and - ymmq_mode. - (OP_E_extended): Updated to use OP_E_register and - OP_E_memory. - (OP_XMM): Handle VEX. - (OP_EX): Likewise. - (XMM_Fixup): Likewise. - (CMP_Fixup): Use ARRAY_SIZE. - - * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, - CPU_FMA_FLAGS and CPU_AVX_FLAGS. - (operand_type_init): Add OPERAND_TYPE_REGYMM and - OPERAND_TYPE_VEX_IMM4. - (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. - (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, - VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, - VexImmExt and SSE2AVX. - (operand_types): Add RegYMM, Ymmword and Vex_Imm4. - - * i386-opc.h (CpuAVX): New. - (CpuAES): Likewise. - (CpuCLMUL): Likewise. - (CpuFMA): Likewise. - (Vex): Likewise. - (Vex256): Likewise. - (VexNDS): Likewise. - (VexNDD): Likewise. - (VexW0): Likewise. - (VexW1): Likewise. - (Vex0F): Likewise. - (Vex0F38): Likewise. - (Vex0F3A): Likewise. - (Vex3Sources): Likewise. - (VexImmExt): Likewise. - (SSE2AVX): Likewise. - (RegYMM): Likewise. - (Ymmword): Likewise. - (Vex_Imm4): Likewise. - (Implicit1stXmm0): Likewise. - (CpuXsave): Updated. - (CpuLM): Likewise. - (ByteOkIntel): Likewise. - (OldGcc): Likewise. - (Control): Likewise. - (Unspecified): Likewise. - (OTMax): Likewise. - (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. - (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, - vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, - vex3sources, veximmext and sse2avx. - (i386_operand_type): Add regymm, ymmword and vex_imm4. - - * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. - - * i386-reg.tbl: Add AVX registers, ymm0..ymm15. - - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com> - - From Robin Getz <robin.getz@analog.com> - * bfin-dis.c (bu32): Typedef. - (enum const_forms_t): Add c_uimm32 and c_huimm32. - (constant_formats[]): Add uimm32 and huimm16. - (fmtconst_val): New. - (uimm32): Define. - (huimm32): Define. - (imm16_val): Define. - (luimm16_val): Define. - (struct saved_state): Define. - (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, - A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, - LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. - (get_allreg): New. - (decode_LDIMMhalf_0): Print out the whole register value. - - From Jie Zhang <jie.zhang@analog.com> - * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for - multiply and multiply-accumulate to data register instruction. - - * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, - c_imm32, c_huimm32e): Define. - (constant_formats): Add flags for printing decimal, leading spaces, and - exact symbols. - (comment, parallel): Add global flags in all disassembly. - (fmtconst): Take advantage of new flags, and print default in hex. - (fmtconst_val): Likewise. - (decode_macfunc): Be consistant with spaces, tabs, comments, - capitalization in disassembly, fix minor coding style issues. - (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. - (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, - decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, - decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, - decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, - decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, - decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, - decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, - decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, - decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, - _print_insn_bfin, print_insn_bfin): Likewise. - -2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> + (vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2 + and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2. + (putop): Support "%XW". + (intel_operand_size): Handle vex_w_dq_mode. - * aclocal.m4: Regenerate. - * configure: Likewise. - * Makefile.in: Likewise. + * i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS. -2008-03-13 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * configure: Regenerate. - -2008-03-07 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (powerpc_opcodes): Order and format. - -2008-03-01 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64. + * i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA + instructions. Add new FMA instructions. * i386-tbl.h: Regenerated. -2008-02-23 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Disallow 16-bit near indirect branches for - x86-64. - * i386-tbl.h: Regenerated. - -2008-02-21 Jan Beulich <jbeulich@novell.com> - - * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword - and Fword for far indirect jmp. Allow Reg16 and Word for near - indirect jmp on x86-64. Disallow Fword for lcall. - * i386-tbl.h: Re-generate. - -2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - - * cr16-opc.c (cr16_num_optab): Defined - -2008-02-16 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG. - * i386-init.h: Regenerated. - -2008-02-14 Nick Clifton <nickc@redhat.com> - - PR binutils/5524 - * configure.in (SHARED_LIBADD): Select the correct host specific - file extension for shared libraries. - * configure: Regenerate. - -2008-02-13 Jan Beulich <jbeulich@novell.com> - - * i386-opc.h (RegFlat): New. - * i386-reg.tbl (flat): Add. - * i386-tbl.h: Re-generate. - -2008-02-13 Jan Beulich <jbeulich@novell.com> - - * i386-dis.c (a_mode): New. - (cond_jump_mode): Adjust. - (Ma): Change to a_mode. - (intel_operand_size): Handle a_mode. - * i386-opc.tbl: Allow Dword and Qword for bound. - * i386-tbl.h: Re-generate. - -2008-02-13 Jan Beulich <jbeulich@novell.com> - - * i386-gen.c (process_i386_registers): Process new fields. - * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to - unsigned char. Add dw2_regnum and Dw2Inval. - * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo - register names. - * i386-tbl.h: Re-generate. - -2008-02-11 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS. - * i386-init.h: Updated. - -2008-02-11 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flags): Add CpuXsave. - - * i386-opc.h (CpuXsave): New. - (CpuLM): Updated. - (i386_cpu_flags): Add cpuxsave. - - * i386-dis.c (MOD_0FAE_REG_4): New. - (RM_0F01_REG_2): Likewise. - (MOD_0FAE_REG_5): Updated. - (RM_0F01_REG_3): Likewise. - (reg_table): Use MOD_0FAE_REG_4. - (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated - for xrstor. - (rm_table): Add RM_0F01_REG_2. - - * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-02-11 Jan Beulich <jbeulich@novell.com> - - * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove - Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz). - * i386-tbl.h: Re-generate. - -2008-02-04 H.J. Lu <hongjiu.lu@intel.com> - - PR 5715 - * configure: Regenerated. - -2008-02-04 Adam Nemet <anemet@caviumnetworks.com> - - * mips-dis.c: Update copyright. - (mips_arch_choices): Add Octeon. - * mips-opc.c: Update copyright. - (IOCT): New macro. - (mips_builtin_opcodes): Add Octeon instruction synciobdma. - -2008-01-29 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Support optional L form mtmsr. - -2008-01-24 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (OP_E_extended): Handle r12 like rsp. - -2008-01-23 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS. - * i386-init.h: Regenerated. - -2008-01-23 Tristan Gingold <gingold@adacore.com> - - * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr, - ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr. - -2008-01-22 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flag_init): Remove CpuMMX2. - (cpu_flags): Likewise. - - * i386-opc.h (CpuMMX2): Removed. - (CpuSSE): Updated. - - * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-01-22 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and - CPU_SMX_FLAGS. - * i386-init.h: Regenerated. - -2008-01-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Use Qword on movddup. - * i386-tbl.h: Regenerated. - -2008-01-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax. - * i386-tbl.h: Regenerated. - -2008-01-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (Mx): New. - (PREFIX_0FC3): Likewise. - (PREFIX_0FC7_REG_6): Updated. - (dis386_twobyte): Use PREFIX_0FC3. - (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd. - Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on - movntss. - -2008-01-14 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (opcode_modifiers): Add IntelSyntax. - (operand_types): Add Mem. - - * i386-opc.h (IntelSyntax): New. - * i386-opc.h (Mem): New. - (Byte): Updated. - (Opcode_Modifier_Max): Updated. - (i386_opcode_modifier): Add intelsyntax. - (i386_operand_type): Add mem. - - * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more - instructions. - - * i386-reg.tbl: Add size for accumulator. - - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-01-13 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.h (Byte): Fix a typo. - -2008-01-12 H.J. Lu <hongjiu.lu@intel.com> - - PR gas/5534 - * i386-gen.c (operand_type_init): Add Dword to - OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64. - (opcode_modifiers): Remove CheckSize, Byte, Word, Dword, - Qword and Xmmword. - (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte, - Xmmword, Unspecified and Anysize. - (set_bitfield): Make Mmword an alias of Qword. Make Oword - an alias of Xmmword. - - * i386-opc.h (CheckSize): Removed. - (Byte): Updated. - (Word): Likewise. - (Dword): Likewise. - (Qword): Likewise. - (Xmmword): Likewise. - (FWait): Updated. - (OTMax): Likewise. - (i386_opcode_modifier): Remove checksize, byte, word, dword, - qword and xmmword. - (Fword): New. - (TBYTE): Likewise. - (Unspecified): Likewise. - (Anysize): Likewise. - (i386_operand_type): Add byte, word, dword, fword, qword, - tbyte xmmword, unspecified and anysize. - - * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword, - Tbyte, Xmmword, Unspecified and Anysize. - - * i386-reg.tbl: Add size for accumulator. - - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-01-10 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (REG_0F0E): Renamed to REG_0F0D. - (REG_0F18): Updated. - (reg_table): Updated. - (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e. - (twobyte_has_modrm): Set 1 for 0x19 to 0x1e. - -2008-01-08 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (set_bitfield): Use fail () on error. - -2008-01-08 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (lineno): New. - (filename): Likewise. - (set_bitfield): Report filename and line numer on error. - (process_i386_opcodes): Set filename and update lineno. - (process_i386_registers): Likewise. - -2008-01-05 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to - ATTSyntax. - - * i386-opc.h (IntelMnemonic): Renamed to .. - (ATTSyntax): This - (Opcode_Modifier_Max): Updated. - (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax - and intelsyntax. - - * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax - on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp. - * i386-tbl.h: Regenerated. - -2008-01-04 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c: Update copyright to 2008. - * i386-opc.h: Likewise. - * i386-opc.tbl: Likewise. - - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-01-04 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps, - pextrb, pextrw, pinsrb, pinsrw and pmovmskb. - * i386-tbl.h: Regenerated. - -2008-01-03 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and - CpuSSE4_2_Or_ABM. - (cpu_flags): Likewise. - - * i386-opc.h (CpuSSE4_1_Or_5): Removed. - (CpuSSE4_2_Or_ABM): Likewise. - (CpuLM): Updated. - (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm. - - * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and - Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2 - and CpuPadLock, respectively. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-01-03 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (opcode_modifiers): Remove No_xSuf. - - * i386-opc.h (No_xSuf): Removed. - (CheckSize): Updated. - - * i386-tbl.h: Regenerated. - -2008-01-02 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to - CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and - CPU_SSE5_FLAGS. - (cpu_flags): Add CpuSSE4_2_Or_ABM. - - * i386-opc.h (CpuSSE4_2_Or_ABM): New. - (CpuLM): Updated. - (i386_cpu_flags): Add cpusse4_2_or_abm. - - * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of - CpuABM|CpuSSE4_2 on popcnt. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2008-01-02 H.J. Lu <hongjiu.lu@intel.com> - - * i386-opc.h: Update comments. - -2008-01-02 H.J. Lu <hongjiu.lu@intel.com> - - * i386-gen.c (opcode_modifiers): Use Qword instead of QWord. - * i386-opc.h: Likewise. - * i386-opc.tbl: Likewise. - -2008-01-02 H.J. Lu <hongjiu.lu@intel.com> - - PR gas/5534 - * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize, - Byte, Word, Dword, QWord and Xmmword. - - * i386-opc.h (No_xSuf): New. - (CheckSize): Likewise. - (Byte): Likewise. - (Word): Likewise. - (Dword): Likewise. - (QWord): Likewise. - (Xmmword): Likewise. - (FWait): Updated. - (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word, - Dword, QWord and Xmmword. - - * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is - used. - * i386-tbl.h: Regenerated. - -2008-01-02 Mark Kettenis <kettenis@gnu.org> +2009-01-02 Matthias Klose <doko@ubuntu.com> - * m88k-dis.c (instructions): Fix fcvt.* instructions. - From Miod Vallat. + * or32-opc.c (or32_print_register, or32_print_immediate, + disassemble_insn): Don't rely on undefined sprintf behaviour. -For older changes see ChangeLog-2007 +For older changes see ChangeLog-2008 Local Variables: mode: change-log diff --git a/opcodes/ChangeLog-2008 b/opcodes/ChangeLog-2008 new file mode 100644 index 00000000000..4b4f7ba6424 --- /dev/null +++ b/opcodes/ChangeLog-2008 @@ -0,0 +1,1204 @@ +2008-12-30 Martin Schwidefsky <schwidefskyy@de.ibm.com> + + * s390-opc.txt: Add ptff instruction. + +2008-12-24 Jan Kratochvil <jan.kratochvil@redhat.com> + + * Makefile.am (CFILES, ALL_MACHINES): Add LM32 source and object files. + * Makefile.in: Regenerate. + +2008-12-23 Jon Beniston <jon@beniston.com> + + * Makefile.am: Add LM32 object files and dependencies. + * Makefile.in: Regenerate. + * configure.in: Add LM32 target. + * configure: Regenerate. + * disassemble.c: Add LM32 disassembler. + * cgen-asm.in: Update copyright year. + * cgen-dis.in: Update copyright year. + * cgen-ibld.in: Update copyright year. + * lm32-asm.c: New file. + * lm32-desc.c: New file. + * lm32-desc.h: New file. + * lm32-dis.c: New file. + * lm32-ibld.c: New file. + * lm32-opc.c: New file. + * lm32-opc.h: New file. + * lm32-opinst.c: New file. + +2008-12-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (EXdS): New. + (EXdVexS): Likewise. + (EXqVexS): Likewise. + (d_swap_mode): Likewise. + (q_mode): Updated. + (prefix_table): Use EXdS on movss and EXqS on movsd. + (vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd. + (intel_operand_size): Handle d_swap_mode. + (OP_EX): Likewise. + + * i386-opc.h (S): Update comments. + + * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd. + * i386-tbl.h: Regenerated. + +2008-12-23 Nick Clifton <nickc@redhat.com> + + * po/ga.po: Updated Irish translation. + +2008-12-20 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (EbS): New. + (EvS): Likewise. + (EMS): Likewise. + (EXqS): Likewise. + (EXxS): Likewise. + (b_swap_mode): Likewise. + (v_swap_mode): Likewise. + (q_swap_mode): Likewise. + (x_swap_mode): Likewise. + (v_mode): Updated. + (w_mode): Likewise. + (t_mode): Likewise. + (xmm_mode): Likewise. + (swap_operand): Likewise. + (dis386): Use EbS on movB. Use EvS on moveS. + (dis386_twobyte): Use EXxS on movapX. + (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa, + vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq. + (vex_table): Use EXxS on vmovapX. + (vex_len_table): Use EXqS on vmovq. + (intel_operand_size): Handle b_swap_mode, v_swap_mode, + q_swap_mode and x_swap_mode. + (OP_E_register): Handle b_swap_mode and v_swap_mode. + (OP_EM): Handle v_swap_mode. + (OP_EX): x_swap_mode and q_swap_mode. + + * i386-gen.c (opcode_modifiers): Add S. + + * i386-opc.h (S): New. + (Modrm): Updated. + (i386_opcode_modifier): Add s. + + * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq, + movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq. + * i386-tbl.h: Regenerated. + +2008-12-18 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (mnemonicendp): New. + (op): Likewise. + (print_insn): Use mnemonicendp. + (OP_3DNowSuffix): Likewise. + (CMP_Fixup): Likewise. + (CMPXCHG8B_Fixup): Likewise. + (CRC32_Fixup): Likewise. + (OP_DREX_FCMP): Likewise. + (OP_DREX_ICMP): Likewise. + (VZERO_Fixup): Likewise. + (VCMP_Fixup): Likewise. + (PCLMUL_Fixup): Likewise. + (VPERMIL2_Fixup): Likewise. + (MOVBE_Fixup): Likewise. + (putop): Update mnemonicendp. + (oappend): Use stpcpy. + (simd_cmp_op): Changed to struct op. + (vex_cmp_op): Likewise. + (pclmul_op): Likewise. + (vpermil2_op): Likewise. + +2008-12-18 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> + + * configure: Regenerate. + +2008-12-15 Richard Earnshaw <rearnsha@arm.com> + + * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using + unified syntax. + +2008-12-08 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD. + +2008-12-08 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (putop): Remove strayed comments. + +2008-12-04 Ben Elliston <bje@au.ibm.com> + + * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE + for -Mbooke. + (print_ppc_disassembler_options): Update usage. + * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove. + (BOOKE64): Remove. + (PPCCHLK64): Likewise. + (powerpc_opcodes): Remove all BOOKE64 instructions. + +2008-11-28 Joshua Kinard <kumba@gentoo.org> + + * mips-dis.c (mips_arch_choices): Add r14000, r16000. + +2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com> + + * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and + adjusted the mask for 32-bit branch instruction. + +2008-11-27 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (extract_sprg): Correct operand range check. + +2008-11-26 Andreas Schwab <schwab@suse.de> + + * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE) + (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling. + (save_printer, save_print_address): Remove. + (fetch_data): Don't use them. + (match_insn_m68k): Always restore printing functions. + (print_insn_m68k): Don't save/restore printing functions. + +2008-11-25 Nick Clifton <nickc@redhat.com> + + * m68k-dis.c: Rewrite to remove use of setjmp/longjmp. + +2008-11-18 Catherine Moore <clm@codesourcery.com> + + * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt + instructions. + (neon_opcodes): Likewise. + (print_insn_coprocessor): Print 't' or 'b' for vcvt + instructions. + +2008-11-14 Tristan Gingold <gingold@adacore.com> + + * makefile.vms (OBJS): Update list of objects. + (DEFS): Update + (CFLAGS): Update. + +2008-11-06 Chao-ying Fu <fu@mips.com> + + * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these + before sync. + (sync): New instruction with 5-bit sync type. + * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values. + +2008-11-06 Nick Clifton <nickc@redhat.com> + + * avr-dis.c: Replace uses of sprintf without a format string with + calls to strcpy. + +2008-11-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add cmovpe and cmovpo. + * i386-tbl.h: Regenerated. + +2008-10-22 Nick Clifton <nickc@redhat.com> + + PR 6937 + * configure.in (SHARED_LIBADD): Revert previous change. + Add a comment explaining why. + (SHARED_DEPENDENCIES): Revert previous change. + * configure: Regenerate. + +2008-10-10 Nick Clifton <nickc@redhat.com> + + PR 6937 + * configure.in (SHARED_LIBADD): Add libiberty.a. + (SHARED_DEPENDENCIES): Add libiberty.a. + +2008-09-30 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c: Include "hashtab.h". + (next_field): Take a new argument, last. Check last. + (process_i386_cpu_flag): Updated. + (process_i386_opcode_modifier): Likewise. + (process_i386_operand_type): Likewise. + (process_i386_registers): Likewise. + (output_i386_opcode): New. + (opcode_hash_entry): Likewise. + (opcode_hash_table): Likewise. + (opcode_hash_hash): Likewise. + (opcode_hash_eq): Likewise. + (process_i386_opcodes): Use opcode hash table and opcode array. + +2008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390-opc.txt (stdy, stey): Fix description + +2008-09-30 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2008-09-29 H.J. Lu <hongjiu.lu@intel.com> + + * aclocal.m4: Regenerated. + * configure: Likewise. + * Makefile.in: Likewise. + +2008-09-29 Nick Clifton <nickc@redhat.com> + + * po/vi.po: Updated Vietnamese translation. + * po/fr.po: Updated French translation. + +2008-09-26 Florian Krohm <fkrohm@us.ibm.com> + + * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF. + (cfxr, cfdr, cfer, clclu): Add esa flag. + (sqd): Instruction added. + (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF. + * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed. + +2008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl> + + * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes. + (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions. + +2008-09-11 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd]. + * i386-tbl.h: Regenerated. + +2008-08-28 Jan Beulich <jbeulich@novell.com> + + * i386-dis.c (dis386): Adjust far return mnemonics. + * i386-opc.tbl: Add retf. + * i386-tbl.h: Re-generate. + +2008-08-28 Jan Beulich <jbeulich@novell.com> + + * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics. + +2008-08-28 H.J. Lu <hongjiu.lu@intel.com> + + * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1. + * ia64-gen.c (lookup_specifier): Likewise. + + * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1. + * ia64-raw.tbl: Likewise. + * ia64-waw.tbl: Likewise. + * ia64-asmtab.c: Regenerated. + +2008-08-27 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Correct fidivr operand size. + + * i386-tbl.h: Regenerated. + +2008-08-24 Alan Modra <amodra@bigpond.net.au> + + * configure.in: Update a number of obsolete autoconf macros. + * aclocal.m4: Regenerate. + +2008-08-20 H.J. Lu <hongjiu.lu@intel.com> + + AVX Programming Reference (August, 2008) + * i386-dis.c (PREFIX_VEX_38DB): New. + (PREFIX_VEX_38DC): Likewise. + (PREFIX_VEX_38DD): Likewise. + (PREFIX_VEX_38DE): Likewise. + (PREFIX_VEX_38DF): Likewise. + (PREFIX_VEX_3ADF): Likewise. + (VEX_LEN_38DB_P_2): Likewise. + (VEX_LEN_38DC_P_2): Likewise. + (VEX_LEN_38DD_P_2): Likewise. + (VEX_LEN_38DE_P_2): Likewise. + (VEX_LEN_38DF_P_2): Likewise. + (VEX_LEN_3ADF_P_2): Likewise. + (PREFIX_VEX_3A04): Updated. + (VEX_LEN_3A06_P_2): Likewise. + (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC, + PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF. + (x86_64_table): Likewise. + (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2, + VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and + VEX_LEN_3ADF_P_2. + + * i386-opc.tbl: Add AES + AVX instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format. + * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format. + +2008-08-15 Alan Modra <amodra@bigpond.net.au> + + PR 6526 + * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS. + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + +2008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de> + + PR 6825 + * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300. + +2008-08-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add syscall and sysret for Cpu64. + + * i386-tbl.h: Regenerated. + +2008-08-04 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am (POTFILES.in): Set LC_ALL=C. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2008-08-01 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. + (print_insn_powerpc): Prepend 'vs' when printing VSX registers. + (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. + * ppc-opc.c (insert_xt6): New static function. + (extract_xt6): Likewise. + (insert_xa6): Likewise. + (extract_xa6: Likewise. + (insert_xb6): Likewise. + (extract_xb6): Likewise. + (insert_xb6s): Likewise. + (extract_xb6s): Likewise. + (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, + XX3DM_MASK, PPCVSX): New. + (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", + "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp". + +2008-08-01 Pedro Alves <pedro@codesourcery.com> + + * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation. + * Makefile.in: Regenerate. + +2008-08-01 H.J. Lu <hongjiu.lu@intel.com> + + * i386-reg.tbl: Use Dw2Inval on AVX registers. + * i386-tbl.h: Regenerated. + +2008-07-30 Michael J. Eager <eager@eagercon.com> + + * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields. + * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands. + (insert_sprg, PPC405): Use PPC_OPCODE_405. + (powerpc_opcodes): Add Xilinx APU related opcodes. + +2008-07-30 Alan Modra <amodra@bigpond.net.au> + + * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings. + +2008-07-10 Richard Sandiford <rdsandiford@googlemail.com> + + * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16. + +2008-07-07 Adam Nemet <anemet@caviumnetworks.com> + + * mips-opc.c (CP): New macro. + (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the + membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and + dmtc2 Octeon instructions. + +2008-07-07 Stan Shebs <stan@codesourcery.com> + + * dis-init.c (init_disassemble_info): Init endian_code field. + * arm-dis.c (print_insn): Disassemble code according to + setting of endian_code. + (print_insn_big_arm): Detect when BE8 extension flag has been set. + +2008-06-30 Richard Sandiford <rdsandiford@googlemail.com> + + * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check + for ELF symbols. + +2008-06-25 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (powerpc_init_dialect): Handle -M464. + (print_ppc_disassembler_options): Likewise. + * ppc-opc.c (PPC464): Define. + (powerpc_opcodes): Add mfdcrux and mtdcrux. + +2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> + + * configure: Regenerate. + +2008-06-13 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (print_insn_powerpc): Update prototye to use new + ppc_cpu_t typedef. + (struct dis_private): New. + (POWERPC_DIALECT): New define. + (powerpc_dialect): Renamed to... + (powerpc_init_dialect): This. Update to use ppc_cpu_t and + struct dis_private. + (print_insn_big_powerpc): Update for using structure in + info->private_data. + (print_insn_little_powerpc): Likewise. + (operand_value_powerpc): Change type of dialect param to ppc_cpu_t. + (skip_optional_operands): Likewise. + (print_insn_powerpc): Likewise. Remove initialization of dialect. + * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp, + extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe, + extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr, + extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm, + insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe, + insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs, + insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect + param to be of type ppc_cpu_t. Update prototype. + +2008-06-12 Adam Nemet <anemet@caviumnetworks.com> + + * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, + +s, +S. + * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions + baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, + syncw, syncws, vm3mulu, vm0 and vmulu. + + * mips-dis.c (print_insn_args): Handle field descriptor +Q. + * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, + seqi, sne and snei. + +2008-05-30 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add vmovd with 64bit operand. + * i386-tbl.h: Regenerated. + +2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format. + +2008-05-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi. + * i386-tbl.h: Regenerated. + +2008-05-22 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/6517 + * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss + into 32bit and 64bit. Remove Reg64|Qword and add + IgnoreSize|No_qSuf on 32bit version. + * i386-tbl.h: Regenerated. + +2008-05-21 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. + * i386-tbl.h: Regenerated. + +2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com> + + * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond. + +2008-05-14 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2008-05-02 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (MOVBE_Fixup): New. + (Mo): Likewise. + (PREFIX_0F3880): Likewise. + (PREFIX_0F3881): Likewise. + (PREFIX_0F38F0): Updated. + (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update + PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. + (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. + + * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and + CPU_EPT_FLAGS. + (cpu_flags): Add CpuMovbe and CpuEPT. + + * i386-opc.h (CpuMovbe): New. + (CpuEPT): Likewise. + (CpuLM): Updated. + (i386_cpu_flags): Add cpumovbe and cpuept. + + * i386-opc.tbl: Add entries for movbe and EPT instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-04-29 Adam Nemet <anemet@caviumnetworks.com> + + * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for + the two drem and the two dremu macros. + +2008-04-28 Adam Nemet <anemet@caviumnetworks.com> + + * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1 + instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and + cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros + INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D. + +2008-04-25 David S. Miller <davem@davemloft.net> + + * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr + instead of %sys_tick_cmpr, as suggested in architecture manuals. + +2008-04-23 Paolo Bonzini <bonzini@gnu.org> + + * aclocal.m4: Regenerate. + * configure: Regenerate. + +2008-04-23 David S. Miller <davem@davemloft.net> + + * sparc-opc.c (asi_table): Add UltraSPARC and Niagara + extended values. + (prefetch_table): Add missing values. + +2008-04-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (opcode_modifiers): Add NoAVX. + + * i386-opc.h (NoAVX): New. + (OldGcc): Updated. + (i386_opcode_modifier): Add noavx. + + * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3 + instructions which don't have AVX equivalent. + * i386-tbl.h: Regenerated. + +2008-04-18 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (OP_VEX_FMA): New. + (OP_EX_VexImmW): Likewise. + (VexFMA): Likewise. + (Vex128FMA): Likewise. + (EXVexImmW): Likewise. + (get_vex_imm8): Likewise. + (OP_EX_VexReg): Likewise. + (vex_i4_done): Renamed to ... + (vex_w_done): This. + (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps + and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on + FMA instructions. + (print_insn): Updated. + (OP_EX_VexW): Rewrite to swap register in VEX with EX. + (OP_REG_VexI4): Check invalid high registers. + +2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + Michael Meissner <michael.meissner@amd.com> + + * i386-opc.tbl: Fix protX to allow memory in the middle operand. + * i386-tbl.h: Regenerate from i386-opc.tbl. + +2008-04-14 Edmar Wienskoski <edmar@freescale.com> + + * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to + accept Power E500MC instructions. + (print_ppc_disassembler_options): Document -Me500mc. + * ppc-opc.c (DUIS, DUI, T): New. + (XRT, XRTRA): Likewise. + (E500MC): Likewise. + (powerpc_opcodes): Add new Power E500MC instructions. + +2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> + + * s390-dis.c (init_disasm): Evaluate disassembler_options. + (print_s390_disassembler_options): New function. + * disassemble.c (disassembler_usage): Invoke + print_s390_disassembler_options. + +2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> + + * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes + of local variables used for mnemonic parsing: prefix, suffix and + number. + +2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> + + * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic + extensions for conditional jumps (o, p, m, nz, z, nm, np, no). + (s390_crb_extensions): New extensions table. + (insertExpandedMnemonic): Handle '$' tag. + * s390-opc.txt: Remove conditional jump variants which can now + be expanded automatically. + Replace '*' tag with '$' in the compare and branch instructions. + +2008-04-07 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (PREFIX_VEX_38XX): Add a tab. + (PREFIX_VEX_3AXX): Likewis. + +2008-04-07 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Remove 4 extra blank lines. + +2008-04-04 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL + with CPU_PCLMUL_FLAGS/CpuPCLMUL. + (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. + * i386-opc.tbl: Likewise. + + * i386-opc.h (CpuCLMUL): Renamed to ... + (CpuPCLMUL): This. + (CpuFMA): Updated. + (i386_cpu_flags): Replace cpuclmul with cpupclmul. + + * i386-init.h: Regenerated. + +2008-04-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (OP_E_register): New. + (OP_E_memory): Likewise. + (OP_VEX): Likewise. + (OP_EX_Vex): Likewise. + (OP_EX_VexW): Likewise. + (OP_XMM_Vex): Likewise. + (OP_XMM_VexW): Likewise. + (OP_REG_VexI4): Likewise. + (PCLMUL_Fixup): Likewise. + (VEXI4_Fixup): Likewise. + (VZERO_Fixup): Likewise. + (VCMP_Fixup): Likewise. + (VPERMIL2_Fixup): Likewise. + (rex_original): Likewise. + (rex_ignored): Likewise. + (Mxmm): Likewise. + (XMM): Likewise. + (EXxmm): Likewise. + (EXxmmq): Likewise. + (EXymmq): Likewise. + (Vex): Likewise. + (Vex128): Likewise. + (Vex256): Likewise. + (VexI4): Likewise. + (EXdVex): Likewise. + (EXqVex): Likewise. + (EXVexW): Likewise. + (EXdVexW): Likewise. + (EXqVexW): Likewise. + (XMVex): Likewise. + (XMVexW): Likewise. + (XMVexI4): Likewise. + (PCLMUL): Likewise. + (VZERO): Likewise. + (VCMP): Likewise. + (VPERMIL2): Likewise. + (xmm_mode): Likewise. + (xmmq_mode): Likewise. + (ymmq_mode): Likewise. + (vex_mode): Likewise. + (vex128_mode): Likewise. + (vex256_mode): Likewise. + (USE_VEX_C4_TABLE): Likewise. + (USE_VEX_C5_TABLE): Likewise. + (USE_VEX_LEN_TABLE): Likewise. + (VEX_C4_TABLE): Likewise. + (VEX_C5_TABLE): Likewise. + (VEX_LEN_TABLE): Likewise. + (REG_VEX_XX): Likewise. + (MOD_VEX_XXX): Likewise. + (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. + (PREFIX_0F3A44): Likewise. + (PREFIX_0F3ADF): Likewise. + (PREFIX_VEX_XXX): Likewise. + (VEX_OF): Likewise. + (VEX_OF38): Likewise. + (VEX_OF3A): Likewise. + (VEX_LEN_XXX): Likewise. + (vex): Likewise. + (need_vex): Likewise. + (need_vex_reg): Likewise. + (vex_i4_done): Likewise. + (vex_table): Likewise. + (vex_len_table): Likewise. + (OP_REG_VexI4): Likewise. + (vex_cmp_op): Likewise. + (pclmul_op): Likewise. + (vpermil2_op): Likewise. + (m_mode): Updated. + (es_reg): Likewise. + (PREFIX_0F38F0): Likewise. + (PREFIX_0F3A60): Likewise. + (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. + (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF + and PREFIX_VEX_XXX entries. + (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. + (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and + PREFIX_0F3ADF. + (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. + Add MOD_VEX_XXX entries. + (ckprefix): Initialize rex_original and rex_ignored. Store the + REX byte in rex_original. + (get_valid_dis386): Handle the implicit prefix in VEX prefix + bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. + (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before + calling get_valid_dis386. Use rex_original and rex_ignored when + printing out REX. + (putop): Handle "XY". + (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and + ymmq_mode. + (OP_E_extended): Updated to use OP_E_register and + OP_E_memory. + (OP_XMM): Handle VEX. + (OP_EX): Likewise. + (XMM_Fixup): Likewise. + (CMP_Fixup): Use ARRAY_SIZE. + + * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, + CPU_FMA_FLAGS and CPU_AVX_FLAGS. + (operand_type_init): Add OPERAND_TYPE_REGYMM and + OPERAND_TYPE_VEX_IMM4. + (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. + (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, + VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, + VexImmExt and SSE2AVX. + (operand_types): Add RegYMM, Ymmword and Vex_Imm4. + + * i386-opc.h (CpuAVX): New. + (CpuAES): Likewise. + (CpuCLMUL): Likewise. + (CpuFMA): Likewise. + (Vex): Likewise. + (Vex256): Likewise. + (VexNDS): Likewise. + (VexNDD): Likewise. + (VexW0): Likewise. + (VexW1): Likewise. + (Vex0F): Likewise. + (Vex0F38): Likewise. + (Vex0F3A): Likewise. + (Vex3Sources): Likewise. + (VexImmExt): Likewise. + (SSE2AVX): Likewise. + (RegYMM): Likewise. + (Ymmword): Likewise. + (Vex_Imm4): Likewise. + (Implicit1stXmm0): Likewise. + (CpuXsave): Updated. + (CpuLM): Likewise. + (ByteOkIntel): Likewise. + (OldGcc): Likewise. + (Control): Likewise. + (Unspecified): Likewise. + (OTMax): Likewise. + (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. + (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, + vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, + vex3sources, veximmext and sse2avx. + (i386_operand_type): Add regymm, ymmword and vex_imm4. + + * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. + + * i386-reg.tbl: Add AVX registers, ymm0..ymm15. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com> + + From Robin Getz <robin.getz@analog.com> + * bfin-dis.c (bu32): Typedef. + (enum const_forms_t): Add c_uimm32 and c_huimm32. + (constant_formats[]): Add uimm32 and huimm16. + (fmtconst_val): New. + (uimm32): Define. + (huimm32): Define. + (imm16_val): Define. + (luimm16_val): Define. + (struct saved_state): Define. + (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, + A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, + LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. + (get_allreg): New. + (decode_LDIMMhalf_0): Print out the whole register value. + + From Jie Zhang <jie.zhang@analog.com> + * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for + multiply and multiply-accumulate to data register instruction. + + * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, + c_imm32, c_huimm32e): Define. + (constant_formats): Add flags for printing decimal, leading spaces, and + exact symbols. + (comment, parallel): Add global flags in all disassembly. + (fmtconst): Take advantage of new flags, and print default in hex. + (fmtconst_val): Likewise. + (decode_macfunc): Be consistant with spaces, tabs, comments, + capitalization in disassembly, fix minor coding style issues. + (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. + (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, + decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, + decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, + decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, + decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, + decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, + decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, + decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, + decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, + _print_insn_bfin, print_insn_bfin): Likewise. + +2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> + + * aclocal.m4: Regenerate. + * configure: Likewise. + * Makefile.in: Likewise. + +2008-03-13 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * configure: Regenerate. + +2008-03-07 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (powerpc_opcodes): Order and format. + +2008-03-01 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64. + * i386-tbl.h: Regenerated. + +2008-02-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Disallow 16-bit near indirect branches for + x86-64. + * i386-tbl.h: Regenerated. + +2008-02-21 Jan Beulich <jbeulich@novell.com> + + * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword + and Fword for far indirect jmp. Allow Reg16 and Word for near + indirect jmp on x86-64. Disallow Fword for lcall. + * i386-tbl.h: Re-generate. + +2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> + + * cr16-opc.c (cr16_num_optab): Defined + +2008-02-16 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG. + * i386-init.h: Regenerated. + +2008-02-14 Nick Clifton <nickc@redhat.com> + + PR binutils/5524 + * configure.in (SHARED_LIBADD): Select the correct host specific + file extension for shared libraries. + * configure: Regenerate. + +2008-02-13 Jan Beulich <jbeulich@novell.com> + + * i386-opc.h (RegFlat): New. + * i386-reg.tbl (flat): Add. + * i386-tbl.h: Re-generate. + +2008-02-13 Jan Beulich <jbeulich@novell.com> + + * i386-dis.c (a_mode): New. + (cond_jump_mode): Adjust. + (Ma): Change to a_mode. + (intel_operand_size): Handle a_mode. + * i386-opc.tbl: Allow Dword and Qword for bound. + * i386-tbl.h: Re-generate. + +2008-02-13 Jan Beulich <jbeulich@novell.com> + + * i386-gen.c (process_i386_registers): Process new fields. + * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to + unsigned char. Add dw2_regnum and Dw2Inval. + * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo + register names. + * i386-tbl.h: Re-generate. + +2008-02-11 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS. + * i386-init.h: Updated. + +2008-02-11 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flags): Add CpuXsave. + + * i386-opc.h (CpuXsave): New. + (CpuLM): Updated. + (i386_cpu_flags): Add cpuxsave. + + * i386-dis.c (MOD_0FAE_REG_4): New. + (RM_0F01_REG_2): Likewise. + (MOD_0FAE_REG_5): Updated. + (RM_0F01_REG_3): Likewise. + (reg_table): Use MOD_0FAE_REG_4. + (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated + for xrstor. + (rm_table): Add RM_0F01_REG_2. + + * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-02-11 Jan Beulich <jbeulich@novell.com> + + * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove + Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz). + * i386-tbl.h: Re-generate. + +2008-02-04 H.J. Lu <hongjiu.lu@intel.com> + + PR 5715 + * configure: Regenerated. + +2008-02-04 Adam Nemet <anemet@caviumnetworks.com> + + * mips-dis.c: Update copyright. + (mips_arch_choices): Add Octeon. + * mips-opc.c: Update copyright. + (IOCT): New macro. + (mips_builtin_opcodes): Add Octeon instruction synciobdma. + +2008-01-29 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c: Support optional L form mtmsr. + +2008-01-24 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (OP_E_extended): Handle r12 like rsp. + +2008-01-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS. + * i386-init.h: Regenerated. + +2008-01-23 Tristan Gingold <gingold@adacore.com> + + * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr, + ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr. + +2008-01-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Remove CpuMMX2. + (cpu_flags): Likewise. + + * i386-opc.h (CpuMMX2): Removed. + (CpuSSE): Updated. + + * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and + CPU_SMX_FLAGS. + * i386-init.h: Regenerated. + +2008-01-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Use Qword on movddup. + * i386-tbl.h: Regenerated. + +2008-01-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax. + * i386-tbl.h: Regenerated. + +2008-01-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (Mx): New. + (PREFIX_0FC3): Likewise. + (PREFIX_0FC7_REG_6): Updated. + (dis386_twobyte): Use PREFIX_0FC3. + (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd. + Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on + movntss. + +2008-01-14 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (opcode_modifiers): Add IntelSyntax. + (operand_types): Add Mem. + + * i386-opc.h (IntelSyntax): New. + * i386-opc.h (Mem): New. + (Byte): Updated. + (Opcode_Modifier_Max): Updated. + (i386_opcode_modifier): Add intelsyntax. + (i386_operand_type): Add mem. + + * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more + instructions. + + * i386-reg.tbl: Add size for accumulator. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-13 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.h (Byte): Fix a typo. + +2008-01-12 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/5534 + * i386-gen.c (operand_type_init): Add Dword to + OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64. + (opcode_modifiers): Remove CheckSize, Byte, Word, Dword, + Qword and Xmmword. + (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte, + Xmmword, Unspecified and Anysize. + (set_bitfield): Make Mmword an alias of Qword. Make Oword + an alias of Xmmword. + + * i386-opc.h (CheckSize): Removed. + (Byte): Updated. + (Word): Likewise. + (Dword): Likewise. + (Qword): Likewise. + (Xmmword): Likewise. + (FWait): Updated. + (OTMax): Likewise. + (i386_opcode_modifier): Remove checksize, byte, word, dword, + qword and xmmword. + (Fword): New. + (TBYTE): Likewise. + (Unspecified): Likewise. + (Anysize): Likewise. + (i386_operand_type): Add byte, word, dword, fword, qword, + tbyte xmmword, unspecified and anysize. + + * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword, + Tbyte, Xmmword, Unspecified and Anysize. + + * i386-reg.tbl: Add size for accumulator. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-10 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (REG_0F0E): Renamed to REG_0F0D. + (REG_0F18): Updated. + (reg_table): Updated. + (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e. + (twobyte_has_modrm): Set 1 for 0x19 to 0x1e. + +2008-01-08 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (set_bitfield): Use fail () on error. + +2008-01-08 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (lineno): New. + (filename): Likewise. + (set_bitfield): Report filename and line numer on error. + (process_i386_opcodes): Set filename and update lineno. + (process_i386_registers): Likewise. + +2008-01-05 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to + ATTSyntax. + + * i386-opc.h (IntelMnemonic): Renamed to .. + (ATTSyntax): This + (Opcode_Modifier_Max): Updated. + (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax + and intelsyntax. + + * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax + on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp. + * i386-tbl.h: Regenerated. + +2008-01-04 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c: Update copyright to 2008. + * i386-opc.h: Likewise. + * i386-opc.tbl: Likewise. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-04 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps, + pextrb, pextrw, pinsrb, pinsrw and pmovmskb. + * i386-tbl.h: Regenerated. + +2008-01-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and + CpuSSE4_2_Or_ABM. + (cpu_flags): Likewise. + + * i386-opc.h (CpuSSE4_1_Or_5): Removed. + (CpuSSE4_2_Or_ABM): Likewise. + (CpuLM): Updated. + (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm. + + * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and + Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2 + and CpuPadLock, respectively. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (opcode_modifiers): Remove No_xSuf. + + * i386-opc.h (No_xSuf): Removed. + (CheckSize): Updated. + + * i386-tbl.h: Regenerated. + +2008-01-02 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to + CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and + CPU_SSE5_FLAGS. + (cpu_flags): Add CpuSSE4_2_Or_ABM. + + * i386-opc.h (CpuSSE4_2_Or_ABM): New. + (CpuLM): Updated. + (i386_cpu_flags): Add cpusse4_2_or_abm. + + * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of + CpuABM|CpuSSE4_2 on popcnt. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-02 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.h: Update comments. + +2008-01-02 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (opcode_modifiers): Use Qword instead of QWord. + * i386-opc.h: Likewise. + * i386-opc.tbl: Likewise. + +2008-01-02 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/5534 + * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize, + Byte, Word, Dword, QWord and Xmmword. + + * i386-opc.h (No_xSuf): New. + (CheckSize): Likewise. + (Byte): Likewise. + (Word): Likewise. + (Dword): Likewise. + (QWord): Likewise. + (Xmmword): Likewise. + (FWait): Updated. + (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word, + Dword, QWord and Xmmword. + + * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is + used. + * i386-tbl.h: Regenerated. + +2008-01-02 Mark Kettenis <kettenis@gnu.org> + + * m88k-dis.c (instructions): Fix fcvt.* instructions. + From Miod Vallat. + +For older changes see ChangeLog-2007 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index e89f200295e..58e36d99c5e 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,6 +1,6 @@ /* Print i386 instructions for GDB, the GNU debugger. Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -93,18 +93,12 @@ static void OP_MS (int, int); static void OP_XS (int, int); static void OP_M (int, int); static void OP_VEX (int, int); -static void OP_VEX_FMA (int, int); static void OP_EX_Vex (int, int); -static void OP_EX_VexW (int, int); -static void OP_EX_VexImmW (int, int); static void OP_XMM_Vex (int, int); -static void OP_XMM_VexW (int, int); static void OP_REG_VexI4 (int, int); static void PCLMUL_Fixup (int, int); -static void VEXI4_Fixup (int, int); static void VZERO_Fixup (int, int); static void VCMP_Fixup (int, int); -static void VPERMIL2_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); @@ -370,6 +364,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EXxmm { OP_EX, xmm_mode } #define EXxmmq { OP_EX, xmmq_mode } #define EXymmq { OP_EX, ymmq_mode } +#define EXVexWdq { OP_EX, vex_w_dq_mode } #define MS { OP_MS, v_mode } #define XS { OP_XS, v_mode } #define EMCq { OP_EMC, q_mode } @@ -381,24 +376,15 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex { OP_VEX, vex_mode } #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } -#define VexI4 { VEXI4_Fixup, 0} -#define VexFMA { OP_VEX_FMA, vex_mode } -#define Vex128FMA { OP_VEX_FMA, vex128_mode } #define EXdVex { OP_EX_Vex, d_mode } #define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXqVex { OP_EX_Vex, q_mode } #define EXqVexS { OP_EX_Vex, q_swap_mode } -#define EXVexW { OP_EX_VexW, x_mode } -#define EXdVexW { OP_EX_VexW, d_mode } -#define EXqVexW { OP_EX_VexW, q_mode } -#define EXVexImmW { OP_EX_VexImmW, x_mode } #define XMVex { OP_XMM_Vex, 0 } -#define XMVexW { OP_XMM_VexW, 0 } #define XMVexI4 { OP_REG_VexI4, x_mode } #define PCLMUL { PCLMUL_Fixup, 0 } #define VZERO { VZERO_Fixup, 0 } #define VCMP { VCMP_Fixup, 0 } -#define VPERMIL2 { VPERMIL2_Fixup, 0 } /* Used handle "rep" prefix for string instructions. */ #define Xbr { REP_Fixup, eSI_reg } @@ -477,8 +463,10 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define vex128_mode (vex_mode + 1) /* 256bit vex mode */ #define vex256_mode (vex128_mode + 1) +/* operand size depends on the VEX.W bit. */ +#define vex_w_dq_mode (vex256_mode + 1) -#define es_reg (vex256_mode + 1) +#define es_reg (vex_w_dq_mode + 1) #define cs_reg (es_reg + 1) #define ss_reg (cs_reg + 1) #define ds_reg (ss_reg + 1) @@ -957,7 +945,37 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1) #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1) #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1) -#define PREFIX_VEX_38DB (PREFIX_VEX_3841 + 1) +#define PREFIX_VEX_3896 (PREFIX_VEX_3841 + 1) +#define PREFIX_VEX_3897 (PREFIX_VEX_3896 + 1) +#define PREFIX_VEX_3898 (PREFIX_VEX_3897 + 1) +#define PREFIX_VEX_3899 (PREFIX_VEX_3898 + 1) +#define PREFIX_VEX_389A (PREFIX_VEX_3899 + 1) +#define PREFIX_VEX_389B (PREFIX_VEX_389A + 1) +#define PREFIX_VEX_389C (PREFIX_VEX_389B + 1) +#define PREFIX_VEX_389D (PREFIX_VEX_389C + 1) +#define PREFIX_VEX_389E (PREFIX_VEX_389D + 1) +#define PREFIX_VEX_389F (PREFIX_VEX_389E + 1) +#define PREFIX_VEX_38A6 (PREFIX_VEX_389F + 1) +#define PREFIX_VEX_38A7 (PREFIX_VEX_38A6 + 1) +#define PREFIX_VEX_38A8 (PREFIX_VEX_38A7 + 1) +#define PREFIX_VEX_38A9 (PREFIX_VEX_38A8 + 1) +#define PREFIX_VEX_38AA (PREFIX_VEX_38A9 + 1) +#define PREFIX_VEX_38AB (PREFIX_VEX_38AA + 1) +#define PREFIX_VEX_38AC (PREFIX_VEX_38AB + 1) +#define PREFIX_VEX_38AD (PREFIX_VEX_38AC + 1) +#define PREFIX_VEX_38AE (PREFIX_VEX_38AD + 1) +#define PREFIX_VEX_38AF (PREFIX_VEX_38AE + 1) +#define PREFIX_VEX_38B6 (PREFIX_VEX_38AF + 1) +#define PREFIX_VEX_38B7 (PREFIX_VEX_38B6 + 1) +#define PREFIX_VEX_38B8 (PREFIX_VEX_38B7 + 1) +#define PREFIX_VEX_38B9 (PREFIX_VEX_38B8 + 1) +#define PREFIX_VEX_38BA (PREFIX_VEX_38B9 + 1) +#define PREFIX_VEX_38BB (PREFIX_VEX_38BA + 1) +#define PREFIX_VEX_38BC (PREFIX_VEX_38BB + 1) +#define PREFIX_VEX_38BD (PREFIX_VEX_38BC + 1) +#define PREFIX_VEX_38BE (PREFIX_VEX_38BD + 1) +#define PREFIX_VEX_38BF (PREFIX_VEX_38BE + 1) +#define PREFIX_VEX_38DB (PREFIX_VEX_38BF + 1) #define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1) #define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1) #define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1) @@ -985,36 +1003,14 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1) #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1) #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1) -#define PREFIX_VEX_3A48 (PREFIX_VEX_3A42 + 1) -#define PREFIX_VEX_3A49 (PREFIX_VEX_3A48 + 1) -#define PREFIX_VEX_3A4A (PREFIX_VEX_3A49 + 1) +#define PREFIX_VEX_3A4A (PREFIX_VEX_3A42 + 1) #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1) #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1) -#define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1) -#define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1) -#define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1) -#define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1) -#define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1) +#define PREFIX_VEX_3A60 (PREFIX_VEX_3A4C + 1) #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1) #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1) #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1) -#define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1) -#define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1) -#define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1) -#define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1) -#define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1) -#define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1) -#define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1) -#define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1) -#define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1) -#define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1) -#define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1) -#define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1) -#define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1) -#define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1) -#define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1) -#define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1) -#define PREFIX_VEX_3ADF (PREFIX_VEX_3A7F + 1) +#define PREFIX_VEX_3ADF (PREFIX_VEX_3A63 + 1) #define X86_64_06 0 #define X86_64_07 (X86_64_06 + 1) @@ -1250,15 +1246,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1) #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1) #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1) -#define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1) -#define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1) -#define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1) -#define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1) -#define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1) -#define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1) -#define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1) -#define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1) -#define VEX_LEN_3ADF_P_2 (VEX_LEN_3A7F_P_2 + 1) +#define VEX_LEN_3ADF_P_2 (VEX_LEN_3A63_P_2 + 1) typedef void (*op_rtn) (int bytemode, int sizeflag); @@ -1310,6 +1298,7 @@ struct dis386 { 2 upper case letter macros: "XY" => print 'x' or 'y' if no register operands or suffix_always is true. + 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA) 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand or suffix_always is true @@ -4573,459 +4562,523 @@ static const struct dis386 prefix_table[][4] = { { "(bad)", { XX } }, }, - /* PREFIX_VEX_38DB */ + /* PREFIX_VEX_3896 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) }, + { "vfmaddsub132p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_38DC */ + /* PREFIX_VEX_3897 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) }, + { "vfmsubadd132p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_38DD */ + /* PREFIX_VEX_3898 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) }, + { "vfmadd132p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_38DE */ + /* PREFIX_VEX_3899 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) }, + { "vfmadd132s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_38DF */ + /* PREFIX_VEX_389A */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) }, + { "vfmsub132p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A04 */ + /* PREFIX_VEX_389B */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vpermilps", { XM, EXx, Ib } }, + { "vfmsub132s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A05 */ + /* PREFIX_VEX_389C */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vpermilpd", { XM, EXx, Ib } }, + { "vfnmadd132p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A06 */ + /* PREFIX_VEX_389D */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) }, + { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A08 */ + /* PREFIX_VEX_389E */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vroundps", { XM, EXx, Ib } }, + { "vfnmsub132p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A09 */ + /* PREFIX_VEX_389F */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vroundpd", { XM, EXx, Ib } }, + { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A0A */ + /* PREFIX_VEX_38A6 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) }, + { "vfmaddsub213p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A0B */ + /* PREFIX_VEX_38A7 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) }, + { "vfmsubadd213p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A0C */ + /* PREFIX_VEX_38A8 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vblendps", { XM, Vex, EXx, Ib } }, + { "vfmadd213p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A0D */ + /* PREFIX_VEX_38A9 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vblendpd", { XM, Vex, EXx, Ib } }, + { "vfmadd213s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A0E */ + /* PREFIX_VEX_38AA */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) }, + { "vfmsub213p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A0F */ + /* PREFIX_VEX_38AB */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) }, + { "vfmsub213s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A14 */ + /* PREFIX_VEX_38AC */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) }, + { "vfnmadd213p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A15 */ + /* PREFIX_VEX_38AD */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) }, + { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A16 */ + /* PREFIX_VEX_38AE */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) }, + { "vfnmsub213p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A17 */ + /* PREFIX_VEX_38AF */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) }, + { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A18 */ + /* PREFIX_VEX_38B6 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) }, + { "vfmaddsub231p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A19 */ + /* PREFIX_VEX_38B7 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) }, + { "vfmsubadd231p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A20 */ + /* PREFIX_VEX_38B8 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) }, + { "vfmadd231p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A21 */ + /* PREFIX_VEX_38B9 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) }, + { "vfmadd231s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A22 */ + /* PREFIX_VEX_38BA */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) }, + { "vfmsub231p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A40 */ + /* PREFIX_VEX_38BB */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vdpps", { XM, Vex, EXx, Ib } }, + { "vfmsub231s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A41 */ + /* PREFIX_VEX_38BC */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) }, + { "vfnmadd231p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A42 */ + /* PREFIX_VEX_38BD */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) }, + { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A48 */ + /* PREFIX_VEX_38BE */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } }, + { "vfnmsub231p%XW", { XM, Vex, EXx } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A49 */ + /* PREFIX_VEX_38BF */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } }, + { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A4A */ + /* PREFIX_VEX_38DB */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A4B */ + /* PREFIX_VEX_38DC */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A4C */ + /* PREFIX_VEX_38DD */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A5C */ + /* PREFIX_VEX_38DE */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A5D */ + /* PREFIX_VEX_38DF */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A5E */ + /* PREFIX_VEX_3A04 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { "vpermilps", { XM, EXx, Ib } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A5F */ + /* PREFIX_VEX_3A05 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { "vpermilpd", { XM, EXx, Ib } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A60 */ + /* PREFIX_VEX_3A06 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A61 */ + /* PREFIX_VEX_3A08 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) }, + { "vroundps", { XM, EXx, Ib } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A62 */ + /* PREFIX_VEX_3A09 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) }, + { "vroundpd", { XM, EXx, Ib } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A63 */ + /* PREFIX_VEX_3A0A */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0B */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0C */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vblendps", { XM, Vex, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0D */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vblendpd", { XM, Vex, EXx, Ib } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A68 */ + /* PREFIX_VEX_3A0E */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A0F */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A14 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A15 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A16 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A69 */ + /* PREFIX_VEX_3A17 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A6A */ + /* PREFIX_VEX_3A18 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A6B */ + /* PREFIX_VEX_3A19 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A6C */ + /* PREFIX_VEX_3A20 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A6D */ + /* PREFIX_VEX_3A21 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A6E */ + /* PREFIX_VEX_3A22 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) }, + { "(bad)", { XX } }, + }, + + /* PREFIX_VEX_3A40 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) }, + { "vdpps", { XM, Vex, EXx, Ib } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A6F */ + /* PREFIX_VEX_3A41 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A78 */ + /* PREFIX_VEX_3A42 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A79 */ + /* PREFIX_VEX_3A4A */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A7A */ + /* PREFIX_VEX_3A4B */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) }, + { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A7B */ + /* PREFIX_VEX_3A4C */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A7C */ + /* PREFIX_VEX_3A60 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A7D */ + /* PREFIX_VEX_3A61 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, + { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A7E */ + /* PREFIX_VEX_3A62 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) }, { "(bad)", { XX } }, }, - /* PREFIX_VEX_3A7F */ + /* PREFIX_VEX_3A63 */ { { "(bad)", { XX } }, { "(bad)", { XX } }, - { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) }, { "(bad)", { XX } }, }, @@ -7420,17 +7473,17 @@ static const struct dis386 vex_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_3896) }, + { PREFIX_TABLE (PREFIX_VEX_3897) }, /* 98 */ - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_3898) }, + { PREFIX_TABLE (PREFIX_VEX_3899) }, + { PREFIX_TABLE (PREFIX_VEX_389A) }, + { PREFIX_TABLE (PREFIX_VEX_389B) }, + { PREFIX_TABLE (PREFIX_VEX_389C) }, + { PREFIX_TABLE (PREFIX_VEX_389D) }, + { PREFIX_TABLE (PREFIX_VEX_389E) }, + { PREFIX_TABLE (PREFIX_VEX_389F) }, /* a0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -7438,17 +7491,17 @@ static const struct dis386 vex_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_38A6) }, + { PREFIX_TABLE (PREFIX_VEX_38A7) }, /* a8 */ - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_38A8) }, + { PREFIX_TABLE (PREFIX_VEX_38A9) }, + { PREFIX_TABLE (PREFIX_VEX_38AA) }, + { PREFIX_TABLE (PREFIX_VEX_38AB) }, + { PREFIX_TABLE (PREFIX_VEX_38AC) }, + { PREFIX_TABLE (PREFIX_VEX_38AD) }, + { PREFIX_TABLE (PREFIX_VEX_38AE) }, + { PREFIX_TABLE (PREFIX_VEX_38AF) }, /* b0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -7456,17 +7509,17 @@ static const struct dis386 vex_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_38B6) }, + { PREFIX_TABLE (PREFIX_VEX_38B7) }, /* b8 */ - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREFIX_TABLE (PREFIX_VEX_38B8) }, + { PREFIX_TABLE (PREFIX_VEX_38B9) }, + { PREFIX_TABLE (PREFIX_VEX_38BA) }, + { PREFIX_TABLE (PREFIX_VEX_38BB) }, + { PREFIX_TABLE (PREFIX_VEX_38BC) }, + { PREFIX_TABLE (PREFIX_VEX_38BD) }, + { PREFIX_TABLE (PREFIX_VEX_38BE) }, + { PREFIX_TABLE (PREFIX_VEX_38BF) }, /* c0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -7624,8 +7677,8 @@ static const struct dis386 vex_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, /* 48 */ - { PREFIX_TABLE (PREFIX_VEX_3A48) }, - { PREFIX_TABLE (PREFIX_VEX_3A49) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, { PREFIX_TABLE (PREFIX_VEX_3A4A) }, { PREFIX_TABLE (PREFIX_VEX_3A4B) }, { PREFIX_TABLE (PREFIX_VEX_3A4C) }, @@ -7646,10 +7699,10 @@ static const struct dis386 vex_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { PREFIX_TABLE (PREFIX_VEX_3A5C) }, - { PREFIX_TABLE (PREFIX_VEX_3A5D) }, - { PREFIX_TABLE (PREFIX_VEX_3A5E) }, - { PREFIX_TABLE (PREFIX_VEX_3A5F) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, /* 60 */ { PREFIX_TABLE (PREFIX_VEX_3A60) }, { PREFIX_TABLE (PREFIX_VEX_3A61) }, @@ -7660,14 +7713,14 @@ static const struct dis386 vex_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, /* 68 */ - { PREFIX_TABLE (PREFIX_VEX_3A68) }, - { PREFIX_TABLE (PREFIX_VEX_3A69) }, - { PREFIX_TABLE (PREFIX_VEX_3A6A) }, - { PREFIX_TABLE (PREFIX_VEX_3A6B) }, - { PREFIX_TABLE (PREFIX_VEX_3A6C) }, - { PREFIX_TABLE (PREFIX_VEX_3A6D) }, - { PREFIX_TABLE (PREFIX_VEX_3A6E) }, - { PREFIX_TABLE (PREFIX_VEX_3A6F) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, /* 70 */ { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -7678,14 +7731,14 @@ static const struct dis386 vex_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, /* 78 */ - { PREFIX_TABLE (PREFIX_VEX_3A78) }, - { PREFIX_TABLE (PREFIX_VEX_3A79) }, - { PREFIX_TABLE (PREFIX_VEX_3A7A) }, - { PREFIX_TABLE (PREFIX_VEX_3A7B) }, - { PREFIX_TABLE (PREFIX_VEX_3A7C) }, - { PREFIX_TABLE (PREFIX_VEX_3A7D) }, - { PREFIX_TABLE (PREFIX_VEX_3A7E) }, - { PREFIX_TABLE (PREFIX_VEX_3A7F) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, /* 80 */ { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -8998,54 +9051,6 @@ static const struct dis386 vex_len_table[][2] = { { "(bad)", { XX } }, }, - /* VEX_LEN_3A6A_P_2 */ - { - { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - - /* VEX_LEN_3A6B_P_2 */ - { - { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - - /* VEX_LEN_3A6E_P_2 */ - { - { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - - /* VEX_LEN_3A6F_P_2 */ - { - { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - - /* VEX_LEN_3A7A_P_2 */ - { - { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - - /* VEX_LEN_3A7B_P_2 */ - { - { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - - /* VEX_LEN_3A7E_P_2 */ - { - { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - - /* VEX_LEN_3A7F_P_2 */ - { - { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, - { "(bad)", { XX } }, - }, - /* VEX_LEN_3ADF_P_2 */ { { "vaeskeygenassist", { XM, EXx, Ib } }, @@ -11197,21 +11202,35 @@ case_Q: } break; case 'W': - /* operand size flag for cwtl, cbtw */ - USED_REX (REX_W); - if (rex & REX_W) + if (l == 0 && len == 1) { - if (intel_syntax) - *obufp++ = 'd'; + /* operand size flag for cwtl, cbtw */ + USED_REX (REX_W); + if (rex & REX_W) + { + if (intel_syntax) + *obufp++ = 'd'; + else + *obufp++ = 'l'; + } + else if (sizeflag & DFLAG) + *obufp++ = 'w'; else - *obufp++ = 'l'; + *obufp++ = 'b'; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); } - else if (sizeflag & DFLAG) - *obufp++ = 'w'; else - *obufp++ = 'b'; - if (!(rex & REX_W)) - used_prefixes |= (prefixes & PREFIX_DATA); + { + if (l != 1 || len != 2 || last[0] != 'X') + { + SAVE_LAST (*p); + break; + } + if (!need_vex) + abort (); + *obufp++ = vex.w ? 'd': 's'; + } break; } alt = 0; @@ -11501,6 +11520,15 @@ intel_operand_size (int bytemode, int sizeflag) case o_mode: oappend ("OWORD PTR "); break; + case vex_w_dq_mode: + if (!need_vex) + abort (); + + if (vex.w) + oappend ("QWORD PTR "); + else + oappend ("DWORD PTR "); + break; default: break; } @@ -13458,204 +13486,6 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) oappend (scratchbuf + intel_syntax); } -/* Get the VEX immediate byte without moving codep. */ - -static unsigned char -get_vex_imm8 (int sizeflag) -{ - int bytes_before_imm = 0; - - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; - - if (modrm.mod != 3) - { - /* There are SIB/displacement bytes. */ - if ((sizeflag & AFLAG) || address_mode == mode_64bit) - { - /* 32/64 bit address mode */ - int base = modrm.rm; - - /* Check SIB byte. */ - if (base == 4) - { - FETCH_DATA (the_info, codep + 1); - base = *codep & 7; - bytes_before_imm++; - } - - switch (modrm.mod) - { - case 0: - /* When modrm.rm == 5 or modrm.rm == 4 and base in - SIB == 5, there is a 4 byte displacement. */ - if (base != 5) - /* No displacement. */ - break; - case 2: - /* 4 byte displacement. */ - bytes_before_imm += 4; - break; - case 1: - /* 1 byte displacement. */ - bytes_before_imm++; - break; - } - } - else - { /* 16 bit address mode */ - switch (modrm.mod) - { - case 0: - /* When modrm.rm == 6, there is a 2 byte displacement. */ - if (modrm.rm != 6) - /* No displacement. */ - break; - case 2: - /* 2 byte displacement. */ - bytes_before_imm += 2; - break; - case 1: - /* 1 byte displacement. */ - bytes_before_imm++; - break; - } - } - } - - FETCH_DATA (the_info, codep + bytes_before_imm + 1); - return codep [bytes_before_imm]; -} - -static void -OP_EX_VexReg (int bytemode, int sizeflag, int reg) -{ - if (reg == -1 && modrm.mod != 3) - { - OP_E_memory (bytemode, sizeflag, 0); - return; - } - else - { - if (reg == -1) - { - reg = modrm.rm; - USED_REX (REX_B); - if (rex & REX_B) - reg += 8; - } - else if (reg > 7 && address_mode != mode_64bit) - BadOp (); - } - - switch (vex.length) - { - case 128: - sprintf (scratchbuf, "%%xmm%d", reg); - break; - case 256: - sprintf (scratchbuf, "%%ymm%d", reg); - break; - default: - abort (); - } - oappend (scratchbuf + intel_syntax); -} - -static void -OP_EX_VexImmW (int bytemode, int sizeflag) -{ - int reg = -1; - static unsigned char vex_imm8; - - if (!vex_w_done) - { - vex_imm8 = get_vex_imm8 (sizeflag); - if (vex.w) - reg = vex_imm8 >> 4; - vex_w_done = 1; - } - else - { - if (!vex.w) - reg = vex_imm8 >> 4; - } - - OP_EX_VexReg (bytemode, sizeflag, reg); -} - -static void -OP_EX_VexW (int bytemode, int sizeflag) -{ - int reg = -1; - - if (!vex_w_done) - { - vex_w_done = 1; - if (vex.w) - reg = vex.register_specifier; - } - else - { - if (!vex.w) - reg = vex.register_specifier; - } - - OP_EX_VexReg (bytemode, sizeflag, reg); -} - -static void -OP_VEX_FMA (int bytemode, int sizeflag) -{ - int reg = get_vex_imm8 (sizeflag) >> 4; - - if (reg > 7 && address_mode != mode_64bit) - BadOp (); - - switch (vex.length) - { - case 128: - switch (bytemode) - { - case vex_mode: - case vex128_mode: - break; - default: - abort (); - return; - } - - sprintf (scratchbuf, "%%xmm%d", reg); - break; - case 256: - switch (bytemode) - { - case vex_mode: - break; - default: - abort (); - return; - } - - sprintf (scratchbuf, "%%ymm%d", reg); - break; - default: - abort (); - } - oappend (scratchbuf + intel_syntax); -} - -static void -VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* Skip the immediate byte and check for invalid bits. */ - FETCH_DATA (the_info, codep + 1); - if (*codep++ & 0xf) - BadOp (); -} - static void OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { @@ -13688,15 +13518,6 @@ OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) } static void -OP_XMM_VexW (int bytemode, int sizeflag) -{ - /* Turn off the REX.W bit since it is used for swapping operands - now. */ - rex &= ~REX_W; - OP_XMM (bytemode, sizeflag); -} - -static void OP_EX_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) @@ -13847,43 +13668,6 @@ PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, } } -static const struct op vpermil2_op[] = -{ - { STRING_COMMA_LEN ("td") }, - { STRING_COMMA_LEN ("td") }, - { STRING_COMMA_LEN ("mo") }, - { STRING_COMMA_LEN ("mz") } -}; - -static void -VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - unsigned int vpermil2_type; - - FETCH_DATA (the_info, codep + 1); - vpermil2_type = *codep++ & 0xf; - if (vpermil2_type < ARRAY_SIZE (vpermil2_op)) - { - char suffix [4]; - char *p = mnemonicendp - 3; - suffix[0] = p[0]; - suffix[1] = p[1]; - suffix[2] = p[2]; - suffix[3] = '\0'; - sprintf (p, "%s%s", vpermil2_op[vpermil2_type].name, suffix); - mnemonicendp += vpermil2_op[vpermil2_type].len; - } - else - { - /* We have a reserved extension byte. Output it directly. */ - scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, vpermil2_type); - oappend (scratchbuf + intel_syntax); - scratchbuf[0] = '\0'; - } -} - static void MOVBE_Fixup (int bytemode, int sizeflag) { diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 7fa61c2d265..cac9daa9b24 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1,5 +1,5 @@ /* Declarations for Intel 80386 opcode table - Copyright 2007, 2008 + Copyright 2007, 2008, 2009 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -248,8 +248,9 @@ typedef union i386_cpu_flags #define Vex (Drexc + 1) /* insn has 256bit VEX prefix. */ #define Vex256 (Vex + 1) -/* insn has VEX NDS. Register-only source is encoded in Vex - prefix. */ +/* insn has VEX NDS. Register-only source is encoded in Vex prefix. + We use VexNDS on insns with VEX DDS since the register-only source + is the second source register. */ #define VexNDS (Vex256 + 1) /* insn has VEX NDD. Register destination is encoded in Vex prefix. */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 29d3a0f1868..be4c89a2e04 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1,5 +1,5 @@ // i386 opcode table. -// Copyright 2007, 2008 +// Copyright 2007, 2008, 2009 // Free Software Foundation, Inc. // // This file is part of the GNU opcodes library. @@ -2192,14 +2192,6 @@ vpcmpgtw, 3, 0x6665, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf| vpcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } vpcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } vperm2f128, 4, 0x6606, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } @@ -2208,30 +2200,6 @@ vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bS vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } -vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } @@ -2389,70 +2357,102 @@ vaeskeygenassist, 3, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|Vex0F3A|IgnoreSiz // FMA instructions -vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } -vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } -vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd132sd, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd132ss, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213sd, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213ss, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231sd, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231ss, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub132sd, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub132ss, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213sd, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213ss, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231sd, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231ss, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd132sd, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132ss, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213sd, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213ss, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231sd, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231ss, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub132sd, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132ss, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213sd, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213ss, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231sd, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } // AMD 3DNow! instructions. diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 553582e0aaa..aa6f622cb00 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -22579,174 +22579,6 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vpermil2pd", 5, 0x6649, None, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermil2pd", 5, 0x6649, None, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermil2pd", 5, 0x6649, None, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermil2pd", 5, 0x6649, None, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermil2ps", 5, 0x6648, None, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 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0, 1, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermil2ps", 5, 0x6648, None, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, { "vpermilpd", 3, 0x660d, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -22867,438 +22699,6 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmo2pd", 4, 0x6649, 0x2, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmo2pd", 4, 0x6649, 0x2, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmo2pd", 4, 0x6649, 0x2, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmo2pd", 4, 0x6649, 0x2, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmz2pd", 4, 0x6649, 0x3, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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{ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmz2ps", 4, 0x6648, 0x3, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmz2ps", 4, 0x6648, 0x3, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermilmz2ps", 4, 0x6648, 0x3, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermiltd2ps", 4, 0x6648, 0x0, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermiltd2ps", 4, 0x6648, 0x0, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermiltd2ps", 4, 0x6648, 0x0, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, - { "vpermiltd2ps", 4, 0x6648, 0x0, 1, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, - { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 1, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } } } }, { "vpextrb", 3, 0x6614, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -25483,12 +24883,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddpd", 4, 0x6669, None, 1, + { "vfmadd132pd", 3, 0x6698, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -25497,20 +24897,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmadd132pd", 3, 0x6698, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddpd", 4, 0x6669, None, 1, + { "vfmadd132ps", 3, 0x6698, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25519,12 +24928,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddpd", 4, 0x6669, None, 1, + { "vfmadd132ps", 3, 0x6698, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -25533,20 +24942,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmadd213pd", 3, 0x66a8, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddpd", 4, 0x6669, None, 1, + { "vfmadd213pd", 3, 0x66a8, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25555,12 +24973,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddps", 4, 0x6668, None, 1, + { "vfmadd213ps", 3, 0x66a8, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -25569,20 +24987,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmadd213ps", 3, 0x66a8, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddps", 4, 0x6668, None, 1, + { "vfmadd231pd", 3, 0x66b8, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25591,12 +25018,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddps", 4, 0x6668, None, 1, + { "vfmadd231pd", 3, 0x66b8, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -25605,20 +25032,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmadd231ps", 3, 0x66b8, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddps", 4, 0x6668, None, 1, + { "vfmadd231ps", 3, 0x66b8, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25627,12 +25063,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsd", 4, 0x666b, None, 1, + { "vfmadd132sd", 3, 0x6699, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, @@ -25641,20 +25077,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsd", 4, 0x666b, None, 1, + { "vfmadd132ss", 3, 0x6699, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmadd213sd", 3, 0x66a9, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25663,12 +25108,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddss", 4, 0x666a, None, 1, + { "vfmadd213ss", 3, 0x66a9, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, @@ -25677,20 +25122,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddss", 4, 0x666a, None, 1, + { "vfmadd231sd", 3, 0x66b9, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmadd231ss", 3, 0x66b9, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25699,12 +25153,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubpd", 4, 0x665d, None, 1, + { "vfmaddsub132pd", 3, 0x6696, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -25713,20 +25167,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmaddsub132pd", 3, 0x6696, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubpd", 4, 0x665d, None, 1, + { "vfmaddsub132ps", 3, 0x6696, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25735,12 +25198,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubpd", 4, 0x665d, None, 1, + { "vfmaddsub132ps", 3, 0x6696, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -25749,20 +25212,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmaddsub213pd", 3, 0x66a6, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubpd", 4, 0x665d, None, 1, + { "vfmaddsub213pd", 3, 0x66a6, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25771,12 +25243,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubps", 4, 0x665c, None, 1, + { "vfmaddsub213ps", 3, 0x66a6, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -25785,20 +25257,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmaddsub213ps", 3, 0x66a6, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubps", 4, 0x665c, None, 1, + { "vfmaddsub231pd", 3, 0x66b6, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25807,12 +25288,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubps", 4, 0x665c, None, 1, + { "vfmaddsub231pd", 3, 0x66b6, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -25821,20 +25302,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmaddsub231ps", 3, 0x66b6, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmaddsubps", 4, 0x665c, None, 1, + { "vfmaddsub231ps", 3, 0x66b6, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25843,12 +25333,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddpd", 4, 0x665f, None, 1, + { "vfmsubadd132pd", 3, 0x6697, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -25857,20 +25347,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsubadd132pd", 3, 0x6697, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddpd", 4, 0x665f, None, 1, + { "vfmsubadd132ps", 3, 0x6697, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25879,12 +25378,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddpd", 4, 0x665f, None, 1, + { "vfmsubadd132ps", 3, 0x6697, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -25893,20 +25392,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsubadd213pd", 3, 0x66a7, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddpd", 4, 0x665f, None, 1, + { "vfmsubadd213pd", 3, 0x66a7, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25915,12 +25423,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddps", 4, 0x665e, None, 1, + { "vfmsubadd213ps", 3, 0x66a7, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -25929,20 +25437,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsubadd213ps", 3, 0x66a7, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddps", 4, 0x665e, None, 1, + { "vfmsubadd231pd", 3, 0x66b7, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25951,12 +25468,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddps", 4, 0x665e, None, 1, + { "vfmsubadd231pd", 3, 0x66b7, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -25965,20 +25482,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsubadd231ps", 3, 0x66b7, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubaddps", 4, 0x665e, None, 1, + { "vfmsubadd231ps", 3, 0x66b7, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -25987,12 +25513,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubpd", 4, 0x666d, None, 1, + { "vfmsub132pd", 3, 0x669a, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -26001,20 +25527,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsub132pd", 3, 0x669a, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubpd", 4, 0x666d, None, 1, + { "vfmsub132ps", 3, 0x669a, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26023,12 +25558,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubpd", 4, 0x666d, None, 1, + { "vfmsub132ps", 3, 0x669a, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -26037,20 +25572,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsub213pd", 3, 0x66aa, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubpd", 4, 0x666d, None, 1, + { "vfmsub213pd", 3, 0x66aa, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26059,12 +25603,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubps", 4, 0x666c, None, 1, + { "vfmsub213ps", 3, 0x66aa, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -26073,20 +25617,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsub213ps", 3, 0x66aa, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubps", 4, 0x666c, None, 1, + { "vfmsub231pd", 3, 0x66ba, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26095,12 +25648,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubps", 4, 0x666c, None, 1, + { "vfmsub231pd", 3, 0x66ba, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -26109,20 +25662,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsub231ps", 3, 0x66ba, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubps", 4, 0x666c, None, 1, + { "vfmsub231ps", 3, 0x66ba, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26131,12 +25693,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubsd", 4, 0x666f, None, 1, + { "vfmsub132sd", 3, 0x669b, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, @@ -26145,20 +25707,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubsd", 4, 0x666f, None, 1, + { "vfmsub132ss", 3, 0x669b, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsub213sd", 3, 0x66ab, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26167,12 +25738,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubss", 4, 0x666e, None, 1, + { "vfmsub213ss", 3, 0x66ab, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, @@ -26181,20 +25752,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfmsubss", 4, 0x666e, None, 1, + { "vfmsub231sd", 3, 0x66bb, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfmsub231ss", 3, 0x66bb, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26203,12 +25783,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddpd", 4, 0x6679, None, 1, + { "vfnmadd132pd", 3, 0x669c, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -26217,20 +25797,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmadd132pd", 3, 0x669c, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddpd", 4, 0x6679, None, 1, + { "vfnmadd132ps", 3, 0x669c, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26239,12 +25828,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddpd", 4, 0x6679, None, 1, + { "vfnmadd132ps", 3, 0x669c, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -26253,20 +25842,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmadd213pd", 3, 0x66ac, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddpd", 4, 0x6679, None, 1, + { "vfnmadd213pd", 3, 0x66ac, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26275,12 +25873,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddps", 4, 0x6678, None, 1, + { "vfnmadd213ps", 3, 0x66ac, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -26289,20 +25887,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmadd213ps", 3, 0x66ac, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddps", 4, 0x6678, None, 1, + { "vfnmadd231pd", 3, 0x66bc, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26311,12 +25918,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddps", 4, 0x6678, None, 1, + { "vfnmadd231pd", 3, 0x66bc, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -26325,20 +25932,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmadd231ps", 3, 0x66bc, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddps", 4, 0x6678, None, 1, + { "vfnmadd231ps", 3, 0x66bc, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26347,12 +25963,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddsd", 4, 0x667b, None, 1, + { "vfnmadd132sd", 3, 0x669d, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, @@ -26361,20 +25977,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddsd", 4, 0x667b, None, 1, + { "vfnmadd132ss", 3, 0x669d, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmadd213sd", 3, 0x66ad, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26383,12 +26008,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddss", 4, 0x667a, None, 1, + { "vfnmadd213ss", 3, 0x66ad, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, @@ -26397,20 +26022,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmaddss", 4, 0x667a, None, 1, + { "vfnmadd231sd", 3, 0x66bd, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmadd231ss", 3, 0x66bd, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26419,12 +26053,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubpd", 4, 0x667d, None, 1, + { "vfnmsub132pd", 3, 0x669e, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -26433,20 +26067,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmsub132pd", 3, 0x669e, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubpd", 4, 0x667d, None, 1, + { "vfnmsub132ps", 3, 0x669e, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26455,12 +26098,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubpd", 4, 0x667d, None, 1, + { "vfnmsub132ps", 3, 0x669e, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -26469,20 +26112,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmsub213pd", 3, 0x66ae, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubpd", 4, 0x667d, None, 1, + { "vfnmsub213pd", 3, 0x66ae, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26491,12 +26143,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubps", 4, 0x667c, None, 1, + { "vfnmsub213ps", 3, 0x66ae, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, @@ -26505,20 +26157,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmsub213ps", 3, 0x66ae, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubps", 4, 0x667c, None, 1, + { "vfnmsub231pd", 3, 0x66be, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26527,12 +26188,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubps", 4, 0x667c, None, 1, + { "vfnmsub231pd", 3, 0x66be, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, @@ -26541,20 +26202,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmsub231ps", 3, 0x66be, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubps", 4, 0x667c, None, 1, + { "vfnmsub231ps", 3, 0x66be, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26563,12 +26233,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubsd", 4, 0x667f, None, 1, + { "vfnmsub132sd", 3, 0x669f, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, @@ -26577,20 +26247,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubsd", 4, 0x667f, None, 1, + { "vfnmsub132ss", 3, 0x669f, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmsub213sd", 3, 0x66af, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -26599,12 +26278,12 @@ const template i386_optab[] = { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubss", 4, 0x667e, None, 1, + { "vfnmsub213ss", 3, 0x66af, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, @@ -26613,20 +26292,29 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "vfnmsubss", 4, 0x667e, None, 1, + { "vfnmsub231sd", 3, 0x66bf, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }, + 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "vfnmsub231ss", 3, 0x66bf, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |