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-rw-r--r--sim/testsuite/sim/arm/add.cgs43
1 files changed, 43 insertions, 0 deletions
diff --git a/sim/testsuite/sim/arm/add.cgs b/sim/testsuite/sim/arm/add.cgs
new file mode 100644
index 00000000000..eba32e0550c
--- /dev/null
+++ b/sim/testsuite/sim/arm/add.cgs
@@ -0,0 +1,43 @@
+# arm testcase for add
+# mach: all
+
+# ??? Unfinished, more tests needed.
+
+ .include "testutils.inc"
+
+ start
+
+# add$cond${set-cc?} $rd,$rn,$imm12
+
+ .global add_imm
+add_imm:
+ mvi_h_gr r4,1
+ mvi_h_cnvz 0,0,0,0
+ add r5,r4,#1
+ test_h_cnvz 0,0,0,0
+ test_h_gr r5,2
+
+# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
+
+ .global add_reg_imm_shift
+add_reg_imm_shift:
+ mvi_h_gr r4,1
+ mvi_h_gr r5,1
+ mvi_h_cnvz 0,0,0,0
+ add r6,r4,r5,lsl #2
+ test_h_cnvz 0,0,0,0
+ test_h_gr r6,5
+
+# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
+
+ .global add_reg_reg_shift
+add_reg_reg_shift:
+ mvi_h_gr r4,1
+ mvi_h_gr r5,1
+ mvi_h_gr r6,2
+ mvi_h_cnvz 0,0,0,0
+ add r7,r4,r5,lsl r6
+ test_h_cnvz 0,0,0,0
+ test_h_gr r7,5
+
+ pass