diff options
Diffstat (limited to 'sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs')
| -rw-r--r-- | sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs new file mode 100644 index 00000000000..33086c9630f --- /dev/null +++ b/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs @@ -0,0 +1,173 @@ +# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT +# mach: xscale +# as: -mcpu=xscale+iwmmxt + + .include "testutils.inc" + + start + + .global wcmpgt +wcmpgt: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Unsigned Byte Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtub wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffff00 + + # Test Signed Byte Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsb wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + # Test Unsigned Half Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtuh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffffff + + # Test Signed Half Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsh wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + # Test Unsigned Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtuw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0xffffffff + + # Test Signed Word Wide Compare Greater Than + + mvi_h_gr r0, 0x12345678 + mvi_h_gr r1, 0x9abcde00 + mvi_h_gr r2, 0x11111111 + mvi_h_gr r3, 0x22222222 + mvi_h_gr r4, 0 + mvi_h_gr r5, 0 + + tmcrr wr0, r0, r1 + tmcrr wr1, r2, r3 + tmcrr wr2, r4, r5 + + wcmpgtsw wr2, wr0, wr1 + + tmrrc r0, r1, wr0 + tmrrc r2, r3, wr1 + tmrrc r4, r5, wr2 + + test_h_gr r0, 0x12345678 + test_h_gr r1, 0x9abcde00 + test_h_gr r2, 0x11111111 + test_h_gr r3, 0x22222222 + test_h_gr r4, 0xffffffff + test_h_gr r5, 0x00000000 + + pass |