diff options
Diffstat (limited to 'sim/testsuite/sim/arm/thumb')
81 files changed, 1068 insertions, 0 deletions
diff --git a/sim/testsuite/sim/arm/thumb/adc.cgs b/sim/testsuite/sim/arm/thumb/adc.cgs new file mode 100644 index 00000000000..58d74c178f2 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/adc.cgs @@ -0,0 +1,12 @@ +# arm testcase for adc $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_adc +alu_adc: + adc r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs new file mode 100644 index 00000000000..0307acc4a32 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_hd_hs +add_hd_hs: + add r8,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs new file mode 100644 index 00000000000..ca080f7e98a --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_hd_rs +add_hd_rs: + add r8,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs new file mode 100644 index 00000000000..46373a0ab10 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_rd_hs +add_rd_hs: + add r0,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add-sp.cgs b/sim/testsuite/sim/arm/thumb/add-sp.cgs new file mode 100644 index 00000000000..54efa2abe33 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add sp,#$sword7 +# mach: unfinished + + .include "testutils.inc" + + start + + .global add_sp +add_sp: + add sp,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/add.cgs b/sim/testsuite/sim/arm/thumb/add.cgs new file mode 100644 index 00000000000..63cc20c275f --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/add.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$rs,$rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global add +add: + add r0,r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/addi.cgs b/sim/testsuite/sim/arm/thumb/addi.cgs new file mode 100644 index 00000000000..00ec76d0f88 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/addi.cgs @@ -0,0 +1,12 @@ +# arm testcase for add $rd,$rs,#$offset3 +# mach: unfinished + + .include "testutils.inc" + + start + + .global addi +addi: + add r0,r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/addi8.cgs b/sim/testsuite/sim/arm/thumb/addi8.cgs new file mode 100644 index 00000000000..d8e9f8162e4 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/addi8.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global addi8 +addi8: + add r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/allthumb.exp b/sim/testsuite/sim/arm/thumb/allthumb.exp new file mode 100644 index 00000000000..9674bca4845 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/allthumb.exp @@ -0,0 +1,21 @@ +# ARM simulator testsuite. + +if { [istarget arm*-*-*] + || [istarget thumb*-*-*] } { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "arm7tdmi" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/arm/thumb/and.cgs b/sim/testsuite/sim/arm/thumb/and.cgs new file mode 100644 index 00000000000..d67adf47533 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/and.cgs @@ -0,0 +1,12 @@ +# arm testcase for and $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_and +alu_and: + and r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/asr.cgs b/sim/testsuite/sim/arm/thumb/asr.cgs new file mode 100644 index 00000000000..4d21daedc23 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/asr.cgs @@ -0,0 +1,14 @@ +# arm testcase for asr $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_asr +alu_asr: + asr r0,r0 + +# FIXME: Also asr $rd,$rs,#$offset5 + + pass diff --git a/sim/testsuite/sim/arm/thumb/b.cgs b/sim/testsuite/sim/arm/thumb/b.cgs new file mode 100644 index 00000000000..ecae5373f3b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/b.cgs @@ -0,0 +1,12 @@ +# arm testcase for b $offset11 +# mach: unfinished + + .include "testutils.inc" + + start + + .global b +b: + b footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bcc.cgs b/sim/testsuite/sim/arm/thumb/bcc.cgs new file mode 100644 index 00000000000..6c84458e637 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bcc.cgs @@ -0,0 +1,12 @@ +# arm testcase for bcc $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bcc +bcc: + bcc footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bcs.cgs b/sim/testsuite/sim/arm/thumb/bcs.cgs new file mode 100644 index 00000000000..a29a8fb25ec --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bcs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bcs $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bcs +bcs: + bcs footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/beq.cgs b/sim/testsuite/sim/arm/thumb/beq.cgs new file mode 100644 index 00000000000..33f374829a1 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/beq.cgs @@ -0,0 +1,12 @@ +# arm testcase for beq $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global beq +beq: + beq footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bge.cgs b/sim/testsuite/sim/arm/thumb/bge.cgs new file mode 100644 index 00000000000..4eb543dcae2 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bge.cgs @@ -0,0 +1,12 @@ +# arm testcase for bge $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bge +bge: + bge footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bgt.cgs b/sim/testsuite/sim/arm/thumb/bgt.cgs new file mode 100644 index 00000000000..1ffe0927ff2 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bgt.cgs @@ -0,0 +1,12 @@ +# arm testcase for bgt $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bgt +bgt: + bgt footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bhi.cgs b/sim/testsuite/sim/arm/thumb/bhi.cgs new file mode 100644 index 00000000000..c9811c6b2b0 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bhi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bhi $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bhi +bhi: + bhi footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bic.cgs b/sim/testsuite/sim/arm/thumb/bic.cgs new file mode 100644 index 00000000000..6dca1efe137 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bic.cgs @@ -0,0 +1,12 @@ +# arm testcase for bic $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_bic +alu_bic: + bic r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/bl-hi.cgs b/sim/testsuite/sim/arm/thumb/bl-hi.cgs new file mode 100644 index 00000000000..c7400c7f481 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bl-hi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bl-hi ${lbwl-hi} +# mach: unfinished + + .include "testutils.inc" + + start + + .global bl_hi +bl_hi: + bl-hi 0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/bl-lo.cgs b/sim/testsuite/sim/arm/thumb/bl-lo.cgs new file mode 100644 index 00000000000..ed766130930 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bl-lo.cgs @@ -0,0 +1,12 @@ +# arm testcase for bl-lo ${lbwl-lo} +# mach: unfinished + + .include "testutils.inc" + + start + + .global bl_lo +bl_lo: + bl-lo 0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/ble.cgs b/sim/testsuite/sim/arm/thumb/ble.cgs new file mode 100644 index 00000000000..e9c5a8f5503 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ble.cgs @@ -0,0 +1,12 @@ +# arm testcase for ble $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global ble +ble: + ble footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bls.cgs b/sim/testsuite/sim/arm/thumb/bls.cgs new file mode 100644 index 00000000000..483412b872b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bls.cgs @@ -0,0 +1,12 @@ +# arm testcase for bls $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bls +bls: + bls footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/blt.cgs b/sim/testsuite/sim/arm/thumb/blt.cgs new file mode 100644 index 00000000000..0fbcbe8942b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/blt.cgs @@ -0,0 +1,12 @@ +# arm testcase for blt $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global blt +blt: + blt footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bmi.cgs b/sim/testsuite/sim/arm/thumb/bmi.cgs new file mode 100644 index 00000000000..8f7558a46ad --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bmi.cgs @@ -0,0 +1,12 @@ +# arm testcase for bmi $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bmi +bmi: + bmi footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bne.cgs b/sim/testsuite/sim/arm/thumb/bne.cgs new file mode 100644 index 00000000000..a5ac34841f7 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bne.cgs @@ -0,0 +1,12 @@ +# arm testcase for bne $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bne +bne: + bne footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bpl.cgs b/sim/testsuite/sim/arm/thumb/bpl.cgs new file mode 100644 index 00000000000..8f642591d4e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bpl.cgs @@ -0,0 +1,12 @@ +# arm testcase for bpl $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bpl +bpl: + bpl footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bvc.cgs b/sim/testsuite/sim/arm/thumb/bvc.cgs new file mode 100644 index 00000000000..bbd3af52833 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bvc.cgs @@ -0,0 +1,12 @@ +# arm testcase for bvc $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bvc +bvc: + bvc footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bvs.cgs b/sim/testsuite/sim/arm/thumb/bvs.cgs new file mode 100644 index 00000000000..8c9a551353c --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bvs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bvs $soffset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global bvs +bvs: + bvs footext + + pass diff --git a/sim/testsuite/sim/arm/thumb/bx-hs.cgs b/sim/testsuite/sim/arm/thumb/bx-hs.cgs new file mode 100644 index 00000000000..d96338791e4 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bx-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx $hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx_hs +bx_hs: + bx r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/bx-rs.cgs b/sim/testsuite/sim/arm/thumb/bx-rs.cgs new file mode 100644 index 00000000000..f6db8c86339 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/bx-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for bx $rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global bx_rs +bx_rs: + bx r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmn.cgs b/sim/testsuite/sim/arm/thumb/cmn.cgs new file mode 100644 index 00000000000..96d53a1f95f --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmn.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmn $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_cmn +alu_cmn: + cmn r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs new file mode 100644 index 00000000000..96a91a2fb34 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_hd_hs +cmp_hd_hs: + cmp r8,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs new file mode 100644 index 00000000000..9fc4875ff7e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_hd_rs +cmp_hd_rs: + cmp r8,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs new file mode 100644 index 00000000000..e3f7a4a2d61 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for cmp $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp_rd_hs +cmp_rd_hs: + cmp r0,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/cmp.cgs b/sim/testsuite/sim/arm/thumb/cmp.cgs new file mode 100644 index 00000000000..7564099c76d --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/cmp.cgs @@ -0,0 +1,14 @@ +# arm testcase for cmp ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global cmp +cmp: + cmp r0,#0 + +# FIXME: Also: cmp $rd,$rs + + pass diff --git a/sim/testsuite/sim/arm/thumb/eor.cgs b/sim/testsuite/sim/arm/thumb/eor.cgs new file mode 100644 index 00000000000..cc6021c5309 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/eor.cgs @@ -0,0 +1,12 @@ +# arm testcase for eor $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_eor +alu_eor: + eor r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/lda-pc.cgs b/sim/testsuite/sim/arm/thumb/lda-pc.cgs new file mode 100644 index 00000000000..74407e20b5a --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lda-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},pc,$word8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lda_pc +lda_pc: + add r0,pc,0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/lda-sp.cgs b/sim/testsuite/sim/arm/thumb/lda-sp.cgs new file mode 100644 index 00000000000..ce2b62ef4fc --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lda-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add ${bit10-rd},sp,$word8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lda_sp +lda_sp: + add r0,sp,0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldmia.cgs b/sim/testsuite/sim/arm/thumb/ldmia.cgs new file mode 100644 index 00000000000..550031ef648 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldmia.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldmia $rb!,{$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldmia +ldmia: + ldmia r0!,{0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs b/sim/testsuite/sim/arm/thumb/ldr-imm.cgs new file mode 100644 index 00000000000..a757f33957e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr $rd,[$rb,#${offset5-7}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_imm +ldr_imm: + ldr r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs b/sim/testsuite/sim/arm/thumb/ldr-pc.cgs new file mode 100644 index 00000000000..8227562bbbe --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr ${bit10-rd},[pc,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_pc +ldr_pc: + ldr r0,[pc,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs b/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs new file mode 100644 index 00000000000..11eee26401d --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr ${bit10-rd},[sp,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr_sprel +ldr_sprel: + ldr r0,[sp,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldr.cgs b/sim/testsuite/sim/arm/thumb/ldr.cgs new file mode 100644 index 00000000000..03af925a656 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldr.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldr $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldr +ldr: + ldr r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs new file mode 100644 index 00000000000..c1eeafe414b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrb $rd,[$rb,#$offset5] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb_imm +ldrb_imm: + ldrb r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrb.cgs b/sim/testsuite/sim/arm/thumb/ldrb.cgs new file mode 100644 index 00000000000..316a10f2a00 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrb.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrb +ldrb: + ldrb r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs new file mode 100644 index 00000000000..81ea1e037ff --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrh $rd,[$rb,#${offset5-6}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh_imm +ldrh_imm: + ldrh r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldrh.cgs b/sim/testsuite/sim/arm/thumb/ldrh.cgs new file mode 100644 index 00000000000..3ff8f4e4ce8 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldrh.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldrh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldrh +ldrh: + ldrh r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldsb.cgs b/sim/testsuite/sim/arm/thumb/ldsb.cgs new file mode 100644 index 00000000000..e1612c93a4e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldsb.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldsb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldsb +ldsb: + ldsb r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/ldsh.cgs b/sim/testsuite/sim/arm/thumb/ldsh.cgs new file mode 100644 index 00000000000..46d49ac2920 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ldsh.cgs @@ -0,0 +1,12 @@ +# arm testcase for ldsh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global ldsh +ldsh: + ldsh r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/lsl.cgs b/sim/testsuite/sim/arm/thumb/lsl.cgs new file mode 100644 index 00000000000..05222e72c5a --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lsl.cgs @@ -0,0 +1,14 @@ +# arm testcase for lsl $rd,$rs,#$offset5 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lsl +lsl: + lsl r0,r0,#0 + +# FIXME: Also lsl $rd,$rs + + pass diff --git a/sim/testsuite/sim/arm/thumb/lsr.cgs b/sim/testsuite/sim/arm/thumb/lsr.cgs new file mode 100644 index 00000000000..fe38fe0a31a --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/lsr.cgs @@ -0,0 +1,14 @@ +# arm testcase for lsr $rd,$rs,#$offset5 +# mach: unfinished + + .include "testutils.inc" + + start + + .global lsr +lsr: + lsr r0,r0,#0 + +# FIXME: Also lsr $rd,$rs + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs new file mode 100644 index 00000000000..2050908dca5 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $hd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_hd_hs +mov_hd_hs: + mov r8,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs new file mode 100644 index 00000000000..3d229c32f71 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $hd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_hd_rs +mov_hd_rs: + mov r8,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs new file mode 100644 index 00000000000..0661dfab5a3 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov $rd,$hs +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov_rd_hs +mov_rd_hs: + mov r0,r8 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mov.cgs b/sim/testsuite/sim/arm/thumb/mov.cgs new file mode 100644 index 00000000000..b497b0f5c62 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mov.cgs @@ -0,0 +1,12 @@ +# arm testcase for mov ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global mov +mov: + mov r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mul.cgs b/sim/testsuite/sim/arm/thumb/mul.cgs new file mode 100644 index 00000000000..d160c569fae --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mul.cgs @@ -0,0 +1,12 @@ +# arm testcase for mul $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_mul +alu_mul: + mul r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/mvn.cgs b/sim/testsuite/sim/arm/thumb/mvn.cgs new file mode 100644 index 00000000000..606ce859325 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/mvn.cgs @@ -0,0 +1,12 @@ +# arm testcase for mvn $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_mvn +alu_mvn: + mvn r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/neg.cgs b/sim/testsuite/sim/arm/thumb/neg.cgs new file mode 100644 index 00000000000..09f0c81f0ce --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/neg.cgs @@ -0,0 +1,12 @@ +# arm testcase for neg $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_neg +alu_neg: + neg r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/orr.cgs b/sim/testsuite/sim/arm/thumb/orr.cgs new file mode 100644 index 00000000000..de6f6880c65 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/orr.cgs @@ -0,0 +1,12 @@ +# arm testcase for orr $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_orr +alu_orr: + orr r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/pop-pc.cgs b/sim/testsuite/sim/arm/thumb/pop-pc.cgs new file mode 100644 index 00000000000..4579cad6bc2 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/pop-pc.cgs @@ -0,0 +1,12 @@ +# arm testcase for pop {${rlist-pc}} +# mach: unfinished + + .include "testutils.inc" + + start + + .global pop_pc +pop_pc: + pop {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/pop.cgs b/sim/testsuite/sim/arm/thumb/pop.cgs new file mode 100644 index 00000000000..b156e1dd8af --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/pop.cgs @@ -0,0 +1,12 @@ +# arm testcase for pop {$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global pop +pop: + pop {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/push-lr.cgs b/sim/testsuite/sim/arm/thumb/push-lr.cgs new file mode 100644 index 00000000000..ee700a4e305 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/push-lr.cgs @@ -0,0 +1,12 @@ +# arm testcase for push {${rlist-lr}} +# mach: unfinished + + .include "testutils.inc" + + start + + .global push_lr +push_lr: + push {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/push.cgs b/sim/testsuite/sim/arm/thumb/push.cgs new file mode 100644 index 00000000000..ff94ca5ab4b --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/push.cgs @@ -0,0 +1,12 @@ +# arm testcase for push {$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global push +push: + push {0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/ror.cgs b/sim/testsuite/sim/arm/thumb/ror.cgs new file mode 100644 index 00000000000..991fa66fdc1 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/ror.cgs @@ -0,0 +1,12 @@ +# arm testcase for ror $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_ror +alu_ror: + ror r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/sbc.cgs b/sim/testsuite/sim/arm/thumb/sbc.cgs new file mode 100644 index 00000000000..078b06118cb --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/sbc.cgs @@ -0,0 +1,12 @@ +# arm testcase for sbc $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_sbc +alu_sbc: + sbc r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/stmia.cgs b/sim/testsuite/sim/arm/thumb/stmia.cgs new file mode 100644 index 00000000000..0e1c30cef23 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/stmia.cgs @@ -0,0 +1,12 @@ +# arm testcase for stmia $rb!,{$rlist} +# mach: unfinished + + .include "testutils.inc" + + start + + .global stmia +stmia: + stmia r0!,{0} + + pass diff --git a/sim/testsuite/sim/arm/thumb/str-imm.cgs b/sim/testsuite/sim/arm/thumb/str-imm.cgs new file mode 100644 index 00000000000..ce759413ca7 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/str-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for str $rd,[$rb,#${offset5-7}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_imm +str_imm: + str r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/str-sprel.cgs b/sim/testsuite/sim/arm/thumb/str-sprel.cgs new file mode 100644 index 00000000000..132edfb6f4f --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/str-sprel.cgs @@ -0,0 +1,12 @@ +# arm testcase for str ${bit10-rd},[sp,#$word8] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str_sprel +str_sprel: + str r0,[sp,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/str.cgs b/sim/testsuite/sim/arm/thumb/str.cgs new file mode 100644 index 00000000000..073e20b4eb7 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/str.cgs @@ -0,0 +1,12 @@ +# arm testcase for str $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global str +str: + str r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strb-imm.cgs b/sim/testsuite/sim/arm/thumb/strb-imm.cgs new file mode 100644 index 00000000000..2b5bcf7ff7e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strb-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for strb $rd,[$rb,#$offset5] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb_imm +strb_imm: + strb r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strb.cgs b/sim/testsuite/sim/arm/thumb/strb.cgs new file mode 100644 index 00000000000..b7cb7638696 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strb.cgs @@ -0,0 +1,12 @@ +# arm testcase for strb $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strb +strb: + strb r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strh-imm.cgs b/sim/testsuite/sim/arm/thumb/strh-imm.cgs new file mode 100644 index 00000000000..95002882448 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strh-imm.cgs @@ -0,0 +1,12 @@ +# arm testcase for strh $rd,[$rb,#${offset5-6}] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh_imm +strh_imm: + strh r0,[r0,#0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/strh.cgs b/sim/testsuite/sim/arm/thumb/strh.cgs new file mode 100644 index 00000000000..13f3a0d6875 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/strh.cgs @@ -0,0 +1,12 @@ +# arm testcase for strh $rd,[$rb,$ro] +# mach: unfinished + + .include "testutils.inc" + + start + + .global strh +strh: + strh r0,[r0,r0] + + pass diff --git a/sim/testsuite/sim/arm/thumb/sub-sp.cgs b/sim/testsuite/sim/arm/thumb/sub-sp.cgs new file mode 100644 index 00000000000..e676f58fb30 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/sub-sp.cgs @@ -0,0 +1,12 @@ +# arm testcase for add sp,#-$sword7 +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub_sp +sub_sp: + add sp,#-0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/sub.cgs b/sim/testsuite/sim/arm/thumb/sub.cgs new file mode 100644 index 00000000000..91cd7abb39c --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/sub.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub $rd,$rs,$rn +# mach: unfinished + + .include "testutils.inc" + + start + + .global sub +sub: + sub r0,r0,r0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/subi.cgs b/sim/testsuite/sim/arm/thumb/subi.cgs new file mode 100644 index 00000000000..044efd0d048 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/subi.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub $rd,$rs,#$offset3 +# mach: unfinished + + .include "testutils.inc" + + start + + .global subi +subi: + sub r0,r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/subi8.cgs b/sim/testsuite/sim/arm/thumb/subi8.cgs new file mode 100644 index 00000000000..0c4d717ef08 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/subi8.cgs @@ -0,0 +1,12 @@ +# arm testcase for sub ${bit10-rd},#$offset8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global subi8 +subi8: + sub r0,#0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/swi.cgs b/sim/testsuite/sim/arm/thumb/swi.cgs new file mode 100644 index 00000000000..1724c14c9d5 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/swi.cgs @@ -0,0 +1,12 @@ +# arm testcase for swi $value8 +# mach: unfinished + + .include "testutils.inc" + + start + + .global swi +swi: + swi 0 + + pass diff --git a/sim/testsuite/sim/arm/thumb/testutils.inc b/sim/testsuite/sim/arm/thumb/testutils.inc new file mode 100644 index 00000000000..bdae29bef19 --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/testutils.inc @@ -0,0 +1,91 @@ +# FIXME: wip, copied from ../testutils.inc +# r0-r3 are used as tmps, consider them call clobbered by these macros. +# This uses the angel rom monitor calls. +# ??? How do we use the \@ facility of .macros ??? +# @ is the comment char! + + .macro a_mvi_h_gr reg, val + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro mvaddr_h_gr reg, addr + ldr \reg,[pc] + b . + 8 + .word \val + .endm + + .macro start + .data +failmsg: + .asciz "fail\n" +passmsg: + .asciz "pass\n" + .text + +do_pass: + ldr r1, passmsg_addr + mov r0, #4 + swi #0x123456 + exit 0 +passmsg_addr: + .word passmsg + +do_fail: + ldr r1, failmsg_addr + mov r0, #4 + swi #0x123456 + exit 1 +failmsg_addr: + .word failmsg + + .global _start +_start: + .endm + +# *** Other macros know pass/fail are 4 bytes in size! Yuck. + + .macro pass + b do_pass + .endm + + .macro fail + b do_fail + .endm + + .macro exit rc + mov r1, #\rc + mov r0, #0x2a @ decimal 42 + swi #1 + # If that returns, punt with a sigill. + stc 0,cr0,[r0] + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + cmp \reg, r0 + beq . + 8 + fail + .endm + + .macro mvi_h_cc c, n, v, z + ldi8 r0, 0 + ldi8 r1, 1 + .if xxx + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_cc c, n, v, z + .if xxx + bc . + 8 + fail + .else + bnc . + 8 + fail + .endif + .endm diff --git a/sim/testsuite/sim/arm/thumb/tst.cgs b/sim/testsuite/sim/arm/thumb/tst.cgs new file mode 100644 index 00000000000..068fccc427e --- /dev/null +++ b/sim/testsuite/sim/arm/thumb/tst.cgs @@ -0,0 +1,12 @@ +# arm testcase for tst $rd,$rs +# mach: unfinished + + .include "testutils.inc" + + start + + .global alu_tst +alu_tst: + tst r0,r0 + + pass |