summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/cris/asm/tjsrcv32.ms
diff options
context:
space:
mode:
Diffstat (limited to 'sim/testsuite/sim/cris/asm/tjsrcv32.ms')
-rw-r--r--sim/testsuite/sim/cris/asm/tjsrcv32.ms13
1 files changed, 13 insertions, 0 deletions
diff --git a/sim/testsuite/sim/cris/asm/tjsrcv32.ms b/sim/testsuite/sim/cris/asm/tjsrcv32.ms
new file mode 100644
index 00000000000..a777f01bda6
--- /dev/null
+++ b/sim/testsuite/sim/cris/asm/tjsrcv32.ms
@@ -0,0 +1,13 @@
+#mach: crisv32
+#output: Basic clock cycles, total @: 6\n
+#output: Memory source stall cycles: 0\n
+#output: Memory read-after-write stall cycles: 0\n
+#output: Movem source stall cycles: 0\n
+#output: Movem destination stall cycles: 0\n
+#output: Movem address stall cycles: 0\n
+#output: Multiplication source stall cycles: 0\n
+#output: Jump source stall cycles: 2\n
+#output: Branch misprediction stall cycles: 0\n
+#output: Jump target stall cycles: 0\n
+#sim: --cris-cycles=basic
+ .include "tjsrcv10.ms"