1 files changed, 0 insertions, 113 deletions
diff --git a/sim/testsuite/sim/fr30/div1.cgs b/sim/testsuite/sim/fr30/div1.cgs
deleted file mode 100644
index dac35fe15c4..00000000000
--- a/sim/testsuite/sim/fr30/div1.cgs
+++ /dev/null
@@ -1,113 +0,0 @@
-# fr30 testcase for div1 $Ri
-# mach(): fr30
-
-	.include "testutils.inc"
-
-	START
-
-	.text
-	.global div1
-div1:
-	; Test div1 $Ri
-	; example from the manual -- all status bits 0
-	mvi_h_gr   	0x00ffffff,r2
-	mvi_h_dr   	0x00ffffff,mdh
-	mvi_h_dr   	0x00000000,mdl
-	set_dbits	0x0
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 0
-	test_dbits	0x0
-	test_h_gr  	0x00ffffff,r2
-	test_h_dr  	0x00ffffff,mdh	; misprinted in manual?
-	test_h_dr  	0x00000001,mdl
-
-	; D0 == 1
-	set_dbits	0x1
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 0
-	test_dbits	0x1
-	test_h_gr  	0x00ffffff,r2
-	test_h_dr  	0x01fffffe,mdh
-	test_h_dr  	0x00000002,mdl
-
-	; D1 == 1
-	set_dbits	0x2
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 0
-	test_dbits	0x2
-	test_h_gr  	0x00ffffff,r2
-	test_h_dr  	0x03fffffc,mdh
-	test_h_dr  	0x00000004,mdl
-
-	; D0 == 1, D1 == 1
-	set_dbits	0x3
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 0
-	test_dbits	0x3
-	test_h_gr  	0x00ffffff,r2
-	test_h_dr  	0x08fffff7,mdh
-	test_h_dr  	0x00000009,mdl
-
-	; C == 1
-	mvi_h_gr  	0x11ffffef,r2
-	set_dbits	0x0
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 1
-	test_dbits	0x0
-	test_h_gr  	0x11ffffef,r2
-	test_h_dr  	0x11ffffee,mdh
-	test_h_dr  	0x00000012,mdl
-
-	; D0 == 1, C == 1
-	mvi_h_gr  	0x23ffffdd,r2
-	set_dbits	0x1
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 1
-	test_dbits	0x1
-	test_h_gr  	0x23ffffdd,r2
-	test_h_dr  	0xffffffff,mdh
-	test_h_dr  	0x00000025,mdl
-
-	; D1 == 1, C == 1
-	mvi_h_gr  	0x00000003,r2
-	set_dbits	0x2
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 1
-	test_dbits	0x2
-	test_h_gr  	0x00000003,r2
-	test_h_dr  	0x00000001,mdh
-	test_h_dr  	0x0000004b,mdl
-
-	; D0 == 1, D1 == 1, C == 1
-	mvi_h_gr  	0xfffffffe,r2
-	set_dbits	0x3
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 0 0 1
-	test_dbits	0x3
-	test_h_gr  	0xfffffffe,r2
-	test_h_dr  	0x00000002,mdh
-	test_h_dr  	0x00000096,mdl
-
-	; remainder is zero
-	mvi_h_gr  	0x00000004,r2
-	set_dbits	0x0
-	set_cc          0x00
-	div1      	r2
-	test_cc		0 1 0 0
-	test_dbits	0x0
-	test_h_gr  	0x00000004,r2
-	test_h_dr  	0x00000000,mdh
-	test_h_dr  	0x0000012d,mdl
-
-	pass
-
-
-