diff options
Diffstat (limited to 'sim/testsuite/sim/frv/caddcc.cgs')
| -rw-r--r-- | sim/testsuite/sim/frv/caddcc.cgs | 163 |
1 files changed, 0 insertions, 163 deletions
diff --git a/sim/testsuite/sim/frv/caddcc.cgs b/sim/testsuite/sim/frv/caddcc.cgs deleted file mode 100644 index ddfd41e359b..00000000000 --- a/sim/testsuite/sim/frv/caddcc.cgs +++ /dev/null @@ -1,163 +0,0 @@ -# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global caddcc -caddcc: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_immed 1,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_immed 1,gr8 - - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_immed 1,gr8 - - set_icc 0x08,2 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc6,1 - test_icc 1 0 0 0 icc2 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_immed 1,gr8 - - set_icc 0x08,3 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc7,1 - test_icc 1 0 0 0 icc3 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - - pass |