diff options
Diffstat (limited to 'sim/testsuite/sim/frv/fr550/msubhus.cgs')
-rw-r--r-- | sim/testsuite/sim/frv/fr550/msubhus.cgs | 77 |
1 files changed, 0 insertions, 77 deletions
diff --git a/sim/testsuite/sim/frv/fr550/msubhus.cgs b/sim/testsuite/sim/frv/fr550/msubhus.cgs deleted file mode 100644 index 5a3cd26f773..00000000000 --- a/sim/testsuite/sim/frv/fr550/msubhus.cgs +++ /dev/null @@ -1,77 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - msubhus.p fr10,fr10,fr12 - msubhus fr10,fr11,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass |