diff options
Diffstat (limited to 'sim/testsuite/sim/frv/maddhss.cgs')
| -rw-r--r-- | sim/testsuite/sim/frv/maddhss.cgs | 100 |
1 files changed, 0 insertions, 100 deletions
diff --git a/sim/testsuite/sim/frv/maddhss.cgs b/sim/testsuite/sim/frv/maddhss.cgs deleted file mode 100644 index 289ecc77d8a..00000000000 --- a/sim/testsuite/sim/frv/maddhss.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for maddhss $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global maddhss -maddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maddhss.p fr10,fr10,fr12 - maddhss fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass |