summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/frv/sraicc.cgs
diff options
context:
space:
mode:
Diffstat (limited to 'sim/testsuite/sim/frv/sraicc.cgs')
-rw-r--r--sim/testsuite/sim/frv/sraicc.cgs34
1 files changed, 34 insertions, 0 deletions
diff --git a/sim/testsuite/sim/frv/sraicc.cgs b/sim/testsuite/sim/frv/sraicc.cgs
new file mode 100644
index 00000000000..5dbd1e600c6
--- /dev/null
+++ b/sim/testsuite/sim/frv/sraicc.cgs
@@ -0,0 +1,34 @@
+# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1
+# mach: all
+
+ .include "testutils.inc"
+
+ start
+
+ .global sraicc
+sraicc:
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x05,0 ; Set mask opposite of expected
+ sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0
+ test_icc 1 0 0 0 icc0
+ test_gr_limmed 0x8000,0x0000,gr8
+
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x07,0 ; Set mask opposite of expected
+ sraicc gr8,-31,gr8,icc0 ; Shift by 1
+ test_icc 1 0 1 0 icc0
+ test_gr_limmed 0xc000,0x0000,gr8
+
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x07,0 ; Set mask opposite of expected
+ sraicc gr8,31,gr8,icc0 ; Shift by 31
+ test_icc 1 0 1 0 icc0
+ test_gr_immed -1,gr8
+
+ set_gr_limmed 0x4000,0x0000,gr8
+ set_icc 0x0a,0 ; Set mask opposite of expected
+ sraicc gr8,31,gr8,icc0 ; clear register
+ test_icc 0 1 1 1 icc0
+ test_gr_immed 0x00000000,gr8
+
+ pass