diff options
Diffstat (limited to 'sim/testsuite/sim/frv/udivi.cgs')
| -rw-r--r-- | sim/testsuite/sim/frv/udivi.cgs | 49 |
1 files changed, 0 insertions, 49 deletions
diff --git a/sim/testsuite/sim/frv/udivi.cgs b/sim/testsuite/sim/frv/udivi.cgs deleted file mode 100644 index 6a505900d07..00000000000 --- a/sim/testsuite/sim/frv/udivi.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for udivi $GRi,$s12,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global udivi -udivi: - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - udivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - udivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - udivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udivi gr1,0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail |