diff options
Diffstat (limited to 'sim/testsuite/sim/m32r')
108 files changed, 2343 insertions, 0 deletions
diff --git a/sim/testsuite/sim/m32r/add.cgs b/sim/testsuite/sim/m32r/add.cgs new file mode 100644 index 00000000000..8ed2b3a2ad3 --- /dev/null +++ b/sim/testsuite/sim/m32r/add.cgs @@ -0,0 +1,16 @@ +# m32r testcase for add $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add +add: + + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + add r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/add3.cgs b/sim/testsuite/sim/m32r/add3.cgs new file mode 100644 index 00000000000..d1cc8480ad4 --- /dev/null +++ b/sim/testsuite/sim/m32r/add3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for add3 $dr,$sr,#$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add3 +add3: + + mvi_h_gr r5, 1 + add3 r4, r5, 2 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/addi.cgs b/sim/testsuite/sim/m32r/addi.cgs new file mode 100644 index 00000000000..1448d0d2e2b --- /dev/null +++ b/sim/testsuite/sim/m32r/addi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for addi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addi +addi: + + mvi_h_gr r5, 1 + addi r5, 2 + test_h_gr r5, 3 + + pass + diff --git a/sim/testsuite/sim/m32r/addv.cgs b/sim/testsuite/sim/m32r/addv.cgs new file mode 100644 index 00000000000..704be83c914 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv.cgs @@ -0,0 +1,21 @@ +# m32r testcase for addv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv +addv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 0x80000000 + + addv r4, r5 + + bnc not_ok + test_h_gr r4, 0 + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/addv3.cgs b/sim/testsuite/sim/m32r/addv3.cgs new file mode 100644 index 00000000000..a8c0a108561 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv3.cgs @@ -0,0 +1,28 @@ +# m32r testcase for addv3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv3 +addv3: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 1 + + addv3 r4, r5, #2 + + bc not_ok + + test_h_gr r4, 3 + + mvi_h_gr r5, 0x7fff8001 + + addv3 r4, r5, #0x7fff + + bnc not_ok + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/addx.cgs b/sim/testsuite/sim/m32r/addx.cgs new file mode 100644 index 00000000000..630e3dbe15a --- /dev/null +++ b/sim/testsuite/sim/m32r/addx.cgs @@ -0,0 +1,42 @@ +# m32r testcase for addx $dr,$sr +# mach(): m32r m32rx +# timeout(): 42 + +# timeout is set to test it + + .include "testutils.inc" + + start + + .global addx +addx: + mvi_h_condbit 1 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + addx r4, r5 + bc not_ok + test_h_gr r4, 4 + + mvi_h_gr r4, 0xfffffffe + addx r4, r5 + bnc not_ok + test_h_gr r4, 0 + + mvi_h_gr r4, -1 + mvi_h_gr r5, -1 + mvi_h_condbit 1 + addx r4,r5 + bnc not_ok + test_h_gr r4, -1 + + mvi_h_gr r4,-1 + mvi_h_gr r5,0x7fffffff + mvi_h_condbit 1 + addx r5,r4 + bnc not_ok + test_h_gr r5,0x7fffffff + + pass + +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/allinsn.exp b/sim/testsuite/sim/m32r/allinsn.exp new file mode 100644 index 00000000000..8eed80f91d6 --- /dev/null +++ b/sim/testsuite/sim/m32r/allinsn.exp @@ -0,0 +1,21 @@ +# M32R simulator testsuite. + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/m32r/and.cgs b/sim/testsuite/sim/m32r/and.cgs new file mode 100644 index 00000000000..1c268855411 --- /dev/null +++ b/sim/testsuite/sim/m32r/and.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and +and: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + and r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/and3.cgs b/sim/testsuite/sim/m32r/and3.cgs new file mode 100644 index 00000000000..395de3028e9 --- /dev/null +++ b/sim/testsuite/sim/m32r/and3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and3 +and3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + and3 r4, r5, #3 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/bc24.cgs b/sim/testsuite/sim/m32r/bc24.cgs new file mode 100644 index 00000000000..6bb43334e8f --- /dev/null +++ b/sim/testsuite/sim/m32r/bc24.cgs @@ -0,0 +1,24 @@ +# m32r testcase for bc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bc.l test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.l test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/sim/m32r/bc8.cgs b/sim/testsuite/sim/m32r/bc8.cgs new file mode 100644 index 00000000000..ceb622c1661 --- /dev/null +++ b/sim/testsuite/sim/m32r/bc8.cgs @@ -0,0 +1,23 @@ +# m32r testcase for bc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc8 +bc8: + + mvi_h_condbit 0 + bc.s test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.s test1pass + fail +test1pass: + + pass diff --git a/sim/testsuite/sim/m32r/beq.cgs b/sim/testsuite/sim/m32r/beq.cgs new file mode 100644 index 00000000000..c4d6d8bf0aa --- /dev/null +++ b/sim/testsuite/sim/m32r/beq.cgs @@ -0,0 +1,20 @@ +# m32r testcase for beq $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + mvi_h_gr r4, 12 + mvi_h_gr r5, 12 + beq r4, r5, ok +not_ok: + fail +ok: + mvi_h_gr r5, 11 + beq r4, r5, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/beqz.cgs b/sim/testsuite/sim/m32r/beqz.cgs new file mode 100644 index 00000000000..654737d3d46 --- /dev/null +++ b/sim/testsuite/sim/m32r/beqz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for beqz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beqz +beqz: + mvi_h_gr r4, 0 + beqz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 1 + beqz r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bgez.cgs b/sim/testsuite/sim/m32r/bgez.cgs new file mode 100644 index 00000000000..f7031f0edcb --- /dev/null +++ b/sim/testsuite/sim/m32r/bgez.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgez +bgez: + mvi_h_gr r4, 1 + bgez r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, -1 + bgez r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bgtz.cgs b/sim/testsuite/sim/m32r/bgtz.cgs new file mode 100644 index 00000000000..6ab8989c7e0 --- /dev/null +++ b/sim/testsuite/sim/m32r/bgtz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgtz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgtz +bgtz: + mvi_h_gr r4, 1 + bgtz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 0 + bgtz r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bl24.cgs b/sim/testsuite/sim/m32r/bl24.cgs new file mode 100644 index 00000000000..fd6f0dd69d5 --- /dev/null +++ b/sim/testsuite/sim/m32r/bl24.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl24 +bl24: + bl.l test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bl8.cgs b/sim/testsuite/sim/m32r/bl8.cgs new file mode 100644 index 00000000000..d26369853b7 --- /dev/null +++ b/sim/testsuite/sim/m32r/bl8.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl8 +bl8: + bl.s test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/blez.cgs b/sim/testsuite/sim/m32r/blez.cgs new file mode 100644 index 00000000000..e3d198d93ad --- /dev/null +++ b/sim/testsuite/sim/m32r/blez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for blez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global blez +blez: + mvi_h_gr r4, 0 + blez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 1 + blez r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bltz.cgs b/sim/testsuite/sim/m32r/bltz.cgs new file mode 100644 index 00000000000..c9377fcaab1 --- /dev/null +++ b/sim/testsuite/sim/m32r/bltz.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bltz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bltz +bltz: + mvi_h_gr r4, -1 + bltz r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bltz r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnc24.cgs b/sim/testsuite/sim/m32r/bnc24.cgs new file mode 100644 index 00000000000..692d2d58436 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc24.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc24 +bnc24: + mvi_h_condbit 0 + bnc.l test0pass + +test1fail: + fail +test0pass: + + mvi_h_condbit 1 + bnc.l test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnc8.cgs b/sim/testsuite/sim/m32r/bnc8.cgs new file mode 100644 index 00000000000..dae2613cc9f --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc8.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc8 +bnc8: + mvi_h_condbit 0 + bnc.s test0pass + +test1fail: + fail + +test0pass: + mvi_h_condbit 1 + bnc.s test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bne.cgs b/sim/testsuite/sim/m32r/bne.cgs new file mode 100644 index 00000000000..5e1d7a6ecc5 --- /dev/null +++ b/sim/testsuite/sim/m32r/bne.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bne $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bne +bne: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + bne r4, r5, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 2 + bne r4, r5, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnez.cgs b/sim/testsuite/sim/m32r/bnez.cgs new file mode 100644 index 00000000000..9f102895029 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bnez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnez +bnez: + mvi_h_gr r4, 1 + bnez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bnez r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bra24.cgs b/sim/testsuite/sim/m32r/bra24.cgs new file mode 100644 index 00000000000..d62d2bf0ec3 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra24.cgs @@ -0,0 +1,15 @@ +# m32r testcase for bra $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra24 +bra24: + bra.l ok + + fail + +ok: + pass diff --git a/sim/testsuite/sim/m32r/bra8.cgs b/sim/testsuite/sim/m32r/bra8.cgs new file mode 100644 index 00000000000..f5f50ad2d93 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for bra $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra8 +bra8: + bra.s ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/cmp.cgs b/sim/testsuite/sim/m32r/cmp.cgs new file mode 100644 index 00000000000..6ea67206218 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmp.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmp $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmp +cmp: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + cmp r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmp r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/cmpi.cgs b/sim/testsuite/sim/m32r/cmpi.cgs new file mode 100644 index 00000000000..af11283d68d --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpi.cgs @@ -0,0 +1,24 @@ +# m32r testcase for cmpi $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + cmpi r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmpi r4, #2 + bc not_ok + + + pass diff --git a/sim/testsuite/sim/m32r/cmpu.cgs b/sim/testsuite/sim/m32r/cmpu.cgs new file mode 100644 index 00000000000..e0b4ef10180 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmpu $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpu +cmpu: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, -2 + cmpu r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpu r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/cmpui.cgs b/sim/testsuite/sim/m32r/cmpui.cgs new file mode 100644 index 00000000000..aa30207d933 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpui.cgs @@ -0,0 +1,22 @@ +# m32r testcase for cmpui $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpui +cmpui: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + cmpui r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpui r4, #2 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/div.cgs b/sim/testsuite/sim/m32r/div.cgs new file mode 100644 index 00000000000..733f3629680 --- /dev/null +++ b/sim/testsuite/sim/m32r/div.cgs @@ -0,0 +1,17 @@ +# m32r testcase for div $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global div +div: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + div r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/sim/m32r/divu.cgs b/sim/testsuite/sim/m32r/divu.cgs new file mode 100644 index 00000000000..25342d5dccc --- /dev/null +++ b/sim/testsuite/sim/m32r/divu.cgs @@ -0,0 +1,17 @@ +# m32r testcase for divu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global divu +divu: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + divu r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/sim/m32r/hello.ms b/sim/testsuite/sim/m32r/hello.ms new file mode 100644 index 00000000000..7ae22778001 --- /dev/null +++ b/sim/testsuite/sim/m32r/hello.ms @@ -0,0 +1,19 @@ +# output(): Hello world!\n +# mach(): m32r m32rx + + .globl _start +_start: + +; write (hello world) + ldi8 r3,#14 + ld24 r2,#hello + ldi8 r1,#1 + ldi8 r0,#5 + trap #0 +; exit (0) + ldi8 r1,#0 + ldi8 r0,#1 + trap #0 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/m32r/hw-trap.ms b/sim/testsuite/sim/m32r/hw-trap.ms new file mode 100644 index 00000000000..2aa200b5d70 --- /dev/null +++ b/sim/testsuite/sim/m32r/hw-trap.ms @@ -0,0 +1,31 @@ +# mach(): m32r m32rx +# output(): pass\n + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#bra_insn + ld r0,@r0 + ld24 r1,#trap2_handler + addi r1,#-0x48 ; pc relative address from trap 2 slot to handler + srai r1,#2 + or r0,r1 + ld24 r2,#0x48 ; address of trap 2 slot + st r0,@r2 + +; perform trap + ldi r4,#0 + trap #2 + test_h_gr r4,42 + + pass + +; trap 2 handler +trap2_handler: + ldi r4,#42 + rte + +bra_insn: + bra.l 0 diff --git a/sim/testsuite/sim/m32r/jl.cgs b/sim/testsuite/sim/m32r/jl.cgs new file mode 100644 index 00000000000..a89c26a86bf --- /dev/null +++ b/sim/testsuite/sim/m32r/jl.cgs @@ -0,0 +1,18 @@ +# m32r testcase for jl $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jl +jl: + mvaddr_h_gr r4, ok + jl r4 +not_ok: + fail +ok: + mvaddr_h_gr r4, not_ok + bne r4, r14, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/jmp.cgs b/sim/testsuite/sim/m32r/jmp.cgs new file mode 100644 index 00000000000..ba0864a53f0 --- /dev/null +++ b/sim/testsuite/sim/m32r/jmp.cgs @@ -0,0 +1,19 @@ +# m32r testcase for jmp $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jmp +jmp: + mvaddr_h_gr r4, ok1 + jmp r4 + fail +ok1: + mvaddr_h_gr r4, ok2 + addi r4,#1 + jmp r4 + fail +ok2: + pass diff --git a/sim/testsuite/sim/m32r/ld-d.cgs b/sim/testsuite/sim/m32r/ld-d.cgs new file mode 100644 index 00000000000..151743672b2 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-d.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ld $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_d +ld_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @(#4, r4) + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x11223344 + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ld-plus.cgs b/sim/testsuite/sim/m32r/ld-plus.cgs new file mode 100644 index 00000000000..5feaf62596e --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for ld $dr,@$sr+ +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_plus +ld_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4+ + + test_h_gr r5, 0x12345678 + + mvaddr_h_gr r5, data_loc2 + bne r4, r5, not_ok + + pass +not_ok: + fail + +data_loc: + .word 0x12345678 +data_loc2: + .word 0x11223344 + diff --git a/sim/testsuite/sim/m32r/ld.cgs b/sim/testsuite/sim/m32r/ld.cgs new file mode 100644 index 00000000000..ad0b86ff6d5 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ld $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld +ld: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4 + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ld24.cgs b/sim/testsuite/sim/m32r/ld24.cgs new file mode 100644 index 00000000000..74b155518c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld24.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ld24 $dr,#$uimm24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld24 +ld24: + ld24 r4, #0x123456 + + test_h_gr r4, 0x123456 + + pass diff --git a/sim/testsuite/sim/m32r/ldb-d.cgs b/sim/testsuite/sim/m32r/ldb-d.cgs new file mode 100644 index 00000000000..4a1cebb1fc3 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for ldb $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb_d +ldb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @(#2, r4) + + test_h_gr r5, 0x56 ; big endian processor + + pass + +data_loc: + .word 0x12345678 diff --git a/sim/testsuite/sim/m32r/ldb.cgs b/sim/testsuite/sim/m32r/ldb.cgs new file mode 100644 index 00000000000..9b895450f08 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldb $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb +ldb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @r4 + + test_h_gr r5, 0x12 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ldh-d.cgs b/sim/testsuite/sim/m32r/ldh-d.cgs new file mode 100644 index 00000000000..0be0309b1ef --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh_d +ldh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @(#2, r4) + + test_h_gr r5, 0x5678 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ldh.cgs b/sim/testsuite/sim/m32r/ldh.cgs new file mode 100644 index 00000000000..3d8db953d3d --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ldh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh +ldh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @r4 + + test_h_gr r5, 0x1234 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + + pass diff --git a/sim/testsuite/sim/m32r/ldi16.cgs b/sim/testsuite/sim/m32r/ldi16.cgs new file mode 100644 index 00000000000..478df1c1b32 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi16.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi16 +ldi16: + ldi r4, #0x1234 + + test_h_gr r4, 0x1234 + + pass diff --git a/sim/testsuite/sim/m32r/ldi8.cgs b/sim/testsuite/sim/m32r/ldi8.cgs new file mode 100644 index 00000000000..081e7a86f35 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi8 +ldi8: + ldi r4, #0x78 + + test_h_gr r4, 0x78 + + pass diff --git a/sim/testsuite/sim/m32r/ldub-d.cgs b/sim/testsuite/sim/m32r/ldub-d.cgs new file mode 100644 index 00000000000..7661071b820 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub_d +ldub_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @(#2, r4) + + test_h_gr r5, 0xa0 ; big endian processor + + pass + +data_loc: + .word 0x8090a0b0 + diff --git a/sim/testsuite/sim/m32r/ldub.cgs b/sim/testsuite/sim/m32r/ldub.cgs new file mode 100644 index 00000000000..27913b51f59 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub +ldub: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @r4 + + test_h_gr r5, 0x80 ; big endian processor + + pass + +data_loc: + .word 0x800000f0 + diff --git a/sim/testsuite/sim/m32r/lduh-d.cgs b/sim/testsuite/sim/m32r/lduh-d.cgs new file mode 100644 index 00000000000..96e294f0ec8 --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for lduh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh_d +lduh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @(#2, r4) + + test_h_gr r5, 0xf000 ; big endian processor + + pass + +data_loc: + .word 0x8000f000 diff --git a/sim/testsuite/sim/m32r/lduh.cgs b/sim/testsuite/sim/m32r/lduh.cgs new file mode 100644 index 00000000000..a03bbee240d --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for lduh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh +lduh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @r4 + + test_h_gr r5, 0x8010 ; big endian processor + + pass + +data_loc: + .word 0x8010f020 + + pass diff --git a/sim/testsuite/sim/m32r/lock.cgs b/sim/testsuite/sim/m32r/lock.cgs new file mode 100644 index 00000000000..631525ebbbf --- /dev/null +++ b/sim/testsuite/sim/m32r/lock.cgs @@ -0,0 +1,25 @@ +# m32r testcase for lock $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lock +lock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lock r5, @r4 + + test_h_gr r5, 0x12345678 + + ; There is no way to test the lock bit + + unlock r5, @r4 ; Unlock the processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/machi.cgs b/sim/testsuite/sim/m32r/machi.cgs new file mode 100644 index 00000000000..2e2ef00294c --- /dev/null +++ b/sim/testsuite/sim/m32r/machi.cgs @@ -0,0 +1,17 @@ +# m32r testcase for machi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global machi +machi: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + machi r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/maclo.cgs b/sim/testsuite/sim/m32r/maclo.cgs new file mode 100644 index 00000000000..5d035394dc4 --- /dev/null +++ b/sim/testsuite/sim/m32r/maclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for maclo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global maclo +maclo: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x1230001 + mvi_h_gr r5, 0x4560002 + maclo r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/macwhi.cgs b/sim/testsuite/sim/m32r/macwhi.cgs new file mode 100644 index 00000000000..9ee7a5b0bb9 --- /dev/null +++ b/sim/testsuite/sim/m32r/macwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwhi +macwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + macwhi r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/sim/m32r/macwlo.cgs b/sim/testsuite/sim/m32r/macwlo.cgs new file mode 100644 index 00000000000..a7ce4edac5c --- /dev/null +++ b/sim/testsuite/sim/m32r/macwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwlo +macwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + macwlo r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/sim/m32r/misc.exp b/sim/testsuite/sim/m32r/misc.exp new file mode 100644 index 00000000000..6ed5638ab29 --- /dev/null +++ b/sim/testsuite/sim/m32r/misc.exp @@ -0,0 +1,21 @@ +# Miscellaneous M32R simulator testcases + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/m32r/mul.cgs b/sim/testsuite/sim/m32r/mul.cgs new file mode 100644 index 00000000000..c78f24b8117 --- /dev/null +++ b/sim/testsuite/sim/m32r/mul.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mul $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mul +mul: + mvi_h_gr r4, 3 + mvi_h_gr r5, 7 + + mul r5, r4 + + test_h_gr r5, 21 + + pass diff --git a/sim/testsuite/sim/m32r/mulhi.cgs b/sim/testsuite/sim/m32r/mulhi.cgs new file mode 100644 index 00000000000..77c103d6f36 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulhi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mulhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulhi +mulhi: + + mvi_h_gr r4, 0x40000 + mvi_h_gr r5, 0x50000 + mulhi r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mullo.cgs b/sim/testsuite/sim/m32r/mullo.cgs new file mode 100644 index 00000000000..11aadff3794 --- /dev/null +++ b/sim/testsuite/sim/m32r/mullo.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mullo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mullo +mullo: + + mvi_h_gr r4, 4 + mvi_h_gr r5, 5 + mullo r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mulwhi.cgs b/sim/testsuite/sim/m32r/mulwhi.cgs new file mode 100644 index 00000000000..eb18562d9e7 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwhi +mulwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + mulwhi r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/sim/m32r/mulwlo.cgs b/sim/testsuite/sim/m32r/mulwlo.cgs new file mode 100644 index 00000000000..d22c26827cd --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwlo +mulwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + mulwlo r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/sim/m32r/mv.cgs b/sim/testsuite/sim/m32r/mv.cgs new file mode 100644 index 00000000000..694569535b7 --- /dev/null +++ b/sim/testsuite/sim/m32r/mv.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mv +mv: + mvi_h_gr r4, 1 + mvi_h_gr r5, 0 + + mv r5, r4 + + test_h_gr r5, 1 + + pass diff --git a/sim/testsuite/sim/m32r/mvfachi.cgs b/sim/testsuite/sim/m32r/mvfachi.cgs new file mode 100644 index 00000000000..0222e1b9118 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfachi.cgs @@ -0,0 +1,22 @@ +# m32r testcase for mvfachi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfachi +mvfachi: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0x223344 + + mvi_h_accum0 0x99aabbcc, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0xffaabbcc + + pass diff --git a/sim/testsuite/sim/m32r/mvfaclo.cgs b/sim/testsuite/sim/m32r/mvfaclo.cgs new file mode 100644 index 00000000000..0a88d849aee --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvfaclo $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfaclo +mvfaclo: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfaclo r4 + + test_h_gr r4, 0x55667788 + + pass diff --git a/sim/testsuite/sim/m32r/mvfacmi.cgs b/sim/testsuite/sim/m32r/mvfacmi.cgs new file mode 100644 index 00000000000..580bcae9890 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfacmi.cgs @@ -0,0 +1,15 @@ +# m32r testcase for mvfacmi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfacmi +mvfacmi: + + mvi_h_accum0 0x12345678, 0x87654321 + mvfacmi r4 + test_h_gr r4, 0x56788765 + + pass diff --git a/sim/testsuite/sim/m32r/mvfc.cgs b/sim/testsuite/sim/m32r/mvfc.cgs new file mode 100644 index 00000000000..ca2470e1e2d --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfc.cgs @@ -0,0 +1,23 @@ +# m32r testcase for mvfc $dr,$scr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfc +mvfc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvfc r4, cr1 + + test_h_gr r4, 0 + + mvi_h_condbit 1 + + mvfc r4, cr1 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/sim/m32r/mvtachi.cgs b/sim/testsuite/sim/m32r/mvtachi.cgs new file mode 100644 index 00000000000..6d596169557 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtachi.cgs @@ -0,0 +1,20 @@ +# m32r testcase for mvtachi $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtachi +mvtachi: + mvi_h_accum0 0, 0 + + mvi_h_gr r4, 0x11223344 + mvtachi r4 + test_h_accum0 0x223344, 0x0 + + mvi_h_gr r4, 0x99aabbcc + mvtachi r4 + test_h_accum0 0xffaabbcc, 0x0 + + pass diff --git a/sim/testsuite/sim/m32r/mvtaclo.cgs b/sim/testsuite/sim/m32r/mvtaclo.cgs new file mode 100644 index 00000000000..baafd839acb --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvtaclo $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtaclo +mvtaclo: + mvi_h_accum0 0, 0 + mvi_h_gr r4, 0x11223344 + + mvtaclo r4 + + test_h_accum0 0, 0x11223344 + + pass diff --git a/sim/testsuite/sim/m32r/mvtc.cgs b/sim/testsuite/sim/m32r/mvtc.cgs new file mode 100644 index 00000000000..94780dfa11a --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtc.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mvtc $sr,$dcr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtc +mvtc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvtc r4, cr1 + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/neg.cgs b/sim/testsuite/sim/m32r/neg.cgs new file mode 100644 index 00000000000..6051efaf256 --- /dev/null +++ b/sim/testsuite/sim/m32r/neg.cgs @@ -0,0 +1,17 @@ +# m32r testcase for neg $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global neg +neg: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + neg r4, r5 + + test_h_gr r4, -2 + + pass diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs new file mode 100644 index 00000000000..05b44bc552d --- /dev/null +++ b/sim/testsuite/sim/m32r/nop.cgs @@ -0,0 +1,10 @@ +# m32r testcase for nop +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global nop +nop: + pass diff --git a/sim/testsuite/sim/m32r/not.cgs b/sim/testsuite/sim/m32r/not.cgs new file mode 100644 index 00000000000..e6ceb643ebf --- /dev/null +++ b/sim/testsuite/sim/m32r/not.cgs @@ -0,0 +1,17 @@ +# m32r testcase for not $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global not +not: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + not r4, r5 + + test_h_gr r4, 0xfffffffd + + pass diff --git a/sim/testsuite/sim/m32r/or.cgs b/sim/testsuite/sim/m32r/or.cgs new file mode 100644 index 00000000000..1b08bd0c2a7 --- /dev/null +++ b/sim/testsuite/sim/m32r/or.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or +or: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + or r4, r5 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/sim/m32r/or3.cgs b/sim/testsuite/sim/m32r/or3.cgs new file mode 100644 index 00000000000..dc76ada9333 --- /dev/null +++ b/sim/testsuite/sim/m32r/or3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or3 $dr,$sr,#$ulo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or3 +or3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + or3 r4, r5, #3 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/sim/m32r/rac.cgs b/sim/testsuite/sim/m32r/rac.cgs new file mode 100644 index 00000000000..35b9ae3cd91 --- /dev/null +++ b/sim/testsuite/sim/m32r/rac.cgs @@ -0,0 +1,23 @@ +# m32r testcase for rac +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac +rac: + + mvi_h_accum0 1, 0x4001 + rac + test_h_accum0 2, 0x10000 + + mvi_h_accum0 0x3fff, 0xffff4000 + rac + test_h_accum0 0x7fff, 0xffff0000 + + mvi_h_accum0 0xffff8000, 0 + rac + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rach.cgs b/sim/testsuite/sim/m32r/rach.cgs new file mode 100644 index 00000000000..c22469834f7 --- /dev/null +++ b/sim/testsuite/sim/m32r/rach.cgs @@ -0,0 +1,22 @@ +# m32r testcase for rach +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach +rach: + mvi_h_accum0 1, 0x40004001 + rach + test_h_accum0 3, 0 + + mvi_h_accum0 0x3fff, 0xc0000000 + rach + test_h_accum0 0x7fff, 0 + + mvi_h_accum0 0xffff8000, 0 + rach + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rem.cgs b/sim/testsuite/sim/m32r/rem.cgs new file mode 100644 index 00000000000..78c11cbcf90 --- /dev/null +++ b/sim/testsuite/sim/m32r/rem.cgs @@ -0,0 +1,17 @@ +# m32r testcase for rem $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rem +rem: + mvi_h_gr r4, 12345678 + mvi_h_gr r5, 7 + + rem r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/remu.cgs b/sim/testsuite/sim/m32r/remu.cgs new file mode 100644 index 00000000000..36336306b27 --- /dev/null +++ b/sim/testsuite/sim/m32r/remu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for remu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global remu +remu: + mvi_h_gr r4, 17 + mvi_h_gr r5, 7 + + remu r4, r5 + + test_h_gr r4, 3 + + mvi_h_gr r4, -17 + + remu r4, r5 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/sim/m32r/rte.cgs b/sim/testsuite/sim/m32r/rte.cgs new file mode 100644 index 00000000000..b389fe15431 --- /dev/null +++ b/sim/testsuite/sim/m32r/rte.cgs @@ -0,0 +1,87 @@ +# m32r testcase for rte +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rte +rte: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = ret1 + mvaddr_h_gr r4, ret1 + mvtc r4, bpc + + rte + fail + +ret1: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvfc r4, cr0 + test_h_gr r4, 0xc1 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = 0 + mvfc r4, bpc + test_h_gr r4, 0 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = ret2 + 2 + mvaddr_h_gr r4, ret2 + 2 + mvtc r4, bpc + + rte + fail + +ret2: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc100 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = 42 + mvfc r4, bpc + test_h_gr r4, 42 + + pass diff --git a/sim/testsuite/sim/m32r/seth.cgs b/sim/testsuite/sim/m32r/seth.cgs new file mode 100644 index 00000000000..aec3230a548 --- /dev/null +++ b/sim/testsuite/sim/m32r/seth.cgs @@ -0,0 +1,20 @@ +# m32r testcase for seth $dr,#$hi16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global seth +seth: + seth r4, #0x1234 + + ; do not use test_h_gr macro since this uses seth + + srli r4, #16 + ld24 r5, #0x1234 + beq r4, r5, ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/sll.cgs b/sim/testsuite/sim/m32r/sll.cgs new file mode 100644 index 00000000000..fa3cfed8861 --- /dev/null +++ b/sim/testsuite/sim/m32r/sll.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll +sll: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + sll r4, r5 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/sll3.cgs b/sim/testsuite/sim/m32r/sll3.cgs new file mode 100644 index 00000000000..ddd360cd111 --- /dev/null +++ b/sim/testsuite/sim/m32r/sll3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll3 +sll3: + mvi_h_gr r4, 1 + mvi_h_gr r5, 6 + sll3 r4, r5, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/slli.cgs b/sim/testsuite/sim/m32r/slli.cgs new file mode 100644 index 00000000000..eab77daa695 --- /dev/null +++ b/sim/testsuite/sim/m32r/slli.cgs @@ -0,0 +1,14 @@ +# m32r testcase for slli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global slli +slli: + mvi_h_gr r4, 6 + slli r4, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/sra.cgs b/sim/testsuite/sim/m32r/sra.cgs new file mode 100644 index 00000000000..11671ed8658 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra +sra: + + mvi_h_gr r4, 0xf0f0f0ff + mvi_h_gr r5, 4 + sra r4, r5 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/sra3.cgs b/sim/testsuite/sim/m32r/sra3.cgs new file mode 100644 index 00000000000..0dd387adf46 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra3 +sra3: + + mvi_h_gr r4, 0 + mvi_h_gr r5, 0xf0f0f0ff + sra3 r4, r5, #4 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/srai.cgs b/sim/testsuite/sim/m32r/srai.cgs new file mode 100644 index 00000000000..2a1569422a5 --- /dev/null +++ b/sim/testsuite/sim/m32r/srai.cgs @@ -0,0 +1,14 @@ +# m32r testcase for srai $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srai +srai: + mvi_h_gr r5, 0xf0f0f0ff + srai r5, #4 + test_h_gr r5, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/srl.cgs b/sim/testsuite/sim/m32r/srl.cgs new file mode 100644 index 00000000000..8838c2fbd48 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl +srl: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + srl r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/srl3.cgs b/sim/testsuite/sim/m32r/srl3.cgs new file mode 100644 index 00000000000..a1dc4840f63 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl3 +srl3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + srl3 r4, r5, #1 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/srli.cgs b/sim/testsuite/sim/m32r/srli.cgs new file mode 100644 index 00000000000..f358a768a7f --- /dev/null +++ b/sim/testsuite/sim/m32r/srli.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srli +srli: + mvi_h_gr r5, 6 + srli r5, #1 + test_h_gr r5, 3 + + + pass diff --git a/sim/testsuite/sim/m32r/st-d.cgs b/sim/testsuite/sim/m32r/st-d.cgs new file mode 100644 index 00000000000..e2668a05c04 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-d.cgs @@ -0,0 +1,26 @@ +# m32r testcase for st $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_d +st_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/sim/m32r/st-minus.cgs b/sim/testsuite/sim/m32r/st-minus.cgs new file mode 100644 index 00000000000..fc90351c389 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-minus.cgs @@ -0,0 +1,29 @@ +# m32r testcase for st $src1,@-$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_minus +st_minus: + mvaddr_h_gr r4, data_loc2 + mvi_h_gr r5, 1 + + st r5, @-r4 + + mvaddr_h_gr r5, data_loc + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/sim/m32r/st-plus.cgs b/sim/testsuite/sim/m32r/st-plus.cgs new file mode 100644 index 00000000000..7bb4dd16fe7 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for st $src1,@+$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_plus +st_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @+r4 + + mvaddr_h_gr r5, data_loc2 + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/st.cgs b/sim/testsuite/sim/m32r/st.cgs new file mode 100644 index 00000000000..9588b8c40c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/st.cgs @@ -0,0 +1,21 @@ +# m32r testcase for st $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st +st: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @r4 + + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/stb-d.cgs b/sim/testsuite/sim/m32r/stb-d.cgs new file mode 100644 index 00000000000..37c2d733d72 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for stb $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb_d +stb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/stb.cgs b/sim/testsuite/sim/m32r/stb.cgs new file mode 100644 index 00000000000..01283169023 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for stb $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb +stb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/sth-d.cgs b/sim/testsuite/sim/m32r/sth-d.cgs new file mode 100644 index 00000000000..11aaa6d76c1 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for sth $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth_d +sth_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/sth.cgs b/sim/testsuite/sim/m32r/sth.cgs new file mode 100644 index 00000000000..1a10fde1ce3 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth.cgs @@ -0,0 +1,21 @@ +# m32r testcase for sth $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth +sth: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/sub.cgs b/sim/testsuite/sim/m32r/sub.cgs new file mode 100644 index 00000000000..4d676e58083 --- /dev/null +++ b/sim/testsuite/sim/m32r/sub.cgs @@ -0,0 +1,18 @@ +# m32r testcase for sub $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sub +sub: + + mvi_h_gr r4, 7 + mvi_h_gr r5, 3 + + sub r4, r5 + + test_h_gr r4, 4 + + pass diff --git a/sim/testsuite/sim/m32r/subv.cgs b/sim/testsuite/sim/m32r/subv.cgs new file mode 100644 index 00000000000..9474766e55b --- /dev/null +++ b/sim/testsuite/sim/m32r/subv.cgs @@ -0,0 +1,20 @@ +# m32r testcase for subv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subv +subv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 3 + + subv r4, r5 + + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/subx.cgs b/sim/testsuite/sim/m32r/subx.cgs new file mode 100644 index 00000000000..e890fcfabd7 --- /dev/null +++ b/sim/testsuite/sim/m32r/subx.cgs @@ -0,0 +1,26 @@ +# m32r testcase for subx $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subx +subx: + mvi_h_condbit 1 + mvi_h_gr r4, 6 + mvi_h_gr r5, 4 + subx r4, r5 + bc not_ok + test_h_gr r4, 1 + + mvi_h_condbit 1 + mvi_h_gr r4, 4 + mvi_h_gr r5, 4 + subx r4, r5 + bnc not_ok + test_h_gr r4, 0xffffffff + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/testutils.inc b/sim/testsuite/sim/m32r/testutils.inc new file mode 100644 index 00000000000..1d8822ae098 --- /dev/null +++ b/sim/testsuite/sim/m32r/testutils.inc @@ -0,0 +1,95 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + .endm + + .macro exit rc + ldi8 r1, \rc + ldi8 r0, #1 + trap #0 + .endm + + .macro pass + ldi8 r3, 5 + ld24 r2, passmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 0 + .endm + + .macro fail + ldi8 r3, 5 + ld24 r2, failmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 1 + .endm + + .macro mvi_h_gr reg, val + .if (\val >= -128) && (\val <= 127) + ldi8 \reg, \val + .else + seth \reg, high(\val) + or3 \reg, \reg, low(\val) + .endif + .endm + + .macro mvaddr_h_gr reg, addr + seth \reg, high(\addr) + or3 \reg, \reg, low(\addr) + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + beq \reg, r0, test_gr\@ + fail +test_gr\@: + .endm + + .macro mvi_h_condbit val + ldi8 r0, 0 + ldi8 r1, 1 + .if \val + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_condbit val + .if \val + bc test_c1\@ + fail +test_c1\@: + .else + bnc test_c0\@ + fail +test_c0\@: + .endif + .endm + + .macro mvi_h_accum0 hi, lo + mvi_h_gr r0, \hi + mvtachi r0 + mvi_h_gr r0, \lo + mvtaclo r0 + .endm + + .macro test_h_accum0 hi, lo + mvfachi r1 + test_h_gr r1, \hi + mvfaclo r1 + test_h_gr r1, \lo + .endm + diff --git a/sim/testsuite/sim/m32r/trap.cgs b/sim/testsuite/sim/m32r/trap.cgs new file mode 100644 index 00000000000..59e136a0173 --- /dev/null +++ b/sim/testsuite/sim/m32r/trap.cgs @@ -0,0 +1,109 @@ +# m32r testcase for trap #$uimm4 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global trap +trap: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bpc + + ; Copy trap2_handler to trap area of memory. + ld24 r0,#0x48 ; address of trap 2 handler + ld24 r1,#trap2_handler + ld r2,@r1 + st r2,@r0 + ; Set up return address. + ld24 r5,#trap2_ret1 + +trap_insn1: + trap #2 + fail + +trap2_ret1: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn1 + 4 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bpc + + ; Set up return address. + ld24 r5,#trap2_ret2 + +trap_insn2: + trap #2 + fail + +trap2_ret2: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc180 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn2 + 4 + + pass + + .data + +; Don't use rte as it will undo the effects of trap we're testing. + + .p2align 2 +trap2_handler: + jmp r5 + nop diff --git a/sim/testsuite/sim/m32r/unlock.cgs b/sim/testsuite/sim/m32r/unlock.cgs new file mode 100644 index 00000000000..1a51b7ae4cf --- /dev/null +++ b/sim/testsuite/sim/m32r/unlock.cgs @@ -0,0 +1,30 @@ +# m32r testcase for unlock $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global unlock +unlock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + lock r5, @r4 + + mvi_h_gr r5, 2 + unlock r5, @r4 + + ld r6, @r4 + test_h_gr r6, 2 + + mvi_h_gr r5, 0 + unlock r5, @r4 ; This should be a nop since the processor should be unlocked. + + ld r6, @r4 + test_h_gr r6, 2 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/uread16.ms b/sim/testsuite/sim/m32r/uread16.ms new file mode 100644 index 00000000000..550e99a2dfc --- /dev/null +++ b/sim/testsuite/sim/m32r/uread16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ldh r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/sim/m32r/uread32.ms b/sim/testsuite/sim/m32r/uread32.ms new file mode 100644 index 00000000000..935c71624e4 --- /dev/null +++ b/sim/testsuite/sim/m32r/uread32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ld r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/sim/m32r/uwrite16.ms b/sim/testsuite/sim/m32r/uwrite16.ms new file mode 100644 index 00000000000..11bfd6ee2a9 --- /dev/null +++ b/sim/testsuite/sim/m32r/uwrite16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + sth r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/sim/m32r/uwrite32.ms b/sim/testsuite/sim/m32r/uwrite32.ms new file mode 100644 index 00000000000..495a123b60e --- /dev/null +++ b/sim/testsuite/sim/m32r/uwrite32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + st r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/sim/m32r/xor.cgs b/sim/testsuite/sim/m32r/xor.cgs new file mode 100644 index 00000000000..254da798167 --- /dev/null +++ b/sim/testsuite/sim/m32r/xor.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor +xor: + + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + xor r4, r5 + test_h_gr r4, 5 + + pass diff --git a/sim/testsuite/sim/m32r/xor3.cgs b/sim/testsuite/sim/m32r/xor3.cgs new file mode 100644 index 00000000000..eee7269f934 --- /dev/null +++ b/sim/testsuite/sim/m32r/xor3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor3 +xor3: + + mvi_h_gr r5, 0 + mvi_h_gr r4, 3 + xor3 r5, r4, #6 + test_h_gr r5, 5 + + pass |